1 /* 2 * Freescale SPI/eSPI controller driver library. 3 * 4 * Maintainer: Kumar Gala 5 * 6 * Copyright 2010 Freescale Semiconductor, Inc. 7 * Copyright (C) 2006 Polycom, Inc. 8 * 9 * CPM SPI and QE buffer descriptors mode support: 10 * Copyright (c) 2009 MontaVista Software, Inc. 11 * Author: Anton Vorontsov <avorontsov@ru.mvista.com> 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the 15 * Free Software Foundation; either version 2 of the License, or (at your 16 * option) any later version. 17 */ 18 #ifndef __SPI_FSL_LIB_H__ 19 #define __SPI_FSL_LIB_H__ 20 21 #include <asm/io.h> 22 23 /* SPI/eSPI Controller driver's private data. */ 24 struct mpc8xxx_spi { 25 struct device *dev; 26 void __iomem *reg_base; 27 28 /* rx & tx bufs from the spi_transfer */ 29 const void *tx; 30 void *rx; 31 32 int subblock; 33 struct spi_pram __iomem *pram; 34 #ifdef CONFIG_FSL_SOC 35 struct cpm_buf_desc __iomem *tx_bd; 36 struct cpm_buf_desc __iomem *rx_bd; 37 #endif 38 39 struct spi_transfer *xfer_in_progress; 40 41 /* dma addresses for CPM transfers */ 42 dma_addr_t tx_dma; 43 dma_addr_t rx_dma; 44 bool map_tx_dma; 45 bool map_rx_dma; 46 47 dma_addr_t dma_dummy_tx; 48 dma_addr_t dma_dummy_rx; 49 50 /* functions to deal with different sized buffers */ 51 void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *); 52 u32(*get_tx) (struct mpc8xxx_spi *); 53 54 unsigned int count; 55 unsigned int irq; 56 57 unsigned nsecs; /* (clock cycle time)/2 */ 58 59 u32 spibrg; /* SPIBRG input clock */ 60 u32 rx_shift; /* RX data reg shift when in qe mode */ 61 u32 tx_shift; /* TX data reg shift when in qe mode */ 62 63 unsigned int flags; 64 65 #if IS_ENABLED(CONFIG_SPI_FSL_SPI) 66 int type; 67 int native_chipselects; 68 u8 max_bits_per_word; 69 70 void (*set_shifts)(u32 *rx_shift, u32 *tx_shift, 71 int bits_per_word, int msb_first); 72 #endif 73 74 struct completion done; 75 }; 76 77 struct spi_mpc8xxx_cs { 78 /* functions to deal with different sized buffers */ 79 void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *); 80 u32 (*get_tx) (struct mpc8xxx_spi *); 81 u32 rx_shift; /* RX data reg shift when in qe mode */ 82 u32 tx_shift; /* TX data reg shift when in qe mode */ 83 u32 hw_mode; /* Holds HW mode register settings */ 84 }; 85 86 static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val) 87 { 88 iowrite32be(val, reg); 89 } 90 91 static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg) 92 { 93 return ioread32be(reg); 94 } 95 96 struct mpc8xxx_spi_probe_info { 97 struct fsl_spi_platform_data pdata; 98 int *gpios; 99 bool *alow_flags; 100 }; 101 102 extern u32 mpc8xxx_spi_tx_buf_u8(struct mpc8xxx_spi *mpc8xxx_spi); 103 extern u32 mpc8xxx_spi_tx_buf_u16(struct mpc8xxx_spi *mpc8xxx_spi); 104 extern u32 mpc8xxx_spi_tx_buf_u32(struct mpc8xxx_spi *mpc8xxx_spi); 105 extern void mpc8xxx_spi_rx_buf_u8(u32 data, struct mpc8xxx_spi *mpc8xxx_spi); 106 extern void mpc8xxx_spi_rx_buf_u16(u32 data, struct mpc8xxx_spi *mpc8xxx_spi); 107 extern void mpc8xxx_spi_rx_buf_u32(u32 data, struct mpc8xxx_spi *mpc8xxx_spi); 108 109 extern struct mpc8xxx_spi_probe_info *to_of_pinfo( 110 struct fsl_spi_platform_data *pdata); 111 extern int mpc8xxx_spi_bufs(struct mpc8xxx_spi *mspi, 112 struct spi_transfer *t, unsigned int len); 113 extern const char *mpc8xxx_spi_strmode(unsigned int flags); 114 extern void mpc8xxx_spi_probe(struct device *dev, struct resource *mem, 115 unsigned int irq); 116 extern int mpc8xxx_spi_remove(struct device *dev); 117 extern int of_mpc8xxx_spi_probe(struct platform_device *ofdev); 118 119 #endif /* __SPI_FSL_LIB_H__ */ 120