xref: /openbmc/linux/drivers/spi/spi-fsl-lib.c (revision cd5d5810)
1 /*
2  * Freescale SPI/eSPI controller driver library.
3  *
4  * Maintainer: Kumar Gala
5  *
6  * Copyright (C) 2006 Polycom, Inc.
7  *
8  * CPM SPI and QE buffer descriptors mode support:
9  * Copyright (c) 2009  MontaVista Software, Inc.
10  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
11  *
12  * Copyright 2010 Freescale Semiconductor, Inc.
13  *
14  * This program is free software; you can redistribute  it and/or modify it
15  * under  the terms of  the GNU General  Public License as published by the
16  * Free Software Foundation;  either version 2 of the  License, or (at your
17  * option) any later version.
18  */
19 #include <linux/kernel.h>
20 #include <linux/interrupt.h>
21 #include <linux/fsl_devices.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/mm.h>
24 #include <linux/of_platform.h>
25 #include <linux/spi/spi.h>
26 #ifdef CONFIG_FSL_SOC
27 #include <sysdev/fsl_soc.h>
28 #endif
29 
30 #include "spi-fsl-lib.h"
31 
32 #define MPC8XXX_SPI_RX_BUF(type) 					  \
33 void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \
34 {									  \
35 	type *rx = mpc8xxx_spi->rx;					  \
36 	*rx++ = (type)(data >> mpc8xxx_spi->rx_shift);			  \
37 	mpc8xxx_spi->rx = rx;						  \
38 }
39 
40 #define MPC8XXX_SPI_TX_BUF(type)				\
41 u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi)	\
42 {								\
43 	u32 data;						\
44 	const type *tx = mpc8xxx_spi->tx;			\
45 	if (!tx)						\
46 		return 0;					\
47 	data = *tx++ << mpc8xxx_spi->tx_shift;			\
48 	mpc8xxx_spi->tx = tx;					\
49 	return data;						\
50 }
51 
52 MPC8XXX_SPI_RX_BUF(u8)
53 MPC8XXX_SPI_RX_BUF(u16)
54 MPC8XXX_SPI_RX_BUF(u32)
55 MPC8XXX_SPI_TX_BUF(u8)
56 MPC8XXX_SPI_TX_BUF(u16)
57 MPC8XXX_SPI_TX_BUF(u32)
58 
59 struct mpc8xxx_spi_probe_info *to_of_pinfo(struct fsl_spi_platform_data *pdata)
60 {
61 	return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
62 }
63 
64 static void mpc8xxx_spi_work(struct work_struct *work)
65 {
66 	struct mpc8xxx_spi *mpc8xxx_spi = container_of(work, struct mpc8xxx_spi,
67 						       work);
68 
69 	spin_lock_irq(&mpc8xxx_spi->lock);
70 	while (!list_empty(&mpc8xxx_spi->queue)) {
71 		struct spi_message *m = container_of(mpc8xxx_spi->queue.next,
72 						   struct spi_message, queue);
73 
74 		list_del_init(&m->queue);
75 		spin_unlock_irq(&mpc8xxx_spi->lock);
76 
77 		if (mpc8xxx_spi->spi_do_one_msg)
78 			mpc8xxx_spi->spi_do_one_msg(m);
79 
80 		spin_lock_irq(&mpc8xxx_spi->lock);
81 	}
82 	spin_unlock_irq(&mpc8xxx_spi->lock);
83 }
84 
85 int mpc8xxx_spi_transfer(struct spi_device *spi,
86 				struct spi_message *m)
87 {
88 	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
89 	unsigned long flags;
90 
91 	m->actual_length = 0;
92 	m->status = -EINPROGRESS;
93 
94 	spin_lock_irqsave(&mpc8xxx_spi->lock, flags);
95 	list_add_tail(&m->queue, &mpc8xxx_spi->queue);
96 	queue_work(mpc8xxx_spi->workqueue, &mpc8xxx_spi->work);
97 	spin_unlock_irqrestore(&mpc8xxx_spi->lock, flags);
98 
99 	return 0;
100 }
101 
102 void mpc8xxx_spi_cleanup(struct spi_device *spi)
103 {
104 	kfree(spi->controller_state);
105 }
106 
107 const char *mpc8xxx_spi_strmode(unsigned int flags)
108 {
109 	if (flags & SPI_QE_CPU_MODE) {
110 		return "QE CPU";
111 	} else if (flags & SPI_CPM_MODE) {
112 		if (flags & SPI_QE)
113 			return "QE";
114 		else if (flags & SPI_CPM2)
115 			return "CPM2";
116 		else
117 			return "CPM1";
118 	}
119 	return "CPU";
120 }
121 
122 int mpc8xxx_spi_probe(struct device *dev, struct resource *mem,
123 			unsigned int irq)
124 {
125 	struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
126 	struct spi_master *master;
127 	struct mpc8xxx_spi *mpc8xxx_spi;
128 	int ret = 0;
129 
130 	master = dev_get_drvdata(dev);
131 
132 	/* the spi->mode bits understood by this driver: */
133 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH
134 			| SPI_LSB_FIRST | SPI_LOOP;
135 
136 	master->transfer = mpc8xxx_spi_transfer;
137 	master->cleanup = mpc8xxx_spi_cleanup;
138 	master->dev.of_node = dev->of_node;
139 
140 	mpc8xxx_spi = spi_master_get_devdata(master);
141 	mpc8xxx_spi->dev = dev;
142 	mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8;
143 	mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8;
144 	mpc8xxx_spi->flags = pdata->flags;
145 	mpc8xxx_spi->spibrg = pdata->sysclk;
146 	mpc8xxx_spi->irq = irq;
147 
148 	mpc8xxx_spi->rx_shift = 0;
149 	mpc8xxx_spi->tx_shift = 0;
150 
151 	init_completion(&mpc8xxx_spi->done);
152 
153 	master->bus_num = pdata->bus_num;
154 	master->num_chipselect = pdata->max_chipselect;
155 
156 	spin_lock_init(&mpc8xxx_spi->lock);
157 	init_completion(&mpc8xxx_spi->done);
158 	INIT_WORK(&mpc8xxx_spi->work, mpc8xxx_spi_work);
159 	INIT_LIST_HEAD(&mpc8xxx_spi->queue);
160 
161 	mpc8xxx_spi->workqueue = create_singlethread_workqueue(
162 		dev_name(master->dev.parent));
163 	if (mpc8xxx_spi->workqueue == NULL) {
164 		ret = -EBUSY;
165 		goto err;
166 	}
167 
168 	return 0;
169 
170 err:
171 	return ret;
172 }
173 
174 int mpc8xxx_spi_remove(struct device *dev)
175 {
176 	struct mpc8xxx_spi *mpc8xxx_spi;
177 	struct spi_master *master;
178 
179 	master = dev_get_drvdata(dev);
180 	mpc8xxx_spi = spi_master_get_devdata(master);
181 
182 	flush_workqueue(mpc8xxx_spi->workqueue);
183 	destroy_workqueue(mpc8xxx_spi->workqueue);
184 	spi_unregister_master(master);
185 
186 	free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
187 
188 	if (mpc8xxx_spi->spi_remove)
189 		mpc8xxx_spi->spi_remove(mpc8xxx_spi);
190 
191 	return 0;
192 }
193 
194 int of_mpc8xxx_spi_probe(struct platform_device *ofdev)
195 {
196 	struct device *dev = &ofdev->dev;
197 	struct device_node *np = ofdev->dev.of_node;
198 	struct mpc8xxx_spi_probe_info *pinfo;
199 	struct fsl_spi_platform_data *pdata;
200 	const void *prop;
201 	int ret = -ENOMEM;
202 
203 	pinfo = kzalloc(sizeof(*pinfo), GFP_KERNEL);
204 	if (!pinfo)
205 		return -ENOMEM;
206 
207 	pdata = &pinfo->pdata;
208 	dev->platform_data = pdata;
209 
210 	/* Allocate bus num dynamically. */
211 	pdata->bus_num = -1;
212 
213 #ifdef CONFIG_FSL_SOC
214 	/* SPI controller is either clocked from QE or SoC clock. */
215 	pdata->sysclk = get_brgfreq();
216 	if (pdata->sysclk == -1) {
217 		pdata->sysclk = fsl_get_sys_freq();
218 		if (pdata->sysclk == -1) {
219 			ret = -ENODEV;
220 			goto err;
221 		}
222 	}
223 #else
224 	ret = of_property_read_u32(np, "clock-frequency", &pdata->sysclk);
225 	if (ret)
226 		goto err;
227 #endif
228 
229 	prop = of_get_property(np, "mode", NULL);
230 	if (prop && !strcmp(prop, "cpu-qe"))
231 		pdata->flags = SPI_QE_CPU_MODE;
232 	else if (prop && !strcmp(prop, "qe"))
233 		pdata->flags = SPI_CPM_MODE | SPI_QE;
234 	else if (of_device_is_compatible(np, "fsl,cpm2-spi"))
235 		pdata->flags = SPI_CPM_MODE | SPI_CPM2;
236 	else if (of_device_is_compatible(np, "fsl,cpm1-spi"))
237 		pdata->flags = SPI_CPM_MODE | SPI_CPM1;
238 
239 	return 0;
240 
241 err:
242 	kfree(pinfo);
243 	return ret;
244 }
245