1 /* 2 * Freescale eSPI controller driver. 3 * 4 * Copyright 2010 Freescale Semiconductor, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 #include <linux/delay.h> 12 #include <linux/err.h> 13 #include <linux/fsl_devices.h> 14 #include <linux/interrupt.h> 15 #include <linux/module.h> 16 #include <linux/mm.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_platform.h> 21 #include <linux/platform_device.h> 22 #include <linux/spi/spi.h> 23 #include <linux/pm_runtime.h> 24 #include <sysdev/fsl_soc.h> 25 26 /* eSPI Controller registers */ 27 #define ESPI_SPMODE 0x00 /* eSPI mode register */ 28 #define ESPI_SPIE 0x04 /* eSPI event register */ 29 #define ESPI_SPIM 0x08 /* eSPI mask register */ 30 #define ESPI_SPCOM 0x0c /* eSPI command register */ 31 #define ESPI_SPITF 0x10 /* eSPI transmit FIFO access register*/ 32 #define ESPI_SPIRF 0x14 /* eSPI receive FIFO access register*/ 33 #define ESPI_SPMODE0 0x20 /* eSPI cs0 mode register */ 34 35 #define ESPI_SPMODEx(x) (ESPI_SPMODE0 + (x) * 4) 36 37 /* eSPI Controller mode register definitions */ 38 #define SPMODE_ENABLE BIT(31) 39 #define SPMODE_LOOP BIT(30) 40 #define SPMODE_TXTHR(x) ((x) << 8) 41 #define SPMODE_RXTHR(x) ((x) << 0) 42 43 /* eSPI Controller CS mode register definitions */ 44 #define CSMODE_CI_INACTIVEHIGH BIT(31) 45 #define CSMODE_CP_BEGIN_EDGECLK BIT(30) 46 #define CSMODE_REV BIT(29) 47 #define CSMODE_DIV16 BIT(28) 48 #define CSMODE_PM(x) ((x) << 24) 49 #define CSMODE_POL_1 BIT(20) 50 #define CSMODE_LEN(x) ((x) << 16) 51 #define CSMODE_BEF(x) ((x) << 12) 52 #define CSMODE_AFT(x) ((x) << 8) 53 #define CSMODE_CG(x) ((x) << 3) 54 55 #define FSL_ESPI_FIFO_SIZE 32 56 #define FSL_ESPI_RXTHR 15 57 58 /* Default mode/csmode for eSPI controller */ 59 #define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(FSL_ESPI_RXTHR)) 60 #define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \ 61 | CSMODE_AFT(0) | CSMODE_CG(1)) 62 63 /* SPIE register values */ 64 #define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F) 65 #define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F) 66 #define SPIE_TXE BIT(15) /* TX FIFO empty */ 67 #define SPIE_DON BIT(14) /* TX done */ 68 #define SPIE_RXT BIT(13) /* RX FIFO threshold */ 69 #define SPIE_RXF BIT(12) /* RX FIFO full */ 70 #define SPIE_TXT BIT(11) /* TX FIFO threshold*/ 71 #define SPIE_RNE BIT(9) /* RX FIFO not empty */ 72 #define SPIE_TNF BIT(8) /* TX FIFO not full */ 73 74 /* SPIM register values */ 75 #define SPIM_TXE BIT(15) /* TX FIFO empty */ 76 #define SPIM_DON BIT(14) /* TX done */ 77 #define SPIM_RXT BIT(13) /* RX FIFO threshold */ 78 #define SPIM_RXF BIT(12) /* RX FIFO full */ 79 #define SPIM_TXT BIT(11) /* TX FIFO threshold*/ 80 #define SPIM_RNE BIT(9) /* RX FIFO not empty */ 81 #define SPIM_TNF BIT(8) /* TX FIFO not full */ 82 83 /* SPCOM register values */ 84 #define SPCOM_CS(x) ((x) << 30) 85 #define SPCOM_DO BIT(28) /* Dual output */ 86 #define SPCOM_TO BIT(27) /* TX only */ 87 #define SPCOM_RXSKIP(x) ((x) << 16) 88 #define SPCOM_TRANLEN(x) ((x) << 0) 89 90 #define SPCOM_TRANLEN_MAX 0x10000 /* Max transaction length */ 91 92 #define AUTOSUSPEND_TIMEOUT 2000 93 94 struct fsl_espi { 95 struct device *dev; 96 void __iomem *reg_base; 97 98 const void *tx; 99 void *rx; 100 101 unsigned int rx_len; 102 unsigned int tx_len; 103 unsigned int rxskip; 104 105 u8 *local_buf; 106 spinlock_t lock; 107 108 u32 spibrg; /* SPIBRG input clock */ 109 110 struct completion done; 111 }; 112 113 struct fsl_espi_cs { 114 u32 hw_mode; 115 }; 116 117 static inline u32 fsl_espi_read_reg(struct fsl_espi *espi, int offset) 118 { 119 return ioread32be(espi->reg_base + offset); 120 } 121 122 static inline u8 fsl_espi_read_reg8(struct fsl_espi *espi, int offset) 123 { 124 return ioread8(espi->reg_base + offset); 125 } 126 127 static inline void fsl_espi_write_reg(struct fsl_espi *espi, int offset, 128 u32 val) 129 { 130 iowrite32be(val, espi->reg_base + offset); 131 } 132 133 static inline void fsl_espi_write_reg8(struct fsl_espi *espi, int offset, 134 u8 val) 135 { 136 iowrite8(val, espi->reg_base + offset); 137 } 138 139 static void fsl_espi_memcpy_swab(void *to, const void *from, 140 struct spi_message *m, 141 struct spi_transfer *t) 142 { 143 unsigned int len = t->len; 144 145 if (!(m->spi->mode & SPI_LSB_FIRST) || t->bits_per_word <= 8) { 146 memcpy(to, from, len); 147 return; 148 } 149 150 /* In case of LSB-first and bits_per_word > 8 byte-swap all words */ 151 while (len) 152 if (len >= 4) { 153 *(u32 *)to = swahb32p(from); 154 to += 4; 155 from += 4; 156 len -= 4; 157 } else { 158 *(u16 *)to = swab16p(from); 159 to += 2; 160 from += 2; 161 len -= 2; 162 } 163 } 164 165 static void fsl_espi_copy_to_buf(struct spi_message *m, 166 struct fsl_espi *espi) 167 { 168 struct spi_transfer *t; 169 u8 *buf = espi->local_buf; 170 171 list_for_each_entry(t, &m->transfers, transfer_list) { 172 if (t->tx_buf) 173 fsl_espi_memcpy_swab(buf, t->tx_buf, m, t); 174 /* In RXSKIP mode controller shifts out zeros internally */ 175 else if (!espi->rxskip) 176 memset(buf, 0, t->len); 177 buf += t->len; 178 } 179 } 180 181 static void fsl_espi_copy_from_buf(struct spi_message *m, 182 struct fsl_espi *espi) 183 { 184 struct spi_transfer *t; 185 u8 *buf = espi->local_buf; 186 187 list_for_each_entry(t, &m->transfers, transfer_list) { 188 if (t->rx_buf) 189 fsl_espi_memcpy_swab(t->rx_buf, buf, m, t); 190 buf += t->len; 191 } 192 } 193 194 static int fsl_espi_check_message(struct spi_message *m) 195 { 196 struct fsl_espi *espi = spi_master_get_devdata(m->spi->master); 197 struct spi_transfer *t, *first; 198 199 if (m->frame_length > SPCOM_TRANLEN_MAX) { 200 dev_err(espi->dev, "message too long, size is %u bytes\n", 201 m->frame_length); 202 return -EMSGSIZE; 203 } 204 205 first = list_first_entry(&m->transfers, struct spi_transfer, 206 transfer_list); 207 208 list_for_each_entry(t, &m->transfers, transfer_list) { 209 if (first->bits_per_word != t->bits_per_word || 210 first->speed_hz != t->speed_hz) { 211 dev_err(espi->dev, "bits_per_word/speed_hz should be the same for all transfers\n"); 212 return -EINVAL; 213 } 214 } 215 216 /* ESPI supports MSB-first transfers for word size 8 / 16 only */ 217 if (!(m->spi->mode & SPI_LSB_FIRST) && first->bits_per_word != 8 && 218 first->bits_per_word != 16) { 219 dev_err(espi->dev, 220 "MSB-first transfer not supported for wordsize %u\n", 221 first->bits_per_word); 222 return -EINVAL; 223 } 224 225 return 0; 226 } 227 228 static unsigned int fsl_espi_check_rxskip_mode(struct spi_message *m) 229 { 230 struct spi_transfer *t; 231 unsigned int i = 0, rxskip = 0; 232 233 /* 234 * prerequisites for ESPI rxskip mode: 235 * - message has two transfers 236 * - first transfer is a write and second is a read 237 * 238 * In addition the current low-level transfer mechanism requires 239 * that the rxskip bytes fit into the TX FIFO. Else the transfer 240 * would hang because after the first FSL_ESPI_FIFO_SIZE bytes 241 * the TX FIFO isn't re-filled. 242 */ 243 list_for_each_entry(t, &m->transfers, transfer_list) { 244 if (i == 0) { 245 if (!t->tx_buf || t->rx_buf || 246 t->len > FSL_ESPI_FIFO_SIZE) 247 return 0; 248 rxskip = t->len; 249 } else if (i == 1) { 250 if (t->tx_buf || !t->rx_buf) 251 return 0; 252 } 253 i++; 254 } 255 256 return i == 2 ? rxskip : 0; 257 } 258 259 static void fsl_espi_fill_tx_fifo(struct fsl_espi *espi, u32 events) 260 { 261 u32 tx_fifo_avail; 262 263 /* if events is zero transfer has not started and tx fifo is empty */ 264 tx_fifo_avail = events ? SPIE_TXCNT(events) : FSL_ESPI_FIFO_SIZE; 265 266 while (tx_fifo_avail >= min(4U, espi->tx_len) && espi->tx_len) 267 if (espi->tx_len >= 4) { 268 fsl_espi_write_reg(espi, ESPI_SPITF, *(u32 *)espi->tx); 269 espi->tx += 4; 270 espi->tx_len -= 4; 271 tx_fifo_avail -= 4; 272 } else { 273 fsl_espi_write_reg8(espi, ESPI_SPITF, *(u8 *)espi->tx); 274 espi->tx += 1; 275 espi->tx_len -= 1; 276 tx_fifo_avail -= 1; 277 } 278 } 279 280 static void fsl_espi_read_rx_fifo(struct fsl_espi *espi, u32 events) 281 { 282 u32 rx_fifo_avail = SPIE_RXCNT(events); 283 284 while (rx_fifo_avail >= min(4U, espi->rx_len) && espi->rx_len) 285 if (espi->rx_len >= 4) { 286 *(u32 *)espi->rx = fsl_espi_read_reg(espi, ESPI_SPIRF); 287 espi->rx += 4; 288 espi->rx_len -= 4; 289 rx_fifo_avail -= 4; 290 } else { 291 *(u8 *)espi->rx = fsl_espi_read_reg8(espi, ESPI_SPIRF); 292 espi->rx += 1; 293 espi->rx_len -= 1; 294 rx_fifo_avail -= 1; 295 } 296 } 297 298 static void fsl_espi_setup_transfer(struct spi_device *spi, 299 struct spi_transfer *t) 300 { 301 struct fsl_espi *espi = spi_master_get_devdata(spi->master); 302 int bits_per_word = t ? t->bits_per_word : spi->bits_per_word; 303 u32 pm, hz = t ? t->speed_hz : spi->max_speed_hz; 304 struct fsl_espi_cs *cs = spi_get_ctldata(spi); 305 u32 hw_mode_old = cs->hw_mode; 306 307 /* mask out bits we are going to set */ 308 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF)); 309 310 cs->hw_mode |= CSMODE_LEN(bits_per_word - 1); 311 312 pm = DIV_ROUND_UP(espi->spibrg, hz * 4) - 1; 313 314 if (pm > 15) { 315 cs->hw_mode |= CSMODE_DIV16; 316 pm = DIV_ROUND_UP(espi->spibrg, hz * 16 * 4) - 1; 317 318 WARN_ONCE(pm > 15, 319 "%s: Requested speed is too low: %u Hz. Will use %u Hz instead.\n", 320 dev_name(&spi->dev), hz, 321 espi->spibrg / (4 * 16 * (15 + 1))); 322 if (pm > 15) 323 pm = 15; 324 } 325 326 cs->hw_mode |= CSMODE_PM(pm); 327 328 /* don't write the mode register if the mode doesn't change */ 329 if (cs->hw_mode != hw_mode_old) 330 fsl_espi_write_reg(espi, ESPI_SPMODEx(spi->chip_select), 331 cs->hw_mode); 332 } 333 334 static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t) 335 { 336 struct fsl_espi *espi = spi_master_get_devdata(spi->master); 337 u32 mask, spcom; 338 int ret; 339 340 espi->rx_len = t->len; 341 espi->tx_len = t->len; 342 343 espi->tx = t->tx_buf; 344 espi->rx = t->rx_buf; 345 346 reinit_completion(&espi->done); 347 348 /* Set SPCOM[CS] and SPCOM[TRANLEN] field */ 349 spcom = SPCOM_CS(spi->chip_select); 350 spcom |= SPCOM_TRANLEN(t->len - 1); 351 352 /* configure RXSKIP mode */ 353 if (espi->rxskip) { 354 spcom |= SPCOM_RXSKIP(espi->rxskip); 355 espi->tx_len = espi->rxskip; 356 espi->rx_len = t->len - espi->rxskip; 357 espi->rx = t->rx_buf + espi->rxskip; 358 if (t->rx_nbits == SPI_NBITS_DUAL) 359 spcom |= SPCOM_DO; 360 } 361 362 fsl_espi_write_reg(espi, ESPI_SPCOM, spcom); 363 364 /* enable interrupts */ 365 mask = SPIM_DON; 366 if (espi->rx_len > FSL_ESPI_FIFO_SIZE) 367 mask |= SPIM_RXT; 368 fsl_espi_write_reg(espi, ESPI_SPIM, mask); 369 370 /* Prevent filling the fifo from getting interrupted */ 371 spin_lock_irq(&espi->lock); 372 fsl_espi_fill_tx_fifo(espi, 0); 373 spin_unlock_irq(&espi->lock); 374 375 /* Won't hang up forever, SPI bus sometimes got lost interrupts... */ 376 ret = wait_for_completion_timeout(&espi->done, 2 * HZ); 377 if (ret == 0) 378 dev_err(espi->dev, 379 "Transaction hanging up (left %u tx bytes, %u rx bytes)\n", 380 espi->tx_len, espi->rx_len); 381 382 /* disable rx ints */ 383 fsl_espi_write_reg(espi, ESPI_SPIM, 0); 384 385 return ret == 0 ? -ETIMEDOUT : 0; 386 } 387 388 static int fsl_espi_trans(struct spi_message *m, struct spi_transfer *trans) 389 { 390 struct fsl_espi *espi = spi_master_get_devdata(m->spi->master); 391 struct spi_device *spi = m->spi; 392 int ret; 393 394 espi->rxskip = fsl_espi_check_rxskip_mode(m); 395 if (trans->rx_nbits == SPI_NBITS_DUAL && !espi->rxskip) { 396 dev_err(espi->dev, "Dual output mode requires RXSKIP mode!\n"); 397 return -EINVAL; 398 } 399 400 fsl_espi_copy_to_buf(m, espi); 401 fsl_espi_setup_transfer(spi, trans); 402 403 ret = fsl_espi_bufs(spi, trans); 404 405 if (trans->delay_usecs) 406 udelay(trans->delay_usecs); 407 408 if (!ret) 409 fsl_espi_copy_from_buf(m, espi); 410 411 return ret; 412 } 413 414 static int fsl_espi_do_one_msg(struct spi_master *master, 415 struct spi_message *m) 416 { 417 struct fsl_espi *espi = spi_master_get_devdata(m->spi->master); 418 unsigned int delay_usecs = 0, rx_nbits = 0; 419 struct spi_transfer *t, trans = {}; 420 int ret; 421 422 ret = fsl_espi_check_message(m); 423 if (ret) 424 goto out; 425 426 list_for_each_entry(t, &m->transfers, transfer_list) { 427 if (t->delay_usecs > delay_usecs) 428 delay_usecs = t->delay_usecs; 429 if (t->rx_nbits > rx_nbits) 430 rx_nbits = t->rx_nbits; 431 } 432 433 t = list_first_entry(&m->transfers, struct spi_transfer, 434 transfer_list); 435 436 trans.len = m->frame_length; 437 trans.speed_hz = t->speed_hz; 438 trans.bits_per_word = t->bits_per_word; 439 trans.delay_usecs = delay_usecs; 440 trans.tx_buf = espi->local_buf; 441 trans.rx_buf = espi->local_buf; 442 trans.rx_nbits = rx_nbits; 443 444 if (trans.len) 445 ret = fsl_espi_trans(m, &trans); 446 447 m->actual_length = ret ? 0 : trans.len; 448 out: 449 if (m->status == -EINPROGRESS) 450 m->status = ret; 451 452 spi_finalize_current_message(master); 453 454 return ret; 455 } 456 457 static int fsl_espi_setup(struct spi_device *spi) 458 { 459 struct fsl_espi *espi; 460 u32 loop_mode; 461 struct fsl_espi_cs *cs = spi_get_ctldata(spi); 462 463 if (!spi->max_speed_hz) 464 return -EINVAL; 465 466 if (!cs) { 467 cs = kzalloc(sizeof(*cs), GFP_KERNEL); 468 if (!cs) 469 return -ENOMEM; 470 spi_set_ctldata(spi, cs); 471 } 472 473 espi = spi_master_get_devdata(spi->master); 474 475 pm_runtime_get_sync(espi->dev); 476 477 cs->hw_mode = fsl_espi_read_reg(espi, ESPI_SPMODEx(spi->chip_select)); 478 /* mask out bits we are going to set */ 479 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH 480 | CSMODE_REV); 481 482 if (spi->mode & SPI_CPHA) 483 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK; 484 if (spi->mode & SPI_CPOL) 485 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH; 486 if (!(spi->mode & SPI_LSB_FIRST)) 487 cs->hw_mode |= CSMODE_REV; 488 489 /* Handle the loop mode */ 490 loop_mode = fsl_espi_read_reg(espi, ESPI_SPMODE); 491 loop_mode &= ~SPMODE_LOOP; 492 if (spi->mode & SPI_LOOP) 493 loop_mode |= SPMODE_LOOP; 494 fsl_espi_write_reg(espi, ESPI_SPMODE, loop_mode); 495 496 fsl_espi_setup_transfer(spi, NULL); 497 498 pm_runtime_mark_last_busy(espi->dev); 499 pm_runtime_put_autosuspend(espi->dev); 500 501 return 0; 502 } 503 504 static void fsl_espi_cleanup(struct spi_device *spi) 505 { 506 struct fsl_espi_cs *cs = spi_get_ctldata(spi); 507 508 kfree(cs); 509 spi_set_ctldata(spi, NULL); 510 } 511 512 static void fsl_espi_cpu_irq(struct fsl_espi *espi, u32 events) 513 { 514 if (espi->rx_len) 515 fsl_espi_read_rx_fifo(espi, events); 516 517 if (espi->tx_len) 518 fsl_espi_fill_tx_fifo(espi, events); 519 520 if (espi->tx_len || espi->rx_len) 521 return; 522 523 /* we're done, but check for errors before returning */ 524 events = fsl_espi_read_reg(espi, ESPI_SPIE); 525 526 if (!(events & SPIE_DON)) 527 dev_err(espi->dev, 528 "Transfer done but SPIE_DON isn't set!\n"); 529 530 if (SPIE_RXCNT(events) || SPIE_TXCNT(events) != FSL_ESPI_FIFO_SIZE) 531 dev_err(espi->dev, "Transfer done but rx/tx fifo's aren't empty!\n"); 532 533 complete(&espi->done); 534 } 535 536 static irqreturn_t fsl_espi_irq(s32 irq, void *context_data) 537 { 538 struct fsl_espi *espi = context_data; 539 u32 events; 540 541 spin_lock(&espi->lock); 542 543 /* Get interrupt events(tx/rx) */ 544 events = fsl_espi_read_reg(espi, ESPI_SPIE); 545 if (!events) { 546 spin_unlock(&espi->lock); 547 return IRQ_NONE; 548 } 549 550 dev_vdbg(espi->dev, "%s: events %x\n", __func__, events); 551 552 fsl_espi_cpu_irq(espi, events); 553 554 /* Clear the events */ 555 fsl_espi_write_reg(espi, ESPI_SPIE, events); 556 557 spin_unlock(&espi->lock); 558 559 return IRQ_HANDLED; 560 } 561 562 #ifdef CONFIG_PM 563 static int fsl_espi_runtime_suspend(struct device *dev) 564 { 565 struct spi_master *master = dev_get_drvdata(dev); 566 struct fsl_espi *espi = spi_master_get_devdata(master); 567 u32 regval; 568 569 regval = fsl_espi_read_reg(espi, ESPI_SPMODE); 570 regval &= ~SPMODE_ENABLE; 571 fsl_espi_write_reg(espi, ESPI_SPMODE, regval); 572 573 return 0; 574 } 575 576 static int fsl_espi_runtime_resume(struct device *dev) 577 { 578 struct spi_master *master = dev_get_drvdata(dev); 579 struct fsl_espi *espi = spi_master_get_devdata(master); 580 u32 regval; 581 582 regval = fsl_espi_read_reg(espi, ESPI_SPMODE); 583 regval |= SPMODE_ENABLE; 584 fsl_espi_write_reg(espi, ESPI_SPMODE, regval); 585 586 return 0; 587 } 588 #endif 589 590 static size_t fsl_espi_max_message_size(struct spi_device *spi) 591 { 592 return SPCOM_TRANLEN_MAX; 593 } 594 595 static void fsl_espi_init_regs(struct device *dev, bool initial) 596 { 597 struct spi_master *master = dev_get_drvdata(dev); 598 struct fsl_espi *espi = spi_master_get_devdata(master); 599 struct device_node *nc; 600 u32 csmode, cs, prop; 601 int ret; 602 603 /* SPI controller initializations */ 604 fsl_espi_write_reg(espi, ESPI_SPMODE, 0); 605 fsl_espi_write_reg(espi, ESPI_SPIM, 0); 606 fsl_espi_write_reg(espi, ESPI_SPCOM, 0); 607 fsl_espi_write_reg(espi, ESPI_SPIE, 0xffffffff); 608 609 /* Init eSPI CS mode register */ 610 for_each_available_child_of_node(master->dev.of_node, nc) { 611 /* get chip select */ 612 ret = of_property_read_u32(nc, "reg", &cs); 613 if (ret || cs >= master->num_chipselect) 614 continue; 615 616 csmode = CSMODE_INIT_VAL; 617 618 /* check if CSBEF is set in device tree */ 619 ret = of_property_read_u32(nc, "fsl,csbef", &prop); 620 if (!ret) { 621 csmode &= ~(CSMODE_BEF(0xf)); 622 csmode |= CSMODE_BEF(prop); 623 } 624 625 /* check if CSAFT is set in device tree */ 626 ret = of_property_read_u32(nc, "fsl,csaft", &prop); 627 if (!ret) { 628 csmode &= ~(CSMODE_AFT(0xf)); 629 csmode |= CSMODE_AFT(prop); 630 } 631 632 fsl_espi_write_reg(espi, ESPI_SPMODEx(cs), csmode); 633 634 if (initial) 635 dev_info(dev, "cs=%u, init_csmode=0x%x\n", cs, csmode); 636 } 637 638 /* Enable SPI interface */ 639 fsl_espi_write_reg(espi, ESPI_SPMODE, SPMODE_INIT_VAL | SPMODE_ENABLE); 640 } 641 642 static int fsl_espi_probe(struct device *dev, struct resource *mem, 643 unsigned int irq, unsigned int num_cs) 644 { 645 struct spi_master *master; 646 struct fsl_espi *espi; 647 int ret; 648 649 master = spi_alloc_master(dev, sizeof(struct fsl_espi)); 650 if (!master) 651 return -ENOMEM; 652 653 dev_set_drvdata(dev, master); 654 655 master->mode_bits = SPI_RX_DUAL | SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | 656 SPI_LSB_FIRST | SPI_LOOP; 657 master->dev.of_node = dev->of_node; 658 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); 659 master->setup = fsl_espi_setup; 660 master->cleanup = fsl_espi_cleanup; 661 master->transfer_one_message = fsl_espi_do_one_msg; 662 master->auto_runtime_pm = true; 663 master->max_message_size = fsl_espi_max_message_size; 664 master->num_chipselect = num_cs; 665 666 espi = spi_master_get_devdata(master); 667 spin_lock_init(&espi->lock); 668 669 espi->dev = dev; 670 espi->spibrg = fsl_get_sys_freq(); 671 if (espi->spibrg == -1) { 672 dev_err(dev, "Can't get sys frequency!\n"); 673 ret = -EINVAL; 674 goto err_probe; 675 } 676 677 init_completion(&espi->done); 678 679 espi->local_buf = devm_kmalloc(dev, SPCOM_TRANLEN_MAX, GFP_KERNEL); 680 if (!espi->local_buf) { 681 ret = -ENOMEM; 682 goto err_probe; 683 } 684 685 espi->reg_base = devm_ioremap_resource(dev, mem); 686 if (IS_ERR(espi->reg_base)) { 687 ret = PTR_ERR(espi->reg_base); 688 goto err_probe; 689 } 690 691 /* Register for SPI Interrupt */ 692 ret = devm_request_irq(dev, irq, fsl_espi_irq, 0, "fsl_espi", espi); 693 if (ret) 694 goto err_probe; 695 696 fsl_espi_init_regs(dev, true); 697 698 pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT); 699 pm_runtime_use_autosuspend(dev); 700 pm_runtime_set_active(dev); 701 pm_runtime_enable(dev); 702 pm_runtime_get_sync(dev); 703 704 ret = devm_spi_register_master(dev, master); 705 if (ret < 0) 706 goto err_pm; 707 708 dev_info(dev, "at 0x%p (irq = %u)\n", espi->reg_base, irq); 709 710 pm_runtime_mark_last_busy(dev); 711 pm_runtime_put_autosuspend(dev); 712 713 return 0; 714 715 err_pm: 716 pm_runtime_put_noidle(dev); 717 pm_runtime_disable(dev); 718 pm_runtime_set_suspended(dev); 719 err_probe: 720 spi_master_put(master); 721 return ret; 722 } 723 724 static int of_fsl_espi_get_chipselects(struct device *dev) 725 { 726 struct device_node *np = dev->of_node; 727 u32 num_cs; 728 int ret; 729 730 ret = of_property_read_u32(np, "fsl,espi-num-chipselects", &num_cs); 731 if (ret) { 732 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n"); 733 return 0; 734 } 735 736 return num_cs; 737 } 738 739 static int of_fsl_espi_probe(struct platform_device *ofdev) 740 { 741 struct device *dev = &ofdev->dev; 742 struct device_node *np = ofdev->dev.of_node; 743 struct resource mem; 744 unsigned int irq, num_cs; 745 int ret; 746 747 if (of_property_read_bool(np, "mode")) { 748 dev_err(dev, "mode property is not supported on ESPI!\n"); 749 return -EINVAL; 750 } 751 752 num_cs = of_fsl_espi_get_chipselects(dev); 753 if (!num_cs) 754 return -EINVAL; 755 756 ret = of_address_to_resource(np, 0, &mem); 757 if (ret) 758 return ret; 759 760 irq = irq_of_parse_and_map(np, 0); 761 if (!irq) 762 return -EINVAL; 763 764 return fsl_espi_probe(dev, &mem, irq, num_cs); 765 } 766 767 static int of_fsl_espi_remove(struct platform_device *dev) 768 { 769 pm_runtime_disable(&dev->dev); 770 771 return 0; 772 } 773 774 #ifdef CONFIG_PM_SLEEP 775 static int of_fsl_espi_suspend(struct device *dev) 776 { 777 struct spi_master *master = dev_get_drvdata(dev); 778 int ret; 779 780 ret = spi_master_suspend(master); 781 if (ret) { 782 dev_warn(dev, "cannot suspend master\n"); 783 return ret; 784 } 785 786 ret = pm_runtime_force_suspend(dev); 787 if (ret < 0) 788 return ret; 789 790 return 0; 791 } 792 793 static int of_fsl_espi_resume(struct device *dev) 794 { 795 struct spi_master *master = dev_get_drvdata(dev); 796 int ret; 797 798 fsl_espi_init_regs(dev, false); 799 800 ret = pm_runtime_force_resume(dev); 801 if (ret < 0) 802 return ret; 803 804 return spi_master_resume(master); 805 } 806 #endif /* CONFIG_PM_SLEEP */ 807 808 static const struct dev_pm_ops espi_pm = { 809 SET_RUNTIME_PM_OPS(fsl_espi_runtime_suspend, 810 fsl_espi_runtime_resume, NULL) 811 SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume) 812 }; 813 814 static const struct of_device_id of_fsl_espi_match[] = { 815 { .compatible = "fsl,mpc8536-espi" }, 816 {} 817 }; 818 MODULE_DEVICE_TABLE(of, of_fsl_espi_match); 819 820 static struct platform_driver fsl_espi_driver = { 821 .driver = { 822 .name = "fsl_espi", 823 .of_match_table = of_fsl_espi_match, 824 .pm = &espi_pm, 825 }, 826 .probe = of_fsl_espi_probe, 827 .remove = of_fsl_espi_remove, 828 }; 829 module_platform_driver(fsl_espi_driver); 830 831 MODULE_AUTHOR("Mingkai Hu"); 832 MODULE_DESCRIPTION("Enhanced Freescale SPI Driver"); 833 MODULE_LICENSE("GPL"); 834