1 /* 2 * drivers/spi/spi-fsl-dspi.c 3 * 4 * Copyright 2013 Freescale Semiconductor, Inc. 5 * 6 * Freescale DSPI driver 7 * This file contains a driver for the Freescale DSPI 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 */ 15 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/err.h> 19 #include <linux/errno.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/kernel.h> 23 #include <linux/math64.h> 24 #include <linux/module.h> 25 #include <linux/of.h> 26 #include <linux/of_device.h> 27 #include <linux/pinctrl/consumer.h> 28 #include <linux/platform_device.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/regmap.h> 31 #include <linux/sched.h> 32 #include <linux/spi/spi.h> 33 #include <linux/spi/spi_bitbang.h> 34 #include <linux/time.h> 35 36 #define DRIVER_NAME "fsl-dspi" 37 38 #define TRAN_STATE_RX_VOID 0x01 39 #define TRAN_STATE_TX_VOID 0x02 40 #define TRAN_STATE_WORD_ODD_NUM 0x04 41 42 #define DSPI_FIFO_SIZE 4 43 44 #define SPI_MCR 0x00 45 #define SPI_MCR_MASTER (1 << 31) 46 #define SPI_MCR_PCSIS (0x3F << 16) 47 #define SPI_MCR_CLR_TXF (1 << 11) 48 #define SPI_MCR_CLR_RXF (1 << 10) 49 50 #define SPI_TCR 0x08 51 #define SPI_TCR_GET_TCNT(x) (((x) & 0xffff0000) >> 16) 52 53 #define SPI_CTAR(x) (0x0c + (((x) & 0x3) * 4)) 54 #define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27) 55 #define SPI_CTAR_CPOL(x) ((x) << 26) 56 #define SPI_CTAR_CPHA(x) ((x) << 25) 57 #define SPI_CTAR_LSBFE(x) ((x) << 24) 58 #define SPI_CTAR_PCSSCK(x) (((x) & 0x00000003) << 22) 59 #define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20) 60 #define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18) 61 #define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16) 62 #define SPI_CTAR_CSSCK(x) (((x) & 0x0000000f) << 12) 63 #define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8) 64 #define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4) 65 #define SPI_CTAR_BR(x) ((x) & 0x0000000f) 66 #define SPI_CTAR_SCALE_BITS 0xf 67 68 #define SPI_CTAR0_SLAVE 0x0c 69 70 #define SPI_SR 0x2c 71 #define SPI_SR_EOQF 0x10000000 72 #define SPI_SR_TCFQF 0x80000000 73 74 #define SPI_RSER 0x30 75 #define SPI_RSER_EOQFE 0x10000000 76 #define SPI_RSER_TCFQE 0x80000000 77 78 #define SPI_PUSHR 0x34 79 #define SPI_PUSHR_CONT (1 << 31) 80 #define SPI_PUSHR_CTAS(x) (((x) & 0x00000003) << 28) 81 #define SPI_PUSHR_EOQ (1 << 27) 82 #define SPI_PUSHR_CTCNT (1 << 26) 83 #define SPI_PUSHR_PCS(x) (((1 << x) & 0x0000003f) << 16) 84 #define SPI_PUSHR_TXDATA(x) ((x) & 0x0000ffff) 85 86 #define SPI_PUSHR_SLAVE 0x34 87 88 #define SPI_POPR 0x38 89 #define SPI_POPR_RXDATA(x) ((x) & 0x0000ffff) 90 91 #define SPI_TXFR0 0x3c 92 #define SPI_TXFR1 0x40 93 #define SPI_TXFR2 0x44 94 #define SPI_TXFR3 0x48 95 #define SPI_RXFR0 0x7c 96 #define SPI_RXFR1 0x80 97 #define SPI_RXFR2 0x84 98 #define SPI_RXFR3 0x88 99 100 #define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1) 101 #define SPI_FRAME_BITS_MASK SPI_CTAR_FMSZ(0xf) 102 #define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf) 103 #define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7) 104 105 #define SPI_CS_INIT 0x01 106 #define SPI_CS_ASSERT 0x02 107 #define SPI_CS_DROP 0x04 108 109 #define SPI_TCR_TCNT_MAX 0x10000 110 111 struct chip_data { 112 u32 mcr_val; 113 u32 ctar_val; 114 u16 void_write_data; 115 }; 116 117 enum dspi_trans_mode { 118 DSPI_EOQ_MODE = 0, 119 DSPI_TCFQ_MODE, 120 }; 121 122 struct fsl_dspi_devtype_data { 123 enum dspi_trans_mode trans_mode; 124 u8 max_clock_factor; 125 }; 126 127 static const struct fsl_dspi_devtype_data vf610_data = { 128 .trans_mode = DSPI_EOQ_MODE, 129 .max_clock_factor = 2, 130 }; 131 132 static const struct fsl_dspi_devtype_data ls1021a_v1_data = { 133 .trans_mode = DSPI_TCFQ_MODE, 134 .max_clock_factor = 8, 135 }; 136 137 static const struct fsl_dspi_devtype_data ls2085a_data = { 138 .trans_mode = DSPI_TCFQ_MODE, 139 .max_clock_factor = 8, 140 }; 141 142 struct fsl_dspi { 143 struct spi_master *master; 144 struct platform_device *pdev; 145 146 struct regmap *regmap; 147 int irq; 148 struct clk *clk; 149 150 struct spi_transfer *cur_transfer; 151 struct spi_message *cur_msg; 152 struct chip_data *cur_chip; 153 size_t len; 154 void *tx; 155 void *tx_end; 156 void *rx; 157 void *rx_end; 158 char dataflags; 159 u8 cs; 160 u16 void_write_data; 161 u32 cs_change; 162 struct fsl_dspi_devtype_data *devtype_data; 163 164 wait_queue_head_t waitq; 165 u32 waitflags; 166 167 u32 spi_tcnt; 168 }; 169 170 static inline int is_double_byte_mode(struct fsl_dspi *dspi) 171 { 172 unsigned int val; 173 174 regmap_read(dspi->regmap, SPI_CTAR(0), &val); 175 176 return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1; 177 } 178 179 static void hz_to_spi_baud(char *pbr, char *br, int speed_hz, 180 unsigned long clkrate) 181 { 182 /* Valid baud rate pre-scaler values */ 183 int pbr_tbl[4] = {2, 3, 5, 7}; 184 int brs[16] = { 2, 4, 6, 8, 185 16, 32, 64, 128, 186 256, 512, 1024, 2048, 187 4096, 8192, 16384, 32768 }; 188 int scale_needed, scale, minscale = INT_MAX; 189 int i, j; 190 191 scale_needed = clkrate / speed_hz; 192 if (clkrate % speed_hz) 193 scale_needed++; 194 195 for (i = 0; i < ARRAY_SIZE(brs); i++) 196 for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) { 197 scale = brs[i] * pbr_tbl[j]; 198 if (scale >= scale_needed) { 199 if (scale < minscale) { 200 minscale = scale; 201 *br = i; 202 *pbr = j; 203 } 204 break; 205 } 206 } 207 208 if (minscale == INT_MAX) { 209 pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n", 210 speed_hz, clkrate); 211 *pbr = ARRAY_SIZE(pbr_tbl) - 1; 212 *br = ARRAY_SIZE(brs) - 1; 213 } 214 } 215 216 static void ns_delay_scale(char *psc, char *sc, int delay_ns, 217 unsigned long clkrate) 218 { 219 int pscale_tbl[4] = {1, 3, 5, 7}; 220 int scale_needed, scale, minscale = INT_MAX; 221 int i, j; 222 u32 remainder; 223 224 scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC, 225 &remainder); 226 if (remainder) 227 scale_needed++; 228 229 for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++) 230 for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) { 231 scale = pscale_tbl[i] * (2 << j); 232 if (scale >= scale_needed) { 233 if (scale < minscale) { 234 minscale = scale; 235 *psc = i; 236 *sc = j; 237 } 238 break; 239 } 240 } 241 242 if (minscale == INT_MAX) { 243 pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value", 244 delay_ns, clkrate); 245 *psc = ARRAY_SIZE(pscale_tbl) - 1; 246 *sc = SPI_CTAR_SCALE_BITS; 247 } 248 } 249 250 static u32 dspi_data_to_pushr(struct fsl_dspi *dspi, int tx_word) 251 { 252 u16 d16; 253 254 if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) 255 d16 = tx_word ? *(u16 *)dspi->tx : *(u8 *)dspi->tx; 256 else 257 d16 = dspi->void_write_data; 258 259 dspi->tx += tx_word + 1; 260 dspi->len -= tx_word + 1; 261 262 return SPI_PUSHR_TXDATA(d16) | 263 SPI_PUSHR_PCS(dspi->cs) | 264 SPI_PUSHR_CTAS(0) | 265 SPI_PUSHR_CONT; 266 } 267 268 static void dspi_data_from_popr(struct fsl_dspi *dspi, int rx_word) 269 { 270 u16 d; 271 unsigned int val; 272 273 regmap_read(dspi->regmap, SPI_POPR, &val); 274 d = SPI_POPR_RXDATA(val); 275 276 if (!(dspi->dataflags & TRAN_STATE_RX_VOID)) 277 rx_word ? (*(u16 *)dspi->rx = d) : (*(u8 *)dspi->rx = d); 278 279 dspi->rx += rx_word + 1; 280 } 281 282 static int dspi_eoq_write(struct fsl_dspi *dspi) 283 { 284 int tx_count = 0; 285 int tx_word; 286 u32 dspi_pushr = 0; 287 288 tx_word = is_double_byte_mode(dspi); 289 290 while (dspi->len && (tx_count < DSPI_FIFO_SIZE)) { 291 /* If we are in word mode, only have a single byte to transfer 292 * switch to byte mode temporarily. Will switch back at the 293 * end of the transfer. 294 */ 295 if (tx_word && (dspi->len == 1)) { 296 dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM; 297 regmap_update_bits(dspi->regmap, SPI_CTAR(0), 298 SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8)); 299 tx_word = 0; 300 } 301 302 dspi_pushr = dspi_data_to_pushr(dspi, tx_word); 303 304 if (dspi->len == 0 || tx_count == DSPI_FIFO_SIZE - 1) { 305 /* last transfer in the transfer */ 306 dspi_pushr |= SPI_PUSHR_EOQ; 307 if ((dspi->cs_change) && (!dspi->len)) 308 dspi_pushr &= ~SPI_PUSHR_CONT; 309 } else if (tx_word && (dspi->len == 1)) 310 dspi_pushr |= SPI_PUSHR_EOQ; 311 312 regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr); 313 314 tx_count++; 315 } 316 317 return tx_count * (tx_word + 1); 318 } 319 320 static int dspi_eoq_read(struct fsl_dspi *dspi) 321 { 322 int rx_count = 0; 323 int rx_word = is_double_byte_mode(dspi); 324 325 while ((dspi->rx < dspi->rx_end) 326 && (rx_count < DSPI_FIFO_SIZE)) { 327 if (rx_word && (dspi->rx_end - dspi->rx) == 1) 328 rx_word = 0; 329 330 dspi_data_from_popr(dspi, rx_word); 331 rx_count++; 332 } 333 334 return rx_count; 335 } 336 337 static int dspi_tcfq_write(struct fsl_dspi *dspi) 338 { 339 int tx_word; 340 u32 dspi_pushr = 0; 341 342 tx_word = is_double_byte_mode(dspi); 343 344 if (tx_word && (dspi->len == 1)) { 345 dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM; 346 regmap_update_bits(dspi->regmap, SPI_CTAR(0), 347 SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8)); 348 tx_word = 0; 349 } 350 351 dspi_pushr = dspi_data_to_pushr(dspi, tx_word); 352 353 if ((dspi->cs_change) && (!dspi->len)) 354 dspi_pushr &= ~SPI_PUSHR_CONT; 355 356 regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr); 357 358 return tx_word + 1; 359 } 360 361 static void dspi_tcfq_read(struct fsl_dspi *dspi) 362 { 363 int rx_word = is_double_byte_mode(dspi); 364 365 if (rx_word && (dspi->rx_end - dspi->rx) == 1) 366 rx_word = 0; 367 368 dspi_data_from_popr(dspi, rx_word); 369 } 370 371 static int dspi_transfer_one_message(struct spi_master *master, 372 struct spi_message *message) 373 { 374 struct fsl_dspi *dspi = spi_master_get_devdata(master); 375 struct spi_device *spi = message->spi; 376 struct spi_transfer *transfer; 377 int status = 0; 378 enum dspi_trans_mode trans_mode; 379 u32 spi_tcr; 380 381 regmap_read(dspi->regmap, SPI_TCR, &spi_tcr); 382 dspi->spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr); 383 384 message->actual_length = 0; 385 386 list_for_each_entry(transfer, &message->transfers, transfer_list) { 387 dspi->cur_transfer = transfer; 388 dspi->cur_msg = message; 389 dspi->cur_chip = spi_get_ctldata(spi); 390 dspi->cs = spi->chip_select; 391 dspi->cs_change = 0; 392 if (list_is_last(&dspi->cur_transfer->transfer_list, 393 &dspi->cur_msg->transfers) || transfer->cs_change) 394 dspi->cs_change = 1; 395 dspi->void_write_data = dspi->cur_chip->void_write_data; 396 397 dspi->dataflags = 0; 398 dspi->tx = (void *)transfer->tx_buf; 399 dspi->tx_end = dspi->tx + transfer->len; 400 dspi->rx = transfer->rx_buf; 401 dspi->rx_end = dspi->rx + transfer->len; 402 dspi->len = transfer->len; 403 404 if (!dspi->rx) 405 dspi->dataflags |= TRAN_STATE_RX_VOID; 406 407 if (!dspi->tx) 408 dspi->dataflags |= TRAN_STATE_TX_VOID; 409 410 regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val); 411 regmap_update_bits(dspi->regmap, SPI_MCR, 412 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF, 413 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF); 414 regmap_write(dspi->regmap, SPI_CTAR(0), 415 dspi->cur_chip->ctar_val); 416 417 trans_mode = dspi->devtype_data->trans_mode; 418 switch (trans_mode) { 419 case DSPI_EOQ_MODE: 420 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE); 421 dspi_eoq_write(dspi); 422 break; 423 case DSPI_TCFQ_MODE: 424 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TCFQE); 425 dspi_tcfq_write(dspi); 426 break; 427 default: 428 dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n", 429 trans_mode); 430 status = -EINVAL; 431 goto out; 432 } 433 434 if (wait_event_interruptible(dspi->waitq, dspi->waitflags)) 435 dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n"); 436 dspi->waitflags = 0; 437 438 if (transfer->delay_usecs) 439 udelay(transfer->delay_usecs); 440 } 441 442 out: 443 message->status = status; 444 spi_finalize_current_message(master); 445 446 return status; 447 } 448 449 static int dspi_setup(struct spi_device *spi) 450 { 451 struct chip_data *chip; 452 struct fsl_dspi *dspi = spi_master_get_devdata(spi->master); 453 u32 cs_sck_delay = 0, sck_cs_delay = 0; 454 unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0; 455 unsigned char pasc = 0, asc = 0, fmsz = 0; 456 unsigned long clkrate; 457 458 if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) { 459 fmsz = spi->bits_per_word - 1; 460 } else { 461 pr_err("Invalid wordsize\n"); 462 return -ENODEV; 463 } 464 465 /* Only alloc on first setup */ 466 chip = spi_get_ctldata(spi); 467 if (chip == NULL) { 468 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 469 if (!chip) 470 return -ENOMEM; 471 } 472 473 of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay", 474 &cs_sck_delay); 475 476 of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay", 477 &sck_cs_delay); 478 479 chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS | 480 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF; 481 482 chip->void_write_data = 0; 483 484 clkrate = clk_get_rate(dspi->clk); 485 hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate); 486 487 /* Set PCS to SCK delay scale values */ 488 ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate); 489 490 /* Set After SCK delay scale values */ 491 ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate); 492 493 chip->ctar_val = SPI_CTAR_FMSZ(fmsz) 494 | SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0) 495 | SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0) 496 | SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0) 497 | SPI_CTAR_PCSSCK(pcssck) 498 | SPI_CTAR_CSSCK(cssck) 499 | SPI_CTAR_PASC(pasc) 500 | SPI_CTAR_ASC(asc) 501 | SPI_CTAR_PBR(pbr) 502 | SPI_CTAR_BR(br); 503 504 spi_set_ctldata(spi, chip); 505 506 return 0; 507 } 508 509 static void dspi_cleanup(struct spi_device *spi) 510 { 511 struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi); 512 513 dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n", 514 spi->master->bus_num, spi->chip_select); 515 516 kfree(chip); 517 } 518 519 static irqreturn_t dspi_interrupt(int irq, void *dev_id) 520 { 521 struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id; 522 struct spi_message *msg = dspi->cur_msg; 523 enum dspi_trans_mode trans_mode; 524 u32 spi_sr, spi_tcr; 525 u32 spi_tcnt, tcnt_diff; 526 int tx_word; 527 528 regmap_read(dspi->regmap, SPI_SR, &spi_sr); 529 regmap_write(dspi->regmap, SPI_SR, spi_sr); 530 531 532 if (spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF)) { 533 tx_word = is_double_byte_mode(dspi); 534 535 regmap_read(dspi->regmap, SPI_TCR, &spi_tcr); 536 spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr); 537 /* 538 * The width of SPI Transfer Counter in SPI_TCR is 16bits, 539 * so the max couner is 65535. When the counter reach 65535, 540 * it will wrap around, counter reset to zero. 541 * spi_tcnt my be less than dspi->spi_tcnt, it means the 542 * counter already wrapped around. 543 * SPI Transfer Counter is a counter of transmitted frames. 544 * The size of frame maybe two bytes. 545 */ 546 tcnt_diff = ((spi_tcnt + SPI_TCR_TCNT_MAX) - dspi->spi_tcnt) 547 % SPI_TCR_TCNT_MAX; 548 tcnt_diff *= (tx_word + 1); 549 if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM) 550 tcnt_diff--; 551 552 msg->actual_length += tcnt_diff; 553 554 dspi->spi_tcnt = spi_tcnt; 555 556 trans_mode = dspi->devtype_data->trans_mode; 557 switch (trans_mode) { 558 case DSPI_EOQ_MODE: 559 dspi_eoq_read(dspi); 560 break; 561 case DSPI_TCFQ_MODE: 562 dspi_tcfq_read(dspi); 563 break; 564 default: 565 dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n", 566 trans_mode); 567 return IRQ_HANDLED; 568 } 569 570 if (!dspi->len) { 571 if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM) { 572 regmap_update_bits(dspi->regmap, 573 SPI_CTAR(0), 574 SPI_FRAME_BITS_MASK, 575 SPI_FRAME_BITS(16)); 576 dspi->dataflags &= ~TRAN_STATE_WORD_ODD_NUM; 577 } 578 579 dspi->waitflags = 1; 580 wake_up_interruptible(&dspi->waitq); 581 } else { 582 switch (trans_mode) { 583 case DSPI_EOQ_MODE: 584 dspi_eoq_write(dspi); 585 break; 586 case DSPI_TCFQ_MODE: 587 dspi_tcfq_write(dspi); 588 break; 589 default: 590 dev_err(&dspi->pdev->dev, 591 "unsupported trans_mode %u\n", 592 trans_mode); 593 } 594 } 595 } 596 597 return IRQ_HANDLED; 598 } 599 600 static const struct of_device_id fsl_dspi_dt_ids[] = { 601 { .compatible = "fsl,vf610-dspi", .data = (void *)&vf610_data, }, 602 { .compatible = "fsl,ls1021a-v1.0-dspi", 603 .data = (void *)&ls1021a_v1_data, }, 604 { .compatible = "fsl,ls2085a-dspi", .data = (void *)&ls2085a_data, }, 605 { /* sentinel */ } 606 }; 607 MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids); 608 609 #ifdef CONFIG_PM_SLEEP 610 static int dspi_suspend(struct device *dev) 611 { 612 struct spi_master *master = dev_get_drvdata(dev); 613 struct fsl_dspi *dspi = spi_master_get_devdata(master); 614 615 spi_master_suspend(master); 616 clk_disable_unprepare(dspi->clk); 617 618 pinctrl_pm_select_sleep_state(dev); 619 620 return 0; 621 } 622 623 static int dspi_resume(struct device *dev) 624 { 625 struct spi_master *master = dev_get_drvdata(dev); 626 struct fsl_dspi *dspi = spi_master_get_devdata(master); 627 628 pinctrl_pm_select_default_state(dev); 629 630 clk_prepare_enable(dspi->clk); 631 spi_master_resume(master); 632 633 return 0; 634 } 635 #endif /* CONFIG_PM_SLEEP */ 636 637 static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume); 638 639 static const struct regmap_config dspi_regmap_config = { 640 .reg_bits = 32, 641 .val_bits = 32, 642 .reg_stride = 4, 643 .max_register = 0x88, 644 }; 645 646 static int dspi_probe(struct platform_device *pdev) 647 { 648 struct device_node *np = pdev->dev.of_node; 649 struct spi_master *master; 650 struct fsl_dspi *dspi; 651 struct resource *res; 652 void __iomem *base; 653 int ret = 0, cs_num, bus_num; 654 const struct of_device_id *of_id = 655 of_match_device(fsl_dspi_dt_ids, &pdev->dev); 656 657 master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi)); 658 if (!master) 659 return -ENOMEM; 660 661 dspi = spi_master_get_devdata(master); 662 dspi->pdev = pdev; 663 dspi->master = master; 664 665 master->transfer = NULL; 666 master->setup = dspi_setup; 667 master->transfer_one_message = dspi_transfer_one_message; 668 master->dev.of_node = pdev->dev.of_node; 669 670 master->cleanup = dspi_cleanup; 671 master->mode_bits = SPI_CPOL | SPI_CPHA; 672 master->bits_per_word_mask = SPI_BPW_MASK(4) | SPI_BPW_MASK(8) | 673 SPI_BPW_MASK(16); 674 675 ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num); 676 if (ret < 0) { 677 dev_err(&pdev->dev, "can't get spi-num-chipselects\n"); 678 goto out_master_put; 679 } 680 master->num_chipselect = cs_num; 681 682 ret = of_property_read_u32(np, "bus-num", &bus_num); 683 if (ret < 0) { 684 dev_err(&pdev->dev, "can't get bus-num\n"); 685 goto out_master_put; 686 } 687 master->bus_num = bus_num; 688 689 dspi->devtype_data = (struct fsl_dspi_devtype_data *)of_id->data; 690 if (!dspi->devtype_data) { 691 dev_err(&pdev->dev, "can't get devtype_data\n"); 692 ret = -EFAULT; 693 goto out_master_put; 694 } 695 696 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 697 base = devm_ioremap_resource(&pdev->dev, res); 698 if (IS_ERR(base)) { 699 ret = PTR_ERR(base); 700 goto out_master_put; 701 } 702 703 dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base, 704 &dspi_regmap_config); 705 if (IS_ERR(dspi->regmap)) { 706 dev_err(&pdev->dev, "failed to init regmap: %ld\n", 707 PTR_ERR(dspi->regmap)); 708 return PTR_ERR(dspi->regmap); 709 } 710 711 dspi->irq = platform_get_irq(pdev, 0); 712 if (dspi->irq < 0) { 713 dev_err(&pdev->dev, "can't get platform irq\n"); 714 ret = dspi->irq; 715 goto out_master_put; 716 } 717 718 ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0, 719 pdev->name, dspi); 720 if (ret < 0) { 721 dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n"); 722 goto out_master_put; 723 } 724 725 dspi->clk = devm_clk_get(&pdev->dev, "dspi"); 726 if (IS_ERR(dspi->clk)) { 727 ret = PTR_ERR(dspi->clk); 728 dev_err(&pdev->dev, "unable to get clock\n"); 729 goto out_master_put; 730 } 731 clk_prepare_enable(dspi->clk); 732 733 master->max_speed_hz = 734 clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor; 735 736 init_waitqueue_head(&dspi->waitq); 737 platform_set_drvdata(pdev, master); 738 739 ret = spi_register_master(master); 740 if (ret != 0) { 741 dev_err(&pdev->dev, "Problem registering DSPI master\n"); 742 goto out_clk_put; 743 } 744 745 return ret; 746 747 out_clk_put: 748 clk_disable_unprepare(dspi->clk); 749 out_master_put: 750 spi_master_put(master); 751 752 return ret; 753 } 754 755 static int dspi_remove(struct platform_device *pdev) 756 { 757 struct spi_master *master = platform_get_drvdata(pdev); 758 struct fsl_dspi *dspi = spi_master_get_devdata(master); 759 760 /* Disconnect from the SPI framework */ 761 clk_disable_unprepare(dspi->clk); 762 spi_unregister_master(dspi->master); 763 spi_master_put(dspi->master); 764 765 return 0; 766 } 767 768 static struct platform_driver fsl_dspi_driver = { 769 .driver.name = DRIVER_NAME, 770 .driver.of_match_table = fsl_dspi_dt_ids, 771 .driver.owner = THIS_MODULE, 772 .driver.pm = &dspi_pm, 773 .probe = dspi_probe, 774 .remove = dspi_remove, 775 }; 776 module_platform_driver(fsl_dspi_driver); 777 778 MODULE_DESCRIPTION("Freescale DSPI Controller Driver"); 779 MODULE_LICENSE("GPL"); 780 MODULE_ALIAS("platform:" DRIVER_NAME); 781