1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Copyright 2013 Freescale Semiconductor, Inc. 4 // Copyright 2020 NXP 5 // 6 // Freescale DSPI driver 7 // This file contains a driver for the Freescale DSPI 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dmaengine.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/interrupt.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/of_device.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/regmap.h> 19 #include <linux/spi/spi.h> 20 #include <linux/spi/spi-fsl-dspi.h> 21 22 #define DRIVER_NAME "fsl-dspi" 23 24 #define SPI_MCR 0x00 25 #define SPI_MCR_MASTER BIT(31) 26 #define SPI_MCR_PCSIS(x) ((x) << 16) 27 #define SPI_MCR_CLR_TXF BIT(11) 28 #define SPI_MCR_CLR_RXF BIT(10) 29 #define SPI_MCR_XSPI BIT(3) 30 #define SPI_MCR_DIS_TXF BIT(13) 31 #define SPI_MCR_DIS_RXF BIT(12) 32 #define SPI_MCR_HALT BIT(0) 33 34 #define SPI_TCR 0x08 35 #define SPI_TCR_GET_TCNT(x) (((x) & GENMASK(31, 16)) >> 16) 36 37 #define SPI_CTAR(x) (0x0c + (((x) & GENMASK(1, 0)) * 4)) 38 #define SPI_CTAR_FMSZ(x) (((x) << 27) & GENMASK(30, 27)) 39 #define SPI_CTAR_CPOL BIT(26) 40 #define SPI_CTAR_CPHA BIT(25) 41 #define SPI_CTAR_LSBFE BIT(24) 42 #define SPI_CTAR_PCSSCK(x) (((x) << 22) & GENMASK(23, 22)) 43 #define SPI_CTAR_PASC(x) (((x) << 20) & GENMASK(21, 20)) 44 #define SPI_CTAR_PDT(x) (((x) << 18) & GENMASK(19, 18)) 45 #define SPI_CTAR_PBR(x) (((x) << 16) & GENMASK(17, 16)) 46 #define SPI_CTAR_CSSCK(x) (((x) << 12) & GENMASK(15, 12)) 47 #define SPI_CTAR_ASC(x) (((x) << 8) & GENMASK(11, 8)) 48 #define SPI_CTAR_DT(x) (((x) << 4) & GENMASK(7, 4)) 49 #define SPI_CTAR_BR(x) ((x) & GENMASK(3, 0)) 50 #define SPI_CTAR_SCALE_BITS 0xf 51 52 #define SPI_CTAR0_SLAVE 0x0c 53 54 #define SPI_SR 0x2c 55 #define SPI_SR_TCFQF BIT(31) 56 #define SPI_SR_EOQF BIT(28) 57 #define SPI_SR_TFUF BIT(27) 58 #define SPI_SR_TFFF BIT(25) 59 #define SPI_SR_CMDTCF BIT(23) 60 #define SPI_SR_SPEF BIT(21) 61 #define SPI_SR_RFOF BIT(19) 62 #define SPI_SR_TFIWF BIT(18) 63 #define SPI_SR_RFDF BIT(17) 64 #define SPI_SR_CMDFFF BIT(16) 65 #define SPI_SR_CLEAR (SPI_SR_TCFQF | SPI_SR_EOQF | \ 66 SPI_SR_TFUF | SPI_SR_TFFF | \ 67 SPI_SR_CMDTCF | SPI_SR_SPEF | \ 68 SPI_SR_RFOF | SPI_SR_TFIWF | \ 69 SPI_SR_RFDF | SPI_SR_CMDFFF) 70 71 #define SPI_RSER_TFFFE BIT(25) 72 #define SPI_RSER_TFFFD BIT(24) 73 #define SPI_RSER_RFDFE BIT(17) 74 #define SPI_RSER_RFDFD BIT(16) 75 76 #define SPI_RSER 0x30 77 #define SPI_RSER_TCFQE BIT(31) 78 #define SPI_RSER_EOQFE BIT(28) 79 #define SPI_RSER_CMDTCFE BIT(23) 80 81 #define SPI_PUSHR 0x34 82 #define SPI_PUSHR_CMD_CONT BIT(15) 83 #define SPI_PUSHR_CMD_CTAS(x) (((x) << 12 & GENMASK(14, 12))) 84 #define SPI_PUSHR_CMD_EOQ BIT(11) 85 #define SPI_PUSHR_CMD_CTCNT BIT(10) 86 #define SPI_PUSHR_CMD_PCS(x) (BIT(x) & GENMASK(5, 0)) 87 88 #define SPI_PUSHR_SLAVE 0x34 89 90 #define SPI_POPR 0x38 91 92 #define SPI_TXFR0 0x3c 93 #define SPI_TXFR1 0x40 94 #define SPI_TXFR2 0x44 95 #define SPI_TXFR3 0x48 96 #define SPI_RXFR0 0x7c 97 #define SPI_RXFR1 0x80 98 #define SPI_RXFR2 0x84 99 #define SPI_RXFR3 0x88 100 101 #define SPI_CTARE(x) (0x11c + (((x) & GENMASK(1, 0)) * 4)) 102 #define SPI_CTARE_FMSZE(x) (((x) & 0x1) << 16) 103 #define SPI_CTARE_DTCP(x) ((x) & 0x7ff) 104 105 #define SPI_SREX 0x13c 106 107 #define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1) 108 #define SPI_FRAME_EBITS(bits) SPI_CTARE_FMSZE(((bits) - 1) >> 4) 109 110 #define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000) 111 112 struct chip_data { 113 u32 ctar_val; 114 }; 115 116 enum dspi_trans_mode { 117 DSPI_EOQ_MODE = 0, 118 DSPI_XSPI_MODE, 119 DSPI_DMA_MODE, 120 }; 121 122 struct fsl_dspi_devtype_data { 123 enum dspi_trans_mode trans_mode; 124 u8 max_clock_factor; 125 int fifo_size; 126 }; 127 128 enum { 129 LS1021A, 130 LS1012A, 131 LS1028A, 132 LS1043A, 133 LS1046A, 134 LS2080A, 135 LS2085A, 136 LX2160A, 137 MCF5441X, 138 VF610, 139 }; 140 141 static const struct fsl_dspi_devtype_data devtype_data[] = { 142 [VF610] = { 143 .trans_mode = DSPI_DMA_MODE, 144 .max_clock_factor = 2, 145 .fifo_size = 4, 146 }, 147 [LS1021A] = { 148 /* Has A-011218 DMA erratum */ 149 .trans_mode = DSPI_XSPI_MODE, 150 .max_clock_factor = 8, 151 .fifo_size = 4, 152 }, 153 [LS1012A] = { 154 /* Has A-011218 DMA erratum */ 155 .trans_mode = DSPI_XSPI_MODE, 156 .max_clock_factor = 8, 157 .fifo_size = 16, 158 }, 159 [LS1028A] = { 160 .trans_mode = DSPI_XSPI_MODE, 161 .max_clock_factor = 8, 162 .fifo_size = 4, 163 }, 164 [LS1043A] = { 165 /* Has A-011218 DMA erratum */ 166 .trans_mode = DSPI_XSPI_MODE, 167 .max_clock_factor = 8, 168 .fifo_size = 16, 169 }, 170 [LS1046A] = { 171 /* Has A-011218 DMA erratum */ 172 .trans_mode = DSPI_XSPI_MODE, 173 .max_clock_factor = 8, 174 .fifo_size = 16, 175 }, 176 [LS2080A] = { 177 .trans_mode = DSPI_DMA_MODE, 178 .max_clock_factor = 8, 179 .fifo_size = 4, 180 }, 181 [LS2085A] = { 182 .trans_mode = DSPI_DMA_MODE, 183 .max_clock_factor = 8, 184 .fifo_size = 4, 185 }, 186 [LX2160A] = { 187 .trans_mode = DSPI_DMA_MODE, 188 .max_clock_factor = 8, 189 .fifo_size = 4, 190 }, 191 [MCF5441X] = { 192 .trans_mode = DSPI_EOQ_MODE, 193 .max_clock_factor = 8, 194 .fifo_size = 16, 195 }, 196 }; 197 198 struct fsl_dspi_dma { 199 u32 *tx_dma_buf; 200 struct dma_chan *chan_tx; 201 dma_addr_t tx_dma_phys; 202 struct completion cmd_tx_complete; 203 struct dma_async_tx_descriptor *tx_desc; 204 205 u32 *rx_dma_buf; 206 struct dma_chan *chan_rx; 207 dma_addr_t rx_dma_phys; 208 struct completion cmd_rx_complete; 209 struct dma_async_tx_descriptor *rx_desc; 210 }; 211 212 struct fsl_dspi { 213 struct spi_controller *ctlr; 214 struct platform_device *pdev; 215 216 struct regmap *regmap; 217 struct regmap *regmap_pushr; 218 int irq; 219 struct clk *clk; 220 221 struct spi_transfer *cur_transfer; 222 struct spi_message *cur_msg; 223 struct chip_data *cur_chip; 224 size_t progress; 225 size_t len; 226 const void *tx; 227 void *rx; 228 u16 tx_cmd; 229 const struct fsl_dspi_devtype_data *devtype_data; 230 231 struct completion xfer_done; 232 233 struct fsl_dspi_dma *dma; 234 235 int oper_word_size; 236 int oper_bits_per_word; 237 238 int words_in_flight; 239 240 /* 241 * Offsets for CMD and TXDATA within SPI_PUSHR when accessed 242 * individually (in XSPI mode) 243 */ 244 int pushr_cmd; 245 int pushr_tx; 246 247 void (*host_to_dev)(struct fsl_dspi *dspi, u32 *txdata); 248 void (*dev_to_host)(struct fsl_dspi *dspi, u32 rxdata); 249 }; 250 251 static void dspi_native_host_to_dev(struct fsl_dspi *dspi, u32 *txdata) 252 { 253 switch (dspi->oper_word_size) { 254 case 1: 255 *txdata = *(u8 *)dspi->tx; 256 break; 257 case 2: 258 *txdata = *(u16 *)dspi->tx; 259 break; 260 case 4: 261 *txdata = *(u32 *)dspi->tx; 262 break; 263 } 264 dspi->tx += dspi->oper_word_size; 265 } 266 267 static void dspi_native_dev_to_host(struct fsl_dspi *dspi, u32 rxdata) 268 { 269 switch (dspi->oper_word_size) { 270 case 1: 271 *(u8 *)dspi->rx = rxdata; 272 break; 273 case 2: 274 *(u16 *)dspi->rx = rxdata; 275 break; 276 case 4: 277 *(u32 *)dspi->rx = rxdata; 278 break; 279 } 280 dspi->rx += dspi->oper_word_size; 281 } 282 283 static void dspi_8on32_host_to_dev(struct fsl_dspi *dspi, u32 *txdata) 284 { 285 *txdata = cpu_to_be32(*(u32 *)dspi->tx); 286 dspi->tx += sizeof(u32); 287 } 288 289 static void dspi_8on32_dev_to_host(struct fsl_dspi *dspi, u32 rxdata) 290 { 291 *(u32 *)dspi->rx = be32_to_cpu(rxdata); 292 dspi->rx += sizeof(u32); 293 } 294 295 static void dspi_8on16_host_to_dev(struct fsl_dspi *dspi, u32 *txdata) 296 { 297 *txdata = cpu_to_be16(*(u16 *)dspi->tx); 298 dspi->tx += sizeof(u16); 299 } 300 301 static void dspi_8on16_dev_to_host(struct fsl_dspi *dspi, u32 rxdata) 302 { 303 *(u16 *)dspi->rx = be16_to_cpu(rxdata); 304 dspi->rx += sizeof(u16); 305 } 306 307 static void dspi_16on32_host_to_dev(struct fsl_dspi *dspi, u32 *txdata) 308 { 309 u16 hi = *(u16 *)dspi->tx; 310 u16 lo = *(u16 *)(dspi->tx + 2); 311 312 *txdata = (u32)hi << 16 | lo; 313 dspi->tx += sizeof(u32); 314 } 315 316 static void dspi_16on32_dev_to_host(struct fsl_dspi *dspi, u32 rxdata) 317 { 318 u16 hi = rxdata & 0xffff; 319 u16 lo = rxdata >> 16; 320 321 *(u16 *)dspi->rx = lo; 322 *(u16 *)(dspi->rx + 2) = hi; 323 dspi->rx += sizeof(u32); 324 } 325 326 /* 327 * Pop one word from the TX buffer for pushing into the 328 * PUSHR register (TX FIFO) 329 */ 330 static u32 dspi_pop_tx(struct fsl_dspi *dspi) 331 { 332 u32 txdata = 0; 333 334 if (dspi->tx) 335 dspi->host_to_dev(dspi, &txdata); 336 dspi->len -= dspi->oper_word_size; 337 return txdata; 338 } 339 340 /* Prepare one TX FIFO entry (txdata plus cmd) */ 341 static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi) 342 { 343 u16 cmd = dspi->tx_cmd, data = dspi_pop_tx(dspi); 344 345 if (spi_controller_is_slave(dspi->ctlr)) 346 return data; 347 348 if (dspi->len > 0) 349 cmd |= SPI_PUSHR_CMD_CONT; 350 return cmd << 16 | data; 351 } 352 353 /* Push one word to the RX buffer from the POPR register (RX FIFO) */ 354 static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata) 355 { 356 if (!dspi->rx) 357 return; 358 dspi->dev_to_host(dspi, rxdata); 359 } 360 361 static void dspi_tx_dma_callback(void *arg) 362 { 363 struct fsl_dspi *dspi = arg; 364 struct fsl_dspi_dma *dma = dspi->dma; 365 366 complete(&dma->cmd_tx_complete); 367 } 368 369 static void dspi_rx_dma_callback(void *arg) 370 { 371 struct fsl_dspi *dspi = arg; 372 struct fsl_dspi_dma *dma = dspi->dma; 373 int i; 374 375 if (dspi->rx) { 376 for (i = 0; i < dspi->words_in_flight; i++) 377 dspi_push_rx(dspi, dspi->dma->rx_dma_buf[i]); 378 } 379 380 complete(&dma->cmd_rx_complete); 381 } 382 383 static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi) 384 { 385 struct device *dev = &dspi->pdev->dev; 386 struct fsl_dspi_dma *dma = dspi->dma; 387 int time_left; 388 int i; 389 390 for (i = 0; i < dspi->words_in_flight; i++) 391 dspi->dma->tx_dma_buf[i] = dspi_pop_tx_pushr(dspi); 392 393 dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx, 394 dma->tx_dma_phys, 395 dspi->words_in_flight * 396 DMA_SLAVE_BUSWIDTH_4_BYTES, 397 DMA_MEM_TO_DEV, 398 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 399 if (!dma->tx_desc) { 400 dev_err(dev, "Not able to get desc for DMA xfer\n"); 401 return -EIO; 402 } 403 404 dma->tx_desc->callback = dspi_tx_dma_callback; 405 dma->tx_desc->callback_param = dspi; 406 if (dma_submit_error(dmaengine_submit(dma->tx_desc))) { 407 dev_err(dev, "DMA submit failed\n"); 408 return -EINVAL; 409 } 410 411 dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx, 412 dma->rx_dma_phys, 413 dspi->words_in_flight * 414 DMA_SLAVE_BUSWIDTH_4_BYTES, 415 DMA_DEV_TO_MEM, 416 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 417 if (!dma->rx_desc) { 418 dev_err(dev, "Not able to get desc for DMA xfer\n"); 419 return -EIO; 420 } 421 422 dma->rx_desc->callback = dspi_rx_dma_callback; 423 dma->rx_desc->callback_param = dspi; 424 if (dma_submit_error(dmaengine_submit(dma->rx_desc))) { 425 dev_err(dev, "DMA submit failed\n"); 426 return -EINVAL; 427 } 428 429 reinit_completion(&dspi->dma->cmd_rx_complete); 430 reinit_completion(&dspi->dma->cmd_tx_complete); 431 432 dma_async_issue_pending(dma->chan_rx); 433 dma_async_issue_pending(dma->chan_tx); 434 435 if (spi_controller_is_slave(dspi->ctlr)) { 436 wait_for_completion_interruptible(&dspi->dma->cmd_rx_complete); 437 return 0; 438 } 439 440 time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete, 441 DMA_COMPLETION_TIMEOUT); 442 if (time_left == 0) { 443 dev_err(dev, "DMA tx timeout\n"); 444 dmaengine_terminate_all(dma->chan_tx); 445 dmaengine_terminate_all(dma->chan_rx); 446 return -ETIMEDOUT; 447 } 448 449 time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete, 450 DMA_COMPLETION_TIMEOUT); 451 if (time_left == 0) { 452 dev_err(dev, "DMA rx timeout\n"); 453 dmaengine_terminate_all(dma->chan_tx); 454 dmaengine_terminate_all(dma->chan_rx); 455 return -ETIMEDOUT; 456 } 457 458 return 0; 459 } 460 461 static void dspi_setup_accel(struct fsl_dspi *dspi); 462 463 static int dspi_dma_xfer(struct fsl_dspi *dspi) 464 { 465 struct spi_message *message = dspi->cur_msg; 466 struct device *dev = &dspi->pdev->dev; 467 int ret = 0; 468 469 /* 470 * dspi->len gets decremented by dspi_pop_tx_pushr in 471 * dspi_next_xfer_dma_submit 472 */ 473 while (dspi->len) { 474 /* Figure out operational bits-per-word for this chunk */ 475 dspi_setup_accel(dspi); 476 477 dspi->words_in_flight = dspi->len / dspi->oper_word_size; 478 if (dspi->words_in_flight > dspi->devtype_data->fifo_size) 479 dspi->words_in_flight = dspi->devtype_data->fifo_size; 480 481 message->actual_length += dspi->words_in_flight * 482 dspi->oper_word_size; 483 484 ret = dspi_next_xfer_dma_submit(dspi); 485 if (ret) { 486 dev_err(dev, "DMA transfer failed\n"); 487 break; 488 } 489 } 490 491 return ret; 492 } 493 494 static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr) 495 { 496 int dma_bufsize = dspi->devtype_data->fifo_size * 2; 497 struct device *dev = &dspi->pdev->dev; 498 struct dma_slave_config cfg; 499 struct fsl_dspi_dma *dma; 500 int ret; 501 502 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 503 if (!dma) 504 return -ENOMEM; 505 506 dma->chan_rx = dma_request_chan(dev, "rx"); 507 if (IS_ERR(dma->chan_rx)) { 508 dev_err(dev, "rx dma channel not available\n"); 509 ret = PTR_ERR(dma->chan_rx); 510 return ret; 511 } 512 513 dma->chan_tx = dma_request_chan(dev, "tx"); 514 if (IS_ERR(dma->chan_tx)) { 515 dev_err(dev, "tx dma channel not available\n"); 516 ret = PTR_ERR(dma->chan_tx); 517 goto err_tx_channel; 518 } 519 520 dma->tx_dma_buf = dma_alloc_coherent(dma->chan_tx->device->dev, 521 dma_bufsize, &dma->tx_dma_phys, 522 GFP_KERNEL); 523 if (!dma->tx_dma_buf) { 524 ret = -ENOMEM; 525 goto err_tx_dma_buf; 526 } 527 528 dma->rx_dma_buf = dma_alloc_coherent(dma->chan_rx->device->dev, 529 dma_bufsize, &dma->rx_dma_phys, 530 GFP_KERNEL); 531 if (!dma->rx_dma_buf) { 532 ret = -ENOMEM; 533 goto err_rx_dma_buf; 534 } 535 536 cfg.src_addr = phy_addr + SPI_POPR; 537 cfg.dst_addr = phy_addr + SPI_PUSHR; 538 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 539 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 540 cfg.src_maxburst = 1; 541 cfg.dst_maxburst = 1; 542 543 cfg.direction = DMA_DEV_TO_MEM; 544 ret = dmaengine_slave_config(dma->chan_rx, &cfg); 545 if (ret) { 546 dev_err(dev, "can't configure rx dma channel\n"); 547 ret = -EINVAL; 548 goto err_slave_config; 549 } 550 551 cfg.direction = DMA_MEM_TO_DEV; 552 ret = dmaengine_slave_config(dma->chan_tx, &cfg); 553 if (ret) { 554 dev_err(dev, "can't configure tx dma channel\n"); 555 ret = -EINVAL; 556 goto err_slave_config; 557 } 558 559 dspi->dma = dma; 560 init_completion(&dma->cmd_tx_complete); 561 init_completion(&dma->cmd_rx_complete); 562 563 return 0; 564 565 err_slave_config: 566 dma_free_coherent(dma->chan_rx->device->dev, 567 dma_bufsize, dma->rx_dma_buf, dma->rx_dma_phys); 568 err_rx_dma_buf: 569 dma_free_coherent(dma->chan_tx->device->dev, 570 dma_bufsize, dma->tx_dma_buf, dma->tx_dma_phys); 571 err_tx_dma_buf: 572 dma_release_channel(dma->chan_tx); 573 err_tx_channel: 574 dma_release_channel(dma->chan_rx); 575 576 devm_kfree(dev, dma); 577 dspi->dma = NULL; 578 579 return ret; 580 } 581 582 static void dspi_release_dma(struct fsl_dspi *dspi) 583 { 584 int dma_bufsize = dspi->devtype_data->fifo_size * 2; 585 struct fsl_dspi_dma *dma = dspi->dma; 586 587 if (!dma) 588 return; 589 590 if (dma->chan_tx) { 591 dma_free_coherent(dma->chan_tx->device->dev, dma_bufsize, 592 dma->tx_dma_buf, dma->tx_dma_phys); 593 dma_release_channel(dma->chan_tx); 594 } 595 596 if (dma->chan_rx) { 597 dma_free_coherent(dma->chan_rx->device->dev, dma_bufsize, 598 dma->rx_dma_buf, dma->rx_dma_phys); 599 dma_release_channel(dma->chan_rx); 600 } 601 } 602 603 static void hz_to_spi_baud(char *pbr, char *br, int speed_hz, 604 unsigned long clkrate) 605 { 606 /* Valid baud rate pre-scaler values */ 607 int pbr_tbl[4] = {2, 3, 5, 7}; 608 int brs[16] = { 2, 4, 6, 8, 609 16, 32, 64, 128, 610 256, 512, 1024, 2048, 611 4096, 8192, 16384, 32768 }; 612 int scale_needed, scale, minscale = INT_MAX; 613 int i, j; 614 615 scale_needed = clkrate / speed_hz; 616 if (clkrate % speed_hz) 617 scale_needed++; 618 619 for (i = 0; i < ARRAY_SIZE(brs); i++) 620 for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) { 621 scale = brs[i] * pbr_tbl[j]; 622 if (scale >= scale_needed) { 623 if (scale < minscale) { 624 minscale = scale; 625 *br = i; 626 *pbr = j; 627 } 628 break; 629 } 630 } 631 632 if (minscale == INT_MAX) { 633 pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n", 634 speed_hz, clkrate); 635 *pbr = ARRAY_SIZE(pbr_tbl) - 1; 636 *br = ARRAY_SIZE(brs) - 1; 637 } 638 } 639 640 static void ns_delay_scale(char *psc, char *sc, int delay_ns, 641 unsigned long clkrate) 642 { 643 int scale_needed, scale, minscale = INT_MAX; 644 int pscale_tbl[4] = {1, 3, 5, 7}; 645 u32 remainder; 646 int i, j; 647 648 scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC, 649 &remainder); 650 if (remainder) 651 scale_needed++; 652 653 for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++) 654 for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) { 655 scale = pscale_tbl[i] * (2 << j); 656 if (scale >= scale_needed) { 657 if (scale < minscale) { 658 minscale = scale; 659 *psc = i; 660 *sc = j; 661 } 662 break; 663 } 664 } 665 666 if (minscale == INT_MAX) { 667 pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value", 668 delay_ns, clkrate); 669 *psc = ARRAY_SIZE(pscale_tbl) - 1; 670 *sc = SPI_CTAR_SCALE_BITS; 671 } 672 } 673 674 static void dspi_pushr_write(struct fsl_dspi *dspi) 675 { 676 regmap_write(dspi->regmap, SPI_PUSHR, dspi_pop_tx_pushr(dspi)); 677 } 678 679 static void dspi_pushr_cmd_write(struct fsl_dspi *dspi, u16 cmd) 680 { 681 /* 682 * The only time when the PCS doesn't need continuation after this word 683 * is when it's last. We need to look ahead, because we actually call 684 * dspi_pop_tx (the function that decrements dspi->len) _after_ 685 * dspi_pushr_cmd_write with XSPI mode. As for how much in advance? One 686 * word is enough. If there's more to transmit than that, 687 * dspi_xspi_write will know to split the FIFO writes in 2, and 688 * generate a new PUSHR command with the final word that will have PCS 689 * deasserted (not continued) here. 690 */ 691 if (dspi->len > dspi->oper_word_size) 692 cmd |= SPI_PUSHR_CMD_CONT; 693 regmap_write(dspi->regmap_pushr, dspi->pushr_cmd, cmd); 694 } 695 696 static void dspi_pushr_txdata_write(struct fsl_dspi *dspi, u16 txdata) 697 { 698 regmap_write(dspi->regmap_pushr, dspi->pushr_tx, txdata); 699 } 700 701 static void dspi_xspi_fifo_write(struct fsl_dspi *dspi, int num_words) 702 { 703 int num_bytes = num_words * dspi->oper_word_size; 704 u16 tx_cmd = dspi->tx_cmd; 705 706 /* 707 * If the PCS needs to de-assert (i.e. we're at the end of the buffer 708 * and cs_change does not want the PCS to stay on), then we need a new 709 * PUSHR command, since this one (for the body of the buffer) 710 * necessarily has the CONT bit set. 711 * So send one word less during this go, to force a split and a command 712 * with a single word next time, when CONT will be unset. 713 */ 714 if (!(dspi->tx_cmd & SPI_PUSHR_CMD_CONT) && num_bytes == dspi->len) 715 tx_cmd |= SPI_PUSHR_CMD_EOQ; 716 717 /* Update CTARE */ 718 regmap_write(dspi->regmap, SPI_CTARE(0), 719 SPI_FRAME_EBITS(dspi->oper_bits_per_word) | 720 SPI_CTARE_DTCP(num_words)); 721 722 /* 723 * Write the CMD FIFO entry first, and then the two 724 * corresponding TX FIFO entries (or one...). 725 */ 726 dspi_pushr_cmd_write(dspi, tx_cmd); 727 728 /* Fill TX FIFO with as many transfers as possible */ 729 while (num_words--) { 730 u32 data = dspi_pop_tx(dspi); 731 732 dspi_pushr_txdata_write(dspi, data & 0xFFFF); 733 if (dspi->oper_bits_per_word > 16) 734 dspi_pushr_txdata_write(dspi, data >> 16); 735 } 736 } 737 738 static void dspi_eoq_fifo_write(struct fsl_dspi *dspi, int num_words) 739 { 740 u16 xfer_cmd = dspi->tx_cmd; 741 742 /* Fill TX FIFO with as many transfers as possible */ 743 while (num_words--) { 744 dspi->tx_cmd = xfer_cmd; 745 /* Request EOQF for last transfer in FIFO */ 746 if (num_words == 0) 747 dspi->tx_cmd |= SPI_PUSHR_CMD_EOQ; 748 /* Write combined TX FIFO and CMD FIFO entry */ 749 dspi_pushr_write(dspi); 750 } 751 } 752 753 static u32 dspi_popr_read(struct fsl_dspi *dspi) 754 { 755 u32 rxdata = 0; 756 757 regmap_read(dspi->regmap, SPI_POPR, &rxdata); 758 return rxdata; 759 } 760 761 static void dspi_fifo_read(struct fsl_dspi *dspi) 762 { 763 int num_fifo_entries = dspi->words_in_flight; 764 765 /* Read one FIFO entry and push to rx buffer */ 766 while (num_fifo_entries--) 767 dspi_push_rx(dspi, dspi_popr_read(dspi)); 768 } 769 770 static void dspi_setup_accel(struct fsl_dspi *dspi) 771 { 772 struct spi_transfer *xfer = dspi->cur_transfer; 773 bool odd = !!(dspi->len & 1); 774 775 /* No accel for frames not multiple of 8 bits at the moment */ 776 if (xfer->bits_per_word % 8) 777 goto no_accel; 778 779 if (!odd && dspi->len <= dspi->devtype_data->fifo_size * 2) { 780 dspi->oper_bits_per_word = 16; 781 } else if (odd && dspi->len <= dspi->devtype_data->fifo_size) { 782 dspi->oper_bits_per_word = 8; 783 } else { 784 /* Start off with maximum supported by hardware */ 785 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) 786 dspi->oper_bits_per_word = 32; 787 else 788 dspi->oper_bits_per_word = 16; 789 790 /* 791 * And go down only if the buffer can't be sent with 792 * words this big 793 */ 794 do { 795 if (dspi->len >= DIV_ROUND_UP(dspi->oper_bits_per_word, 8)) 796 break; 797 798 dspi->oper_bits_per_word /= 2; 799 } while (dspi->oper_bits_per_word > 8); 800 } 801 802 if (xfer->bits_per_word == 8 && dspi->oper_bits_per_word == 32) { 803 dspi->dev_to_host = dspi_8on32_dev_to_host; 804 dspi->host_to_dev = dspi_8on32_host_to_dev; 805 } else if (xfer->bits_per_word == 8 && dspi->oper_bits_per_word == 16) { 806 dspi->dev_to_host = dspi_8on16_dev_to_host; 807 dspi->host_to_dev = dspi_8on16_host_to_dev; 808 } else if (xfer->bits_per_word == 16 && dspi->oper_bits_per_word == 32) { 809 dspi->dev_to_host = dspi_16on32_dev_to_host; 810 dspi->host_to_dev = dspi_16on32_host_to_dev; 811 } else { 812 no_accel: 813 dspi->dev_to_host = dspi_native_dev_to_host; 814 dspi->host_to_dev = dspi_native_host_to_dev; 815 dspi->oper_bits_per_word = xfer->bits_per_word; 816 } 817 818 dspi->oper_word_size = DIV_ROUND_UP(dspi->oper_bits_per_word, 8); 819 820 /* 821 * Update CTAR here (code is common for EOQ, XSPI and DMA modes). 822 * We will update CTARE in the portion specific to XSPI, when we 823 * also know the preload value (DTCP). 824 */ 825 regmap_write(dspi->regmap, SPI_CTAR(0), 826 dspi->cur_chip->ctar_val | 827 SPI_FRAME_BITS(dspi->oper_bits_per_word)); 828 } 829 830 static void dspi_fifo_write(struct fsl_dspi *dspi) 831 { 832 int num_fifo_entries = dspi->devtype_data->fifo_size; 833 struct spi_transfer *xfer = dspi->cur_transfer; 834 struct spi_message *msg = dspi->cur_msg; 835 int num_words, num_bytes; 836 837 dspi_setup_accel(dspi); 838 839 /* In XSPI mode each 32-bit word occupies 2 TX FIFO entries */ 840 if (dspi->oper_word_size == 4) 841 num_fifo_entries /= 2; 842 843 /* 844 * Integer division intentionally trims off odd (or non-multiple of 4) 845 * numbers of bytes at the end of the buffer, which will be sent next 846 * time using a smaller oper_word_size. 847 */ 848 num_words = dspi->len / dspi->oper_word_size; 849 if (num_words > num_fifo_entries) 850 num_words = num_fifo_entries; 851 852 /* Update total number of bytes that were transferred */ 853 num_bytes = num_words * dspi->oper_word_size; 854 msg->actual_length += num_bytes; 855 dspi->progress += num_bytes / DIV_ROUND_UP(xfer->bits_per_word, 8); 856 857 /* 858 * Update shared variable for use in the next interrupt (both in 859 * dspi_fifo_read and in dspi_fifo_write). 860 */ 861 dspi->words_in_flight = num_words; 862 863 spi_take_timestamp_pre(dspi->ctlr, xfer, dspi->progress, !dspi->irq); 864 865 if (dspi->devtype_data->trans_mode == DSPI_EOQ_MODE) 866 dspi_eoq_fifo_write(dspi, num_words); 867 else 868 dspi_xspi_fifo_write(dspi, num_words); 869 /* 870 * Everything after this point is in a potential race with the next 871 * interrupt, so we must never use dspi->words_in_flight again since it 872 * might already be modified by the next dspi_fifo_write. 873 */ 874 875 spi_take_timestamp_post(dspi->ctlr, dspi->cur_transfer, 876 dspi->progress, !dspi->irq); 877 } 878 879 static int dspi_rxtx(struct fsl_dspi *dspi) 880 { 881 dspi_fifo_read(dspi); 882 883 if (!dspi->len) 884 /* Success! */ 885 return 0; 886 887 dspi_fifo_write(dspi); 888 889 return -EINPROGRESS; 890 } 891 892 static int dspi_poll(struct fsl_dspi *dspi) 893 { 894 int tries = 1000; 895 u32 spi_sr; 896 897 do { 898 regmap_read(dspi->regmap, SPI_SR, &spi_sr); 899 regmap_write(dspi->regmap, SPI_SR, spi_sr); 900 901 if (spi_sr & (SPI_SR_EOQF | SPI_SR_CMDTCF)) 902 break; 903 } while (--tries); 904 905 if (!tries) 906 return -ETIMEDOUT; 907 908 return dspi_rxtx(dspi); 909 } 910 911 static irqreturn_t dspi_interrupt(int irq, void *dev_id) 912 { 913 struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id; 914 u32 spi_sr; 915 916 regmap_read(dspi->regmap, SPI_SR, &spi_sr); 917 regmap_write(dspi->regmap, SPI_SR, spi_sr); 918 919 if (!(spi_sr & (SPI_SR_EOQF | SPI_SR_CMDTCF))) 920 return IRQ_NONE; 921 922 if (dspi_rxtx(dspi) == 0) 923 complete(&dspi->xfer_done); 924 925 return IRQ_HANDLED; 926 } 927 928 static int dspi_transfer_one_message(struct spi_controller *ctlr, 929 struct spi_message *message) 930 { 931 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr); 932 struct spi_device *spi = message->spi; 933 struct spi_transfer *transfer; 934 int status = 0; 935 936 message->actual_length = 0; 937 938 list_for_each_entry(transfer, &message->transfers, transfer_list) { 939 dspi->cur_transfer = transfer; 940 dspi->cur_msg = message; 941 dspi->cur_chip = spi_get_ctldata(spi); 942 /* Prepare command word for CMD FIFO */ 943 dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0) | 944 SPI_PUSHR_CMD_PCS(spi->chip_select); 945 if (list_is_last(&dspi->cur_transfer->transfer_list, 946 &dspi->cur_msg->transfers)) { 947 /* Leave PCS activated after last transfer when 948 * cs_change is set. 949 */ 950 if (transfer->cs_change) 951 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT; 952 } else { 953 /* Keep PCS active between transfers in same message 954 * when cs_change is not set, and de-activate PCS 955 * between transfers in the same message when 956 * cs_change is set. 957 */ 958 if (!transfer->cs_change) 959 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT; 960 } 961 962 dspi->tx = transfer->tx_buf; 963 dspi->rx = transfer->rx_buf; 964 dspi->len = transfer->len; 965 dspi->progress = 0; 966 967 regmap_update_bits(dspi->regmap, SPI_MCR, 968 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF, 969 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF); 970 971 spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer, 972 dspi->progress, !dspi->irq); 973 974 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) { 975 status = dspi_dma_xfer(dspi); 976 } else { 977 dspi_fifo_write(dspi); 978 979 if (dspi->irq) { 980 wait_for_completion(&dspi->xfer_done); 981 reinit_completion(&dspi->xfer_done); 982 } else { 983 do { 984 status = dspi_poll(dspi); 985 } while (status == -EINPROGRESS); 986 } 987 } 988 if (status) 989 break; 990 991 spi_transfer_delay_exec(transfer); 992 } 993 994 message->status = status; 995 spi_finalize_current_message(ctlr); 996 997 return status; 998 } 999 1000 static int dspi_setup(struct spi_device *spi) 1001 { 1002 struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller); 1003 unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0; 1004 u32 cs_sck_delay = 0, sck_cs_delay = 0; 1005 struct fsl_dspi_platform_data *pdata; 1006 unsigned char pasc = 0, asc = 0; 1007 struct chip_data *chip; 1008 unsigned long clkrate; 1009 1010 /* Only alloc on first setup */ 1011 chip = spi_get_ctldata(spi); 1012 if (chip == NULL) { 1013 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 1014 if (!chip) 1015 return -ENOMEM; 1016 } 1017 1018 pdata = dev_get_platdata(&dspi->pdev->dev); 1019 1020 if (!pdata) { 1021 of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay", 1022 &cs_sck_delay); 1023 1024 of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay", 1025 &sck_cs_delay); 1026 } else { 1027 cs_sck_delay = pdata->cs_sck_delay; 1028 sck_cs_delay = pdata->sck_cs_delay; 1029 } 1030 1031 clkrate = clk_get_rate(dspi->clk); 1032 hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate); 1033 1034 /* Set PCS to SCK delay scale values */ 1035 ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate); 1036 1037 /* Set After SCK delay scale values */ 1038 ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate); 1039 1040 chip->ctar_val = 0; 1041 if (spi->mode & SPI_CPOL) 1042 chip->ctar_val |= SPI_CTAR_CPOL; 1043 if (spi->mode & SPI_CPHA) 1044 chip->ctar_val |= SPI_CTAR_CPHA; 1045 1046 if (!spi_controller_is_slave(dspi->ctlr)) { 1047 chip->ctar_val |= SPI_CTAR_PCSSCK(pcssck) | 1048 SPI_CTAR_CSSCK(cssck) | 1049 SPI_CTAR_PASC(pasc) | 1050 SPI_CTAR_ASC(asc) | 1051 SPI_CTAR_PBR(pbr) | 1052 SPI_CTAR_BR(br); 1053 1054 if (spi->mode & SPI_LSB_FIRST) 1055 chip->ctar_val |= SPI_CTAR_LSBFE; 1056 } 1057 1058 spi_set_ctldata(spi, chip); 1059 1060 return 0; 1061 } 1062 1063 static void dspi_cleanup(struct spi_device *spi) 1064 { 1065 struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi); 1066 1067 dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n", 1068 spi->controller->bus_num, spi->chip_select); 1069 1070 kfree(chip); 1071 } 1072 1073 static const struct of_device_id fsl_dspi_dt_ids[] = { 1074 { 1075 .compatible = "fsl,vf610-dspi", 1076 .data = &devtype_data[VF610], 1077 }, { 1078 .compatible = "fsl,ls1021a-v1.0-dspi", 1079 .data = &devtype_data[LS1021A], 1080 }, { 1081 .compatible = "fsl,ls1012a-dspi", 1082 .data = &devtype_data[LS1012A], 1083 }, { 1084 .compatible = "fsl,ls1028a-dspi", 1085 .data = &devtype_data[LS1028A], 1086 }, { 1087 .compatible = "fsl,ls1043a-dspi", 1088 .data = &devtype_data[LS1043A], 1089 }, { 1090 .compatible = "fsl,ls1046a-dspi", 1091 .data = &devtype_data[LS1046A], 1092 }, { 1093 .compatible = "fsl,ls2080a-dspi", 1094 .data = &devtype_data[LS2080A], 1095 }, { 1096 .compatible = "fsl,ls2085a-dspi", 1097 .data = &devtype_data[LS2085A], 1098 }, { 1099 .compatible = "fsl,lx2160a-dspi", 1100 .data = &devtype_data[LX2160A], 1101 }, 1102 { /* sentinel */ } 1103 }; 1104 MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids); 1105 1106 #ifdef CONFIG_PM_SLEEP 1107 static int dspi_suspend(struct device *dev) 1108 { 1109 struct spi_controller *ctlr = dev_get_drvdata(dev); 1110 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr); 1111 1112 if (dspi->irq) 1113 disable_irq(dspi->irq); 1114 spi_controller_suspend(ctlr); 1115 clk_disable_unprepare(dspi->clk); 1116 1117 pinctrl_pm_select_sleep_state(dev); 1118 1119 return 0; 1120 } 1121 1122 static int dspi_resume(struct device *dev) 1123 { 1124 struct spi_controller *ctlr = dev_get_drvdata(dev); 1125 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr); 1126 int ret; 1127 1128 pinctrl_pm_select_default_state(dev); 1129 1130 ret = clk_prepare_enable(dspi->clk); 1131 if (ret) 1132 return ret; 1133 spi_controller_resume(ctlr); 1134 if (dspi->irq) 1135 enable_irq(dspi->irq); 1136 1137 return 0; 1138 } 1139 #endif /* CONFIG_PM_SLEEP */ 1140 1141 static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume); 1142 1143 static const struct regmap_range dspi_volatile_ranges[] = { 1144 regmap_reg_range(SPI_MCR, SPI_TCR), 1145 regmap_reg_range(SPI_SR, SPI_SR), 1146 regmap_reg_range(SPI_PUSHR, SPI_RXFR3), 1147 }; 1148 1149 static const struct regmap_access_table dspi_volatile_table = { 1150 .yes_ranges = dspi_volatile_ranges, 1151 .n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges), 1152 }; 1153 1154 static const struct regmap_config dspi_regmap_config = { 1155 .reg_bits = 32, 1156 .val_bits = 32, 1157 .reg_stride = 4, 1158 .max_register = 0x88, 1159 .volatile_table = &dspi_volatile_table, 1160 }; 1161 1162 static const struct regmap_range dspi_xspi_volatile_ranges[] = { 1163 regmap_reg_range(SPI_MCR, SPI_TCR), 1164 regmap_reg_range(SPI_SR, SPI_SR), 1165 regmap_reg_range(SPI_PUSHR, SPI_RXFR3), 1166 regmap_reg_range(SPI_SREX, SPI_SREX), 1167 }; 1168 1169 static const struct regmap_access_table dspi_xspi_volatile_table = { 1170 .yes_ranges = dspi_xspi_volatile_ranges, 1171 .n_yes_ranges = ARRAY_SIZE(dspi_xspi_volatile_ranges), 1172 }; 1173 1174 static const struct regmap_config dspi_xspi_regmap_config[] = { 1175 { 1176 .reg_bits = 32, 1177 .val_bits = 32, 1178 .reg_stride = 4, 1179 .max_register = 0x13c, 1180 .volatile_table = &dspi_xspi_volatile_table, 1181 }, 1182 { 1183 .name = "pushr", 1184 .reg_bits = 16, 1185 .val_bits = 16, 1186 .reg_stride = 2, 1187 .max_register = 0x2, 1188 }, 1189 }; 1190 1191 static int dspi_init(struct fsl_dspi *dspi) 1192 { 1193 unsigned int mcr; 1194 1195 /* Set idle states for all chip select signals to high */ 1196 mcr = SPI_MCR_PCSIS(GENMASK(dspi->ctlr->num_chipselect - 1, 0)); 1197 1198 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) 1199 mcr |= SPI_MCR_XSPI; 1200 if (!spi_controller_is_slave(dspi->ctlr)) 1201 mcr |= SPI_MCR_MASTER; 1202 1203 regmap_write(dspi->regmap, SPI_MCR, mcr); 1204 regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR); 1205 1206 switch (dspi->devtype_data->trans_mode) { 1207 case DSPI_EOQ_MODE: 1208 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE); 1209 break; 1210 case DSPI_XSPI_MODE: 1211 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_CMDTCFE); 1212 break; 1213 case DSPI_DMA_MODE: 1214 regmap_write(dspi->regmap, SPI_RSER, 1215 SPI_RSER_TFFFE | SPI_RSER_TFFFD | 1216 SPI_RSER_RFDFE | SPI_RSER_RFDFD); 1217 break; 1218 default: 1219 dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n", 1220 dspi->devtype_data->trans_mode); 1221 return -EINVAL; 1222 } 1223 1224 return 0; 1225 } 1226 1227 static int dspi_slave_abort(struct spi_master *master) 1228 { 1229 struct fsl_dspi *dspi = spi_master_get_devdata(master); 1230 1231 /* 1232 * Terminate all pending DMA transactions for the SPI working 1233 * in SLAVE mode. 1234 */ 1235 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) { 1236 dmaengine_terminate_sync(dspi->dma->chan_rx); 1237 dmaengine_terminate_sync(dspi->dma->chan_tx); 1238 } 1239 1240 /* Clear the internal DSPI RX and TX FIFO buffers */ 1241 regmap_update_bits(dspi->regmap, SPI_MCR, 1242 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF, 1243 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF); 1244 1245 return 0; 1246 } 1247 1248 /* 1249 * EOQ mode will inevitably deassert its PCS signal on last word in a queue 1250 * (hardware limitation), so we need to inform the spi_device that larger 1251 * buffers than the FIFO size are going to have the chip select randomly 1252 * toggling, so it has a chance to adapt its message sizes. 1253 */ 1254 static size_t dspi_max_message_size(struct spi_device *spi) 1255 { 1256 struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller); 1257 1258 if (dspi->devtype_data->trans_mode == DSPI_EOQ_MODE) 1259 return dspi->devtype_data->fifo_size; 1260 1261 return SIZE_MAX; 1262 } 1263 1264 static int dspi_probe(struct platform_device *pdev) 1265 { 1266 struct device_node *np = pdev->dev.of_node; 1267 const struct regmap_config *regmap_config; 1268 struct fsl_dspi_platform_data *pdata; 1269 struct spi_controller *ctlr; 1270 int ret, cs_num, bus_num = -1; 1271 struct fsl_dspi *dspi; 1272 struct resource *res; 1273 void __iomem *base; 1274 bool big_endian; 1275 1276 ctlr = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi)); 1277 if (!ctlr) 1278 return -ENOMEM; 1279 1280 dspi = spi_controller_get_devdata(ctlr); 1281 dspi->pdev = pdev; 1282 dspi->ctlr = ctlr; 1283 1284 ctlr->setup = dspi_setup; 1285 ctlr->transfer_one_message = dspi_transfer_one_message; 1286 ctlr->max_message_size = dspi_max_message_size; 1287 ctlr->dev.of_node = pdev->dev.of_node; 1288 1289 ctlr->cleanup = dspi_cleanup; 1290 ctlr->slave_abort = dspi_slave_abort; 1291 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; 1292 1293 pdata = dev_get_platdata(&pdev->dev); 1294 if (pdata) { 1295 ctlr->num_chipselect = pdata->cs_num; 1296 ctlr->bus_num = pdata->bus_num; 1297 1298 /* Only Coldfire uses platform data */ 1299 dspi->devtype_data = &devtype_data[MCF5441X]; 1300 big_endian = true; 1301 } else { 1302 1303 ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num); 1304 if (ret < 0) { 1305 dev_err(&pdev->dev, "can't get spi-num-chipselects\n"); 1306 goto out_ctlr_put; 1307 } 1308 ctlr->num_chipselect = cs_num; 1309 1310 of_property_read_u32(np, "bus-num", &bus_num); 1311 ctlr->bus_num = bus_num; 1312 1313 if (of_property_read_bool(np, "spi-slave")) 1314 ctlr->slave = true; 1315 1316 dspi->devtype_data = of_device_get_match_data(&pdev->dev); 1317 if (!dspi->devtype_data) { 1318 dev_err(&pdev->dev, "can't get devtype_data\n"); 1319 ret = -EFAULT; 1320 goto out_ctlr_put; 1321 } 1322 1323 big_endian = of_device_is_big_endian(np); 1324 } 1325 if (big_endian) { 1326 dspi->pushr_cmd = 0; 1327 dspi->pushr_tx = 2; 1328 } else { 1329 dspi->pushr_cmd = 2; 1330 dspi->pushr_tx = 0; 1331 } 1332 1333 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) 1334 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1335 else 1336 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); 1337 1338 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1339 base = devm_ioremap_resource(&pdev->dev, res); 1340 if (IS_ERR(base)) { 1341 ret = PTR_ERR(base); 1342 goto out_ctlr_put; 1343 } 1344 1345 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) 1346 regmap_config = &dspi_xspi_regmap_config[0]; 1347 else 1348 regmap_config = &dspi_regmap_config; 1349 dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base, regmap_config); 1350 if (IS_ERR(dspi->regmap)) { 1351 dev_err(&pdev->dev, "failed to init regmap: %ld\n", 1352 PTR_ERR(dspi->regmap)); 1353 ret = PTR_ERR(dspi->regmap); 1354 goto out_ctlr_put; 1355 } 1356 1357 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) { 1358 dspi->regmap_pushr = devm_regmap_init_mmio( 1359 &pdev->dev, base + SPI_PUSHR, 1360 &dspi_xspi_regmap_config[1]); 1361 if (IS_ERR(dspi->regmap_pushr)) { 1362 dev_err(&pdev->dev, 1363 "failed to init pushr regmap: %ld\n", 1364 PTR_ERR(dspi->regmap_pushr)); 1365 ret = PTR_ERR(dspi->regmap_pushr); 1366 goto out_ctlr_put; 1367 } 1368 } 1369 1370 dspi->clk = devm_clk_get(&pdev->dev, "dspi"); 1371 if (IS_ERR(dspi->clk)) { 1372 ret = PTR_ERR(dspi->clk); 1373 dev_err(&pdev->dev, "unable to get clock\n"); 1374 goto out_ctlr_put; 1375 } 1376 ret = clk_prepare_enable(dspi->clk); 1377 if (ret) 1378 goto out_ctlr_put; 1379 1380 ret = dspi_init(dspi); 1381 if (ret) 1382 goto out_clk_put; 1383 1384 dspi->irq = platform_get_irq(pdev, 0); 1385 if (dspi->irq <= 0) { 1386 dev_info(&pdev->dev, 1387 "can't get platform irq, using poll mode\n"); 1388 dspi->irq = 0; 1389 goto poll_mode; 1390 } 1391 1392 init_completion(&dspi->xfer_done); 1393 1394 ret = request_threaded_irq(dspi->irq, dspi_interrupt, NULL, 1395 IRQF_SHARED, pdev->name, dspi); 1396 if (ret < 0) { 1397 dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n"); 1398 goto out_clk_put; 1399 } 1400 1401 poll_mode: 1402 1403 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) { 1404 ret = dspi_request_dma(dspi, res->start); 1405 if (ret < 0) { 1406 dev_err(&pdev->dev, "can't get dma channels\n"); 1407 goto out_free_irq; 1408 } 1409 } 1410 1411 ctlr->max_speed_hz = 1412 clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor; 1413 1414 if (dspi->devtype_data->trans_mode != DSPI_DMA_MODE) 1415 ctlr->ptp_sts_supported = true; 1416 1417 platform_set_drvdata(pdev, ctlr); 1418 1419 ret = spi_register_controller(ctlr); 1420 if (ret != 0) { 1421 dev_err(&pdev->dev, "Problem registering DSPI ctlr\n"); 1422 goto out_free_irq; 1423 } 1424 1425 return ret; 1426 1427 out_free_irq: 1428 if (dspi->irq) 1429 free_irq(dspi->irq, dspi); 1430 out_clk_put: 1431 clk_disable_unprepare(dspi->clk); 1432 out_ctlr_put: 1433 spi_controller_put(ctlr); 1434 1435 return ret; 1436 } 1437 1438 static int dspi_remove(struct platform_device *pdev) 1439 { 1440 struct spi_controller *ctlr = platform_get_drvdata(pdev); 1441 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr); 1442 1443 /* Disconnect from the SPI framework */ 1444 spi_unregister_controller(dspi->ctlr); 1445 1446 /* Disable RX and TX */ 1447 regmap_update_bits(dspi->regmap, SPI_MCR, 1448 SPI_MCR_DIS_TXF | SPI_MCR_DIS_RXF, 1449 SPI_MCR_DIS_TXF | SPI_MCR_DIS_RXF); 1450 1451 /* Stop Running */ 1452 regmap_update_bits(dspi->regmap, SPI_MCR, SPI_MCR_HALT, SPI_MCR_HALT); 1453 1454 dspi_release_dma(dspi); 1455 if (dspi->irq) 1456 free_irq(dspi->irq, dspi); 1457 clk_disable_unprepare(dspi->clk); 1458 1459 return 0; 1460 } 1461 1462 static void dspi_shutdown(struct platform_device *pdev) 1463 { 1464 dspi_remove(pdev); 1465 } 1466 1467 static struct platform_driver fsl_dspi_driver = { 1468 .driver.name = DRIVER_NAME, 1469 .driver.of_match_table = fsl_dspi_dt_ids, 1470 .driver.owner = THIS_MODULE, 1471 .driver.pm = &dspi_pm, 1472 .probe = dspi_probe, 1473 .remove = dspi_remove, 1474 .shutdown = dspi_shutdown, 1475 }; 1476 module_platform_driver(fsl_dspi_driver); 1477 1478 MODULE_DESCRIPTION("Freescale DSPI Controller Driver"); 1479 MODULE_LICENSE("GPL"); 1480 MODULE_ALIAS("platform:" DRIVER_NAME); 1481