1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Copyright 2013 Freescale Semiconductor, Inc. 4 // 5 // Freescale DSPI driver 6 // This file contains a driver for the Freescale DSPI 7 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/dmaengine.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/interrupt.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/of_device.h> 16 #include <linux/pinctrl/consumer.h> 17 #include <linux/regmap.h> 18 #include <linux/spi/spi.h> 19 #include <linux/spi/spi-fsl-dspi.h> 20 21 #define DRIVER_NAME "fsl-dspi" 22 23 #ifdef CONFIG_M5441x 24 #define DSPI_FIFO_SIZE 16 25 #else 26 #define DSPI_FIFO_SIZE 4 27 #endif 28 #define DSPI_DMA_BUFSIZE (DSPI_FIFO_SIZE * 1024) 29 30 #define SPI_MCR 0x00 31 #define SPI_MCR_MASTER BIT(31) 32 #define SPI_MCR_PCSIS (0x3F << 16) 33 #define SPI_MCR_CLR_TXF BIT(11) 34 #define SPI_MCR_CLR_RXF BIT(10) 35 #define SPI_MCR_XSPI BIT(3) 36 37 #define SPI_TCR 0x08 38 #define SPI_TCR_GET_TCNT(x) (((x) & GENMASK(31, 16)) >> 16) 39 40 #define SPI_CTAR(x) (0x0c + (((x) & GENMASK(1, 0)) * 4)) 41 #define SPI_CTAR_FMSZ(x) (((x) << 27) & GENMASK(30, 27)) 42 #define SPI_CTAR_CPOL BIT(26) 43 #define SPI_CTAR_CPHA BIT(25) 44 #define SPI_CTAR_LSBFE BIT(24) 45 #define SPI_CTAR_PCSSCK(x) (((x) << 22) & GENMASK(23, 22)) 46 #define SPI_CTAR_PASC(x) (((x) << 20) & GENMASK(21, 20)) 47 #define SPI_CTAR_PDT(x) (((x) << 18) & GENMASK(19, 18)) 48 #define SPI_CTAR_PBR(x) (((x) << 16) & GENMASK(17, 16)) 49 #define SPI_CTAR_CSSCK(x) (((x) << 12) & GENMASK(15, 12)) 50 #define SPI_CTAR_ASC(x) (((x) << 8) & GENMASK(11, 8)) 51 #define SPI_CTAR_DT(x) (((x) << 4) & GENMASK(7, 4)) 52 #define SPI_CTAR_BR(x) ((x) & GENMASK(3, 0)) 53 #define SPI_CTAR_SCALE_BITS 0xf 54 55 #define SPI_CTAR0_SLAVE 0x0c 56 57 #define SPI_SR 0x2c 58 #define SPI_SR_TCFQF BIT(31) 59 #define SPI_SR_EOQF BIT(28) 60 #define SPI_SR_TFUF BIT(27) 61 #define SPI_SR_TFFF BIT(25) 62 #define SPI_SR_CMDTCF BIT(23) 63 #define SPI_SR_SPEF BIT(21) 64 #define SPI_SR_RFOF BIT(19) 65 #define SPI_SR_TFIWF BIT(18) 66 #define SPI_SR_RFDF BIT(17) 67 #define SPI_SR_CMDFFF BIT(16) 68 #define SPI_SR_CLEAR (SPI_SR_TCFQF | SPI_SR_EOQF | \ 69 SPI_SR_TFUF | SPI_SR_TFFF | \ 70 SPI_SR_CMDTCF | SPI_SR_SPEF | \ 71 SPI_SR_RFOF | SPI_SR_TFIWF | \ 72 SPI_SR_RFDF | SPI_SR_CMDFFF) 73 74 #define SPI_RSER_TFFFE BIT(25) 75 #define SPI_RSER_TFFFD BIT(24) 76 #define SPI_RSER_RFDFE BIT(17) 77 #define SPI_RSER_RFDFD BIT(16) 78 79 #define SPI_RSER 0x30 80 #define SPI_RSER_TCFQE BIT(31) 81 #define SPI_RSER_EOQFE BIT(28) 82 83 #define SPI_PUSHR 0x34 84 #define SPI_PUSHR_CMD_CONT BIT(15) 85 #define SPI_PUSHR_CMD_CTAS(x) (((x) << 12 & GENMASK(14, 12))) 86 #define SPI_PUSHR_CMD_EOQ BIT(11) 87 #define SPI_PUSHR_CMD_CTCNT BIT(10) 88 #define SPI_PUSHR_CMD_PCS(x) (BIT(x) & GENMASK(5, 0)) 89 90 #define SPI_PUSHR_SLAVE 0x34 91 92 #define SPI_POPR 0x38 93 94 #define SPI_TXFR0 0x3c 95 #define SPI_TXFR1 0x40 96 #define SPI_TXFR2 0x44 97 #define SPI_TXFR3 0x48 98 #define SPI_RXFR0 0x7c 99 #define SPI_RXFR1 0x80 100 #define SPI_RXFR2 0x84 101 #define SPI_RXFR3 0x88 102 103 #define SPI_CTARE(x) (0x11c + (((x) & GENMASK(1, 0)) * 4)) 104 #define SPI_CTARE_FMSZE(x) (((x) & 0x1) << 16) 105 #define SPI_CTARE_DTCP(x) ((x) & 0x7ff) 106 107 #define SPI_SREX 0x13c 108 109 #define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1) 110 #define SPI_FRAME_EBITS(bits) SPI_CTARE_FMSZE(((bits) - 1) >> 4) 111 112 /* Register offsets for regmap_pushr */ 113 #define PUSHR_CMD 0x0 114 #define PUSHR_TX 0x2 115 116 #define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000) 117 118 struct chip_data { 119 u32 ctar_val; 120 u16 void_write_data; 121 }; 122 123 enum dspi_trans_mode { 124 DSPI_EOQ_MODE = 0, 125 DSPI_TCFQ_MODE, 126 DSPI_DMA_MODE, 127 }; 128 129 struct fsl_dspi_devtype_data { 130 enum dspi_trans_mode trans_mode; 131 u8 max_clock_factor; 132 bool ptp_sts_supported; 133 bool xspi_mode; 134 }; 135 136 static const struct fsl_dspi_devtype_data vf610_data = { 137 .trans_mode = DSPI_DMA_MODE, 138 .max_clock_factor = 2, 139 }; 140 141 static const struct fsl_dspi_devtype_data ls1021a_v1_data = { 142 .trans_mode = DSPI_TCFQ_MODE, 143 .max_clock_factor = 8, 144 .ptp_sts_supported = true, 145 .xspi_mode = true, 146 }; 147 148 static const struct fsl_dspi_devtype_data ls2085a_data = { 149 .trans_mode = DSPI_TCFQ_MODE, 150 .max_clock_factor = 8, 151 .ptp_sts_supported = true, 152 }; 153 154 static const struct fsl_dspi_devtype_data coldfire_data = { 155 .trans_mode = DSPI_EOQ_MODE, 156 .max_clock_factor = 8, 157 }; 158 159 struct fsl_dspi_dma { 160 /* Length of transfer in words of DSPI_FIFO_SIZE */ 161 u32 curr_xfer_len; 162 163 u32 *tx_dma_buf; 164 struct dma_chan *chan_tx; 165 dma_addr_t tx_dma_phys; 166 struct completion cmd_tx_complete; 167 struct dma_async_tx_descriptor *tx_desc; 168 169 u32 *rx_dma_buf; 170 struct dma_chan *chan_rx; 171 dma_addr_t rx_dma_phys; 172 struct completion cmd_rx_complete; 173 struct dma_async_tx_descriptor *rx_desc; 174 }; 175 176 struct fsl_dspi { 177 struct spi_controller *ctlr; 178 struct platform_device *pdev; 179 180 struct regmap *regmap; 181 struct regmap *regmap_pushr; 182 int irq; 183 struct clk *clk; 184 185 struct spi_transfer *cur_transfer; 186 struct spi_message *cur_msg; 187 struct chip_data *cur_chip; 188 size_t progress; 189 size_t len; 190 const void *tx; 191 void *rx; 192 void *rx_end; 193 u16 void_write_data; 194 u16 tx_cmd; 195 u8 bits_per_word; 196 u8 bytes_per_word; 197 const struct fsl_dspi_devtype_data *devtype_data; 198 199 wait_queue_head_t waitq; 200 u32 waitflags; 201 202 struct fsl_dspi_dma *dma; 203 }; 204 205 static u32 dspi_pop_tx(struct fsl_dspi *dspi) 206 { 207 u32 txdata = 0; 208 209 if (dspi->tx) { 210 if (dspi->bytes_per_word == 1) 211 txdata = *(u8 *)dspi->tx; 212 else if (dspi->bytes_per_word == 2) 213 txdata = *(u16 *)dspi->tx; 214 else /* dspi->bytes_per_word == 4 */ 215 txdata = *(u32 *)dspi->tx; 216 dspi->tx += dspi->bytes_per_word; 217 } 218 dspi->len -= dspi->bytes_per_word; 219 return txdata; 220 } 221 222 static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi) 223 { 224 u16 cmd = dspi->tx_cmd, data = dspi_pop_tx(dspi); 225 226 if (spi_controller_is_slave(dspi->ctlr)) 227 return data; 228 229 if (dspi->len > 0) 230 cmd |= SPI_PUSHR_CMD_CONT; 231 return cmd << 16 | data; 232 } 233 234 static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata) 235 { 236 if (!dspi->rx) 237 return; 238 239 /* Mask off undefined bits */ 240 rxdata &= (1 << dspi->bits_per_word) - 1; 241 242 if (dspi->bytes_per_word == 1) 243 *(u8 *)dspi->rx = rxdata; 244 else if (dspi->bytes_per_word == 2) 245 *(u16 *)dspi->rx = rxdata; 246 else /* dspi->bytes_per_word == 4 */ 247 *(u32 *)dspi->rx = rxdata; 248 dspi->rx += dspi->bytes_per_word; 249 } 250 251 static void dspi_tx_dma_callback(void *arg) 252 { 253 struct fsl_dspi *dspi = arg; 254 struct fsl_dspi_dma *dma = dspi->dma; 255 256 complete(&dma->cmd_tx_complete); 257 } 258 259 static void dspi_rx_dma_callback(void *arg) 260 { 261 struct fsl_dspi *dspi = arg; 262 struct fsl_dspi_dma *dma = dspi->dma; 263 int i; 264 265 if (dspi->rx) { 266 for (i = 0; i < dma->curr_xfer_len; i++) 267 dspi_push_rx(dspi, dspi->dma->rx_dma_buf[i]); 268 } 269 270 complete(&dma->cmd_rx_complete); 271 } 272 273 static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi) 274 { 275 struct device *dev = &dspi->pdev->dev; 276 struct fsl_dspi_dma *dma = dspi->dma; 277 int time_left; 278 int i; 279 280 for (i = 0; i < dma->curr_xfer_len; i++) 281 dspi->dma->tx_dma_buf[i] = dspi_pop_tx_pushr(dspi); 282 283 dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx, 284 dma->tx_dma_phys, 285 dma->curr_xfer_len * 286 DMA_SLAVE_BUSWIDTH_4_BYTES, 287 DMA_MEM_TO_DEV, 288 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 289 if (!dma->tx_desc) { 290 dev_err(dev, "Not able to get desc for DMA xfer\n"); 291 return -EIO; 292 } 293 294 dma->tx_desc->callback = dspi_tx_dma_callback; 295 dma->tx_desc->callback_param = dspi; 296 if (dma_submit_error(dmaengine_submit(dma->tx_desc))) { 297 dev_err(dev, "DMA submit failed\n"); 298 return -EINVAL; 299 } 300 301 dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx, 302 dma->rx_dma_phys, 303 dma->curr_xfer_len * 304 DMA_SLAVE_BUSWIDTH_4_BYTES, 305 DMA_DEV_TO_MEM, 306 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 307 if (!dma->rx_desc) { 308 dev_err(dev, "Not able to get desc for DMA xfer\n"); 309 return -EIO; 310 } 311 312 dma->rx_desc->callback = dspi_rx_dma_callback; 313 dma->rx_desc->callback_param = dspi; 314 if (dma_submit_error(dmaengine_submit(dma->rx_desc))) { 315 dev_err(dev, "DMA submit failed\n"); 316 return -EINVAL; 317 } 318 319 reinit_completion(&dspi->dma->cmd_rx_complete); 320 reinit_completion(&dspi->dma->cmd_tx_complete); 321 322 dma_async_issue_pending(dma->chan_rx); 323 dma_async_issue_pending(dma->chan_tx); 324 325 if (spi_controller_is_slave(dspi->ctlr)) { 326 wait_for_completion_interruptible(&dspi->dma->cmd_rx_complete); 327 return 0; 328 } 329 330 time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete, 331 DMA_COMPLETION_TIMEOUT); 332 if (time_left == 0) { 333 dev_err(dev, "DMA tx timeout\n"); 334 dmaengine_terminate_all(dma->chan_tx); 335 dmaengine_terminate_all(dma->chan_rx); 336 return -ETIMEDOUT; 337 } 338 339 time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete, 340 DMA_COMPLETION_TIMEOUT); 341 if (time_left == 0) { 342 dev_err(dev, "DMA rx timeout\n"); 343 dmaengine_terminate_all(dma->chan_tx); 344 dmaengine_terminate_all(dma->chan_rx); 345 return -ETIMEDOUT; 346 } 347 348 return 0; 349 } 350 351 static int dspi_dma_xfer(struct fsl_dspi *dspi) 352 { 353 struct spi_message *message = dspi->cur_msg; 354 struct device *dev = &dspi->pdev->dev; 355 struct fsl_dspi_dma *dma = dspi->dma; 356 int curr_remaining_bytes; 357 int bytes_per_buffer; 358 int ret = 0; 359 360 curr_remaining_bytes = dspi->len; 361 bytes_per_buffer = DSPI_DMA_BUFSIZE / DSPI_FIFO_SIZE; 362 while (curr_remaining_bytes) { 363 /* Check if current transfer fits the DMA buffer */ 364 dma->curr_xfer_len = curr_remaining_bytes 365 / dspi->bytes_per_word; 366 if (dma->curr_xfer_len > bytes_per_buffer) 367 dma->curr_xfer_len = bytes_per_buffer; 368 369 ret = dspi_next_xfer_dma_submit(dspi); 370 if (ret) { 371 dev_err(dev, "DMA transfer failed\n"); 372 goto exit; 373 374 } else { 375 const int len = 376 dma->curr_xfer_len * dspi->bytes_per_word; 377 curr_remaining_bytes -= len; 378 message->actual_length += len; 379 if (curr_remaining_bytes < 0) 380 curr_remaining_bytes = 0; 381 } 382 } 383 384 exit: 385 return ret; 386 } 387 388 static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr) 389 { 390 struct device *dev = &dspi->pdev->dev; 391 struct dma_slave_config cfg; 392 struct fsl_dspi_dma *dma; 393 int ret; 394 395 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 396 if (!dma) 397 return -ENOMEM; 398 399 dma->chan_rx = dma_request_chan(dev, "rx"); 400 if (IS_ERR(dma->chan_rx)) { 401 dev_err(dev, "rx dma channel not available\n"); 402 ret = PTR_ERR(dma->chan_rx); 403 return ret; 404 } 405 406 dma->chan_tx = dma_request_chan(dev, "tx"); 407 if (IS_ERR(dma->chan_tx)) { 408 dev_err(dev, "tx dma channel not available\n"); 409 ret = PTR_ERR(dma->chan_tx); 410 goto err_tx_channel; 411 } 412 413 dma->tx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE, 414 &dma->tx_dma_phys, GFP_KERNEL); 415 if (!dma->tx_dma_buf) { 416 ret = -ENOMEM; 417 goto err_tx_dma_buf; 418 } 419 420 dma->rx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE, 421 &dma->rx_dma_phys, GFP_KERNEL); 422 if (!dma->rx_dma_buf) { 423 ret = -ENOMEM; 424 goto err_rx_dma_buf; 425 } 426 427 cfg.src_addr = phy_addr + SPI_POPR; 428 cfg.dst_addr = phy_addr + SPI_PUSHR; 429 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 430 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 431 cfg.src_maxburst = 1; 432 cfg.dst_maxburst = 1; 433 434 cfg.direction = DMA_DEV_TO_MEM; 435 ret = dmaengine_slave_config(dma->chan_rx, &cfg); 436 if (ret) { 437 dev_err(dev, "can't configure rx dma channel\n"); 438 ret = -EINVAL; 439 goto err_slave_config; 440 } 441 442 cfg.direction = DMA_MEM_TO_DEV; 443 ret = dmaengine_slave_config(dma->chan_tx, &cfg); 444 if (ret) { 445 dev_err(dev, "can't configure tx dma channel\n"); 446 ret = -EINVAL; 447 goto err_slave_config; 448 } 449 450 dspi->dma = dma; 451 init_completion(&dma->cmd_tx_complete); 452 init_completion(&dma->cmd_rx_complete); 453 454 return 0; 455 456 err_slave_config: 457 dma_free_coherent(dev, DSPI_DMA_BUFSIZE, 458 dma->rx_dma_buf, dma->rx_dma_phys); 459 err_rx_dma_buf: 460 dma_free_coherent(dev, DSPI_DMA_BUFSIZE, 461 dma->tx_dma_buf, dma->tx_dma_phys); 462 err_tx_dma_buf: 463 dma_release_channel(dma->chan_tx); 464 err_tx_channel: 465 dma_release_channel(dma->chan_rx); 466 467 devm_kfree(dev, dma); 468 dspi->dma = NULL; 469 470 return ret; 471 } 472 473 static void dspi_release_dma(struct fsl_dspi *dspi) 474 { 475 struct fsl_dspi_dma *dma = dspi->dma; 476 struct device *dev = &dspi->pdev->dev; 477 478 if (!dma) 479 return; 480 481 if (dma->chan_tx) { 482 dma_unmap_single(dev, dma->tx_dma_phys, 483 DSPI_DMA_BUFSIZE, DMA_TO_DEVICE); 484 dma_release_channel(dma->chan_tx); 485 } 486 487 if (dma->chan_rx) { 488 dma_unmap_single(dev, dma->rx_dma_phys, 489 DSPI_DMA_BUFSIZE, DMA_FROM_DEVICE); 490 dma_release_channel(dma->chan_rx); 491 } 492 } 493 494 static void hz_to_spi_baud(char *pbr, char *br, int speed_hz, 495 unsigned long clkrate) 496 { 497 /* Valid baud rate pre-scaler values */ 498 int pbr_tbl[4] = {2, 3, 5, 7}; 499 int brs[16] = { 2, 4, 6, 8, 500 16, 32, 64, 128, 501 256, 512, 1024, 2048, 502 4096, 8192, 16384, 32768 }; 503 int scale_needed, scale, minscale = INT_MAX; 504 int i, j; 505 506 scale_needed = clkrate / speed_hz; 507 if (clkrate % speed_hz) 508 scale_needed++; 509 510 for (i = 0; i < ARRAY_SIZE(brs); i++) 511 for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) { 512 scale = brs[i] * pbr_tbl[j]; 513 if (scale >= scale_needed) { 514 if (scale < minscale) { 515 minscale = scale; 516 *br = i; 517 *pbr = j; 518 } 519 break; 520 } 521 } 522 523 if (minscale == INT_MAX) { 524 pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n", 525 speed_hz, clkrate); 526 *pbr = ARRAY_SIZE(pbr_tbl) - 1; 527 *br = ARRAY_SIZE(brs) - 1; 528 } 529 } 530 531 static void ns_delay_scale(char *psc, char *sc, int delay_ns, 532 unsigned long clkrate) 533 { 534 int scale_needed, scale, minscale = INT_MAX; 535 int pscale_tbl[4] = {1, 3, 5, 7}; 536 u32 remainder; 537 int i, j; 538 539 scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC, 540 &remainder); 541 if (remainder) 542 scale_needed++; 543 544 for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++) 545 for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) { 546 scale = pscale_tbl[i] * (2 << j); 547 if (scale >= scale_needed) { 548 if (scale < minscale) { 549 minscale = scale; 550 *psc = i; 551 *sc = j; 552 } 553 break; 554 } 555 } 556 557 if (minscale == INT_MAX) { 558 pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value", 559 delay_ns, clkrate); 560 *psc = ARRAY_SIZE(pscale_tbl) - 1; 561 *sc = SPI_CTAR_SCALE_BITS; 562 } 563 } 564 565 static void fifo_write(struct fsl_dspi *dspi) 566 { 567 regmap_write(dspi->regmap, SPI_PUSHR, dspi_pop_tx_pushr(dspi)); 568 } 569 570 static void cmd_fifo_write(struct fsl_dspi *dspi) 571 { 572 u16 cmd = dspi->tx_cmd; 573 574 if (dspi->len > 0) 575 cmd |= SPI_PUSHR_CMD_CONT; 576 regmap_write(dspi->regmap_pushr, PUSHR_CMD, cmd); 577 } 578 579 static void tx_fifo_write(struct fsl_dspi *dspi, u16 txdata) 580 { 581 regmap_write(dspi->regmap_pushr, PUSHR_TX, txdata); 582 } 583 584 static void dspi_tcfq_write(struct fsl_dspi *dspi) 585 { 586 /* Clear transfer count */ 587 dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT; 588 589 if (dspi->devtype_data->xspi_mode && dspi->bits_per_word > 16) { 590 /* Write the CMD FIFO entry first, and then the two 591 * corresponding TX FIFO entries. 592 */ 593 u32 data = dspi_pop_tx(dspi); 594 595 cmd_fifo_write(dspi); 596 tx_fifo_write(dspi, data & 0xFFFF); 597 tx_fifo_write(dspi, data >> 16); 598 } else { 599 /* Write one entry to both TX FIFO and CMD FIFO 600 * simultaneously. 601 */ 602 fifo_write(dspi); 603 } 604 } 605 606 static u32 fifo_read(struct fsl_dspi *dspi) 607 { 608 u32 rxdata = 0; 609 610 regmap_read(dspi->regmap, SPI_POPR, &rxdata); 611 return rxdata; 612 } 613 614 static void dspi_tcfq_read(struct fsl_dspi *dspi) 615 { 616 dspi_push_rx(dspi, fifo_read(dspi)); 617 } 618 619 static void dspi_eoq_write(struct fsl_dspi *dspi) 620 { 621 int fifo_size = DSPI_FIFO_SIZE; 622 u16 xfer_cmd = dspi->tx_cmd; 623 624 /* Fill TX FIFO with as many transfers as possible */ 625 while (dspi->len && fifo_size--) { 626 dspi->tx_cmd = xfer_cmd; 627 /* Request EOQF for last transfer in FIFO */ 628 if (dspi->len == dspi->bytes_per_word || fifo_size == 0) 629 dspi->tx_cmd |= SPI_PUSHR_CMD_EOQ; 630 /* Clear transfer count for first transfer in FIFO */ 631 if (fifo_size == (DSPI_FIFO_SIZE - 1)) 632 dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT; 633 /* Write combined TX FIFO and CMD FIFO entry */ 634 fifo_write(dspi); 635 } 636 } 637 638 static void dspi_eoq_read(struct fsl_dspi *dspi) 639 { 640 int fifo_size = DSPI_FIFO_SIZE; 641 642 /* Read one FIFO entry and push to rx buffer */ 643 while ((dspi->rx < dspi->rx_end) && fifo_size--) 644 dspi_push_rx(dspi, fifo_read(dspi)); 645 } 646 647 static int dspi_rxtx(struct fsl_dspi *dspi) 648 { 649 struct spi_message *msg = dspi->cur_msg; 650 enum dspi_trans_mode trans_mode; 651 u16 spi_tcnt; 652 u32 spi_tcr; 653 654 spi_take_timestamp_post(dspi->ctlr, dspi->cur_transfer, 655 dspi->progress, !dspi->irq); 656 657 /* Get transfer counter (in number of SPI transfers). It was 658 * reset to 0 when transfer(s) were started. 659 */ 660 regmap_read(dspi->regmap, SPI_TCR, &spi_tcr); 661 spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr); 662 /* Update total number of bytes that were transferred */ 663 msg->actual_length += spi_tcnt * dspi->bytes_per_word; 664 dspi->progress += spi_tcnt; 665 666 trans_mode = dspi->devtype_data->trans_mode; 667 if (trans_mode == DSPI_EOQ_MODE) 668 dspi_eoq_read(dspi); 669 else if (trans_mode == DSPI_TCFQ_MODE) 670 dspi_tcfq_read(dspi); 671 672 if (!dspi->len) 673 /* Success! */ 674 return 0; 675 676 spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer, 677 dspi->progress, !dspi->irq); 678 679 if (trans_mode == DSPI_EOQ_MODE) 680 dspi_eoq_write(dspi); 681 else if (trans_mode == DSPI_TCFQ_MODE) 682 dspi_tcfq_write(dspi); 683 684 return -EINPROGRESS; 685 } 686 687 static int dspi_poll(struct fsl_dspi *dspi) 688 { 689 int tries = 1000; 690 u32 spi_sr; 691 692 do { 693 regmap_read(dspi->regmap, SPI_SR, &spi_sr); 694 regmap_write(dspi->regmap, SPI_SR, spi_sr); 695 696 if (spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF)) 697 break; 698 } while (--tries); 699 700 if (!tries) 701 return -ETIMEDOUT; 702 703 return dspi_rxtx(dspi); 704 } 705 706 static irqreturn_t dspi_interrupt(int irq, void *dev_id) 707 { 708 struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id; 709 u32 spi_sr; 710 711 regmap_read(dspi->regmap, SPI_SR, &spi_sr); 712 regmap_write(dspi->regmap, SPI_SR, spi_sr); 713 714 if (!(spi_sr & SPI_SR_EOQF)) 715 return IRQ_NONE; 716 717 if (dspi_rxtx(dspi) == 0) { 718 dspi->waitflags = 1; 719 wake_up_interruptible(&dspi->waitq); 720 } 721 722 return IRQ_HANDLED; 723 } 724 725 static int dspi_transfer_one_message(struct spi_controller *ctlr, 726 struct spi_message *message) 727 { 728 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr); 729 struct spi_device *spi = message->spi; 730 enum dspi_trans_mode trans_mode; 731 struct spi_transfer *transfer; 732 int status = 0; 733 734 message->actual_length = 0; 735 736 list_for_each_entry(transfer, &message->transfers, transfer_list) { 737 dspi->cur_transfer = transfer; 738 dspi->cur_msg = message; 739 dspi->cur_chip = spi_get_ctldata(spi); 740 /* Prepare command word for CMD FIFO */ 741 dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0) | 742 SPI_PUSHR_CMD_PCS(spi->chip_select); 743 if (list_is_last(&dspi->cur_transfer->transfer_list, 744 &dspi->cur_msg->transfers)) { 745 /* Leave PCS activated after last transfer when 746 * cs_change is set. 747 */ 748 if (transfer->cs_change) 749 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT; 750 } else { 751 /* Keep PCS active between transfers in same message 752 * when cs_change is not set, and de-activate PCS 753 * between transfers in the same message when 754 * cs_change is set. 755 */ 756 if (!transfer->cs_change) 757 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT; 758 } 759 760 dspi->void_write_data = dspi->cur_chip->void_write_data; 761 762 dspi->tx = transfer->tx_buf; 763 dspi->rx = transfer->rx_buf; 764 dspi->rx_end = dspi->rx + transfer->len; 765 dspi->len = transfer->len; 766 dspi->progress = 0; 767 /* Validated transfer specific frame size (defaults applied) */ 768 dspi->bits_per_word = transfer->bits_per_word; 769 if (transfer->bits_per_word <= 8) 770 dspi->bytes_per_word = 1; 771 else if (transfer->bits_per_word <= 16) 772 dspi->bytes_per_word = 2; 773 else 774 dspi->bytes_per_word = 4; 775 776 regmap_update_bits(dspi->regmap, SPI_MCR, 777 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF, 778 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF); 779 regmap_write(dspi->regmap, SPI_CTAR(0), 780 dspi->cur_chip->ctar_val | 781 SPI_FRAME_BITS(transfer->bits_per_word)); 782 if (dspi->devtype_data->xspi_mode) 783 regmap_write(dspi->regmap, SPI_CTARE(0), 784 SPI_FRAME_EBITS(transfer->bits_per_word) | 785 SPI_CTARE_DTCP(1)); 786 787 spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer, 788 dspi->progress, !dspi->irq); 789 790 trans_mode = dspi->devtype_data->trans_mode; 791 switch (trans_mode) { 792 case DSPI_EOQ_MODE: 793 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE); 794 dspi_eoq_write(dspi); 795 break; 796 case DSPI_TCFQ_MODE: 797 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TCFQE); 798 dspi_tcfq_write(dspi); 799 break; 800 case DSPI_DMA_MODE: 801 regmap_write(dspi->regmap, SPI_RSER, 802 SPI_RSER_TFFFE | SPI_RSER_TFFFD | 803 SPI_RSER_RFDFE | SPI_RSER_RFDFD); 804 status = dspi_dma_xfer(dspi); 805 break; 806 default: 807 dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n", 808 trans_mode); 809 status = -EINVAL; 810 goto out; 811 } 812 813 if (!dspi->irq) { 814 do { 815 status = dspi_poll(dspi); 816 } while (status == -EINPROGRESS); 817 } else if (trans_mode != DSPI_DMA_MODE) { 818 status = wait_event_interruptible(dspi->waitq, 819 dspi->waitflags); 820 dspi->waitflags = 0; 821 } 822 if (status) 823 dev_err(&dspi->pdev->dev, 824 "Waiting for transfer to complete failed!\n"); 825 826 spi_transfer_delay_exec(transfer); 827 } 828 829 out: 830 message->status = status; 831 spi_finalize_current_message(ctlr); 832 833 return status; 834 } 835 836 static int dspi_setup(struct spi_device *spi) 837 { 838 struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller); 839 unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0; 840 u32 cs_sck_delay = 0, sck_cs_delay = 0; 841 struct fsl_dspi_platform_data *pdata; 842 unsigned char pasc = 0, asc = 0; 843 struct chip_data *chip; 844 unsigned long clkrate; 845 846 /* Only alloc on first setup */ 847 chip = spi_get_ctldata(spi); 848 if (chip == NULL) { 849 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 850 if (!chip) 851 return -ENOMEM; 852 } 853 854 pdata = dev_get_platdata(&dspi->pdev->dev); 855 856 if (!pdata) { 857 of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay", 858 &cs_sck_delay); 859 860 of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay", 861 &sck_cs_delay); 862 } else { 863 cs_sck_delay = pdata->cs_sck_delay; 864 sck_cs_delay = pdata->sck_cs_delay; 865 } 866 867 chip->void_write_data = 0; 868 869 clkrate = clk_get_rate(dspi->clk); 870 hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate); 871 872 /* Set PCS to SCK delay scale values */ 873 ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate); 874 875 /* Set After SCK delay scale values */ 876 ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate); 877 878 chip->ctar_val = 0; 879 if (spi->mode & SPI_CPOL) 880 chip->ctar_val |= SPI_CTAR_CPOL; 881 if (spi->mode & SPI_CPHA) 882 chip->ctar_val |= SPI_CTAR_CPHA; 883 884 if (!spi_controller_is_slave(dspi->ctlr)) { 885 chip->ctar_val |= SPI_CTAR_PCSSCK(pcssck) | 886 SPI_CTAR_CSSCK(cssck) | 887 SPI_CTAR_PASC(pasc) | 888 SPI_CTAR_ASC(asc) | 889 SPI_CTAR_PBR(pbr) | 890 SPI_CTAR_BR(br); 891 892 if (spi->mode & SPI_LSB_FIRST) 893 chip->ctar_val |= SPI_CTAR_LSBFE; 894 } 895 896 spi_set_ctldata(spi, chip); 897 898 return 0; 899 } 900 901 static void dspi_cleanup(struct spi_device *spi) 902 { 903 struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi); 904 905 dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n", 906 spi->controller->bus_num, spi->chip_select); 907 908 kfree(chip); 909 } 910 911 static const struct of_device_id fsl_dspi_dt_ids[] = { 912 { .compatible = "fsl,vf610-dspi", .data = &vf610_data, }, 913 { .compatible = "fsl,ls1021a-v1.0-dspi", .data = &ls1021a_v1_data, }, 914 { .compatible = "fsl,ls2085a-dspi", .data = &ls2085a_data, }, 915 { /* sentinel */ } 916 }; 917 MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids); 918 919 #ifdef CONFIG_PM_SLEEP 920 static int dspi_suspend(struct device *dev) 921 { 922 struct spi_controller *ctlr = dev_get_drvdata(dev); 923 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr); 924 925 spi_controller_suspend(ctlr); 926 clk_disable_unprepare(dspi->clk); 927 928 pinctrl_pm_select_sleep_state(dev); 929 930 return 0; 931 } 932 933 static int dspi_resume(struct device *dev) 934 { 935 struct spi_controller *ctlr = dev_get_drvdata(dev); 936 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr); 937 int ret; 938 939 pinctrl_pm_select_default_state(dev); 940 941 ret = clk_prepare_enable(dspi->clk); 942 if (ret) 943 return ret; 944 spi_controller_resume(ctlr); 945 946 return 0; 947 } 948 #endif /* CONFIG_PM_SLEEP */ 949 950 static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume); 951 952 static const struct regmap_range dspi_volatile_ranges[] = { 953 regmap_reg_range(SPI_MCR, SPI_TCR), 954 regmap_reg_range(SPI_SR, SPI_SR), 955 regmap_reg_range(SPI_PUSHR, SPI_RXFR3), 956 }; 957 958 static const struct regmap_access_table dspi_volatile_table = { 959 .yes_ranges = dspi_volatile_ranges, 960 .n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges), 961 }; 962 963 static const struct regmap_config dspi_regmap_config = { 964 .reg_bits = 32, 965 .val_bits = 32, 966 .reg_stride = 4, 967 .max_register = 0x88, 968 .volatile_table = &dspi_volatile_table, 969 }; 970 971 static const struct regmap_range dspi_xspi_volatile_ranges[] = { 972 regmap_reg_range(SPI_MCR, SPI_TCR), 973 regmap_reg_range(SPI_SR, SPI_SR), 974 regmap_reg_range(SPI_PUSHR, SPI_RXFR3), 975 regmap_reg_range(SPI_SREX, SPI_SREX), 976 }; 977 978 static const struct regmap_access_table dspi_xspi_volatile_table = { 979 .yes_ranges = dspi_xspi_volatile_ranges, 980 .n_yes_ranges = ARRAY_SIZE(dspi_xspi_volatile_ranges), 981 }; 982 983 static const struct regmap_config dspi_xspi_regmap_config[] = { 984 { 985 .reg_bits = 32, 986 .val_bits = 32, 987 .reg_stride = 4, 988 .max_register = 0x13c, 989 .volatile_table = &dspi_xspi_volatile_table, 990 }, 991 { 992 .name = "pushr", 993 .reg_bits = 16, 994 .val_bits = 16, 995 .reg_stride = 2, 996 .max_register = 0x2, 997 }, 998 }; 999 1000 static void dspi_init(struct fsl_dspi *dspi) 1001 { 1002 unsigned int mcr = SPI_MCR_PCSIS; 1003 1004 if (dspi->devtype_data->xspi_mode) 1005 mcr |= SPI_MCR_XSPI; 1006 if (!spi_controller_is_slave(dspi->ctlr)) 1007 mcr |= SPI_MCR_MASTER; 1008 1009 regmap_write(dspi->regmap, SPI_MCR, mcr); 1010 regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR); 1011 if (dspi->devtype_data->xspi_mode) 1012 regmap_write(dspi->regmap, SPI_CTARE(0), 1013 SPI_CTARE_FMSZE(0) | SPI_CTARE_DTCP(1)); 1014 } 1015 1016 static int dspi_slave_abort(struct spi_master *master) 1017 { 1018 struct fsl_dspi *dspi = spi_master_get_devdata(master); 1019 1020 /* 1021 * Terminate all pending DMA transactions for the SPI working 1022 * in SLAVE mode. 1023 */ 1024 dmaengine_terminate_sync(dspi->dma->chan_rx); 1025 dmaengine_terminate_sync(dspi->dma->chan_tx); 1026 1027 /* Clear the internal DSPI RX and TX FIFO buffers */ 1028 regmap_update_bits(dspi->regmap, SPI_MCR, 1029 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF, 1030 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF); 1031 1032 return 0; 1033 } 1034 1035 static int dspi_probe(struct platform_device *pdev) 1036 { 1037 struct device_node *np = pdev->dev.of_node; 1038 const struct regmap_config *regmap_config; 1039 struct fsl_dspi_platform_data *pdata; 1040 struct spi_controller *ctlr; 1041 int ret, cs_num, bus_num; 1042 struct fsl_dspi *dspi; 1043 struct resource *res; 1044 void __iomem *base; 1045 1046 ctlr = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi)); 1047 if (!ctlr) 1048 return -ENOMEM; 1049 1050 dspi = spi_controller_get_devdata(ctlr); 1051 dspi->pdev = pdev; 1052 dspi->ctlr = ctlr; 1053 1054 ctlr->setup = dspi_setup; 1055 ctlr->transfer_one_message = dspi_transfer_one_message; 1056 ctlr->dev.of_node = pdev->dev.of_node; 1057 1058 ctlr->cleanup = dspi_cleanup; 1059 ctlr->slave_abort = dspi_slave_abort; 1060 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; 1061 1062 pdata = dev_get_platdata(&pdev->dev); 1063 if (pdata) { 1064 ctlr->num_chipselect = pdata->cs_num; 1065 ctlr->bus_num = pdata->bus_num; 1066 1067 dspi->devtype_data = &coldfire_data; 1068 } else { 1069 1070 ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num); 1071 if (ret < 0) { 1072 dev_err(&pdev->dev, "can't get spi-num-chipselects\n"); 1073 goto out_ctlr_put; 1074 } 1075 ctlr->num_chipselect = cs_num; 1076 1077 ret = of_property_read_u32(np, "bus-num", &bus_num); 1078 if (ret < 0) { 1079 dev_err(&pdev->dev, "can't get bus-num\n"); 1080 goto out_ctlr_put; 1081 } 1082 ctlr->bus_num = bus_num; 1083 1084 if (of_property_read_bool(np, "spi-slave")) 1085 ctlr->slave = true; 1086 1087 dspi->devtype_data = of_device_get_match_data(&pdev->dev); 1088 if (!dspi->devtype_data) { 1089 dev_err(&pdev->dev, "can't get devtype_data\n"); 1090 ret = -EFAULT; 1091 goto out_ctlr_put; 1092 } 1093 } 1094 1095 if (dspi->devtype_data->xspi_mode) 1096 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1097 else 1098 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); 1099 1100 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1101 base = devm_ioremap_resource(&pdev->dev, res); 1102 if (IS_ERR(base)) { 1103 ret = PTR_ERR(base); 1104 goto out_ctlr_put; 1105 } 1106 1107 if (dspi->devtype_data->xspi_mode) 1108 regmap_config = &dspi_xspi_regmap_config[0]; 1109 else 1110 regmap_config = &dspi_regmap_config; 1111 dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base, regmap_config); 1112 if (IS_ERR(dspi->regmap)) { 1113 dev_err(&pdev->dev, "failed to init regmap: %ld\n", 1114 PTR_ERR(dspi->regmap)); 1115 ret = PTR_ERR(dspi->regmap); 1116 goto out_ctlr_put; 1117 } 1118 1119 if (dspi->devtype_data->xspi_mode) { 1120 dspi->regmap_pushr = devm_regmap_init_mmio( 1121 &pdev->dev, base + SPI_PUSHR, 1122 &dspi_xspi_regmap_config[1]); 1123 if (IS_ERR(dspi->regmap_pushr)) { 1124 dev_err(&pdev->dev, 1125 "failed to init pushr regmap: %ld\n", 1126 PTR_ERR(dspi->regmap_pushr)); 1127 ret = PTR_ERR(dspi->regmap_pushr); 1128 goto out_ctlr_put; 1129 } 1130 } 1131 1132 dspi->clk = devm_clk_get(&pdev->dev, "dspi"); 1133 if (IS_ERR(dspi->clk)) { 1134 ret = PTR_ERR(dspi->clk); 1135 dev_err(&pdev->dev, "unable to get clock\n"); 1136 goto out_ctlr_put; 1137 } 1138 ret = clk_prepare_enable(dspi->clk); 1139 if (ret) 1140 goto out_ctlr_put; 1141 1142 dspi_init(dspi); 1143 1144 if (dspi->devtype_data->trans_mode == DSPI_TCFQ_MODE) 1145 goto poll_mode; 1146 1147 dspi->irq = platform_get_irq(pdev, 0); 1148 if (dspi->irq <= 0) { 1149 dev_info(&pdev->dev, 1150 "can't get platform irq, using poll mode\n"); 1151 dspi->irq = 0; 1152 goto poll_mode; 1153 } 1154 1155 ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 1156 IRQF_SHARED, pdev->name, dspi); 1157 if (ret < 0) { 1158 dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n"); 1159 goto out_clk_put; 1160 } 1161 1162 init_waitqueue_head(&dspi->waitq); 1163 1164 poll_mode: 1165 1166 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) { 1167 ret = dspi_request_dma(dspi, res->start); 1168 if (ret < 0) { 1169 dev_err(&pdev->dev, "can't get dma channels\n"); 1170 goto out_clk_put; 1171 } 1172 } 1173 1174 ctlr->max_speed_hz = 1175 clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor; 1176 1177 ctlr->ptp_sts_supported = dspi->devtype_data->ptp_sts_supported; 1178 1179 platform_set_drvdata(pdev, ctlr); 1180 1181 ret = spi_register_controller(ctlr); 1182 if (ret != 0) { 1183 dev_err(&pdev->dev, "Problem registering DSPI ctlr\n"); 1184 goto out_clk_put; 1185 } 1186 1187 return ret; 1188 1189 out_clk_put: 1190 clk_disable_unprepare(dspi->clk); 1191 out_ctlr_put: 1192 spi_controller_put(ctlr); 1193 1194 return ret; 1195 } 1196 1197 static int dspi_remove(struct platform_device *pdev) 1198 { 1199 struct spi_controller *ctlr = platform_get_drvdata(pdev); 1200 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr); 1201 1202 /* Disconnect from the SPI framework */ 1203 dspi_release_dma(dspi); 1204 clk_disable_unprepare(dspi->clk); 1205 spi_unregister_controller(dspi->ctlr); 1206 1207 return 0; 1208 } 1209 1210 static struct platform_driver fsl_dspi_driver = { 1211 .driver.name = DRIVER_NAME, 1212 .driver.of_match_table = fsl_dspi_dt_ids, 1213 .driver.owner = THIS_MODULE, 1214 .driver.pm = &dspi_pm, 1215 .probe = dspi_probe, 1216 .remove = dspi_remove, 1217 }; 1218 module_platform_driver(fsl_dspi_driver); 1219 1220 MODULE_DESCRIPTION("Freescale DSPI Controller Driver"); 1221 MODULE_LICENSE("GPL"); 1222 MODULE_ALIAS("platform:" DRIVER_NAME); 1223