1 // SPDX-License-Identifier: GPL-2.0-or-later 2 // Copyright (C) IBM Corporation 2020 3 4 #include <linux/bitfield.h> 5 #include <linux/bits.h> 6 #include <linux/fsi.h> 7 #include <linux/jiffies.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/spi/spi.h> 12 13 #define FSI_ENGID_SPI 0x23 14 #define FSI_MBOX_ROOT_CTRL_8 0x2860 15 #define FSI_MBOX_ROOT_CTRL_8_SPI_MUX 0xf0000000 16 17 #define FSI2SPI_DATA0 0x00 18 #define FSI2SPI_DATA1 0x04 19 #define FSI2SPI_CMD 0x08 20 #define FSI2SPI_CMD_WRITE BIT(31) 21 #define FSI2SPI_RESET 0x18 22 #define FSI2SPI_STATUS 0x1c 23 #define FSI2SPI_STATUS_ANY_ERROR BIT(31) 24 #define FSI2SPI_IRQ 0x20 25 26 #define SPI_FSI_BASE 0x70000 27 #define SPI_FSI_INIT_TIMEOUT_MS 1000 28 #define SPI_FSI_MAX_XFR_SIZE 2048 29 #define SPI_FSI_MAX_XFR_SIZE_RESTRICTED 8 30 31 #define SPI_FSI_ERROR 0x0 32 #define SPI_FSI_COUNTER_CFG 0x1 33 #define SPI_FSI_COUNTER_CFG_LOOPS(x) (((u64)(x) & 0xffULL) << 32) 34 #define SPI_FSI_COUNTER_CFG_N2_RX BIT_ULL(8) 35 #define SPI_FSI_COUNTER_CFG_N2_TX BIT_ULL(9) 36 #define SPI_FSI_COUNTER_CFG_N2_IMPLICIT BIT_ULL(10) 37 #define SPI_FSI_COUNTER_CFG_N2_RELOAD BIT_ULL(11) 38 #define SPI_FSI_CFG1 0x2 39 #define SPI_FSI_CLOCK_CFG 0x3 40 #define SPI_FSI_CLOCK_CFG_MM_ENABLE BIT_ULL(32) 41 #define SPI_FSI_CLOCK_CFG_ECC_DISABLE (BIT_ULL(35) | BIT_ULL(33)) 42 #define SPI_FSI_CLOCK_CFG_RESET1 (BIT_ULL(36) | BIT_ULL(38)) 43 #define SPI_FSI_CLOCK_CFG_RESET2 (BIT_ULL(37) | BIT_ULL(39)) 44 #define SPI_FSI_CLOCK_CFG_MODE (BIT_ULL(41) | BIT_ULL(42)) 45 #define SPI_FSI_CLOCK_CFG_SCK_RECV_DEL GENMASK_ULL(51, 44) 46 #define SPI_FSI_CLOCK_CFG_SCK_NO_DEL BIT_ULL(51) 47 #define SPI_FSI_CLOCK_CFG_SCK_DIV GENMASK_ULL(63, 52) 48 #define SPI_FSI_MMAP 0x4 49 #define SPI_FSI_DATA_TX 0x5 50 #define SPI_FSI_DATA_RX 0x6 51 #define SPI_FSI_SEQUENCE 0x7 52 #define SPI_FSI_SEQUENCE_STOP 0x00 53 #define SPI_FSI_SEQUENCE_SEL_SLAVE(x) (0x10 | ((x) & 0xf)) 54 #define SPI_FSI_SEQUENCE_SHIFT_OUT(x) (0x30 | ((x) & 0xf)) 55 #define SPI_FSI_SEQUENCE_SHIFT_IN(x) (0x40 | ((x) & 0xf)) 56 #define SPI_FSI_SEQUENCE_COPY_DATA_TX 0xc0 57 #define SPI_FSI_SEQUENCE_BRANCH(x) (0xe0 | ((x) & 0xf)) 58 #define SPI_FSI_STATUS 0x8 59 #define SPI_FSI_STATUS_ERROR \ 60 (GENMASK_ULL(31, 21) | GENMASK_ULL(15, 12)) 61 #define SPI_FSI_STATUS_SEQ_STATE GENMASK_ULL(55, 48) 62 #define SPI_FSI_STATUS_SEQ_STATE_IDLE BIT_ULL(48) 63 #define SPI_FSI_STATUS_TDR_UNDERRUN BIT_ULL(57) 64 #define SPI_FSI_STATUS_TDR_OVERRUN BIT_ULL(58) 65 #define SPI_FSI_STATUS_TDR_FULL BIT_ULL(59) 66 #define SPI_FSI_STATUS_RDR_UNDERRUN BIT_ULL(61) 67 #define SPI_FSI_STATUS_RDR_OVERRUN BIT_ULL(62) 68 #define SPI_FSI_STATUS_RDR_FULL BIT_ULL(63) 69 #define SPI_FSI_STATUS_ANY_ERROR \ 70 (SPI_FSI_STATUS_ERROR | \ 71 SPI_FSI_STATUS_TDR_OVERRUN | SPI_FSI_STATUS_RDR_UNDERRUN | \ 72 SPI_FSI_STATUS_RDR_OVERRUN) 73 #define SPI_FSI_PORT_CTRL 0x9 74 75 struct fsi_spi { 76 struct device *dev; /* SPI controller device */ 77 struct fsi_device *fsi; /* FSI2SPI CFAM engine device */ 78 u32 base; 79 size_t max_xfr_size; 80 bool restricted; 81 }; 82 83 struct fsi_spi_sequence { 84 int bit; 85 u64 data; 86 }; 87 88 static int fsi_spi_check_mux(struct fsi_device *fsi, struct device *dev) 89 { 90 int rc; 91 u32 root_ctrl_8; 92 __be32 root_ctrl_8_be; 93 94 rc = fsi_slave_read(fsi->slave, FSI_MBOX_ROOT_CTRL_8, &root_ctrl_8_be, 95 sizeof(root_ctrl_8_be)); 96 if (rc) 97 return rc; 98 99 root_ctrl_8 = be32_to_cpu(root_ctrl_8_be); 100 dev_dbg(dev, "Root control register 8: %08x\n", root_ctrl_8); 101 if ((root_ctrl_8 & FSI_MBOX_ROOT_CTRL_8_SPI_MUX) == 102 FSI_MBOX_ROOT_CTRL_8_SPI_MUX) 103 return 0; 104 105 return -ENOLINK; 106 } 107 108 static int fsi_spi_check_status(struct fsi_spi *ctx) 109 { 110 int rc; 111 u32 sts; 112 __be32 sts_be; 113 114 rc = fsi_device_read(ctx->fsi, FSI2SPI_STATUS, &sts_be, 115 sizeof(sts_be)); 116 if (rc) 117 return rc; 118 119 sts = be32_to_cpu(sts_be); 120 if (sts & FSI2SPI_STATUS_ANY_ERROR) { 121 dev_err(ctx->dev, "Error with FSI2SPI interface: %08x.\n", sts); 122 return -EIO; 123 } 124 125 return 0; 126 } 127 128 static int fsi_spi_read_reg(struct fsi_spi *ctx, u32 offset, u64 *value) 129 { 130 int rc; 131 __be32 cmd_be; 132 __be32 data_be; 133 u32 cmd = offset + ctx->base; 134 135 *value = 0ULL; 136 137 if (cmd & FSI2SPI_CMD_WRITE) 138 return -EINVAL; 139 140 cmd_be = cpu_to_be32(cmd); 141 rc = fsi_device_write(ctx->fsi, FSI2SPI_CMD, &cmd_be, sizeof(cmd_be)); 142 if (rc) 143 return rc; 144 145 rc = fsi_spi_check_status(ctx); 146 if (rc) 147 return rc; 148 149 rc = fsi_device_read(ctx->fsi, FSI2SPI_DATA0, &data_be, 150 sizeof(data_be)); 151 if (rc) 152 return rc; 153 154 *value |= (u64)be32_to_cpu(data_be) << 32; 155 156 rc = fsi_device_read(ctx->fsi, FSI2SPI_DATA1, &data_be, 157 sizeof(data_be)); 158 if (rc) 159 return rc; 160 161 *value |= (u64)be32_to_cpu(data_be); 162 dev_dbg(ctx->dev, "Read %02x[%016llx].\n", offset, *value); 163 164 return 0; 165 } 166 167 static int fsi_spi_write_reg(struct fsi_spi *ctx, u32 offset, u64 value) 168 { 169 int rc; 170 __be32 cmd_be; 171 __be32 data_be; 172 u32 cmd = offset + ctx->base; 173 174 if (cmd & FSI2SPI_CMD_WRITE) 175 return -EINVAL; 176 177 dev_dbg(ctx->dev, "Write %02x[%016llx].\n", offset, value); 178 179 data_be = cpu_to_be32(upper_32_bits(value)); 180 rc = fsi_device_write(ctx->fsi, FSI2SPI_DATA0, &data_be, 181 sizeof(data_be)); 182 if (rc) 183 return rc; 184 185 data_be = cpu_to_be32(lower_32_bits(value)); 186 rc = fsi_device_write(ctx->fsi, FSI2SPI_DATA1, &data_be, 187 sizeof(data_be)); 188 if (rc) 189 return rc; 190 191 cmd_be = cpu_to_be32(cmd | FSI2SPI_CMD_WRITE); 192 rc = fsi_device_write(ctx->fsi, FSI2SPI_CMD, &cmd_be, sizeof(cmd_be)); 193 if (rc) 194 return rc; 195 196 return fsi_spi_check_status(ctx); 197 } 198 199 static int fsi_spi_data_in(u64 in, u8 *rx, int len) 200 { 201 int i; 202 int num_bytes = min(len, 8); 203 204 for (i = 0; i < num_bytes; ++i) 205 rx[i] = (u8)(in >> (8 * ((num_bytes - 1) - i))); 206 207 return num_bytes; 208 } 209 210 static int fsi_spi_data_out(u64 *out, const u8 *tx, int len) 211 { 212 int i; 213 int num_bytes = min(len, 8); 214 u8 *out_bytes = (u8 *)out; 215 216 /* Unused bytes of the tx data should be 0. */ 217 *out = 0ULL; 218 219 for (i = 0; i < num_bytes; ++i) 220 out_bytes[8 - (i + 1)] = tx[i]; 221 222 return num_bytes; 223 } 224 225 static int fsi_spi_reset(struct fsi_spi *ctx) 226 { 227 int rc; 228 229 dev_dbg(ctx->dev, "Resetting SPI controller.\n"); 230 231 rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG, 232 SPI_FSI_CLOCK_CFG_RESET1); 233 if (rc) 234 return rc; 235 236 rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG, 237 SPI_FSI_CLOCK_CFG_RESET2); 238 if (rc) 239 return rc; 240 241 return fsi_spi_write_reg(ctx, SPI_FSI_STATUS, 0ULL); 242 } 243 244 static int fsi_spi_sequence_add(struct fsi_spi_sequence *seq, u8 val) 245 { 246 /* 247 * Add the next byte of instruction to the 8-byte sequence register. 248 * Then decrement the counter so that the next instruction will go in 249 * the right place. Return the index of the slot we just filled in the 250 * sequence register. 251 */ 252 seq->data |= (u64)val << seq->bit; 253 seq->bit -= 8; 254 255 return ((64 - seq->bit) / 8) - 2; 256 } 257 258 static void fsi_spi_sequence_init(struct fsi_spi_sequence *seq) 259 { 260 seq->bit = 56; 261 seq->data = 0ULL; 262 } 263 264 static int fsi_spi_sequence_transfer(struct fsi_spi *ctx, 265 struct fsi_spi_sequence *seq, 266 struct spi_transfer *transfer) 267 { 268 int loops; 269 int idx; 270 int rc; 271 u8 val = 0; 272 u8 len = min(transfer->len, 8U); 273 u8 rem = transfer->len % len; 274 275 loops = transfer->len / len; 276 277 if (transfer->tx_buf) { 278 val = SPI_FSI_SEQUENCE_SHIFT_OUT(len); 279 idx = fsi_spi_sequence_add(seq, val); 280 281 if (rem) 282 rem = SPI_FSI_SEQUENCE_SHIFT_OUT(rem); 283 } else if (transfer->rx_buf) { 284 val = SPI_FSI_SEQUENCE_SHIFT_IN(len); 285 idx = fsi_spi_sequence_add(seq, val); 286 287 if (rem) 288 rem = SPI_FSI_SEQUENCE_SHIFT_IN(rem); 289 } else { 290 return -EINVAL; 291 } 292 293 if (ctx->restricted && loops > 1) { 294 dev_warn(ctx->dev, 295 "Transfer too large; no branches permitted.\n"); 296 return -EINVAL; 297 } 298 299 if (loops > 1) { 300 u64 cfg = SPI_FSI_COUNTER_CFG_LOOPS(loops - 1); 301 302 fsi_spi_sequence_add(seq, SPI_FSI_SEQUENCE_BRANCH(idx)); 303 304 if (transfer->rx_buf) 305 cfg |= SPI_FSI_COUNTER_CFG_N2_RX | 306 SPI_FSI_COUNTER_CFG_N2_TX | 307 SPI_FSI_COUNTER_CFG_N2_IMPLICIT | 308 SPI_FSI_COUNTER_CFG_N2_RELOAD; 309 310 rc = fsi_spi_write_reg(ctx, SPI_FSI_COUNTER_CFG, cfg); 311 if (rc) 312 return rc; 313 } else { 314 fsi_spi_write_reg(ctx, SPI_FSI_COUNTER_CFG, 0ULL); 315 } 316 317 if (rem) 318 fsi_spi_sequence_add(seq, rem); 319 320 return 0; 321 } 322 323 static int fsi_spi_transfer_data(struct fsi_spi *ctx, 324 struct spi_transfer *transfer) 325 { 326 int rc = 0; 327 u64 status = 0ULL; 328 u64 cfg = 0ULL; 329 330 if (transfer->tx_buf) { 331 int nb; 332 int sent = 0; 333 u64 out = 0ULL; 334 const u8 *tx = transfer->tx_buf; 335 336 while (transfer->len > sent) { 337 nb = fsi_spi_data_out(&out, &tx[sent], 338 (int)transfer->len - sent); 339 340 rc = fsi_spi_write_reg(ctx, SPI_FSI_DATA_TX, out); 341 if (rc) 342 return rc; 343 344 do { 345 rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS, 346 &status); 347 if (rc) 348 return rc; 349 350 if (status & SPI_FSI_STATUS_ANY_ERROR) { 351 rc = fsi_spi_reset(ctx); 352 if (rc) 353 return rc; 354 355 return -EREMOTEIO; 356 } 357 } while (status & SPI_FSI_STATUS_TDR_FULL); 358 359 sent += nb; 360 } 361 } else if (transfer->rx_buf) { 362 int recv = 0; 363 u64 in = 0ULL; 364 u8 *rx = transfer->rx_buf; 365 366 rc = fsi_spi_read_reg(ctx, SPI_FSI_COUNTER_CFG, &cfg); 367 if (rc) 368 return rc; 369 370 if (cfg & SPI_FSI_COUNTER_CFG_N2_IMPLICIT) { 371 rc = fsi_spi_write_reg(ctx, SPI_FSI_DATA_TX, 0); 372 if (rc) 373 return rc; 374 } 375 376 while (transfer->len > recv) { 377 do { 378 rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS, 379 &status); 380 if (rc) 381 return rc; 382 383 if (status & SPI_FSI_STATUS_ANY_ERROR) { 384 rc = fsi_spi_reset(ctx); 385 if (rc) 386 return rc; 387 388 return -EREMOTEIO; 389 } 390 } while (!(status & SPI_FSI_STATUS_RDR_FULL)); 391 392 rc = fsi_spi_read_reg(ctx, SPI_FSI_DATA_RX, &in); 393 if (rc) 394 return rc; 395 396 recv += fsi_spi_data_in(in, &rx[recv], 397 (int)transfer->len - recv); 398 } 399 } 400 401 return 0; 402 } 403 404 static int fsi_spi_transfer_init(struct fsi_spi *ctx) 405 { 406 int rc; 407 bool reset = false; 408 unsigned long end; 409 u64 seq_state; 410 u64 clock_cfg = 0ULL; 411 u64 status = 0ULL; 412 u64 wanted_clock_cfg = SPI_FSI_CLOCK_CFG_ECC_DISABLE | 413 SPI_FSI_CLOCK_CFG_SCK_NO_DEL | 414 FIELD_PREP(SPI_FSI_CLOCK_CFG_SCK_DIV, 19); 415 416 end = jiffies + msecs_to_jiffies(SPI_FSI_INIT_TIMEOUT_MS); 417 do { 418 if (time_after(jiffies, end)) 419 return -ETIMEDOUT; 420 421 rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS, &status); 422 if (rc) 423 return rc; 424 425 seq_state = status & SPI_FSI_STATUS_SEQ_STATE; 426 427 if (status & (SPI_FSI_STATUS_ANY_ERROR | 428 SPI_FSI_STATUS_TDR_FULL | 429 SPI_FSI_STATUS_RDR_FULL)) { 430 if (reset) 431 return -EIO; 432 433 rc = fsi_spi_reset(ctx); 434 if (rc) 435 return rc; 436 437 reset = true; 438 continue; 439 } 440 } while (seq_state && (seq_state != SPI_FSI_STATUS_SEQ_STATE_IDLE)); 441 442 rc = fsi_spi_read_reg(ctx, SPI_FSI_CLOCK_CFG, &clock_cfg); 443 if (rc) 444 return rc; 445 446 if ((clock_cfg & (SPI_FSI_CLOCK_CFG_MM_ENABLE | 447 SPI_FSI_CLOCK_CFG_ECC_DISABLE | 448 SPI_FSI_CLOCK_CFG_MODE | 449 SPI_FSI_CLOCK_CFG_SCK_RECV_DEL | 450 SPI_FSI_CLOCK_CFG_SCK_DIV)) != wanted_clock_cfg) 451 rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG, 452 wanted_clock_cfg); 453 454 return rc; 455 } 456 457 static int fsi_spi_transfer_one_message(struct spi_controller *ctlr, 458 struct spi_message *mesg) 459 { 460 int rc; 461 u8 seq_slave = SPI_FSI_SEQUENCE_SEL_SLAVE(mesg->spi->chip_select + 1); 462 struct spi_transfer *transfer; 463 struct fsi_spi *ctx = spi_controller_get_devdata(ctlr); 464 465 rc = fsi_spi_check_mux(ctx->fsi, ctx->dev); 466 if (rc) 467 goto error; 468 469 list_for_each_entry(transfer, &mesg->transfers, transfer_list) { 470 struct fsi_spi_sequence seq; 471 struct spi_transfer *next = NULL; 472 473 /* Sequencer must do shift out (tx) first. */ 474 if (!transfer->tx_buf || 475 transfer->len > (ctx->max_xfr_size + 8)) { 476 rc = -EINVAL; 477 goto error; 478 } 479 480 dev_dbg(ctx->dev, "Start tx of %d bytes.\n", transfer->len); 481 482 rc = fsi_spi_transfer_init(ctx); 483 if (rc < 0) 484 goto error; 485 486 fsi_spi_sequence_init(&seq); 487 fsi_spi_sequence_add(&seq, seq_slave); 488 489 rc = fsi_spi_sequence_transfer(ctx, &seq, transfer); 490 if (rc) 491 goto error; 492 493 if (!list_is_last(&transfer->transfer_list, 494 &mesg->transfers)) { 495 next = list_next_entry(transfer, transfer_list); 496 497 /* Sequencer can only do shift in (rx) after tx. */ 498 if (next->rx_buf) { 499 if (next->len > ctx->max_xfr_size) { 500 rc = -EINVAL; 501 goto error; 502 } 503 504 dev_dbg(ctx->dev, "Sequence rx of %d bytes.\n", 505 next->len); 506 507 rc = fsi_spi_sequence_transfer(ctx, &seq, 508 next); 509 if (rc) 510 goto error; 511 } else { 512 next = NULL; 513 } 514 } 515 516 fsi_spi_sequence_add(&seq, SPI_FSI_SEQUENCE_SEL_SLAVE(0)); 517 518 rc = fsi_spi_write_reg(ctx, SPI_FSI_SEQUENCE, seq.data); 519 if (rc) 520 goto error; 521 522 rc = fsi_spi_transfer_data(ctx, transfer); 523 if (rc) 524 goto error; 525 526 if (next) { 527 rc = fsi_spi_transfer_data(ctx, next); 528 if (rc) 529 goto error; 530 531 transfer = next; 532 } 533 } 534 535 error: 536 mesg->status = rc; 537 spi_finalize_current_message(ctlr); 538 539 return rc; 540 } 541 542 static size_t fsi_spi_max_transfer_size(struct spi_device *spi) 543 { 544 struct fsi_spi *ctx = spi_controller_get_devdata(spi->controller); 545 546 return ctx->max_xfr_size; 547 } 548 549 static int fsi_spi_probe(struct device *dev) 550 { 551 int rc; 552 struct device_node *np; 553 int num_controllers_registered = 0; 554 struct fsi_device *fsi = to_fsi_dev(dev); 555 556 rc = fsi_spi_check_mux(fsi, dev); 557 if (rc) 558 return -ENODEV; 559 560 for_each_available_child_of_node(dev->of_node, np) { 561 u32 base; 562 struct fsi_spi *ctx; 563 struct spi_controller *ctlr; 564 565 if (of_property_read_u32(np, "reg", &base)) 566 continue; 567 568 ctlr = spi_alloc_master(dev, sizeof(*ctx)); 569 if (!ctlr) { 570 of_node_put(np); 571 break; 572 } 573 574 ctlr->dev.of_node = np; 575 ctlr->num_chipselect = of_get_available_child_count(np) ?: 1; 576 ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX; 577 ctlr->max_transfer_size = fsi_spi_max_transfer_size; 578 ctlr->transfer_one_message = fsi_spi_transfer_one_message; 579 580 ctx = spi_controller_get_devdata(ctlr); 581 ctx->dev = &ctlr->dev; 582 ctx->fsi = fsi; 583 ctx->base = base + SPI_FSI_BASE; 584 585 if (of_device_is_compatible(np, "ibm,fsi2spi-restricted")) { 586 ctx->restricted = true; 587 ctx->max_xfr_size = SPI_FSI_MAX_XFR_SIZE_RESTRICTED; 588 } else { 589 ctx->restricted = false; 590 ctx->max_xfr_size = SPI_FSI_MAX_XFR_SIZE; 591 } 592 593 rc = devm_spi_register_controller(dev, ctlr); 594 if (rc) 595 spi_controller_put(ctlr); 596 else 597 num_controllers_registered++; 598 } 599 600 if (!num_controllers_registered) 601 return -ENODEV; 602 603 return 0; 604 } 605 606 static const struct fsi_device_id fsi_spi_ids[] = { 607 { FSI_ENGID_SPI, FSI_VERSION_ANY }, 608 { } 609 }; 610 MODULE_DEVICE_TABLE(fsi, fsi_spi_ids); 611 612 static struct fsi_driver fsi_spi_driver = { 613 .id_table = fsi_spi_ids, 614 .drv = { 615 .name = "spi-fsi", 616 .bus = &fsi_bus_type, 617 .probe = fsi_spi_probe, 618 }, 619 }; 620 module_fsi_driver(fsi_spi_driver); 621 622 MODULE_AUTHOR("Eddie James <eajames@linux.ibm.com>"); 623 MODULE_DESCRIPTION("FSI attached SPI controller"); 624 MODULE_LICENSE("GPL"); 625