1 // SPDX-License-Identifier: GPL-2.0-or-later 2 // Copyright (C) IBM Corporation 2020 3 4 #include <linux/bitfield.h> 5 #include <linux/bits.h> 6 #include <linux/fsi.h> 7 #include <linux/jiffies.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/spi/spi.h> 12 13 #define FSI_ENGID_SPI 0x23 14 #define FSI_MBOX_ROOT_CTRL_8 0x2860 15 #define FSI_MBOX_ROOT_CTRL_8_SPI_MUX 0xf0000000 16 17 #define FSI2SPI_DATA0 0x00 18 #define FSI2SPI_DATA1 0x04 19 #define FSI2SPI_CMD 0x08 20 #define FSI2SPI_CMD_WRITE BIT(31) 21 #define FSI2SPI_RESET 0x18 22 #define FSI2SPI_STATUS 0x1c 23 #define FSI2SPI_STATUS_ANY_ERROR BIT(31) 24 #define FSI2SPI_IRQ 0x20 25 26 #define SPI_FSI_BASE 0x70000 27 #define SPI_FSI_INIT_TIMEOUT_MS 1000 28 #define SPI_FSI_STATUS_TIMEOUT_MS 100 29 #define SPI_FSI_MAX_RX_SIZE 8 30 #define SPI_FSI_MAX_TX_SIZE 40 31 32 #define SPI_FSI_ERROR 0x0 33 #define SPI_FSI_COUNTER_CFG 0x1 34 #define SPI_FSI_CFG1 0x2 35 #define SPI_FSI_CLOCK_CFG 0x3 36 #define SPI_FSI_CLOCK_CFG_MM_ENABLE BIT_ULL(32) 37 #define SPI_FSI_CLOCK_CFG_ECC_DISABLE (BIT_ULL(35) | BIT_ULL(33)) 38 #define SPI_FSI_CLOCK_CFG_RESET1 (BIT_ULL(36) | BIT_ULL(38)) 39 #define SPI_FSI_CLOCK_CFG_RESET2 (BIT_ULL(37) | BIT_ULL(39)) 40 #define SPI_FSI_CLOCK_CFG_MODE (BIT_ULL(41) | BIT_ULL(42)) 41 #define SPI_FSI_CLOCK_CFG_SCK_RECV_DEL GENMASK_ULL(51, 44) 42 #define SPI_FSI_CLOCK_CFG_SCK_NO_DEL BIT_ULL(51) 43 #define SPI_FSI_CLOCK_CFG_SCK_DIV GENMASK_ULL(63, 52) 44 #define SPI_FSI_MMAP 0x4 45 #define SPI_FSI_DATA_TX 0x5 46 #define SPI_FSI_DATA_RX 0x6 47 #define SPI_FSI_SEQUENCE 0x7 48 #define SPI_FSI_SEQUENCE_STOP 0x00 49 #define SPI_FSI_SEQUENCE_SEL_SLAVE(x) (0x10 | ((x) & 0xf)) 50 #define SPI_FSI_SEQUENCE_SHIFT_OUT(x) (0x30 | ((x) & 0xf)) 51 #define SPI_FSI_SEQUENCE_SHIFT_IN(x) (0x40 | ((x) & 0xf)) 52 #define SPI_FSI_SEQUENCE_COPY_DATA_TX 0xc0 53 #define SPI_FSI_SEQUENCE_BRANCH(x) (0xe0 | ((x) & 0xf)) 54 #define SPI_FSI_STATUS 0x8 55 #define SPI_FSI_STATUS_ERROR \ 56 (GENMASK_ULL(31, 21) | GENMASK_ULL(15, 12)) 57 #define SPI_FSI_STATUS_SEQ_STATE GENMASK_ULL(55, 48) 58 #define SPI_FSI_STATUS_SEQ_STATE_IDLE BIT_ULL(48) 59 #define SPI_FSI_STATUS_TDR_UNDERRUN BIT_ULL(57) 60 #define SPI_FSI_STATUS_TDR_OVERRUN BIT_ULL(58) 61 #define SPI_FSI_STATUS_TDR_FULL BIT_ULL(59) 62 #define SPI_FSI_STATUS_RDR_UNDERRUN BIT_ULL(61) 63 #define SPI_FSI_STATUS_RDR_OVERRUN BIT_ULL(62) 64 #define SPI_FSI_STATUS_RDR_FULL BIT_ULL(63) 65 #define SPI_FSI_STATUS_ANY_ERROR \ 66 (SPI_FSI_STATUS_ERROR | \ 67 SPI_FSI_STATUS_TDR_OVERRUN | SPI_FSI_STATUS_RDR_UNDERRUN | \ 68 SPI_FSI_STATUS_RDR_OVERRUN) 69 #define SPI_FSI_PORT_CTRL 0x9 70 71 struct fsi2spi { 72 struct fsi_device *fsi; /* FSI2SPI CFAM engine device */ 73 struct mutex lock; /* lock access to the device */ 74 }; 75 76 struct fsi_spi { 77 struct device *dev; /* SPI controller device */ 78 struct fsi2spi *bridge; /* FSI2SPI device */ 79 u32 base; 80 }; 81 82 struct fsi_spi_sequence { 83 int bit; 84 u64 data; 85 }; 86 87 static int fsi_spi_check_mux(struct fsi_device *fsi, struct device *dev) 88 { 89 int rc; 90 u32 root_ctrl_8; 91 __be32 root_ctrl_8_be; 92 93 rc = fsi_slave_read(fsi->slave, FSI_MBOX_ROOT_CTRL_8, &root_ctrl_8_be, 94 sizeof(root_ctrl_8_be)); 95 if (rc) 96 return rc; 97 98 root_ctrl_8 = be32_to_cpu(root_ctrl_8_be); 99 dev_dbg(dev, "Root control register 8: %08x\n", root_ctrl_8); 100 if ((root_ctrl_8 & FSI_MBOX_ROOT_CTRL_8_SPI_MUX) == 101 FSI_MBOX_ROOT_CTRL_8_SPI_MUX) 102 return 0; 103 104 return -ENOLINK; 105 } 106 107 static int fsi_spi_check_status(struct fsi_spi *ctx) 108 { 109 int rc; 110 u32 sts; 111 __be32 sts_be; 112 113 rc = fsi_device_read(ctx->bridge->fsi, FSI2SPI_STATUS, &sts_be, 114 sizeof(sts_be)); 115 if (rc) 116 return rc; 117 118 sts = be32_to_cpu(sts_be); 119 if (sts & FSI2SPI_STATUS_ANY_ERROR) { 120 dev_err(ctx->dev, "Error with FSI2SPI interface: %08x.\n", sts); 121 return -EIO; 122 } 123 124 return 0; 125 } 126 127 static int fsi_spi_read_reg(struct fsi_spi *ctx, u32 offset, u64 *value) 128 { 129 int rc = 0; 130 __be32 cmd_be; 131 __be32 data_be; 132 u32 cmd = offset + ctx->base; 133 struct fsi2spi *bridge = ctx->bridge; 134 135 *value = 0ULL; 136 137 if (cmd & FSI2SPI_CMD_WRITE) 138 return -EINVAL; 139 140 rc = mutex_lock_interruptible(&bridge->lock); 141 if (rc) 142 return rc; 143 144 cmd_be = cpu_to_be32(cmd); 145 rc = fsi_device_write(bridge->fsi, FSI2SPI_CMD, &cmd_be, 146 sizeof(cmd_be)); 147 if (rc) 148 goto unlock; 149 150 rc = fsi_spi_check_status(ctx); 151 if (rc) 152 goto unlock; 153 154 rc = fsi_device_read(bridge->fsi, FSI2SPI_DATA0, &data_be, 155 sizeof(data_be)); 156 if (rc) 157 goto unlock; 158 159 *value |= (u64)be32_to_cpu(data_be) << 32; 160 161 rc = fsi_device_read(bridge->fsi, FSI2SPI_DATA1, &data_be, 162 sizeof(data_be)); 163 if (rc) 164 goto unlock; 165 166 *value |= (u64)be32_to_cpu(data_be); 167 dev_dbg(ctx->dev, "Read %02x[%016llx].\n", offset, *value); 168 169 unlock: 170 mutex_unlock(&bridge->lock); 171 return rc; 172 } 173 174 static int fsi_spi_write_reg(struct fsi_spi *ctx, u32 offset, u64 value) 175 { 176 int rc = 0; 177 __be32 cmd_be; 178 __be32 data_be; 179 u32 cmd = offset + ctx->base; 180 struct fsi2spi *bridge = ctx->bridge; 181 182 if (cmd & FSI2SPI_CMD_WRITE) 183 return -EINVAL; 184 185 rc = mutex_lock_interruptible(&bridge->lock); 186 if (rc) 187 return rc; 188 189 dev_dbg(ctx->dev, "Write %02x[%016llx].\n", offset, value); 190 191 data_be = cpu_to_be32(upper_32_bits(value)); 192 rc = fsi_device_write(bridge->fsi, FSI2SPI_DATA0, &data_be, 193 sizeof(data_be)); 194 if (rc) 195 goto unlock; 196 197 data_be = cpu_to_be32(lower_32_bits(value)); 198 rc = fsi_device_write(bridge->fsi, FSI2SPI_DATA1, &data_be, 199 sizeof(data_be)); 200 if (rc) 201 goto unlock; 202 203 cmd_be = cpu_to_be32(cmd | FSI2SPI_CMD_WRITE); 204 rc = fsi_device_write(bridge->fsi, FSI2SPI_CMD, &cmd_be, 205 sizeof(cmd_be)); 206 if (rc) 207 goto unlock; 208 209 rc = fsi_spi_check_status(ctx); 210 211 unlock: 212 mutex_unlock(&bridge->lock); 213 return rc; 214 } 215 216 static int fsi_spi_data_in(u64 in, u8 *rx, int len) 217 { 218 int i; 219 int num_bytes = min(len, 8); 220 221 for (i = 0; i < num_bytes; ++i) 222 rx[i] = (u8)(in >> (8 * ((num_bytes - 1) - i))); 223 224 return num_bytes; 225 } 226 227 static int fsi_spi_data_out(u64 *out, const u8 *tx, int len) 228 { 229 int i; 230 int num_bytes = min(len, 8); 231 u8 *out_bytes = (u8 *)out; 232 233 /* Unused bytes of the tx data should be 0. */ 234 *out = 0ULL; 235 236 for (i = 0; i < num_bytes; ++i) 237 out_bytes[8 - (i + 1)] = tx[i]; 238 239 return num_bytes; 240 } 241 242 static int fsi_spi_reset(struct fsi_spi *ctx) 243 { 244 int rc; 245 246 dev_dbg(ctx->dev, "Resetting SPI controller.\n"); 247 248 rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG, 249 SPI_FSI_CLOCK_CFG_RESET1); 250 if (rc) 251 return rc; 252 253 rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG, 254 SPI_FSI_CLOCK_CFG_RESET2); 255 if (rc) 256 return rc; 257 258 return fsi_spi_write_reg(ctx, SPI_FSI_STATUS, 0ULL); 259 } 260 261 static int fsi_spi_status(struct fsi_spi *ctx, u64 *status, const char *dir) 262 { 263 int rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS, status); 264 265 if (rc) 266 return rc; 267 268 if (*status & SPI_FSI_STATUS_ANY_ERROR) { 269 dev_err(ctx->dev, "%s error: %016llx\n", dir, *status); 270 271 rc = fsi_spi_reset(ctx); 272 if (rc) 273 return rc; 274 275 return -EREMOTEIO; 276 } 277 278 return 0; 279 } 280 281 static void fsi_spi_sequence_add(struct fsi_spi_sequence *seq, u8 val) 282 { 283 /* 284 * Add the next byte of instruction to the 8-byte sequence register. 285 * Then decrement the counter so that the next instruction will go in 286 * the right place. Return the index of the slot we just filled in the 287 * sequence register. 288 */ 289 seq->data |= (u64)val << seq->bit; 290 seq->bit -= 8; 291 } 292 293 static void fsi_spi_sequence_init(struct fsi_spi_sequence *seq) 294 { 295 seq->bit = 56; 296 seq->data = 0ULL; 297 } 298 299 static int fsi_spi_transfer_data(struct fsi_spi *ctx, 300 struct spi_transfer *transfer) 301 { 302 int rc = 0; 303 unsigned long end; 304 u64 status = 0ULL; 305 306 if (transfer->tx_buf) { 307 int nb; 308 int sent = 0; 309 u64 out = 0ULL; 310 const u8 *tx = transfer->tx_buf; 311 312 while (transfer->len > sent) { 313 nb = fsi_spi_data_out(&out, &tx[sent], 314 (int)transfer->len - sent); 315 316 rc = fsi_spi_write_reg(ctx, SPI_FSI_DATA_TX, out); 317 if (rc) 318 return rc; 319 320 end = jiffies + msecs_to_jiffies(SPI_FSI_STATUS_TIMEOUT_MS); 321 do { 322 if (time_after(jiffies, end)) 323 return -ETIMEDOUT; 324 325 rc = fsi_spi_status(ctx, &status, "TX"); 326 if (rc) 327 return rc; 328 } while (status & SPI_FSI_STATUS_TDR_FULL); 329 330 sent += nb; 331 } 332 } else if (transfer->rx_buf) { 333 int recv = 0; 334 u64 in = 0ULL; 335 u8 *rx = transfer->rx_buf; 336 337 while (transfer->len > recv) { 338 end = jiffies + msecs_to_jiffies(SPI_FSI_STATUS_TIMEOUT_MS); 339 do { 340 if (time_after(jiffies, end)) 341 return -ETIMEDOUT; 342 343 rc = fsi_spi_status(ctx, &status, "RX"); 344 if (rc) 345 return rc; 346 } while (!(status & SPI_FSI_STATUS_RDR_FULL)); 347 348 rc = fsi_spi_read_reg(ctx, SPI_FSI_DATA_RX, &in); 349 if (rc) 350 return rc; 351 352 recv += fsi_spi_data_in(in, &rx[recv], 353 (int)transfer->len - recv); 354 } 355 } 356 357 return 0; 358 } 359 360 static int fsi_spi_transfer_init(struct fsi_spi *ctx) 361 { 362 int rc; 363 bool reset = false; 364 unsigned long end; 365 u64 seq_state; 366 u64 clock_cfg = 0ULL; 367 u64 status = 0ULL; 368 u64 wanted_clock_cfg = SPI_FSI_CLOCK_CFG_ECC_DISABLE | 369 SPI_FSI_CLOCK_CFG_SCK_NO_DEL | 370 FIELD_PREP(SPI_FSI_CLOCK_CFG_SCK_DIV, 19); 371 372 end = jiffies + msecs_to_jiffies(SPI_FSI_INIT_TIMEOUT_MS); 373 do { 374 if (time_after(jiffies, end)) 375 return -ETIMEDOUT; 376 377 rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS, &status); 378 if (rc) 379 return rc; 380 381 seq_state = status & SPI_FSI_STATUS_SEQ_STATE; 382 383 if (status & (SPI_FSI_STATUS_ANY_ERROR | 384 SPI_FSI_STATUS_TDR_FULL | 385 SPI_FSI_STATUS_RDR_FULL)) { 386 if (reset) { 387 dev_err(ctx->dev, 388 "Initialization error: %08llx\n", 389 status); 390 return -EIO; 391 } 392 393 rc = fsi_spi_reset(ctx); 394 if (rc) 395 return rc; 396 397 reset = true; 398 continue; 399 } 400 } while (seq_state && (seq_state != SPI_FSI_STATUS_SEQ_STATE_IDLE)); 401 402 rc = fsi_spi_write_reg(ctx, SPI_FSI_COUNTER_CFG, 0ULL); 403 if (rc) 404 return rc; 405 406 rc = fsi_spi_read_reg(ctx, SPI_FSI_CLOCK_CFG, &clock_cfg); 407 if (rc) 408 return rc; 409 410 if ((clock_cfg & (SPI_FSI_CLOCK_CFG_MM_ENABLE | 411 SPI_FSI_CLOCK_CFG_ECC_DISABLE | 412 SPI_FSI_CLOCK_CFG_MODE | 413 SPI_FSI_CLOCK_CFG_SCK_RECV_DEL | 414 SPI_FSI_CLOCK_CFG_SCK_DIV)) != wanted_clock_cfg) 415 rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG, 416 wanted_clock_cfg); 417 418 return rc; 419 } 420 421 static int fsi_spi_transfer_one_message(struct spi_controller *ctlr, 422 struct spi_message *mesg) 423 { 424 int rc; 425 u8 seq_slave = SPI_FSI_SEQUENCE_SEL_SLAVE(mesg->spi->chip_select + 1); 426 unsigned int len; 427 struct spi_transfer *transfer; 428 struct fsi_spi *ctx = spi_controller_get_devdata(ctlr); 429 430 rc = fsi_spi_check_mux(ctx->bridge->fsi, ctx->dev); 431 if (rc) 432 goto error; 433 434 list_for_each_entry(transfer, &mesg->transfers, transfer_list) { 435 struct fsi_spi_sequence seq; 436 struct spi_transfer *next = NULL; 437 438 /* Sequencer must do shift out (tx) first. */ 439 if (!transfer->tx_buf || transfer->len > SPI_FSI_MAX_TX_SIZE) { 440 rc = -EINVAL; 441 goto error; 442 } 443 444 dev_dbg(ctx->dev, "Start tx of %d bytes.\n", transfer->len); 445 446 rc = fsi_spi_transfer_init(ctx); 447 if (rc < 0) 448 goto error; 449 450 fsi_spi_sequence_init(&seq); 451 fsi_spi_sequence_add(&seq, seq_slave); 452 453 len = transfer->len; 454 while (len > 8) { 455 fsi_spi_sequence_add(&seq, 456 SPI_FSI_SEQUENCE_SHIFT_OUT(8)); 457 len -= 8; 458 } 459 fsi_spi_sequence_add(&seq, SPI_FSI_SEQUENCE_SHIFT_OUT(len)); 460 461 if (!list_is_last(&transfer->transfer_list, 462 &mesg->transfers)) { 463 next = list_next_entry(transfer, transfer_list); 464 465 /* Sequencer can only do shift in (rx) after tx. */ 466 if (next->rx_buf) { 467 u8 shift; 468 469 if (next->len > SPI_FSI_MAX_RX_SIZE) { 470 rc = -EINVAL; 471 goto error; 472 } 473 474 dev_dbg(ctx->dev, "Sequence rx of %d bytes.\n", 475 next->len); 476 477 shift = SPI_FSI_SEQUENCE_SHIFT_IN(next->len); 478 fsi_spi_sequence_add(&seq, shift); 479 } else { 480 next = NULL; 481 } 482 } 483 484 fsi_spi_sequence_add(&seq, SPI_FSI_SEQUENCE_SEL_SLAVE(0)); 485 486 rc = fsi_spi_write_reg(ctx, SPI_FSI_SEQUENCE, seq.data); 487 if (rc) 488 goto error; 489 490 rc = fsi_spi_transfer_data(ctx, transfer); 491 if (rc) 492 goto error; 493 494 if (next) { 495 rc = fsi_spi_transfer_data(ctx, next); 496 if (rc) 497 goto error; 498 499 transfer = next; 500 } 501 } 502 503 error: 504 mesg->status = rc; 505 spi_finalize_current_message(ctlr); 506 507 return rc; 508 } 509 510 static size_t fsi_spi_max_transfer_size(struct spi_device *spi) 511 { 512 return SPI_FSI_MAX_RX_SIZE; 513 } 514 515 static int fsi_spi_probe(struct device *dev) 516 { 517 int rc; 518 struct device_node *np; 519 int num_controllers_registered = 0; 520 struct fsi2spi *bridge; 521 struct fsi_device *fsi = to_fsi_dev(dev); 522 523 rc = fsi_spi_check_mux(fsi, dev); 524 if (rc) 525 return -ENODEV; 526 527 bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL); 528 if (!bridge) 529 return -ENOMEM; 530 531 bridge->fsi = fsi; 532 mutex_init(&bridge->lock); 533 534 for_each_available_child_of_node(dev->of_node, np) { 535 u32 base; 536 struct fsi_spi *ctx; 537 struct spi_controller *ctlr; 538 539 if (of_property_read_u32(np, "reg", &base)) 540 continue; 541 542 ctlr = spi_alloc_master(dev, sizeof(*ctx)); 543 if (!ctlr) { 544 of_node_put(np); 545 break; 546 } 547 548 ctlr->dev.of_node = np; 549 ctlr->num_chipselect = of_get_available_child_count(np) ?: 1; 550 ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX; 551 ctlr->max_transfer_size = fsi_spi_max_transfer_size; 552 ctlr->transfer_one_message = fsi_spi_transfer_one_message; 553 554 ctx = spi_controller_get_devdata(ctlr); 555 ctx->dev = &ctlr->dev; 556 ctx->bridge = bridge; 557 ctx->base = base + SPI_FSI_BASE; 558 559 rc = devm_spi_register_controller(dev, ctlr); 560 if (rc) 561 spi_controller_put(ctlr); 562 else 563 num_controllers_registered++; 564 } 565 566 if (!num_controllers_registered) 567 return -ENODEV; 568 569 return 0; 570 } 571 572 static const struct fsi_device_id fsi_spi_ids[] = { 573 { FSI_ENGID_SPI, FSI_VERSION_ANY }, 574 { } 575 }; 576 MODULE_DEVICE_TABLE(fsi, fsi_spi_ids); 577 578 static struct fsi_driver fsi_spi_driver = { 579 .id_table = fsi_spi_ids, 580 .drv = { 581 .name = "spi-fsi", 582 .bus = &fsi_bus_type, 583 .probe = fsi_spi_probe, 584 }, 585 }; 586 module_fsi_driver(fsi_spi_driver); 587 588 MODULE_AUTHOR("Eddie James <eajames@linux.ibm.com>"); 589 MODULE_DESCRIPTION("FSI attached SPI controller"); 590 MODULE_LICENSE("GPL"); 591