1 /* 2 * Driver for Cirrus Logic EP93xx SPI controller. 3 * 4 * Copyright (C) 2010-2011 Mika Westerberg 5 * 6 * Explicit FIFO handling code was inspired by amba-pl022 driver. 7 * 8 * Chip select support using other than built-in GPIOs by H. Hartley Sweeten. 9 * 10 * For more information about the SPI controller see documentation on Cirrus 11 * Logic web site: 12 * http://www.cirrus.com/en/pubs/manual/EP93xx_Users_Guide_UM1.pdf 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 */ 18 19 #include <linux/io.h> 20 #include <linux/clk.h> 21 #include <linux/err.h> 22 #include <linux/delay.h> 23 #include <linux/device.h> 24 #include <linux/dmaengine.h> 25 #include <linux/bitops.h> 26 #include <linux/interrupt.h> 27 #include <linux/module.h> 28 #include <linux/platform_device.h> 29 #include <linux/workqueue.h> 30 #include <linux/sched.h> 31 #include <linux/scatterlist.h> 32 #include <linux/spi/spi.h> 33 34 #include <linux/platform_data/dma-ep93xx.h> 35 #include <linux/platform_data/spi-ep93xx.h> 36 37 #define SSPCR0 0x0000 38 #define SSPCR0_MODE_SHIFT 6 39 #define SSPCR0_SCR_SHIFT 8 40 41 #define SSPCR1 0x0004 42 #define SSPCR1_RIE BIT(0) 43 #define SSPCR1_TIE BIT(1) 44 #define SSPCR1_RORIE BIT(2) 45 #define SSPCR1_LBM BIT(3) 46 #define SSPCR1_SSE BIT(4) 47 #define SSPCR1_MS BIT(5) 48 #define SSPCR1_SOD BIT(6) 49 50 #define SSPDR 0x0008 51 52 #define SSPSR 0x000c 53 #define SSPSR_TFE BIT(0) 54 #define SSPSR_TNF BIT(1) 55 #define SSPSR_RNE BIT(2) 56 #define SSPSR_RFF BIT(3) 57 #define SSPSR_BSY BIT(4) 58 #define SSPCPSR 0x0010 59 60 #define SSPIIR 0x0014 61 #define SSPIIR_RIS BIT(0) 62 #define SSPIIR_TIS BIT(1) 63 #define SSPIIR_RORIS BIT(2) 64 #define SSPICR SSPIIR 65 66 /* timeout in milliseconds */ 67 #define SPI_TIMEOUT 5 68 /* maximum depth of RX/TX FIFO */ 69 #define SPI_FIFO_SIZE 8 70 71 /** 72 * struct ep93xx_spi - EP93xx SPI controller structure 73 * @lock: spinlock that protects concurrent accesses to fields @running, 74 * @current_msg and @msg_queue 75 * @pdev: pointer to platform device 76 * @clk: clock for the controller 77 * @regs_base: pointer to ioremap()'d registers 78 * @sspdr_phys: physical address of the SSPDR register 79 * @min_rate: minimum clock rate (in Hz) supported by the controller 80 * @max_rate: maximum clock rate (in Hz) supported by the controller 81 * @running: is the queue running 82 * @wq: workqueue used by the driver 83 * @msg_work: work that is queued for the driver 84 * @wait: wait here until given transfer is completed 85 * @msg_queue: queue for the messages 86 * @current_msg: message that is currently processed (or %NULL if none) 87 * @tx: current byte in transfer to transmit 88 * @rx: current byte in transfer to receive 89 * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one 90 * frame decreases this level and sending one frame increases it. 91 * @dma_rx: RX DMA channel 92 * @dma_tx: TX DMA channel 93 * @dma_rx_data: RX parameters passed to the DMA engine 94 * @dma_tx_data: TX parameters passed to the DMA engine 95 * @rx_sgt: sg table for RX transfers 96 * @tx_sgt: sg table for TX transfers 97 * @zeropage: dummy page used as RX buffer when only TX buffer is passed in by 98 * the client 99 * 100 * This structure holds EP93xx SPI controller specific information. When 101 * @running is %true, driver accepts transfer requests from protocol drivers. 102 * @current_msg is used to hold pointer to the message that is currently 103 * processed. If @current_msg is %NULL, it means that no processing is going 104 * on. 105 * 106 * Most of the fields are only written once and they can be accessed without 107 * taking the @lock. Fields that are accessed concurrently are: @current_msg, 108 * @running, and @msg_queue. 109 */ 110 struct ep93xx_spi { 111 spinlock_t lock; 112 const struct platform_device *pdev; 113 struct clk *clk; 114 void __iomem *regs_base; 115 unsigned long sspdr_phys; 116 unsigned long min_rate; 117 unsigned long max_rate; 118 bool running; 119 struct workqueue_struct *wq; 120 struct work_struct msg_work; 121 struct completion wait; 122 struct list_head msg_queue; 123 struct spi_message *current_msg; 124 size_t tx; 125 size_t rx; 126 size_t fifo_level; 127 struct dma_chan *dma_rx; 128 struct dma_chan *dma_tx; 129 struct ep93xx_dma_data dma_rx_data; 130 struct ep93xx_dma_data dma_tx_data; 131 struct sg_table rx_sgt; 132 struct sg_table tx_sgt; 133 void *zeropage; 134 }; 135 136 /** 137 * struct ep93xx_spi_chip - SPI device hardware settings 138 * @spi: back pointer to the SPI device 139 * @rate: max rate in hz this chip supports 140 * @div_cpsr: cpsr (pre-scaler) divider 141 * @div_scr: scr divider 142 * @ops: private chip operations 143 * 144 * This structure is used to store hardware register specific settings for each 145 * SPI device. Settings are written to hardware by function 146 * ep93xx_spi_chip_setup(). 147 */ 148 struct ep93xx_spi_chip { 149 const struct spi_device *spi; 150 unsigned long rate; 151 u8 div_cpsr; 152 u8 div_scr; 153 struct ep93xx_spi_chip_ops *ops; 154 }; 155 156 /* converts bits per word to CR0.DSS value */ 157 #define bits_per_word_to_dss(bpw) ((bpw) - 1) 158 159 static void ep93xx_spi_write_u8(const struct ep93xx_spi *espi, 160 u16 reg, u8 value) 161 { 162 writeb(value, espi->regs_base + reg); 163 } 164 165 static u8 ep93xx_spi_read_u8(const struct ep93xx_spi *spi, u16 reg) 166 { 167 return readb(spi->regs_base + reg); 168 } 169 170 static void ep93xx_spi_write_u16(const struct ep93xx_spi *espi, 171 u16 reg, u16 value) 172 { 173 writew(value, espi->regs_base + reg); 174 } 175 176 static u16 ep93xx_spi_read_u16(const struct ep93xx_spi *spi, u16 reg) 177 { 178 return readw(spi->regs_base + reg); 179 } 180 181 static int ep93xx_spi_enable(const struct ep93xx_spi *espi) 182 { 183 u8 regval; 184 int err; 185 186 err = clk_enable(espi->clk); 187 if (err) 188 return err; 189 190 regval = ep93xx_spi_read_u8(espi, SSPCR1); 191 regval |= SSPCR1_SSE; 192 ep93xx_spi_write_u8(espi, SSPCR1, regval); 193 194 return 0; 195 } 196 197 static void ep93xx_spi_disable(const struct ep93xx_spi *espi) 198 { 199 u8 regval; 200 201 regval = ep93xx_spi_read_u8(espi, SSPCR1); 202 regval &= ~SSPCR1_SSE; 203 ep93xx_spi_write_u8(espi, SSPCR1, regval); 204 205 clk_disable(espi->clk); 206 } 207 208 static void ep93xx_spi_enable_interrupts(const struct ep93xx_spi *espi) 209 { 210 u8 regval; 211 212 regval = ep93xx_spi_read_u8(espi, SSPCR1); 213 regval |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE); 214 ep93xx_spi_write_u8(espi, SSPCR1, regval); 215 } 216 217 static void ep93xx_spi_disable_interrupts(const struct ep93xx_spi *espi) 218 { 219 u8 regval; 220 221 regval = ep93xx_spi_read_u8(espi, SSPCR1); 222 regval &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE); 223 ep93xx_spi_write_u8(espi, SSPCR1, regval); 224 } 225 226 /** 227 * ep93xx_spi_calc_divisors() - calculates SPI clock divisors 228 * @espi: ep93xx SPI controller struct 229 * @chip: divisors are calculated for this chip 230 * @rate: desired SPI output clock rate 231 * 232 * Function calculates cpsr (clock pre-scaler) and scr divisors based on 233 * given @rate and places them to @chip->div_cpsr and @chip->div_scr. If, 234 * for some reason, divisors cannot be calculated nothing is stored and 235 * %-EINVAL is returned. 236 */ 237 static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi, 238 struct ep93xx_spi_chip *chip, 239 unsigned long rate) 240 { 241 unsigned long spi_clk_rate = clk_get_rate(espi->clk); 242 int cpsr, scr; 243 244 /* 245 * Make sure that max value is between values supported by the 246 * controller. Note that minimum value is already checked in 247 * ep93xx_spi_transfer(). 248 */ 249 rate = clamp(rate, espi->min_rate, espi->max_rate); 250 251 /* 252 * Calculate divisors so that we can get speed according the 253 * following formula: 254 * rate = spi_clock_rate / (cpsr * (1 + scr)) 255 * 256 * cpsr must be even number and starts from 2, scr can be any number 257 * between 0 and 255. 258 */ 259 for (cpsr = 2; cpsr <= 254; cpsr += 2) { 260 for (scr = 0; scr <= 255; scr++) { 261 if ((spi_clk_rate / (cpsr * (scr + 1))) <= rate) { 262 chip->div_scr = (u8)scr; 263 chip->div_cpsr = (u8)cpsr; 264 return 0; 265 } 266 } 267 } 268 269 return -EINVAL; 270 } 271 272 static void ep93xx_spi_cs_control(struct spi_device *spi, bool control) 273 { 274 struct ep93xx_spi_chip *chip = spi_get_ctldata(spi); 275 int value = (spi->mode & SPI_CS_HIGH) ? control : !control; 276 277 if (chip->ops && chip->ops->cs_control) 278 chip->ops->cs_control(spi, value); 279 } 280 281 /** 282 * ep93xx_spi_setup() - setup an SPI device 283 * @spi: SPI device to setup 284 * 285 * This function sets up SPI device mode, speed etc. Can be called multiple 286 * times for a single device. Returns %0 in case of success, negative error in 287 * case of failure. When this function returns success, the device is 288 * deselected. 289 */ 290 static int ep93xx_spi_setup(struct spi_device *spi) 291 { 292 struct ep93xx_spi *espi = spi_master_get_devdata(spi->master); 293 struct ep93xx_spi_chip *chip; 294 295 chip = spi_get_ctldata(spi); 296 if (!chip) { 297 dev_dbg(&espi->pdev->dev, "initial setup for %s\n", 298 spi->modalias); 299 300 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 301 if (!chip) 302 return -ENOMEM; 303 304 chip->spi = spi; 305 chip->ops = spi->controller_data; 306 307 if (chip->ops && chip->ops->setup) { 308 int ret = chip->ops->setup(spi); 309 if (ret) { 310 kfree(chip); 311 return ret; 312 } 313 } 314 315 spi_set_ctldata(spi, chip); 316 } 317 318 if (spi->max_speed_hz != chip->rate) { 319 int err; 320 321 err = ep93xx_spi_calc_divisors(espi, chip, spi->max_speed_hz); 322 if (err != 0) { 323 spi_set_ctldata(spi, NULL); 324 kfree(chip); 325 return err; 326 } 327 chip->rate = spi->max_speed_hz; 328 } 329 330 ep93xx_spi_cs_control(spi, false); 331 return 0; 332 } 333 334 /** 335 * ep93xx_spi_transfer() - queue message to be transferred 336 * @spi: target SPI device 337 * @msg: message to be transferred 338 * 339 * This function is called by SPI device drivers when they are going to transfer 340 * a new message. It simply puts the message in the queue and schedules 341 * workqueue to perform the actual transfer later on. 342 * 343 * Returns %0 on success and negative error in case of failure. 344 */ 345 static int ep93xx_spi_transfer(struct spi_device *spi, struct spi_message *msg) 346 { 347 struct ep93xx_spi *espi = spi_master_get_devdata(spi->master); 348 struct spi_transfer *t; 349 unsigned long flags; 350 351 if (!msg || !msg->complete) 352 return -EINVAL; 353 354 /* first validate each transfer */ 355 list_for_each_entry(t, &msg->transfers, transfer_list) { 356 if (t->speed_hz && t->speed_hz < espi->min_rate) 357 return -EINVAL; 358 } 359 360 /* 361 * Now that we own the message, let's initialize it so that it is 362 * suitable for us. We use @msg->status to signal whether there was 363 * error in transfer and @msg->state is used to hold pointer to the 364 * current transfer (or %NULL if no active current transfer). 365 */ 366 msg->state = NULL; 367 msg->status = 0; 368 msg->actual_length = 0; 369 370 spin_lock_irqsave(&espi->lock, flags); 371 if (!espi->running) { 372 spin_unlock_irqrestore(&espi->lock, flags); 373 return -ESHUTDOWN; 374 } 375 list_add_tail(&msg->queue, &espi->msg_queue); 376 queue_work(espi->wq, &espi->msg_work); 377 spin_unlock_irqrestore(&espi->lock, flags); 378 379 return 0; 380 } 381 382 /** 383 * ep93xx_spi_cleanup() - cleans up master controller specific state 384 * @spi: SPI device to cleanup 385 * 386 * This function releases master controller specific state for given @spi 387 * device. 388 */ 389 static void ep93xx_spi_cleanup(struct spi_device *spi) 390 { 391 struct ep93xx_spi_chip *chip; 392 393 chip = spi_get_ctldata(spi); 394 if (chip) { 395 if (chip->ops && chip->ops->cleanup) 396 chip->ops->cleanup(spi); 397 spi_set_ctldata(spi, NULL); 398 kfree(chip); 399 } 400 } 401 402 /** 403 * ep93xx_spi_chip_setup() - configures hardware according to given @chip 404 * @espi: ep93xx SPI controller struct 405 * @chip: chip specific settings 406 * @bits_per_word: transfer bits_per_word 407 * 408 * This function sets up the actual hardware registers with settings given in 409 * @chip. Note that no validation is done so make sure that callers validate 410 * settings before calling this. 411 */ 412 static void ep93xx_spi_chip_setup(const struct ep93xx_spi *espi, 413 const struct ep93xx_spi_chip *chip, 414 u8 bits_per_word) 415 { 416 u8 dss = bits_per_word_to_dss(bits_per_word); 417 u16 cr0; 418 419 cr0 = chip->div_scr << SSPCR0_SCR_SHIFT; 420 cr0 |= (chip->spi->mode & (SPI_CPHA|SPI_CPOL)) << SSPCR0_MODE_SHIFT; 421 cr0 |= dss; 422 423 dev_dbg(&espi->pdev->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n", 424 chip->spi->mode, chip->div_cpsr, chip->div_scr, dss); 425 dev_dbg(&espi->pdev->dev, "setup: cr0 %#x", cr0); 426 427 ep93xx_spi_write_u8(espi, SSPCPSR, chip->div_cpsr); 428 ep93xx_spi_write_u16(espi, SSPCR0, cr0); 429 } 430 431 static void ep93xx_do_write(struct ep93xx_spi *espi, struct spi_transfer *t) 432 { 433 if (t->bits_per_word > 8) { 434 u16 tx_val = 0; 435 436 if (t->tx_buf) 437 tx_val = ((u16 *)t->tx_buf)[espi->tx]; 438 ep93xx_spi_write_u16(espi, SSPDR, tx_val); 439 espi->tx += sizeof(tx_val); 440 } else { 441 u8 tx_val = 0; 442 443 if (t->tx_buf) 444 tx_val = ((u8 *)t->tx_buf)[espi->tx]; 445 ep93xx_spi_write_u8(espi, SSPDR, tx_val); 446 espi->tx += sizeof(tx_val); 447 } 448 } 449 450 static void ep93xx_do_read(struct ep93xx_spi *espi, struct spi_transfer *t) 451 { 452 if (t->bits_per_word > 8) { 453 u16 rx_val; 454 455 rx_val = ep93xx_spi_read_u16(espi, SSPDR); 456 if (t->rx_buf) 457 ((u16 *)t->rx_buf)[espi->rx] = rx_val; 458 espi->rx += sizeof(rx_val); 459 } else { 460 u8 rx_val; 461 462 rx_val = ep93xx_spi_read_u8(espi, SSPDR); 463 if (t->rx_buf) 464 ((u8 *)t->rx_buf)[espi->rx] = rx_val; 465 espi->rx += sizeof(rx_val); 466 } 467 } 468 469 /** 470 * ep93xx_spi_read_write() - perform next RX/TX transfer 471 * @espi: ep93xx SPI controller struct 472 * 473 * This function transfers next bytes (or half-words) to/from RX/TX FIFOs. If 474 * called several times, the whole transfer will be completed. Returns 475 * %-EINPROGRESS when current transfer was not yet completed otherwise %0. 476 * 477 * When this function is finished, RX FIFO should be empty and TX FIFO should be 478 * full. 479 */ 480 static int ep93xx_spi_read_write(struct ep93xx_spi *espi) 481 { 482 struct spi_message *msg = espi->current_msg; 483 struct spi_transfer *t = msg->state; 484 485 /* read as long as RX FIFO has frames in it */ 486 while ((ep93xx_spi_read_u8(espi, SSPSR) & SSPSR_RNE)) { 487 ep93xx_do_read(espi, t); 488 espi->fifo_level--; 489 } 490 491 /* write as long as TX FIFO has room */ 492 while (espi->fifo_level < SPI_FIFO_SIZE && espi->tx < t->len) { 493 ep93xx_do_write(espi, t); 494 espi->fifo_level++; 495 } 496 497 if (espi->rx == t->len) 498 return 0; 499 500 return -EINPROGRESS; 501 } 502 503 static void ep93xx_spi_pio_transfer(struct ep93xx_spi *espi) 504 { 505 /* 506 * Now everything is set up for the current transfer. We prime the TX 507 * FIFO, enable interrupts, and wait for the transfer to complete. 508 */ 509 if (ep93xx_spi_read_write(espi)) { 510 ep93xx_spi_enable_interrupts(espi); 511 wait_for_completion(&espi->wait); 512 } 513 } 514 515 /** 516 * ep93xx_spi_dma_prepare() - prepares a DMA transfer 517 * @espi: ep93xx SPI controller struct 518 * @dir: DMA transfer direction 519 * 520 * Function configures the DMA, maps the buffer and prepares the DMA 521 * descriptor. Returns a valid DMA descriptor in case of success and ERR_PTR 522 * in case of failure. 523 */ 524 static struct dma_async_tx_descriptor * 525 ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_transfer_direction dir) 526 { 527 struct spi_transfer *t = espi->current_msg->state; 528 struct dma_async_tx_descriptor *txd; 529 enum dma_slave_buswidth buswidth; 530 struct dma_slave_config conf; 531 struct scatterlist *sg; 532 struct sg_table *sgt; 533 struct dma_chan *chan; 534 const void *buf, *pbuf; 535 size_t len = t->len; 536 int i, ret, nents; 537 538 if (t->bits_per_word > 8) 539 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; 540 else 541 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; 542 543 memset(&conf, 0, sizeof(conf)); 544 conf.direction = dir; 545 546 if (dir == DMA_DEV_TO_MEM) { 547 chan = espi->dma_rx; 548 buf = t->rx_buf; 549 sgt = &espi->rx_sgt; 550 551 conf.src_addr = espi->sspdr_phys; 552 conf.src_addr_width = buswidth; 553 } else { 554 chan = espi->dma_tx; 555 buf = t->tx_buf; 556 sgt = &espi->tx_sgt; 557 558 conf.dst_addr = espi->sspdr_phys; 559 conf.dst_addr_width = buswidth; 560 } 561 562 ret = dmaengine_slave_config(chan, &conf); 563 if (ret) 564 return ERR_PTR(ret); 565 566 /* 567 * We need to split the transfer into PAGE_SIZE'd chunks. This is 568 * because we are using @espi->zeropage to provide a zero RX buffer 569 * for the TX transfers and we have only allocated one page for that. 570 * 571 * For performance reasons we allocate a new sg_table only when 572 * needed. Otherwise we will re-use the current one. Eventually the 573 * last sg_table is released in ep93xx_spi_release_dma(). 574 */ 575 576 nents = DIV_ROUND_UP(len, PAGE_SIZE); 577 if (nents != sgt->nents) { 578 sg_free_table(sgt); 579 580 ret = sg_alloc_table(sgt, nents, GFP_KERNEL); 581 if (ret) 582 return ERR_PTR(ret); 583 } 584 585 pbuf = buf; 586 for_each_sg(sgt->sgl, sg, sgt->nents, i) { 587 size_t bytes = min_t(size_t, len, PAGE_SIZE); 588 589 if (buf) { 590 sg_set_page(sg, virt_to_page(pbuf), bytes, 591 offset_in_page(pbuf)); 592 } else { 593 sg_set_page(sg, virt_to_page(espi->zeropage), 594 bytes, 0); 595 } 596 597 pbuf += bytes; 598 len -= bytes; 599 } 600 601 if (WARN_ON(len)) { 602 dev_warn(&espi->pdev->dev, "len = %d expected 0!", len); 603 return ERR_PTR(-EINVAL); 604 } 605 606 nents = dma_map_sg(chan->device->dev, sgt->sgl, sgt->nents, dir); 607 if (!nents) 608 return ERR_PTR(-ENOMEM); 609 610 txd = dmaengine_prep_slave_sg(chan, sgt->sgl, nents, dir, DMA_CTRL_ACK); 611 if (!txd) { 612 dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir); 613 return ERR_PTR(-ENOMEM); 614 } 615 return txd; 616 } 617 618 /** 619 * ep93xx_spi_dma_finish() - finishes with a DMA transfer 620 * @espi: ep93xx SPI controller struct 621 * @dir: DMA transfer direction 622 * 623 * Function finishes with the DMA transfer. After this, the DMA buffer is 624 * unmapped. 625 */ 626 static void ep93xx_spi_dma_finish(struct ep93xx_spi *espi, 627 enum dma_transfer_direction dir) 628 { 629 struct dma_chan *chan; 630 struct sg_table *sgt; 631 632 if (dir == DMA_DEV_TO_MEM) { 633 chan = espi->dma_rx; 634 sgt = &espi->rx_sgt; 635 } else { 636 chan = espi->dma_tx; 637 sgt = &espi->tx_sgt; 638 } 639 640 dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir); 641 } 642 643 static void ep93xx_spi_dma_callback(void *callback_param) 644 { 645 complete(callback_param); 646 } 647 648 static void ep93xx_spi_dma_transfer(struct ep93xx_spi *espi) 649 { 650 struct spi_message *msg = espi->current_msg; 651 struct dma_async_tx_descriptor *rxd, *txd; 652 653 rxd = ep93xx_spi_dma_prepare(espi, DMA_DEV_TO_MEM); 654 if (IS_ERR(rxd)) { 655 dev_err(&espi->pdev->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd)); 656 msg->status = PTR_ERR(rxd); 657 return; 658 } 659 660 txd = ep93xx_spi_dma_prepare(espi, DMA_MEM_TO_DEV); 661 if (IS_ERR(txd)) { 662 ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM); 663 dev_err(&espi->pdev->dev, "DMA TX failed: %ld\n", PTR_ERR(rxd)); 664 msg->status = PTR_ERR(txd); 665 return; 666 } 667 668 /* We are ready when RX is done */ 669 rxd->callback = ep93xx_spi_dma_callback; 670 rxd->callback_param = &espi->wait; 671 672 /* Now submit both descriptors and wait while they finish */ 673 dmaengine_submit(rxd); 674 dmaengine_submit(txd); 675 676 dma_async_issue_pending(espi->dma_rx); 677 dma_async_issue_pending(espi->dma_tx); 678 679 wait_for_completion(&espi->wait); 680 681 ep93xx_spi_dma_finish(espi, DMA_MEM_TO_DEV); 682 ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM); 683 } 684 685 /** 686 * ep93xx_spi_process_transfer() - processes one SPI transfer 687 * @espi: ep93xx SPI controller struct 688 * @msg: current message 689 * @t: transfer to process 690 * 691 * This function processes one SPI transfer given in @t. Function waits until 692 * transfer is complete (may sleep) and updates @msg->status based on whether 693 * transfer was successfully processed or not. 694 */ 695 static void ep93xx_spi_process_transfer(struct ep93xx_spi *espi, 696 struct spi_message *msg, 697 struct spi_transfer *t) 698 { 699 struct ep93xx_spi_chip *chip = spi_get_ctldata(msg->spi); 700 int err; 701 702 msg->state = t; 703 704 err = ep93xx_spi_calc_divisors(espi, chip, t->speed_hz); 705 if (err) { 706 dev_err(&espi->pdev->dev, "failed to adjust speed\n"); 707 msg->status = err; 708 return; 709 } 710 711 ep93xx_spi_chip_setup(espi, chip, t->bits_per_word); 712 713 espi->rx = 0; 714 espi->tx = 0; 715 716 /* 717 * There is no point of setting up DMA for the transfers which will 718 * fit into the FIFO and can be transferred with a single interrupt. 719 * So in these cases we will be using PIO and don't bother for DMA. 720 */ 721 if (espi->dma_rx && t->len > SPI_FIFO_SIZE) 722 ep93xx_spi_dma_transfer(espi); 723 else 724 ep93xx_spi_pio_transfer(espi); 725 726 /* 727 * In case of error during transmit, we bail out from processing 728 * the message. 729 */ 730 if (msg->status) 731 return; 732 733 msg->actual_length += t->len; 734 735 /* 736 * After this transfer is finished, perform any possible 737 * post-transfer actions requested by the protocol driver. 738 */ 739 if (t->delay_usecs) { 740 set_current_state(TASK_UNINTERRUPTIBLE); 741 schedule_timeout(usecs_to_jiffies(t->delay_usecs)); 742 } 743 if (t->cs_change) { 744 if (!list_is_last(&t->transfer_list, &msg->transfers)) { 745 /* 746 * In case protocol driver is asking us to drop the 747 * chipselect briefly, we let the scheduler to handle 748 * any "delay" here. 749 */ 750 ep93xx_spi_cs_control(msg->spi, false); 751 cond_resched(); 752 ep93xx_spi_cs_control(msg->spi, true); 753 } 754 } 755 } 756 757 /* 758 * ep93xx_spi_process_message() - process one SPI message 759 * @espi: ep93xx SPI controller struct 760 * @msg: message to process 761 * 762 * This function processes a single SPI message. We go through all transfers in 763 * the message and pass them to ep93xx_spi_process_transfer(). Chipselect is 764 * asserted during the whole message (unless per transfer cs_change is set). 765 * 766 * @msg->status contains %0 in case of success or negative error code in case of 767 * failure. 768 */ 769 static void ep93xx_spi_process_message(struct ep93xx_spi *espi, 770 struct spi_message *msg) 771 { 772 unsigned long timeout; 773 struct spi_transfer *t; 774 int err; 775 776 /* 777 * Enable the SPI controller and its clock. 778 */ 779 err = ep93xx_spi_enable(espi); 780 if (err) { 781 dev_err(&espi->pdev->dev, "failed to enable SPI controller\n"); 782 msg->status = err; 783 return; 784 } 785 786 /* 787 * Just to be sure: flush any data from RX FIFO. 788 */ 789 timeout = jiffies + msecs_to_jiffies(SPI_TIMEOUT); 790 while (ep93xx_spi_read_u16(espi, SSPSR) & SSPSR_RNE) { 791 if (time_after(jiffies, timeout)) { 792 dev_warn(&espi->pdev->dev, 793 "timeout while flushing RX FIFO\n"); 794 msg->status = -ETIMEDOUT; 795 return; 796 } 797 ep93xx_spi_read_u16(espi, SSPDR); 798 } 799 800 /* 801 * We explicitly handle FIFO level. This way we don't have to check TX 802 * FIFO status using %SSPSR_TNF bit which may cause RX FIFO overruns. 803 */ 804 espi->fifo_level = 0; 805 806 /* 807 * Assert the chipselect. 808 */ 809 ep93xx_spi_cs_control(msg->spi, true); 810 811 list_for_each_entry(t, &msg->transfers, transfer_list) { 812 ep93xx_spi_process_transfer(espi, msg, t); 813 if (msg->status) 814 break; 815 } 816 817 /* 818 * Now the whole message is transferred (or failed for some reason). We 819 * deselect the device and disable the SPI controller. 820 */ 821 ep93xx_spi_cs_control(msg->spi, false); 822 ep93xx_spi_disable(espi); 823 } 824 825 #define work_to_espi(work) (container_of((work), struct ep93xx_spi, msg_work)) 826 827 /** 828 * ep93xx_spi_work() - EP93xx SPI workqueue worker function 829 * @work: work struct 830 * 831 * Workqueue worker function. This function is called when there are new 832 * SPI messages to be processed. Message is taken out from the queue and then 833 * passed to ep93xx_spi_process_message(). 834 * 835 * After message is transferred, protocol driver is notified by calling 836 * @msg->complete(). In case of error, @msg->status is set to negative error 837 * number, otherwise it contains zero (and @msg->actual_length is updated). 838 */ 839 static void ep93xx_spi_work(struct work_struct *work) 840 { 841 struct ep93xx_spi *espi = work_to_espi(work); 842 struct spi_message *msg; 843 844 spin_lock_irq(&espi->lock); 845 if (!espi->running || espi->current_msg || 846 list_empty(&espi->msg_queue)) { 847 spin_unlock_irq(&espi->lock); 848 return; 849 } 850 msg = list_first_entry(&espi->msg_queue, struct spi_message, queue); 851 list_del_init(&msg->queue); 852 espi->current_msg = msg; 853 spin_unlock_irq(&espi->lock); 854 855 ep93xx_spi_process_message(espi, msg); 856 857 /* 858 * Update the current message and re-schedule ourselves if there are 859 * more messages in the queue. 860 */ 861 spin_lock_irq(&espi->lock); 862 espi->current_msg = NULL; 863 if (espi->running && !list_empty(&espi->msg_queue)) 864 queue_work(espi->wq, &espi->msg_work); 865 spin_unlock_irq(&espi->lock); 866 867 /* notify the protocol driver that we are done with this message */ 868 msg->complete(msg->context); 869 } 870 871 static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id) 872 { 873 struct ep93xx_spi *espi = dev_id; 874 u8 irq_status = ep93xx_spi_read_u8(espi, SSPIIR); 875 876 /* 877 * If we got ROR (receive overrun) interrupt we know that something is 878 * wrong. Just abort the message. 879 */ 880 if (unlikely(irq_status & SSPIIR_RORIS)) { 881 /* clear the overrun interrupt */ 882 ep93xx_spi_write_u8(espi, SSPICR, 0); 883 dev_warn(&espi->pdev->dev, 884 "receive overrun, aborting the message\n"); 885 espi->current_msg->status = -EIO; 886 } else { 887 /* 888 * Interrupt is either RX (RIS) or TX (TIS). For both cases we 889 * simply execute next data transfer. 890 */ 891 if (ep93xx_spi_read_write(espi)) { 892 /* 893 * In normal case, there still is some processing left 894 * for current transfer. Let's wait for the next 895 * interrupt then. 896 */ 897 return IRQ_HANDLED; 898 } 899 } 900 901 /* 902 * Current transfer is finished, either with error or with success. In 903 * any case we disable interrupts and notify the worker to handle 904 * any post-processing of the message. 905 */ 906 ep93xx_spi_disable_interrupts(espi); 907 complete(&espi->wait); 908 return IRQ_HANDLED; 909 } 910 911 static bool ep93xx_spi_dma_filter(struct dma_chan *chan, void *filter_param) 912 { 913 if (ep93xx_dma_chan_is_m2p(chan)) 914 return false; 915 916 chan->private = filter_param; 917 return true; 918 } 919 920 static int ep93xx_spi_setup_dma(struct ep93xx_spi *espi) 921 { 922 dma_cap_mask_t mask; 923 int ret; 924 925 espi->zeropage = (void *)get_zeroed_page(GFP_KERNEL); 926 if (!espi->zeropage) 927 return -ENOMEM; 928 929 dma_cap_zero(mask); 930 dma_cap_set(DMA_SLAVE, mask); 931 932 espi->dma_rx_data.port = EP93XX_DMA_SSP; 933 espi->dma_rx_data.direction = DMA_DEV_TO_MEM; 934 espi->dma_rx_data.name = "ep93xx-spi-rx"; 935 936 espi->dma_rx = dma_request_channel(mask, ep93xx_spi_dma_filter, 937 &espi->dma_rx_data); 938 if (!espi->dma_rx) { 939 ret = -ENODEV; 940 goto fail_free_page; 941 } 942 943 espi->dma_tx_data.port = EP93XX_DMA_SSP; 944 espi->dma_tx_data.direction = DMA_MEM_TO_DEV; 945 espi->dma_tx_data.name = "ep93xx-spi-tx"; 946 947 espi->dma_tx = dma_request_channel(mask, ep93xx_spi_dma_filter, 948 &espi->dma_tx_data); 949 if (!espi->dma_tx) { 950 ret = -ENODEV; 951 goto fail_release_rx; 952 } 953 954 return 0; 955 956 fail_release_rx: 957 dma_release_channel(espi->dma_rx); 958 espi->dma_rx = NULL; 959 fail_free_page: 960 free_page((unsigned long)espi->zeropage); 961 962 return ret; 963 } 964 965 static void ep93xx_spi_release_dma(struct ep93xx_spi *espi) 966 { 967 if (espi->dma_rx) { 968 dma_release_channel(espi->dma_rx); 969 sg_free_table(&espi->rx_sgt); 970 } 971 if (espi->dma_tx) { 972 dma_release_channel(espi->dma_tx); 973 sg_free_table(&espi->tx_sgt); 974 } 975 976 if (espi->zeropage) 977 free_page((unsigned long)espi->zeropage); 978 } 979 980 static int ep93xx_spi_probe(struct platform_device *pdev) 981 { 982 struct spi_master *master; 983 struct ep93xx_spi_info *info; 984 struct ep93xx_spi *espi; 985 struct resource *res; 986 int irq; 987 int error; 988 989 info = pdev->dev.platform_data; 990 991 irq = platform_get_irq(pdev, 0); 992 if (irq < 0) { 993 dev_err(&pdev->dev, "failed to get irq resources\n"); 994 return -EBUSY; 995 } 996 997 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 998 if (!res) { 999 dev_err(&pdev->dev, "unable to get iomem resource\n"); 1000 return -ENODEV; 1001 } 1002 1003 master = spi_alloc_master(&pdev->dev, sizeof(*espi)); 1004 if (!master) 1005 return -ENOMEM; 1006 1007 master->setup = ep93xx_spi_setup; 1008 master->transfer = ep93xx_spi_transfer; 1009 master->cleanup = ep93xx_spi_cleanup; 1010 master->bus_num = pdev->id; 1011 master->num_chipselect = info->num_chipselect; 1012 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1013 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); 1014 1015 platform_set_drvdata(pdev, master); 1016 1017 espi = spi_master_get_devdata(master); 1018 1019 espi->clk = devm_clk_get(&pdev->dev, NULL); 1020 if (IS_ERR(espi->clk)) { 1021 dev_err(&pdev->dev, "unable to get spi clock\n"); 1022 error = PTR_ERR(espi->clk); 1023 goto fail_release_master; 1024 } 1025 1026 spin_lock_init(&espi->lock); 1027 init_completion(&espi->wait); 1028 1029 /* 1030 * Calculate maximum and minimum supported clock rates 1031 * for the controller. 1032 */ 1033 espi->max_rate = clk_get_rate(espi->clk) / 2; 1034 espi->min_rate = clk_get_rate(espi->clk) / (254 * 256); 1035 espi->pdev = pdev; 1036 1037 espi->sspdr_phys = res->start + SSPDR; 1038 1039 espi->regs_base = devm_ioremap_resource(&pdev->dev, res); 1040 if (IS_ERR(espi->regs_base)) { 1041 error = PTR_ERR(espi->regs_base); 1042 goto fail_release_master; 1043 } 1044 1045 error = devm_request_irq(&pdev->dev, irq, ep93xx_spi_interrupt, 1046 0, "ep93xx-spi", espi); 1047 if (error) { 1048 dev_err(&pdev->dev, "failed to request irq\n"); 1049 goto fail_release_master; 1050 } 1051 1052 if (info->use_dma && ep93xx_spi_setup_dma(espi)) 1053 dev_warn(&pdev->dev, "DMA setup failed. Falling back to PIO\n"); 1054 1055 espi->wq = create_singlethread_workqueue("ep93xx_spid"); 1056 if (!espi->wq) { 1057 dev_err(&pdev->dev, "unable to create workqueue\n"); 1058 error = -ENOMEM; 1059 goto fail_free_dma; 1060 } 1061 INIT_WORK(&espi->msg_work, ep93xx_spi_work); 1062 INIT_LIST_HEAD(&espi->msg_queue); 1063 espi->running = true; 1064 1065 /* make sure that the hardware is disabled */ 1066 ep93xx_spi_write_u8(espi, SSPCR1, 0); 1067 1068 error = spi_register_master(master); 1069 if (error) { 1070 dev_err(&pdev->dev, "failed to register SPI master\n"); 1071 goto fail_free_queue; 1072 } 1073 1074 dev_info(&pdev->dev, "EP93xx SPI Controller at 0x%08lx irq %d\n", 1075 (unsigned long)res->start, irq); 1076 1077 return 0; 1078 1079 fail_free_queue: 1080 destroy_workqueue(espi->wq); 1081 fail_free_dma: 1082 ep93xx_spi_release_dma(espi); 1083 fail_release_master: 1084 spi_master_put(master); 1085 1086 return error; 1087 } 1088 1089 static int ep93xx_spi_remove(struct platform_device *pdev) 1090 { 1091 struct spi_master *master = platform_get_drvdata(pdev); 1092 struct ep93xx_spi *espi = spi_master_get_devdata(master); 1093 1094 spin_lock_irq(&espi->lock); 1095 espi->running = false; 1096 spin_unlock_irq(&espi->lock); 1097 1098 destroy_workqueue(espi->wq); 1099 1100 /* 1101 * Complete remaining messages with %-ESHUTDOWN status. 1102 */ 1103 spin_lock_irq(&espi->lock); 1104 while (!list_empty(&espi->msg_queue)) { 1105 struct spi_message *msg; 1106 1107 msg = list_first_entry(&espi->msg_queue, 1108 struct spi_message, queue); 1109 list_del_init(&msg->queue); 1110 msg->status = -ESHUTDOWN; 1111 spin_unlock_irq(&espi->lock); 1112 msg->complete(msg->context); 1113 spin_lock_irq(&espi->lock); 1114 } 1115 spin_unlock_irq(&espi->lock); 1116 1117 ep93xx_spi_release_dma(espi); 1118 1119 spi_unregister_master(master); 1120 return 0; 1121 } 1122 1123 static struct platform_driver ep93xx_spi_driver = { 1124 .driver = { 1125 .name = "ep93xx-spi", 1126 .owner = THIS_MODULE, 1127 }, 1128 .probe = ep93xx_spi_probe, 1129 .remove = ep93xx_spi_remove, 1130 }; 1131 module_platform_driver(ep93xx_spi_driver); 1132 1133 MODULE_DESCRIPTION("EP93xx SPI Controller driver"); 1134 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>"); 1135 MODULE_LICENSE("GPL"); 1136 MODULE_ALIAS("platform:ep93xx-spi"); 1137