1 /* 2 * Driver for Cirrus Logic EP93xx SPI controller. 3 * 4 * Copyright (C) 2010-2011 Mika Westerberg 5 * 6 * Explicit FIFO handling code was inspired by amba-pl022 driver. 7 * 8 * Chip select support using other than built-in GPIOs by H. Hartley Sweeten. 9 * 10 * For more information about the SPI controller see documentation on Cirrus 11 * Logic web site: 12 * http://www.cirrus.com/en/pubs/manual/EP93xx_Users_Guide_UM1.pdf 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 */ 18 19 #include <linux/io.h> 20 #include <linux/clk.h> 21 #include <linux/err.h> 22 #include <linux/delay.h> 23 #include <linux/device.h> 24 #include <linux/dmaengine.h> 25 #include <linux/bitops.h> 26 #include <linux/interrupt.h> 27 #include <linux/module.h> 28 #include <linux/platform_device.h> 29 #include <linux/workqueue.h> 30 #include <linux/sched.h> 31 #include <linux/scatterlist.h> 32 #include <linux/spi/spi.h> 33 34 #include <linux/platform_data/dma-ep93xx.h> 35 #include <linux/platform_data/spi-ep93xx.h> 36 37 #define SSPCR0 0x0000 38 #define SSPCR0_MODE_SHIFT 6 39 #define SSPCR0_SCR_SHIFT 8 40 41 #define SSPCR1 0x0004 42 #define SSPCR1_RIE BIT(0) 43 #define SSPCR1_TIE BIT(1) 44 #define SSPCR1_RORIE BIT(2) 45 #define SSPCR1_LBM BIT(3) 46 #define SSPCR1_SSE BIT(4) 47 #define SSPCR1_MS BIT(5) 48 #define SSPCR1_SOD BIT(6) 49 50 #define SSPDR 0x0008 51 52 #define SSPSR 0x000c 53 #define SSPSR_TFE BIT(0) 54 #define SSPSR_TNF BIT(1) 55 #define SSPSR_RNE BIT(2) 56 #define SSPSR_RFF BIT(3) 57 #define SSPSR_BSY BIT(4) 58 #define SSPCPSR 0x0010 59 60 #define SSPIIR 0x0014 61 #define SSPIIR_RIS BIT(0) 62 #define SSPIIR_TIS BIT(1) 63 #define SSPIIR_RORIS BIT(2) 64 #define SSPICR SSPIIR 65 66 /* timeout in milliseconds */ 67 #define SPI_TIMEOUT 5 68 /* maximum depth of RX/TX FIFO */ 69 #define SPI_FIFO_SIZE 8 70 71 /** 72 * struct ep93xx_spi - EP93xx SPI controller structure 73 * @lock: spinlock that protects concurrent accesses to fields @running, 74 * @current_msg and @msg_queue 75 * @pdev: pointer to platform device 76 * @clk: clock for the controller 77 * @regs_base: pointer to ioremap()'d registers 78 * @sspdr_phys: physical address of the SSPDR register 79 * @min_rate: minimum clock rate (in Hz) supported by the controller 80 * @max_rate: maximum clock rate (in Hz) supported by the controller 81 * @running: is the queue running 82 * @wq: workqueue used by the driver 83 * @msg_work: work that is queued for the driver 84 * @wait: wait here until given transfer is completed 85 * @msg_queue: queue for the messages 86 * @current_msg: message that is currently processed (or %NULL if none) 87 * @tx: current byte in transfer to transmit 88 * @rx: current byte in transfer to receive 89 * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one 90 * frame decreases this level and sending one frame increases it. 91 * @dma_rx: RX DMA channel 92 * @dma_tx: TX DMA channel 93 * @dma_rx_data: RX parameters passed to the DMA engine 94 * @dma_tx_data: TX parameters passed to the DMA engine 95 * @rx_sgt: sg table for RX transfers 96 * @tx_sgt: sg table for TX transfers 97 * @zeropage: dummy page used as RX buffer when only TX buffer is passed in by 98 * the client 99 * 100 * This structure holds EP93xx SPI controller specific information. When 101 * @running is %true, driver accepts transfer requests from protocol drivers. 102 * @current_msg is used to hold pointer to the message that is currently 103 * processed. If @current_msg is %NULL, it means that no processing is going 104 * on. 105 * 106 * Most of the fields are only written once and they can be accessed without 107 * taking the @lock. Fields that are accessed concurrently are: @current_msg, 108 * @running, and @msg_queue. 109 */ 110 struct ep93xx_spi { 111 spinlock_t lock; 112 const struct platform_device *pdev; 113 struct clk *clk; 114 void __iomem *regs_base; 115 unsigned long sspdr_phys; 116 unsigned long min_rate; 117 unsigned long max_rate; 118 bool running; 119 struct workqueue_struct *wq; 120 struct work_struct msg_work; 121 struct completion wait; 122 struct list_head msg_queue; 123 struct spi_message *current_msg; 124 size_t tx; 125 size_t rx; 126 size_t fifo_level; 127 struct dma_chan *dma_rx; 128 struct dma_chan *dma_tx; 129 struct ep93xx_dma_data dma_rx_data; 130 struct ep93xx_dma_data dma_tx_data; 131 struct sg_table rx_sgt; 132 struct sg_table tx_sgt; 133 void *zeropage; 134 }; 135 136 /** 137 * struct ep93xx_spi_chip - SPI device hardware settings 138 * @spi: back pointer to the SPI device 139 * @rate: max rate in hz this chip supports 140 * @div_cpsr: cpsr (pre-scaler) divider 141 * @div_scr: scr divider 142 * @dss: bits per word (4 - 16 bits) 143 * @ops: private chip operations 144 * 145 * This structure is used to store hardware register specific settings for each 146 * SPI device. Settings are written to hardware by function 147 * ep93xx_spi_chip_setup(). 148 */ 149 struct ep93xx_spi_chip { 150 const struct spi_device *spi; 151 unsigned long rate; 152 u8 div_cpsr; 153 u8 div_scr; 154 u8 dss; 155 struct ep93xx_spi_chip_ops *ops; 156 }; 157 158 /* converts bits per word to CR0.DSS value */ 159 #define bits_per_word_to_dss(bpw) ((bpw) - 1) 160 161 static void ep93xx_spi_write_u8(const struct ep93xx_spi *espi, 162 u16 reg, u8 value) 163 { 164 writeb(value, espi->regs_base + reg); 165 } 166 167 static u8 ep93xx_spi_read_u8(const struct ep93xx_spi *spi, u16 reg) 168 { 169 return readb(spi->regs_base + reg); 170 } 171 172 static void ep93xx_spi_write_u16(const struct ep93xx_spi *espi, 173 u16 reg, u16 value) 174 { 175 writew(value, espi->regs_base + reg); 176 } 177 178 static u16 ep93xx_spi_read_u16(const struct ep93xx_spi *spi, u16 reg) 179 { 180 return readw(spi->regs_base + reg); 181 } 182 183 static int ep93xx_spi_enable(const struct ep93xx_spi *espi) 184 { 185 u8 regval; 186 int err; 187 188 err = clk_enable(espi->clk); 189 if (err) 190 return err; 191 192 regval = ep93xx_spi_read_u8(espi, SSPCR1); 193 regval |= SSPCR1_SSE; 194 ep93xx_spi_write_u8(espi, SSPCR1, regval); 195 196 return 0; 197 } 198 199 static void ep93xx_spi_disable(const struct ep93xx_spi *espi) 200 { 201 u8 regval; 202 203 regval = ep93xx_spi_read_u8(espi, SSPCR1); 204 regval &= ~SSPCR1_SSE; 205 ep93xx_spi_write_u8(espi, SSPCR1, regval); 206 207 clk_disable(espi->clk); 208 } 209 210 static void ep93xx_spi_enable_interrupts(const struct ep93xx_spi *espi) 211 { 212 u8 regval; 213 214 regval = ep93xx_spi_read_u8(espi, SSPCR1); 215 regval |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE); 216 ep93xx_spi_write_u8(espi, SSPCR1, regval); 217 } 218 219 static void ep93xx_spi_disable_interrupts(const struct ep93xx_spi *espi) 220 { 221 u8 regval; 222 223 regval = ep93xx_spi_read_u8(espi, SSPCR1); 224 regval &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE); 225 ep93xx_spi_write_u8(espi, SSPCR1, regval); 226 } 227 228 /** 229 * ep93xx_spi_calc_divisors() - calculates SPI clock divisors 230 * @espi: ep93xx SPI controller struct 231 * @chip: divisors are calculated for this chip 232 * @rate: desired SPI output clock rate 233 * 234 * Function calculates cpsr (clock pre-scaler) and scr divisors based on 235 * given @rate and places them to @chip->div_cpsr and @chip->div_scr. If, 236 * for some reason, divisors cannot be calculated nothing is stored and 237 * %-EINVAL is returned. 238 */ 239 static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi, 240 struct ep93xx_spi_chip *chip, 241 unsigned long rate) 242 { 243 unsigned long spi_clk_rate = clk_get_rate(espi->clk); 244 int cpsr, scr; 245 246 /* 247 * Make sure that max value is between values supported by the 248 * controller. Note that minimum value is already checked in 249 * ep93xx_spi_transfer(). 250 */ 251 rate = clamp(rate, espi->min_rate, espi->max_rate); 252 253 /* 254 * Calculate divisors so that we can get speed according the 255 * following formula: 256 * rate = spi_clock_rate / (cpsr * (1 + scr)) 257 * 258 * cpsr must be even number and starts from 2, scr can be any number 259 * between 0 and 255. 260 */ 261 for (cpsr = 2; cpsr <= 254; cpsr += 2) { 262 for (scr = 0; scr <= 255; scr++) { 263 if ((spi_clk_rate / (cpsr * (scr + 1))) <= rate) { 264 chip->div_scr = (u8)scr; 265 chip->div_cpsr = (u8)cpsr; 266 return 0; 267 } 268 } 269 } 270 271 return -EINVAL; 272 } 273 274 static void ep93xx_spi_cs_control(struct spi_device *spi, bool control) 275 { 276 struct ep93xx_spi_chip *chip = spi_get_ctldata(spi); 277 int value = (spi->mode & SPI_CS_HIGH) ? control : !control; 278 279 if (chip->ops && chip->ops->cs_control) 280 chip->ops->cs_control(spi, value); 281 } 282 283 /** 284 * ep93xx_spi_setup() - setup an SPI device 285 * @spi: SPI device to setup 286 * 287 * This function sets up SPI device mode, speed etc. Can be called multiple 288 * times for a single device. Returns %0 in case of success, negative error in 289 * case of failure. When this function returns success, the device is 290 * deselected. 291 */ 292 static int ep93xx_spi_setup(struct spi_device *spi) 293 { 294 struct ep93xx_spi *espi = spi_master_get_devdata(spi->master); 295 struct ep93xx_spi_chip *chip; 296 297 chip = spi_get_ctldata(spi); 298 if (!chip) { 299 dev_dbg(&espi->pdev->dev, "initial setup for %s\n", 300 spi->modalias); 301 302 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 303 if (!chip) 304 return -ENOMEM; 305 306 chip->spi = spi; 307 chip->ops = spi->controller_data; 308 309 if (chip->ops && chip->ops->setup) { 310 int ret = chip->ops->setup(spi); 311 if (ret) { 312 kfree(chip); 313 return ret; 314 } 315 } 316 317 spi_set_ctldata(spi, chip); 318 } 319 320 if (spi->max_speed_hz != chip->rate) { 321 int err; 322 323 err = ep93xx_spi_calc_divisors(espi, chip, spi->max_speed_hz); 324 if (err != 0) { 325 spi_set_ctldata(spi, NULL); 326 kfree(chip); 327 return err; 328 } 329 chip->rate = spi->max_speed_hz; 330 } 331 332 chip->dss = bits_per_word_to_dss(spi->bits_per_word); 333 334 ep93xx_spi_cs_control(spi, false); 335 return 0; 336 } 337 338 /** 339 * ep93xx_spi_transfer() - queue message to be transferred 340 * @spi: target SPI device 341 * @msg: message to be transferred 342 * 343 * This function is called by SPI device drivers when they are going to transfer 344 * a new message. It simply puts the message in the queue and schedules 345 * workqueue to perform the actual transfer later on. 346 * 347 * Returns %0 on success and negative error in case of failure. 348 */ 349 static int ep93xx_spi_transfer(struct spi_device *spi, struct spi_message *msg) 350 { 351 struct ep93xx_spi *espi = spi_master_get_devdata(spi->master); 352 struct spi_transfer *t; 353 unsigned long flags; 354 355 if (!msg || !msg->complete) 356 return -EINVAL; 357 358 /* first validate each transfer */ 359 list_for_each_entry(t, &msg->transfers, transfer_list) { 360 if (t->speed_hz && t->speed_hz < espi->min_rate) 361 return -EINVAL; 362 } 363 364 /* 365 * Now that we own the message, let's initialize it so that it is 366 * suitable for us. We use @msg->status to signal whether there was 367 * error in transfer and @msg->state is used to hold pointer to the 368 * current transfer (or %NULL if no active current transfer). 369 */ 370 msg->state = NULL; 371 msg->status = 0; 372 msg->actual_length = 0; 373 374 spin_lock_irqsave(&espi->lock, flags); 375 if (!espi->running) { 376 spin_unlock_irqrestore(&espi->lock, flags); 377 return -ESHUTDOWN; 378 } 379 list_add_tail(&msg->queue, &espi->msg_queue); 380 queue_work(espi->wq, &espi->msg_work); 381 spin_unlock_irqrestore(&espi->lock, flags); 382 383 return 0; 384 } 385 386 /** 387 * ep93xx_spi_cleanup() - cleans up master controller specific state 388 * @spi: SPI device to cleanup 389 * 390 * This function releases master controller specific state for given @spi 391 * device. 392 */ 393 static void ep93xx_spi_cleanup(struct spi_device *spi) 394 { 395 struct ep93xx_spi_chip *chip; 396 397 chip = spi_get_ctldata(spi); 398 if (chip) { 399 if (chip->ops && chip->ops->cleanup) 400 chip->ops->cleanup(spi); 401 spi_set_ctldata(spi, NULL); 402 kfree(chip); 403 } 404 } 405 406 /** 407 * ep93xx_spi_chip_setup() - configures hardware according to given @chip 408 * @espi: ep93xx SPI controller struct 409 * @chip: chip specific settings 410 * 411 * This function sets up the actual hardware registers with settings given in 412 * @chip. Note that no validation is done so make sure that callers validate 413 * settings before calling this. 414 */ 415 static void ep93xx_spi_chip_setup(const struct ep93xx_spi *espi, 416 const struct ep93xx_spi_chip *chip) 417 { 418 u16 cr0; 419 420 cr0 = chip->div_scr << SSPCR0_SCR_SHIFT; 421 cr0 |= (chip->spi->mode & (SPI_CPHA|SPI_CPOL)) << SSPCR0_MODE_SHIFT; 422 cr0 |= chip->dss; 423 424 dev_dbg(&espi->pdev->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n", 425 chip->spi->mode, chip->div_cpsr, chip->div_scr, chip->dss); 426 dev_dbg(&espi->pdev->dev, "setup: cr0 %#x", cr0); 427 428 ep93xx_spi_write_u8(espi, SSPCPSR, chip->div_cpsr); 429 ep93xx_spi_write_u16(espi, SSPCR0, cr0); 430 } 431 432 static void ep93xx_do_write(struct ep93xx_spi *espi, struct spi_transfer *t) 433 { 434 if (t->bits_per_word > 8) { 435 u16 tx_val = 0; 436 437 if (t->tx_buf) 438 tx_val = ((u16 *)t->tx_buf)[espi->tx]; 439 ep93xx_spi_write_u16(espi, SSPDR, tx_val); 440 espi->tx += sizeof(tx_val); 441 } else { 442 u8 tx_val = 0; 443 444 if (t->tx_buf) 445 tx_val = ((u8 *)t->tx_buf)[espi->tx]; 446 ep93xx_spi_write_u8(espi, SSPDR, tx_val); 447 espi->tx += sizeof(tx_val); 448 } 449 } 450 451 static void ep93xx_do_read(struct ep93xx_spi *espi, struct spi_transfer *t) 452 { 453 if (t->bits_per_word > 8) { 454 u16 rx_val; 455 456 rx_val = ep93xx_spi_read_u16(espi, SSPDR); 457 if (t->rx_buf) 458 ((u16 *)t->rx_buf)[espi->rx] = rx_val; 459 espi->rx += sizeof(rx_val); 460 } else { 461 u8 rx_val; 462 463 rx_val = ep93xx_spi_read_u8(espi, SSPDR); 464 if (t->rx_buf) 465 ((u8 *)t->rx_buf)[espi->rx] = rx_val; 466 espi->rx += sizeof(rx_val); 467 } 468 } 469 470 /** 471 * ep93xx_spi_read_write() - perform next RX/TX transfer 472 * @espi: ep93xx SPI controller struct 473 * 474 * This function transfers next bytes (or half-words) to/from RX/TX FIFOs. If 475 * called several times, the whole transfer will be completed. Returns 476 * %-EINPROGRESS when current transfer was not yet completed otherwise %0. 477 * 478 * When this function is finished, RX FIFO should be empty and TX FIFO should be 479 * full. 480 */ 481 static int ep93xx_spi_read_write(struct ep93xx_spi *espi) 482 { 483 struct spi_message *msg = espi->current_msg; 484 struct spi_transfer *t = msg->state; 485 486 /* read as long as RX FIFO has frames in it */ 487 while ((ep93xx_spi_read_u8(espi, SSPSR) & SSPSR_RNE)) { 488 ep93xx_do_read(espi, t); 489 espi->fifo_level--; 490 } 491 492 /* write as long as TX FIFO has room */ 493 while (espi->fifo_level < SPI_FIFO_SIZE && espi->tx < t->len) { 494 ep93xx_do_write(espi, t); 495 espi->fifo_level++; 496 } 497 498 if (espi->rx == t->len) 499 return 0; 500 501 return -EINPROGRESS; 502 } 503 504 static void ep93xx_spi_pio_transfer(struct ep93xx_spi *espi) 505 { 506 /* 507 * Now everything is set up for the current transfer. We prime the TX 508 * FIFO, enable interrupts, and wait for the transfer to complete. 509 */ 510 if (ep93xx_spi_read_write(espi)) { 511 ep93xx_spi_enable_interrupts(espi); 512 wait_for_completion(&espi->wait); 513 } 514 } 515 516 /** 517 * ep93xx_spi_dma_prepare() - prepares a DMA transfer 518 * @espi: ep93xx SPI controller struct 519 * @dir: DMA transfer direction 520 * 521 * Function configures the DMA, maps the buffer and prepares the DMA 522 * descriptor. Returns a valid DMA descriptor in case of success and ERR_PTR 523 * in case of failure. 524 */ 525 static struct dma_async_tx_descriptor * 526 ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_transfer_direction dir) 527 { 528 struct spi_transfer *t = espi->current_msg->state; 529 struct dma_async_tx_descriptor *txd; 530 enum dma_slave_buswidth buswidth; 531 struct dma_slave_config conf; 532 struct scatterlist *sg; 533 struct sg_table *sgt; 534 struct dma_chan *chan; 535 const void *buf, *pbuf; 536 size_t len = t->len; 537 int i, ret, nents; 538 539 if (t->bits_per_word > 8) 540 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; 541 else 542 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; 543 544 memset(&conf, 0, sizeof(conf)); 545 conf.direction = dir; 546 547 if (dir == DMA_DEV_TO_MEM) { 548 chan = espi->dma_rx; 549 buf = t->rx_buf; 550 sgt = &espi->rx_sgt; 551 552 conf.src_addr = espi->sspdr_phys; 553 conf.src_addr_width = buswidth; 554 } else { 555 chan = espi->dma_tx; 556 buf = t->tx_buf; 557 sgt = &espi->tx_sgt; 558 559 conf.dst_addr = espi->sspdr_phys; 560 conf.dst_addr_width = buswidth; 561 } 562 563 ret = dmaengine_slave_config(chan, &conf); 564 if (ret) 565 return ERR_PTR(ret); 566 567 /* 568 * We need to split the transfer into PAGE_SIZE'd chunks. This is 569 * because we are using @espi->zeropage to provide a zero RX buffer 570 * for the TX transfers and we have only allocated one page for that. 571 * 572 * For performance reasons we allocate a new sg_table only when 573 * needed. Otherwise we will re-use the current one. Eventually the 574 * last sg_table is released in ep93xx_spi_release_dma(). 575 */ 576 577 nents = DIV_ROUND_UP(len, PAGE_SIZE); 578 if (nents != sgt->nents) { 579 sg_free_table(sgt); 580 581 ret = sg_alloc_table(sgt, nents, GFP_KERNEL); 582 if (ret) 583 return ERR_PTR(ret); 584 } 585 586 pbuf = buf; 587 for_each_sg(sgt->sgl, sg, sgt->nents, i) { 588 size_t bytes = min_t(size_t, len, PAGE_SIZE); 589 590 if (buf) { 591 sg_set_page(sg, virt_to_page(pbuf), bytes, 592 offset_in_page(pbuf)); 593 } else { 594 sg_set_page(sg, virt_to_page(espi->zeropage), 595 bytes, 0); 596 } 597 598 pbuf += bytes; 599 len -= bytes; 600 } 601 602 if (WARN_ON(len)) { 603 dev_warn(&espi->pdev->dev, "len = %d expected 0!", len); 604 return ERR_PTR(-EINVAL); 605 } 606 607 nents = dma_map_sg(chan->device->dev, sgt->sgl, sgt->nents, dir); 608 if (!nents) 609 return ERR_PTR(-ENOMEM); 610 611 txd = dmaengine_prep_slave_sg(chan, sgt->sgl, nents, dir, DMA_CTRL_ACK); 612 if (!txd) { 613 dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir); 614 return ERR_PTR(-ENOMEM); 615 } 616 return txd; 617 } 618 619 /** 620 * ep93xx_spi_dma_finish() - finishes with a DMA transfer 621 * @espi: ep93xx SPI controller struct 622 * @dir: DMA transfer direction 623 * 624 * Function finishes with the DMA transfer. After this, the DMA buffer is 625 * unmapped. 626 */ 627 static void ep93xx_spi_dma_finish(struct ep93xx_spi *espi, 628 enum dma_transfer_direction dir) 629 { 630 struct dma_chan *chan; 631 struct sg_table *sgt; 632 633 if (dir == DMA_DEV_TO_MEM) { 634 chan = espi->dma_rx; 635 sgt = &espi->rx_sgt; 636 } else { 637 chan = espi->dma_tx; 638 sgt = &espi->tx_sgt; 639 } 640 641 dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir); 642 } 643 644 static void ep93xx_spi_dma_callback(void *callback_param) 645 { 646 complete(callback_param); 647 } 648 649 static void ep93xx_spi_dma_transfer(struct ep93xx_spi *espi) 650 { 651 struct spi_message *msg = espi->current_msg; 652 struct dma_async_tx_descriptor *rxd, *txd; 653 654 rxd = ep93xx_spi_dma_prepare(espi, DMA_DEV_TO_MEM); 655 if (IS_ERR(rxd)) { 656 dev_err(&espi->pdev->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd)); 657 msg->status = PTR_ERR(rxd); 658 return; 659 } 660 661 txd = ep93xx_spi_dma_prepare(espi, DMA_MEM_TO_DEV); 662 if (IS_ERR(txd)) { 663 ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM); 664 dev_err(&espi->pdev->dev, "DMA TX failed: %ld\n", PTR_ERR(rxd)); 665 msg->status = PTR_ERR(txd); 666 return; 667 } 668 669 /* We are ready when RX is done */ 670 rxd->callback = ep93xx_spi_dma_callback; 671 rxd->callback_param = &espi->wait; 672 673 /* Now submit both descriptors and wait while they finish */ 674 dmaengine_submit(rxd); 675 dmaengine_submit(txd); 676 677 dma_async_issue_pending(espi->dma_rx); 678 dma_async_issue_pending(espi->dma_tx); 679 680 wait_for_completion(&espi->wait); 681 682 ep93xx_spi_dma_finish(espi, DMA_MEM_TO_DEV); 683 ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM); 684 } 685 686 /** 687 * ep93xx_spi_process_transfer() - processes one SPI transfer 688 * @espi: ep93xx SPI controller struct 689 * @msg: current message 690 * @t: transfer to process 691 * 692 * This function processes one SPI transfer given in @t. Function waits until 693 * transfer is complete (may sleep) and updates @msg->status based on whether 694 * transfer was successfully processed or not. 695 */ 696 static void ep93xx_spi_process_transfer(struct ep93xx_spi *espi, 697 struct spi_message *msg, 698 struct spi_transfer *t) 699 { 700 struct ep93xx_spi_chip *chip = spi_get_ctldata(msg->spi); 701 int err; 702 703 msg->state = t; 704 705 err = ep93xx_spi_calc_divisors(espi, chip, t->speed_hz); 706 if (err) { 707 dev_err(&espi->pdev->dev, "failed to adjust speed\n"); 708 msg->status = err; 709 return; 710 } 711 712 chip->dss = bits_per_word_to_dss(t->bits_per_word); 713 714 ep93xx_spi_chip_setup(espi, chip); 715 716 espi->rx = 0; 717 espi->tx = 0; 718 719 /* 720 * There is no point of setting up DMA for the transfers which will 721 * fit into the FIFO and can be transferred with a single interrupt. 722 * So in these cases we will be using PIO and don't bother for DMA. 723 */ 724 if (espi->dma_rx && t->len > SPI_FIFO_SIZE) 725 ep93xx_spi_dma_transfer(espi); 726 else 727 ep93xx_spi_pio_transfer(espi); 728 729 /* 730 * In case of error during transmit, we bail out from processing 731 * the message. 732 */ 733 if (msg->status) 734 return; 735 736 msg->actual_length += t->len; 737 738 /* 739 * After this transfer is finished, perform any possible 740 * post-transfer actions requested by the protocol driver. 741 */ 742 if (t->delay_usecs) { 743 set_current_state(TASK_UNINTERRUPTIBLE); 744 schedule_timeout(usecs_to_jiffies(t->delay_usecs)); 745 } 746 if (t->cs_change) { 747 if (!list_is_last(&t->transfer_list, &msg->transfers)) { 748 /* 749 * In case protocol driver is asking us to drop the 750 * chipselect briefly, we let the scheduler to handle 751 * any "delay" here. 752 */ 753 ep93xx_spi_cs_control(msg->spi, false); 754 cond_resched(); 755 ep93xx_spi_cs_control(msg->spi, true); 756 } 757 } 758 } 759 760 /* 761 * ep93xx_spi_process_message() - process one SPI message 762 * @espi: ep93xx SPI controller struct 763 * @msg: message to process 764 * 765 * This function processes a single SPI message. We go through all transfers in 766 * the message and pass them to ep93xx_spi_process_transfer(). Chipselect is 767 * asserted during the whole message (unless per transfer cs_change is set). 768 * 769 * @msg->status contains %0 in case of success or negative error code in case of 770 * failure. 771 */ 772 static void ep93xx_spi_process_message(struct ep93xx_spi *espi, 773 struct spi_message *msg) 774 { 775 unsigned long timeout; 776 struct spi_transfer *t; 777 int err; 778 779 /* 780 * Enable the SPI controller and its clock. 781 */ 782 err = ep93xx_spi_enable(espi); 783 if (err) { 784 dev_err(&espi->pdev->dev, "failed to enable SPI controller\n"); 785 msg->status = err; 786 return; 787 } 788 789 /* 790 * Just to be sure: flush any data from RX FIFO. 791 */ 792 timeout = jiffies + msecs_to_jiffies(SPI_TIMEOUT); 793 while (ep93xx_spi_read_u16(espi, SSPSR) & SSPSR_RNE) { 794 if (time_after(jiffies, timeout)) { 795 dev_warn(&espi->pdev->dev, 796 "timeout while flushing RX FIFO\n"); 797 msg->status = -ETIMEDOUT; 798 return; 799 } 800 ep93xx_spi_read_u16(espi, SSPDR); 801 } 802 803 /* 804 * We explicitly handle FIFO level. This way we don't have to check TX 805 * FIFO status using %SSPSR_TNF bit which may cause RX FIFO overruns. 806 */ 807 espi->fifo_level = 0; 808 809 /* 810 * Assert the chipselect. 811 */ 812 ep93xx_spi_cs_control(msg->spi, true); 813 814 list_for_each_entry(t, &msg->transfers, transfer_list) { 815 ep93xx_spi_process_transfer(espi, msg, t); 816 if (msg->status) 817 break; 818 } 819 820 /* 821 * Now the whole message is transferred (or failed for some reason). We 822 * deselect the device and disable the SPI controller. 823 */ 824 ep93xx_spi_cs_control(msg->spi, false); 825 ep93xx_spi_disable(espi); 826 } 827 828 #define work_to_espi(work) (container_of((work), struct ep93xx_spi, msg_work)) 829 830 /** 831 * ep93xx_spi_work() - EP93xx SPI workqueue worker function 832 * @work: work struct 833 * 834 * Workqueue worker function. This function is called when there are new 835 * SPI messages to be processed. Message is taken out from the queue and then 836 * passed to ep93xx_spi_process_message(). 837 * 838 * After message is transferred, protocol driver is notified by calling 839 * @msg->complete(). In case of error, @msg->status is set to negative error 840 * number, otherwise it contains zero (and @msg->actual_length is updated). 841 */ 842 static void ep93xx_spi_work(struct work_struct *work) 843 { 844 struct ep93xx_spi *espi = work_to_espi(work); 845 struct spi_message *msg; 846 847 spin_lock_irq(&espi->lock); 848 if (!espi->running || espi->current_msg || 849 list_empty(&espi->msg_queue)) { 850 spin_unlock_irq(&espi->lock); 851 return; 852 } 853 msg = list_first_entry(&espi->msg_queue, struct spi_message, queue); 854 list_del_init(&msg->queue); 855 espi->current_msg = msg; 856 spin_unlock_irq(&espi->lock); 857 858 ep93xx_spi_process_message(espi, msg); 859 860 /* 861 * Update the current message and re-schedule ourselves if there are 862 * more messages in the queue. 863 */ 864 spin_lock_irq(&espi->lock); 865 espi->current_msg = NULL; 866 if (espi->running && !list_empty(&espi->msg_queue)) 867 queue_work(espi->wq, &espi->msg_work); 868 spin_unlock_irq(&espi->lock); 869 870 /* notify the protocol driver that we are done with this message */ 871 msg->complete(msg->context); 872 } 873 874 static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id) 875 { 876 struct ep93xx_spi *espi = dev_id; 877 u8 irq_status = ep93xx_spi_read_u8(espi, SSPIIR); 878 879 /* 880 * If we got ROR (receive overrun) interrupt we know that something is 881 * wrong. Just abort the message. 882 */ 883 if (unlikely(irq_status & SSPIIR_RORIS)) { 884 /* clear the overrun interrupt */ 885 ep93xx_spi_write_u8(espi, SSPICR, 0); 886 dev_warn(&espi->pdev->dev, 887 "receive overrun, aborting the message\n"); 888 espi->current_msg->status = -EIO; 889 } else { 890 /* 891 * Interrupt is either RX (RIS) or TX (TIS). For both cases we 892 * simply execute next data transfer. 893 */ 894 if (ep93xx_spi_read_write(espi)) { 895 /* 896 * In normal case, there still is some processing left 897 * for current transfer. Let's wait for the next 898 * interrupt then. 899 */ 900 return IRQ_HANDLED; 901 } 902 } 903 904 /* 905 * Current transfer is finished, either with error or with success. In 906 * any case we disable interrupts and notify the worker to handle 907 * any post-processing of the message. 908 */ 909 ep93xx_spi_disable_interrupts(espi); 910 complete(&espi->wait); 911 return IRQ_HANDLED; 912 } 913 914 static bool ep93xx_spi_dma_filter(struct dma_chan *chan, void *filter_param) 915 { 916 if (ep93xx_dma_chan_is_m2p(chan)) 917 return false; 918 919 chan->private = filter_param; 920 return true; 921 } 922 923 static int ep93xx_spi_setup_dma(struct ep93xx_spi *espi) 924 { 925 dma_cap_mask_t mask; 926 int ret; 927 928 espi->zeropage = (void *)get_zeroed_page(GFP_KERNEL); 929 if (!espi->zeropage) 930 return -ENOMEM; 931 932 dma_cap_zero(mask); 933 dma_cap_set(DMA_SLAVE, mask); 934 935 espi->dma_rx_data.port = EP93XX_DMA_SSP; 936 espi->dma_rx_data.direction = DMA_DEV_TO_MEM; 937 espi->dma_rx_data.name = "ep93xx-spi-rx"; 938 939 espi->dma_rx = dma_request_channel(mask, ep93xx_spi_dma_filter, 940 &espi->dma_rx_data); 941 if (!espi->dma_rx) { 942 ret = -ENODEV; 943 goto fail_free_page; 944 } 945 946 espi->dma_tx_data.port = EP93XX_DMA_SSP; 947 espi->dma_tx_data.direction = DMA_MEM_TO_DEV; 948 espi->dma_tx_data.name = "ep93xx-spi-tx"; 949 950 espi->dma_tx = dma_request_channel(mask, ep93xx_spi_dma_filter, 951 &espi->dma_tx_data); 952 if (!espi->dma_tx) { 953 ret = -ENODEV; 954 goto fail_release_rx; 955 } 956 957 return 0; 958 959 fail_release_rx: 960 dma_release_channel(espi->dma_rx); 961 espi->dma_rx = NULL; 962 fail_free_page: 963 free_page((unsigned long)espi->zeropage); 964 965 return ret; 966 } 967 968 static void ep93xx_spi_release_dma(struct ep93xx_spi *espi) 969 { 970 if (espi->dma_rx) { 971 dma_release_channel(espi->dma_rx); 972 sg_free_table(&espi->rx_sgt); 973 } 974 if (espi->dma_tx) { 975 dma_release_channel(espi->dma_tx); 976 sg_free_table(&espi->tx_sgt); 977 } 978 979 if (espi->zeropage) 980 free_page((unsigned long)espi->zeropage); 981 } 982 983 static int ep93xx_spi_probe(struct platform_device *pdev) 984 { 985 struct spi_master *master; 986 struct ep93xx_spi_info *info; 987 struct ep93xx_spi *espi; 988 struct resource *res; 989 int irq; 990 int error; 991 992 info = pdev->dev.platform_data; 993 994 irq = platform_get_irq(pdev, 0); 995 if (irq < 0) { 996 dev_err(&pdev->dev, "failed to get irq resources\n"); 997 return -EBUSY; 998 } 999 1000 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1001 if (!res) { 1002 dev_err(&pdev->dev, "unable to get iomem resource\n"); 1003 return -ENODEV; 1004 } 1005 1006 master = spi_alloc_master(&pdev->dev, sizeof(*espi)); 1007 if (!master) { 1008 dev_err(&pdev->dev, "failed to allocate spi master\n"); 1009 return -ENOMEM; 1010 } 1011 1012 master->setup = ep93xx_spi_setup; 1013 master->transfer = ep93xx_spi_transfer; 1014 master->cleanup = ep93xx_spi_cleanup; 1015 master->bus_num = pdev->id; 1016 master->num_chipselect = info->num_chipselect; 1017 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1018 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); 1019 1020 platform_set_drvdata(pdev, master); 1021 1022 espi = spi_master_get_devdata(master); 1023 1024 espi->clk = clk_get(&pdev->dev, NULL); 1025 if (IS_ERR(espi->clk)) { 1026 dev_err(&pdev->dev, "unable to get spi clock\n"); 1027 error = PTR_ERR(espi->clk); 1028 goto fail_release_master; 1029 } 1030 1031 spin_lock_init(&espi->lock); 1032 init_completion(&espi->wait); 1033 1034 /* 1035 * Calculate maximum and minimum supported clock rates 1036 * for the controller. 1037 */ 1038 espi->max_rate = clk_get_rate(espi->clk) / 2; 1039 espi->min_rate = clk_get_rate(espi->clk) / (254 * 256); 1040 espi->pdev = pdev; 1041 1042 espi->sspdr_phys = res->start + SSPDR; 1043 1044 espi->regs_base = devm_ioremap_resource(&pdev->dev, res); 1045 if (IS_ERR(espi->regs_base)) { 1046 error = PTR_ERR(espi->regs_base); 1047 goto fail_put_clock; 1048 } 1049 1050 error = devm_request_irq(&pdev->dev, irq, ep93xx_spi_interrupt, 1051 0, "ep93xx-spi", espi); 1052 if (error) { 1053 dev_err(&pdev->dev, "failed to request irq\n"); 1054 goto fail_put_clock; 1055 } 1056 1057 if (info->use_dma && ep93xx_spi_setup_dma(espi)) 1058 dev_warn(&pdev->dev, "DMA setup failed. Falling back to PIO\n"); 1059 1060 espi->wq = create_singlethread_workqueue("ep93xx_spid"); 1061 if (!espi->wq) { 1062 dev_err(&pdev->dev, "unable to create workqueue\n"); 1063 error = -ENOMEM; 1064 goto fail_free_dma; 1065 } 1066 INIT_WORK(&espi->msg_work, ep93xx_spi_work); 1067 INIT_LIST_HEAD(&espi->msg_queue); 1068 espi->running = true; 1069 1070 /* make sure that the hardware is disabled */ 1071 ep93xx_spi_write_u8(espi, SSPCR1, 0); 1072 1073 error = spi_register_master(master); 1074 if (error) { 1075 dev_err(&pdev->dev, "failed to register SPI master\n"); 1076 goto fail_free_queue; 1077 } 1078 1079 dev_info(&pdev->dev, "EP93xx SPI Controller at 0x%08lx irq %d\n", 1080 (unsigned long)res->start, irq); 1081 1082 return 0; 1083 1084 fail_free_queue: 1085 destroy_workqueue(espi->wq); 1086 fail_free_dma: 1087 ep93xx_spi_release_dma(espi); 1088 fail_put_clock: 1089 clk_put(espi->clk); 1090 fail_release_master: 1091 spi_master_put(master); 1092 1093 return error; 1094 } 1095 1096 static int ep93xx_spi_remove(struct platform_device *pdev) 1097 { 1098 struct spi_master *master = platform_get_drvdata(pdev); 1099 struct ep93xx_spi *espi = spi_master_get_devdata(master); 1100 1101 spin_lock_irq(&espi->lock); 1102 espi->running = false; 1103 spin_unlock_irq(&espi->lock); 1104 1105 destroy_workqueue(espi->wq); 1106 1107 /* 1108 * Complete remaining messages with %-ESHUTDOWN status. 1109 */ 1110 spin_lock_irq(&espi->lock); 1111 while (!list_empty(&espi->msg_queue)) { 1112 struct spi_message *msg; 1113 1114 msg = list_first_entry(&espi->msg_queue, 1115 struct spi_message, queue); 1116 list_del_init(&msg->queue); 1117 msg->status = -ESHUTDOWN; 1118 spin_unlock_irq(&espi->lock); 1119 msg->complete(msg->context); 1120 spin_lock_irq(&espi->lock); 1121 } 1122 spin_unlock_irq(&espi->lock); 1123 1124 ep93xx_spi_release_dma(espi); 1125 clk_put(espi->clk); 1126 1127 spi_unregister_master(master); 1128 return 0; 1129 } 1130 1131 static struct platform_driver ep93xx_spi_driver = { 1132 .driver = { 1133 .name = "ep93xx-spi", 1134 .owner = THIS_MODULE, 1135 }, 1136 .probe = ep93xx_spi_probe, 1137 .remove = ep93xx_spi_remove, 1138 }; 1139 module_platform_driver(ep93xx_spi_driver); 1140 1141 MODULE_DESCRIPTION("EP93xx SPI Controller driver"); 1142 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>"); 1143 MODULE_LICENSE("GPL"); 1144 MODULE_ALIAS("platform:ep93xx-spi"); 1145