1 /* 2 * Driver for Cirrus Logic EP93xx SPI controller. 3 * 4 * Copyright (C) 2010-2011 Mika Westerberg 5 * 6 * Explicit FIFO handling code was inspired by amba-pl022 driver. 7 * 8 * Chip select support using other than built-in GPIOs by H. Hartley Sweeten. 9 * 10 * For more information about the SPI controller see documentation on Cirrus 11 * Logic web site: 12 * http://www.cirrus.com/en/pubs/manual/EP93xx_Users_Guide_UM1.pdf 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 */ 18 19 #include <linux/io.h> 20 #include <linux/clk.h> 21 #include <linux/err.h> 22 #include <linux/delay.h> 23 #include <linux/device.h> 24 #include <linux/dmaengine.h> 25 #include <linux/bitops.h> 26 #include <linux/interrupt.h> 27 #include <linux/module.h> 28 #include <linux/platform_device.h> 29 #include <linux/workqueue.h> 30 #include <linux/sched.h> 31 #include <linux/scatterlist.h> 32 #include <linux/spi/spi.h> 33 34 #include <linux/platform_data/dma-ep93xx.h> 35 #include <linux/platform_data/spi-ep93xx.h> 36 37 #define SSPCR0 0x0000 38 #define SSPCR0_MODE_SHIFT 6 39 #define SSPCR0_SCR_SHIFT 8 40 41 #define SSPCR1 0x0004 42 #define SSPCR1_RIE BIT(0) 43 #define SSPCR1_TIE BIT(1) 44 #define SSPCR1_RORIE BIT(2) 45 #define SSPCR1_LBM BIT(3) 46 #define SSPCR1_SSE BIT(4) 47 #define SSPCR1_MS BIT(5) 48 #define SSPCR1_SOD BIT(6) 49 50 #define SSPDR 0x0008 51 52 #define SSPSR 0x000c 53 #define SSPSR_TFE BIT(0) 54 #define SSPSR_TNF BIT(1) 55 #define SSPSR_RNE BIT(2) 56 #define SSPSR_RFF BIT(3) 57 #define SSPSR_BSY BIT(4) 58 #define SSPCPSR 0x0010 59 60 #define SSPIIR 0x0014 61 #define SSPIIR_RIS BIT(0) 62 #define SSPIIR_TIS BIT(1) 63 #define SSPIIR_RORIS BIT(2) 64 #define SSPICR SSPIIR 65 66 /* timeout in milliseconds */ 67 #define SPI_TIMEOUT 5 68 /* maximum depth of RX/TX FIFO */ 69 #define SPI_FIFO_SIZE 8 70 71 /** 72 * struct ep93xx_spi - EP93xx SPI controller structure 73 * @lock: spinlock that protects concurrent accesses to fields @running, 74 * @current_msg and @msg_queue 75 * @pdev: pointer to platform device 76 * @clk: clock for the controller 77 * @regs_base: pointer to ioremap()'d registers 78 * @sspdr_phys: physical address of the SSPDR register 79 * @min_rate: minimum clock rate (in Hz) supported by the controller 80 * @max_rate: maximum clock rate (in Hz) supported by the controller 81 * @running: is the queue running 82 * @wq: workqueue used by the driver 83 * @msg_work: work that is queued for the driver 84 * @wait: wait here until given transfer is completed 85 * @msg_queue: queue for the messages 86 * @current_msg: message that is currently processed (or %NULL if none) 87 * @tx: current byte in transfer to transmit 88 * @rx: current byte in transfer to receive 89 * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one 90 * frame decreases this level and sending one frame increases it. 91 * @dma_rx: RX DMA channel 92 * @dma_tx: TX DMA channel 93 * @dma_rx_data: RX parameters passed to the DMA engine 94 * @dma_tx_data: TX parameters passed to the DMA engine 95 * @rx_sgt: sg table for RX transfers 96 * @tx_sgt: sg table for TX transfers 97 * @zeropage: dummy page used as RX buffer when only TX buffer is passed in by 98 * the client 99 * 100 * This structure holds EP93xx SPI controller specific information. When 101 * @running is %true, driver accepts transfer requests from protocol drivers. 102 * @current_msg is used to hold pointer to the message that is currently 103 * processed. If @current_msg is %NULL, it means that no processing is going 104 * on. 105 * 106 * Most of the fields are only written once and they can be accessed without 107 * taking the @lock. Fields that are accessed concurrently are: @current_msg, 108 * @running, and @msg_queue. 109 */ 110 struct ep93xx_spi { 111 spinlock_t lock; 112 const struct platform_device *pdev; 113 struct clk *clk; 114 void __iomem *regs_base; 115 unsigned long sspdr_phys; 116 unsigned long min_rate; 117 unsigned long max_rate; 118 bool running; 119 struct workqueue_struct *wq; 120 struct work_struct msg_work; 121 struct completion wait; 122 struct list_head msg_queue; 123 struct spi_message *current_msg; 124 size_t tx; 125 size_t rx; 126 size_t fifo_level; 127 struct dma_chan *dma_rx; 128 struct dma_chan *dma_tx; 129 struct ep93xx_dma_data dma_rx_data; 130 struct ep93xx_dma_data dma_tx_data; 131 struct sg_table rx_sgt; 132 struct sg_table tx_sgt; 133 void *zeropage; 134 }; 135 136 /** 137 * struct ep93xx_spi_chip - SPI device hardware settings 138 * @spi: back pointer to the SPI device 139 * @div_cpsr: cpsr (pre-scaler) divider 140 * @div_scr: scr divider 141 * @ops: private chip operations 142 * 143 * This structure is used to store hardware register specific settings for each 144 * SPI device. Settings are written to hardware by function 145 * ep93xx_spi_chip_setup(). 146 */ 147 struct ep93xx_spi_chip { 148 const struct spi_device *spi; 149 u8 div_cpsr; 150 u8 div_scr; 151 struct ep93xx_spi_chip_ops *ops; 152 }; 153 154 /* converts bits per word to CR0.DSS value */ 155 #define bits_per_word_to_dss(bpw) ((bpw) - 1) 156 157 static void ep93xx_spi_write_u8(const struct ep93xx_spi *espi, 158 u16 reg, u8 value) 159 { 160 writeb(value, espi->regs_base + reg); 161 } 162 163 static u8 ep93xx_spi_read_u8(const struct ep93xx_spi *spi, u16 reg) 164 { 165 return readb(spi->regs_base + reg); 166 } 167 168 static void ep93xx_spi_write_u16(const struct ep93xx_spi *espi, 169 u16 reg, u16 value) 170 { 171 writew(value, espi->regs_base + reg); 172 } 173 174 static u16 ep93xx_spi_read_u16(const struct ep93xx_spi *spi, u16 reg) 175 { 176 return readw(spi->regs_base + reg); 177 } 178 179 static int ep93xx_spi_enable(const struct ep93xx_spi *espi) 180 { 181 u8 regval; 182 int err; 183 184 err = clk_enable(espi->clk); 185 if (err) 186 return err; 187 188 regval = ep93xx_spi_read_u8(espi, SSPCR1); 189 regval |= SSPCR1_SSE; 190 ep93xx_spi_write_u8(espi, SSPCR1, regval); 191 192 return 0; 193 } 194 195 static void ep93xx_spi_disable(const struct ep93xx_spi *espi) 196 { 197 u8 regval; 198 199 regval = ep93xx_spi_read_u8(espi, SSPCR1); 200 regval &= ~SSPCR1_SSE; 201 ep93xx_spi_write_u8(espi, SSPCR1, regval); 202 203 clk_disable(espi->clk); 204 } 205 206 static void ep93xx_spi_enable_interrupts(const struct ep93xx_spi *espi) 207 { 208 u8 regval; 209 210 regval = ep93xx_spi_read_u8(espi, SSPCR1); 211 regval |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE); 212 ep93xx_spi_write_u8(espi, SSPCR1, regval); 213 } 214 215 static void ep93xx_spi_disable_interrupts(const struct ep93xx_spi *espi) 216 { 217 u8 regval; 218 219 regval = ep93xx_spi_read_u8(espi, SSPCR1); 220 regval &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE); 221 ep93xx_spi_write_u8(espi, SSPCR1, regval); 222 } 223 224 /** 225 * ep93xx_spi_calc_divisors() - calculates SPI clock divisors 226 * @espi: ep93xx SPI controller struct 227 * @chip: divisors are calculated for this chip 228 * @rate: desired SPI output clock rate 229 * 230 * Function calculates cpsr (clock pre-scaler) and scr divisors based on 231 * given @rate and places them to @chip->div_cpsr and @chip->div_scr. If, 232 * for some reason, divisors cannot be calculated nothing is stored and 233 * %-EINVAL is returned. 234 */ 235 static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi, 236 struct ep93xx_spi_chip *chip, 237 unsigned long rate) 238 { 239 unsigned long spi_clk_rate = clk_get_rate(espi->clk); 240 int cpsr, scr; 241 242 /* 243 * Make sure that max value is between values supported by the 244 * controller. Note that minimum value is already checked in 245 * ep93xx_spi_transfer(). 246 */ 247 rate = clamp(rate, espi->min_rate, espi->max_rate); 248 249 /* 250 * Calculate divisors so that we can get speed according the 251 * following formula: 252 * rate = spi_clock_rate / (cpsr * (1 + scr)) 253 * 254 * cpsr must be even number and starts from 2, scr can be any number 255 * between 0 and 255. 256 */ 257 for (cpsr = 2; cpsr <= 254; cpsr += 2) { 258 for (scr = 0; scr <= 255; scr++) { 259 if ((spi_clk_rate / (cpsr * (scr + 1))) <= rate) { 260 chip->div_scr = (u8)scr; 261 chip->div_cpsr = (u8)cpsr; 262 return 0; 263 } 264 } 265 } 266 267 return -EINVAL; 268 } 269 270 static void ep93xx_spi_cs_control(struct spi_device *spi, bool control) 271 { 272 struct ep93xx_spi_chip *chip = spi_get_ctldata(spi); 273 int value = (spi->mode & SPI_CS_HIGH) ? control : !control; 274 275 if (chip->ops && chip->ops->cs_control) 276 chip->ops->cs_control(spi, value); 277 } 278 279 /** 280 * ep93xx_spi_setup() - setup an SPI device 281 * @spi: SPI device to setup 282 * 283 * This function sets up SPI device mode, speed etc. Can be called multiple 284 * times for a single device. Returns %0 in case of success, negative error in 285 * case of failure. When this function returns success, the device is 286 * deselected. 287 */ 288 static int ep93xx_spi_setup(struct spi_device *spi) 289 { 290 struct ep93xx_spi *espi = spi_master_get_devdata(spi->master); 291 struct ep93xx_spi_chip *chip; 292 293 chip = spi_get_ctldata(spi); 294 if (!chip) { 295 dev_dbg(&espi->pdev->dev, "initial setup for %s\n", 296 spi->modalias); 297 298 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 299 if (!chip) 300 return -ENOMEM; 301 302 chip->spi = spi; 303 chip->ops = spi->controller_data; 304 305 if (chip->ops && chip->ops->setup) { 306 int ret = chip->ops->setup(spi); 307 if (ret) { 308 kfree(chip); 309 return ret; 310 } 311 } 312 313 spi_set_ctldata(spi, chip); 314 } 315 316 ep93xx_spi_cs_control(spi, false); 317 return 0; 318 } 319 320 /** 321 * ep93xx_spi_transfer() - queue message to be transferred 322 * @spi: target SPI device 323 * @msg: message to be transferred 324 * 325 * This function is called by SPI device drivers when they are going to transfer 326 * a new message. It simply puts the message in the queue and schedules 327 * workqueue to perform the actual transfer later on. 328 * 329 * Returns %0 on success and negative error in case of failure. 330 */ 331 static int ep93xx_spi_transfer(struct spi_device *spi, struct spi_message *msg) 332 { 333 struct ep93xx_spi *espi = spi_master_get_devdata(spi->master); 334 struct spi_transfer *t; 335 unsigned long flags; 336 337 if (!msg || !msg->complete) 338 return -EINVAL; 339 340 /* first validate each transfer */ 341 list_for_each_entry(t, &msg->transfers, transfer_list) { 342 if (t->speed_hz && t->speed_hz < espi->min_rate) 343 return -EINVAL; 344 } 345 346 /* 347 * Now that we own the message, let's initialize it so that it is 348 * suitable for us. We use @msg->status to signal whether there was 349 * error in transfer and @msg->state is used to hold pointer to the 350 * current transfer (or %NULL if no active current transfer). 351 */ 352 msg->state = NULL; 353 msg->status = 0; 354 msg->actual_length = 0; 355 356 spin_lock_irqsave(&espi->lock, flags); 357 if (!espi->running) { 358 spin_unlock_irqrestore(&espi->lock, flags); 359 return -ESHUTDOWN; 360 } 361 list_add_tail(&msg->queue, &espi->msg_queue); 362 queue_work(espi->wq, &espi->msg_work); 363 spin_unlock_irqrestore(&espi->lock, flags); 364 365 return 0; 366 } 367 368 /** 369 * ep93xx_spi_cleanup() - cleans up master controller specific state 370 * @spi: SPI device to cleanup 371 * 372 * This function releases master controller specific state for given @spi 373 * device. 374 */ 375 static void ep93xx_spi_cleanup(struct spi_device *spi) 376 { 377 struct ep93xx_spi_chip *chip; 378 379 chip = spi_get_ctldata(spi); 380 if (chip) { 381 if (chip->ops && chip->ops->cleanup) 382 chip->ops->cleanup(spi); 383 spi_set_ctldata(spi, NULL); 384 kfree(chip); 385 } 386 } 387 388 /** 389 * ep93xx_spi_chip_setup() - configures hardware according to given @chip 390 * @espi: ep93xx SPI controller struct 391 * @chip: chip specific settings 392 * @bits_per_word: transfer bits_per_word 393 * 394 * This function sets up the actual hardware registers with settings given in 395 * @chip. Note that no validation is done so make sure that callers validate 396 * settings before calling this. 397 */ 398 static void ep93xx_spi_chip_setup(const struct ep93xx_spi *espi, 399 const struct ep93xx_spi_chip *chip, 400 u8 bits_per_word) 401 { 402 u8 dss = bits_per_word_to_dss(bits_per_word); 403 u16 cr0; 404 405 cr0 = chip->div_scr << SSPCR0_SCR_SHIFT; 406 cr0 |= (chip->spi->mode & (SPI_CPHA|SPI_CPOL)) << SSPCR0_MODE_SHIFT; 407 cr0 |= dss; 408 409 dev_dbg(&espi->pdev->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n", 410 chip->spi->mode, chip->div_cpsr, chip->div_scr, dss); 411 dev_dbg(&espi->pdev->dev, "setup: cr0 %#x", cr0); 412 413 ep93xx_spi_write_u8(espi, SSPCPSR, chip->div_cpsr); 414 ep93xx_spi_write_u16(espi, SSPCR0, cr0); 415 } 416 417 static void ep93xx_do_write(struct ep93xx_spi *espi, struct spi_transfer *t) 418 { 419 if (t->bits_per_word > 8) { 420 u16 tx_val = 0; 421 422 if (t->tx_buf) 423 tx_val = ((u16 *)t->tx_buf)[espi->tx]; 424 ep93xx_spi_write_u16(espi, SSPDR, tx_val); 425 espi->tx += sizeof(tx_val); 426 } else { 427 u8 tx_val = 0; 428 429 if (t->tx_buf) 430 tx_val = ((u8 *)t->tx_buf)[espi->tx]; 431 ep93xx_spi_write_u8(espi, SSPDR, tx_val); 432 espi->tx += sizeof(tx_val); 433 } 434 } 435 436 static void ep93xx_do_read(struct ep93xx_spi *espi, struct spi_transfer *t) 437 { 438 if (t->bits_per_word > 8) { 439 u16 rx_val; 440 441 rx_val = ep93xx_spi_read_u16(espi, SSPDR); 442 if (t->rx_buf) 443 ((u16 *)t->rx_buf)[espi->rx] = rx_val; 444 espi->rx += sizeof(rx_val); 445 } else { 446 u8 rx_val; 447 448 rx_val = ep93xx_spi_read_u8(espi, SSPDR); 449 if (t->rx_buf) 450 ((u8 *)t->rx_buf)[espi->rx] = rx_val; 451 espi->rx += sizeof(rx_val); 452 } 453 } 454 455 /** 456 * ep93xx_spi_read_write() - perform next RX/TX transfer 457 * @espi: ep93xx SPI controller struct 458 * 459 * This function transfers next bytes (or half-words) to/from RX/TX FIFOs. If 460 * called several times, the whole transfer will be completed. Returns 461 * %-EINPROGRESS when current transfer was not yet completed otherwise %0. 462 * 463 * When this function is finished, RX FIFO should be empty and TX FIFO should be 464 * full. 465 */ 466 static int ep93xx_spi_read_write(struct ep93xx_spi *espi) 467 { 468 struct spi_message *msg = espi->current_msg; 469 struct spi_transfer *t = msg->state; 470 471 /* read as long as RX FIFO has frames in it */ 472 while ((ep93xx_spi_read_u8(espi, SSPSR) & SSPSR_RNE)) { 473 ep93xx_do_read(espi, t); 474 espi->fifo_level--; 475 } 476 477 /* write as long as TX FIFO has room */ 478 while (espi->fifo_level < SPI_FIFO_SIZE && espi->tx < t->len) { 479 ep93xx_do_write(espi, t); 480 espi->fifo_level++; 481 } 482 483 if (espi->rx == t->len) 484 return 0; 485 486 return -EINPROGRESS; 487 } 488 489 static void ep93xx_spi_pio_transfer(struct ep93xx_spi *espi) 490 { 491 /* 492 * Now everything is set up for the current transfer. We prime the TX 493 * FIFO, enable interrupts, and wait for the transfer to complete. 494 */ 495 if (ep93xx_spi_read_write(espi)) { 496 ep93xx_spi_enable_interrupts(espi); 497 wait_for_completion(&espi->wait); 498 } 499 } 500 501 /** 502 * ep93xx_spi_dma_prepare() - prepares a DMA transfer 503 * @espi: ep93xx SPI controller struct 504 * @dir: DMA transfer direction 505 * 506 * Function configures the DMA, maps the buffer and prepares the DMA 507 * descriptor. Returns a valid DMA descriptor in case of success and ERR_PTR 508 * in case of failure. 509 */ 510 static struct dma_async_tx_descriptor * 511 ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_transfer_direction dir) 512 { 513 struct spi_transfer *t = espi->current_msg->state; 514 struct dma_async_tx_descriptor *txd; 515 enum dma_slave_buswidth buswidth; 516 struct dma_slave_config conf; 517 struct scatterlist *sg; 518 struct sg_table *sgt; 519 struct dma_chan *chan; 520 const void *buf, *pbuf; 521 size_t len = t->len; 522 int i, ret, nents; 523 524 if (t->bits_per_word > 8) 525 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; 526 else 527 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; 528 529 memset(&conf, 0, sizeof(conf)); 530 conf.direction = dir; 531 532 if (dir == DMA_DEV_TO_MEM) { 533 chan = espi->dma_rx; 534 buf = t->rx_buf; 535 sgt = &espi->rx_sgt; 536 537 conf.src_addr = espi->sspdr_phys; 538 conf.src_addr_width = buswidth; 539 } else { 540 chan = espi->dma_tx; 541 buf = t->tx_buf; 542 sgt = &espi->tx_sgt; 543 544 conf.dst_addr = espi->sspdr_phys; 545 conf.dst_addr_width = buswidth; 546 } 547 548 ret = dmaengine_slave_config(chan, &conf); 549 if (ret) 550 return ERR_PTR(ret); 551 552 /* 553 * We need to split the transfer into PAGE_SIZE'd chunks. This is 554 * because we are using @espi->zeropage to provide a zero RX buffer 555 * for the TX transfers and we have only allocated one page for that. 556 * 557 * For performance reasons we allocate a new sg_table only when 558 * needed. Otherwise we will re-use the current one. Eventually the 559 * last sg_table is released in ep93xx_spi_release_dma(). 560 */ 561 562 nents = DIV_ROUND_UP(len, PAGE_SIZE); 563 if (nents != sgt->nents) { 564 sg_free_table(sgt); 565 566 ret = sg_alloc_table(sgt, nents, GFP_KERNEL); 567 if (ret) 568 return ERR_PTR(ret); 569 } 570 571 pbuf = buf; 572 for_each_sg(sgt->sgl, sg, sgt->nents, i) { 573 size_t bytes = min_t(size_t, len, PAGE_SIZE); 574 575 if (buf) { 576 sg_set_page(sg, virt_to_page(pbuf), bytes, 577 offset_in_page(pbuf)); 578 } else { 579 sg_set_page(sg, virt_to_page(espi->zeropage), 580 bytes, 0); 581 } 582 583 pbuf += bytes; 584 len -= bytes; 585 } 586 587 if (WARN_ON(len)) { 588 dev_warn(&espi->pdev->dev, "len = %d expected 0!", len); 589 return ERR_PTR(-EINVAL); 590 } 591 592 nents = dma_map_sg(chan->device->dev, sgt->sgl, sgt->nents, dir); 593 if (!nents) 594 return ERR_PTR(-ENOMEM); 595 596 txd = dmaengine_prep_slave_sg(chan, sgt->sgl, nents, dir, DMA_CTRL_ACK); 597 if (!txd) { 598 dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir); 599 return ERR_PTR(-ENOMEM); 600 } 601 return txd; 602 } 603 604 /** 605 * ep93xx_spi_dma_finish() - finishes with a DMA transfer 606 * @espi: ep93xx SPI controller struct 607 * @dir: DMA transfer direction 608 * 609 * Function finishes with the DMA transfer. After this, the DMA buffer is 610 * unmapped. 611 */ 612 static void ep93xx_spi_dma_finish(struct ep93xx_spi *espi, 613 enum dma_transfer_direction dir) 614 { 615 struct dma_chan *chan; 616 struct sg_table *sgt; 617 618 if (dir == DMA_DEV_TO_MEM) { 619 chan = espi->dma_rx; 620 sgt = &espi->rx_sgt; 621 } else { 622 chan = espi->dma_tx; 623 sgt = &espi->tx_sgt; 624 } 625 626 dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir); 627 } 628 629 static void ep93xx_spi_dma_callback(void *callback_param) 630 { 631 complete(callback_param); 632 } 633 634 static void ep93xx_spi_dma_transfer(struct ep93xx_spi *espi) 635 { 636 struct spi_message *msg = espi->current_msg; 637 struct dma_async_tx_descriptor *rxd, *txd; 638 639 rxd = ep93xx_spi_dma_prepare(espi, DMA_DEV_TO_MEM); 640 if (IS_ERR(rxd)) { 641 dev_err(&espi->pdev->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd)); 642 msg->status = PTR_ERR(rxd); 643 return; 644 } 645 646 txd = ep93xx_spi_dma_prepare(espi, DMA_MEM_TO_DEV); 647 if (IS_ERR(txd)) { 648 ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM); 649 dev_err(&espi->pdev->dev, "DMA TX failed: %ld\n", PTR_ERR(rxd)); 650 msg->status = PTR_ERR(txd); 651 return; 652 } 653 654 /* We are ready when RX is done */ 655 rxd->callback = ep93xx_spi_dma_callback; 656 rxd->callback_param = &espi->wait; 657 658 /* Now submit both descriptors and wait while they finish */ 659 dmaengine_submit(rxd); 660 dmaengine_submit(txd); 661 662 dma_async_issue_pending(espi->dma_rx); 663 dma_async_issue_pending(espi->dma_tx); 664 665 wait_for_completion(&espi->wait); 666 667 ep93xx_spi_dma_finish(espi, DMA_MEM_TO_DEV); 668 ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM); 669 } 670 671 /** 672 * ep93xx_spi_process_transfer() - processes one SPI transfer 673 * @espi: ep93xx SPI controller struct 674 * @msg: current message 675 * @t: transfer to process 676 * 677 * This function processes one SPI transfer given in @t. Function waits until 678 * transfer is complete (may sleep) and updates @msg->status based on whether 679 * transfer was successfully processed or not. 680 */ 681 static void ep93xx_spi_process_transfer(struct ep93xx_spi *espi, 682 struct spi_message *msg, 683 struct spi_transfer *t) 684 { 685 struct ep93xx_spi_chip *chip = spi_get_ctldata(msg->spi); 686 int err; 687 688 msg->state = t; 689 690 err = ep93xx_spi_calc_divisors(espi, chip, t->speed_hz); 691 if (err) { 692 dev_err(&espi->pdev->dev, "failed to adjust speed\n"); 693 msg->status = err; 694 return; 695 } 696 697 ep93xx_spi_chip_setup(espi, chip, t->bits_per_word); 698 699 espi->rx = 0; 700 espi->tx = 0; 701 702 /* 703 * There is no point of setting up DMA for the transfers which will 704 * fit into the FIFO and can be transferred with a single interrupt. 705 * So in these cases we will be using PIO and don't bother for DMA. 706 */ 707 if (espi->dma_rx && t->len > SPI_FIFO_SIZE) 708 ep93xx_spi_dma_transfer(espi); 709 else 710 ep93xx_spi_pio_transfer(espi); 711 712 /* 713 * In case of error during transmit, we bail out from processing 714 * the message. 715 */ 716 if (msg->status) 717 return; 718 719 msg->actual_length += t->len; 720 721 /* 722 * After this transfer is finished, perform any possible 723 * post-transfer actions requested by the protocol driver. 724 */ 725 if (t->delay_usecs) { 726 set_current_state(TASK_UNINTERRUPTIBLE); 727 schedule_timeout(usecs_to_jiffies(t->delay_usecs)); 728 } 729 if (t->cs_change) { 730 if (!list_is_last(&t->transfer_list, &msg->transfers)) { 731 /* 732 * In case protocol driver is asking us to drop the 733 * chipselect briefly, we let the scheduler to handle 734 * any "delay" here. 735 */ 736 ep93xx_spi_cs_control(msg->spi, false); 737 cond_resched(); 738 ep93xx_spi_cs_control(msg->spi, true); 739 } 740 } 741 } 742 743 /* 744 * ep93xx_spi_process_message() - process one SPI message 745 * @espi: ep93xx SPI controller struct 746 * @msg: message to process 747 * 748 * This function processes a single SPI message. We go through all transfers in 749 * the message and pass them to ep93xx_spi_process_transfer(). Chipselect is 750 * asserted during the whole message (unless per transfer cs_change is set). 751 * 752 * @msg->status contains %0 in case of success or negative error code in case of 753 * failure. 754 */ 755 static void ep93xx_spi_process_message(struct ep93xx_spi *espi, 756 struct spi_message *msg) 757 { 758 unsigned long timeout; 759 struct spi_transfer *t; 760 int err; 761 762 /* 763 * Enable the SPI controller and its clock. 764 */ 765 err = ep93xx_spi_enable(espi); 766 if (err) { 767 dev_err(&espi->pdev->dev, "failed to enable SPI controller\n"); 768 msg->status = err; 769 return; 770 } 771 772 /* 773 * Just to be sure: flush any data from RX FIFO. 774 */ 775 timeout = jiffies + msecs_to_jiffies(SPI_TIMEOUT); 776 while (ep93xx_spi_read_u16(espi, SSPSR) & SSPSR_RNE) { 777 if (time_after(jiffies, timeout)) { 778 dev_warn(&espi->pdev->dev, 779 "timeout while flushing RX FIFO\n"); 780 msg->status = -ETIMEDOUT; 781 return; 782 } 783 ep93xx_spi_read_u16(espi, SSPDR); 784 } 785 786 /* 787 * We explicitly handle FIFO level. This way we don't have to check TX 788 * FIFO status using %SSPSR_TNF bit which may cause RX FIFO overruns. 789 */ 790 espi->fifo_level = 0; 791 792 /* 793 * Assert the chipselect. 794 */ 795 ep93xx_spi_cs_control(msg->spi, true); 796 797 list_for_each_entry(t, &msg->transfers, transfer_list) { 798 ep93xx_spi_process_transfer(espi, msg, t); 799 if (msg->status) 800 break; 801 } 802 803 /* 804 * Now the whole message is transferred (or failed for some reason). We 805 * deselect the device and disable the SPI controller. 806 */ 807 ep93xx_spi_cs_control(msg->spi, false); 808 ep93xx_spi_disable(espi); 809 } 810 811 #define work_to_espi(work) (container_of((work), struct ep93xx_spi, msg_work)) 812 813 /** 814 * ep93xx_spi_work() - EP93xx SPI workqueue worker function 815 * @work: work struct 816 * 817 * Workqueue worker function. This function is called when there are new 818 * SPI messages to be processed. Message is taken out from the queue and then 819 * passed to ep93xx_spi_process_message(). 820 * 821 * After message is transferred, protocol driver is notified by calling 822 * @msg->complete(). In case of error, @msg->status is set to negative error 823 * number, otherwise it contains zero (and @msg->actual_length is updated). 824 */ 825 static void ep93xx_spi_work(struct work_struct *work) 826 { 827 struct ep93xx_spi *espi = work_to_espi(work); 828 struct spi_message *msg; 829 830 spin_lock_irq(&espi->lock); 831 if (!espi->running || espi->current_msg || 832 list_empty(&espi->msg_queue)) { 833 spin_unlock_irq(&espi->lock); 834 return; 835 } 836 msg = list_first_entry(&espi->msg_queue, struct spi_message, queue); 837 list_del_init(&msg->queue); 838 espi->current_msg = msg; 839 spin_unlock_irq(&espi->lock); 840 841 ep93xx_spi_process_message(espi, msg); 842 843 /* 844 * Update the current message and re-schedule ourselves if there are 845 * more messages in the queue. 846 */ 847 spin_lock_irq(&espi->lock); 848 espi->current_msg = NULL; 849 if (espi->running && !list_empty(&espi->msg_queue)) 850 queue_work(espi->wq, &espi->msg_work); 851 spin_unlock_irq(&espi->lock); 852 853 /* notify the protocol driver that we are done with this message */ 854 msg->complete(msg->context); 855 } 856 857 static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id) 858 { 859 struct ep93xx_spi *espi = dev_id; 860 u8 irq_status = ep93xx_spi_read_u8(espi, SSPIIR); 861 862 /* 863 * If we got ROR (receive overrun) interrupt we know that something is 864 * wrong. Just abort the message. 865 */ 866 if (unlikely(irq_status & SSPIIR_RORIS)) { 867 /* clear the overrun interrupt */ 868 ep93xx_spi_write_u8(espi, SSPICR, 0); 869 dev_warn(&espi->pdev->dev, 870 "receive overrun, aborting the message\n"); 871 espi->current_msg->status = -EIO; 872 } else { 873 /* 874 * Interrupt is either RX (RIS) or TX (TIS). For both cases we 875 * simply execute next data transfer. 876 */ 877 if (ep93xx_spi_read_write(espi)) { 878 /* 879 * In normal case, there still is some processing left 880 * for current transfer. Let's wait for the next 881 * interrupt then. 882 */ 883 return IRQ_HANDLED; 884 } 885 } 886 887 /* 888 * Current transfer is finished, either with error or with success. In 889 * any case we disable interrupts and notify the worker to handle 890 * any post-processing of the message. 891 */ 892 ep93xx_spi_disable_interrupts(espi); 893 complete(&espi->wait); 894 return IRQ_HANDLED; 895 } 896 897 static bool ep93xx_spi_dma_filter(struct dma_chan *chan, void *filter_param) 898 { 899 if (ep93xx_dma_chan_is_m2p(chan)) 900 return false; 901 902 chan->private = filter_param; 903 return true; 904 } 905 906 static int ep93xx_spi_setup_dma(struct ep93xx_spi *espi) 907 { 908 dma_cap_mask_t mask; 909 int ret; 910 911 espi->zeropage = (void *)get_zeroed_page(GFP_KERNEL); 912 if (!espi->zeropage) 913 return -ENOMEM; 914 915 dma_cap_zero(mask); 916 dma_cap_set(DMA_SLAVE, mask); 917 918 espi->dma_rx_data.port = EP93XX_DMA_SSP; 919 espi->dma_rx_data.direction = DMA_DEV_TO_MEM; 920 espi->dma_rx_data.name = "ep93xx-spi-rx"; 921 922 espi->dma_rx = dma_request_channel(mask, ep93xx_spi_dma_filter, 923 &espi->dma_rx_data); 924 if (!espi->dma_rx) { 925 ret = -ENODEV; 926 goto fail_free_page; 927 } 928 929 espi->dma_tx_data.port = EP93XX_DMA_SSP; 930 espi->dma_tx_data.direction = DMA_MEM_TO_DEV; 931 espi->dma_tx_data.name = "ep93xx-spi-tx"; 932 933 espi->dma_tx = dma_request_channel(mask, ep93xx_spi_dma_filter, 934 &espi->dma_tx_data); 935 if (!espi->dma_tx) { 936 ret = -ENODEV; 937 goto fail_release_rx; 938 } 939 940 return 0; 941 942 fail_release_rx: 943 dma_release_channel(espi->dma_rx); 944 espi->dma_rx = NULL; 945 fail_free_page: 946 free_page((unsigned long)espi->zeropage); 947 948 return ret; 949 } 950 951 static void ep93xx_spi_release_dma(struct ep93xx_spi *espi) 952 { 953 if (espi->dma_rx) { 954 dma_release_channel(espi->dma_rx); 955 sg_free_table(&espi->rx_sgt); 956 } 957 if (espi->dma_tx) { 958 dma_release_channel(espi->dma_tx); 959 sg_free_table(&espi->tx_sgt); 960 } 961 962 if (espi->zeropage) 963 free_page((unsigned long)espi->zeropage); 964 } 965 966 static int ep93xx_spi_probe(struct platform_device *pdev) 967 { 968 struct spi_master *master; 969 struct ep93xx_spi_info *info; 970 struct ep93xx_spi *espi; 971 struct resource *res; 972 int irq; 973 int error; 974 975 info = pdev->dev.platform_data; 976 977 irq = platform_get_irq(pdev, 0); 978 if (irq < 0) { 979 dev_err(&pdev->dev, "failed to get irq resources\n"); 980 return -EBUSY; 981 } 982 983 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 984 if (!res) { 985 dev_err(&pdev->dev, "unable to get iomem resource\n"); 986 return -ENODEV; 987 } 988 989 master = spi_alloc_master(&pdev->dev, sizeof(*espi)); 990 if (!master) 991 return -ENOMEM; 992 993 master->setup = ep93xx_spi_setup; 994 master->transfer = ep93xx_spi_transfer; 995 master->cleanup = ep93xx_spi_cleanup; 996 master->bus_num = pdev->id; 997 master->num_chipselect = info->num_chipselect; 998 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 999 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); 1000 1001 platform_set_drvdata(pdev, master); 1002 1003 espi = spi_master_get_devdata(master); 1004 1005 espi->clk = devm_clk_get(&pdev->dev, NULL); 1006 if (IS_ERR(espi->clk)) { 1007 dev_err(&pdev->dev, "unable to get spi clock\n"); 1008 error = PTR_ERR(espi->clk); 1009 goto fail_release_master; 1010 } 1011 1012 spin_lock_init(&espi->lock); 1013 init_completion(&espi->wait); 1014 1015 /* 1016 * Calculate maximum and minimum supported clock rates 1017 * for the controller. 1018 */ 1019 espi->max_rate = clk_get_rate(espi->clk) / 2; 1020 espi->min_rate = clk_get_rate(espi->clk) / (254 * 256); 1021 espi->pdev = pdev; 1022 1023 espi->sspdr_phys = res->start + SSPDR; 1024 1025 espi->regs_base = devm_ioremap_resource(&pdev->dev, res); 1026 if (IS_ERR(espi->regs_base)) { 1027 error = PTR_ERR(espi->regs_base); 1028 goto fail_release_master; 1029 } 1030 1031 error = devm_request_irq(&pdev->dev, irq, ep93xx_spi_interrupt, 1032 0, "ep93xx-spi", espi); 1033 if (error) { 1034 dev_err(&pdev->dev, "failed to request irq\n"); 1035 goto fail_release_master; 1036 } 1037 1038 if (info->use_dma && ep93xx_spi_setup_dma(espi)) 1039 dev_warn(&pdev->dev, "DMA setup failed. Falling back to PIO\n"); 1040 1041 espi->wq = create_singlethread_workqueue("ep93xx_spid"); 1042 if (!espi->wq) { 1043 dev_err(&pdev->dev, "unable to create workqueue\n"); 1044 error = -ENOMEM; 1045 goto fail_free_dma; 1046 } 1047 INIT_WORK(&espi->msg_work, ep93xx_spi_work); 1048 INIT_LIST_HEAD(&espi->msg_queue); 1049 espi->running = true; 1050 1051 /* make sure that the hardware is disabled */ 1052 ep93xx_spi_write_u8(espi, SSPCR1, 0); 1053 1054 error = spi_register_master(master); 1055 if (error) { 1056 dev_err(&pdev->dev, "failed to register SPI master\n"); 1057 goto fail_free_queue; 1058 } 1059 1060 dev_info(&pdev->dev, "EP93xx SPI Controller at 0x%08lx irq %d\n", 1061 (unsigned long)res->start, irq); 1062 1063 return 0; 1064 1065 fail_free_queue: 1066 destroy_workqueue(espi->wq); 1067 fail_free_dma: 1068 ep93xx_spi_release_dma(espi); 1069 fail_release_master: 1070 spi_master_put(master); 1071 1072 return error; 1073 } 1074 1075 static int ep93xx_spi_remove(struct platform_device *pdev) 1076 { 1077 struct spi_master *master = platform_get_drvdata(pdev); 1078 struct ep93xx_spi *espi = spi_master_get_devdata(master); 1079 1080 spin_lock_irq(&espi->lock); 1081 espi->running = false; 1082 spin_unlock_irq(&espi->lock); 1083 1084 destroy_workqueue(espi->wq); 1085 1086 /* 1087 * Complete remaining messages with %-ESHUTDOWN status. 1088 */ 1089 spin_lock_irq(&espi->lock); 1090 while (!list_empty(&espi->msg_queue)) { 1091 struct spi_message *msg; 1092 1093 msg = list_first_entry(&espi->msg_queue, 1094 struct spi_message, queue); 1095 list_del_init(&msg->queue); 1096 msg->status = -ESHUTDOWN; 1097 spin_unlock_irq(&espi->lock); 1098 msg->complete(msg->context); 1099 spin_lock_irq(&espi->lock); 1100 } 1101 spin_unlock_irq(&espi->lock); 1102 1103 ep93xx_spi_release_dma(espi); 1104 1105 spi_unregister_master(master); 1106 return 0; 1107 } 1108 1109 static struct platform_driver ep93xx_spi_driver = { 1110 .driver = { 1111 .name = "ep93xx-spi", 1112 .owner = THIS_MODULE, 1113 }, 1114 .probe = ep93xx_spi_probe, 1115 .remove = ep93xx_spi_remove, 1116 }; 1117 module_platform_driver(ep93xx_spi_driver); 1118 1119 MODULE_DESCRIPTION("EP93xx SPI Controller driver"); 1120 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>"); 1121 MODULE_LICENSE("GPL"); 1122 MODULE_ALIAS("platform:ep93xx-spi"); 1123