1 #ifndef DW_SPI_HEADER_H 2 #define DW_SPI_HEADER_H 3 4 #include <linux/io.h> 5 #include <linux/scatterlist.h> 6 #include <linux/gpio.h> 7 8 /* Register offsets */ 9 #define DW_SPI_CTRL0 0x00 10 #define DW_SPI_CTRL1 0x04 11 #define DW_SPI_SSIENR 0x08 12 #define DW_SPI_MWCR 0x0c 13 #define DW_SPI_SER 0x10 14 #define DW_SPI_BAUDR 0x14 15 #define DW_SPI_TXFLTR 0x18 16 #define DW_SPI_RXFLTR 0x1c 17 #define DW_SPI_TXFLR 0x20 18 #define DW_SPI_RXFLR 0x24 19 #define DW_SPI_SR 0x28 20 #define DW_SPI_IMR 0x2c 21 #define DW_SPI_ISR 0x30 22 #define DW_SPI_RISR 0x34 23 #define DW_SPI_TXOICR 0x38 24 #define DW_SPI_RXOICR 0x3c 25 #define DW_SPI_RXUICR 0x40 26 #define DW_SPI_MSTICR 0x44 27 #define DW_SPI_ICR 0x48 28 #define DW_SPI_DMACR 0x4c 29 #define DW_SPI_DMATDLR 0x50 30 #define DW_SPI_DMARDLR 0x54 31 #define DW_SPI_IDR 0x58 32 #define DW_SPI_VERSION 0x5c 33 #define DW_SPI_DR 0x60 34 35 /* Bit fields in CTRLR0 */ 36 #define SPI_DFS_OFFSET 0 37 38 #define SPI_FRF_OFFSET 4 39 #define SPI_FRF_SPI 0x0 40 #define SPI_FRF_SSP 0x1 41 #define SPI_FRF_MICROWIRE 0x2 42 #define SPI_FRF_RESV 0x3 43 44 #define SPI_MODE_OFFSET 6 45 #define SPI_SCPH_OFFSET 6 46 #define SPI_SCOL_OFFSET 7 47 48 #define SPI_TMOD_OFFSET 8 49 #define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET) 50 #define SPI_TMOD_TR 0x0 /* xmit & recv */ 51 #define SPI_TMOD_TO 0x1 /* xmit only */ 52 #define SPI_TMOD_RO 0x2 /* recv only */ 53 #define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */ 54 55 #define SPI_SLVOE_OFFSET 10 56 #define SPI_SRL_OFFSET 11 57 #define SPI_CFS_OFFSET 12 58 59 /* Bit fields in SR, 7 bits */ 60 #define SR_MASK 0x7f /* cover 7 bits */ 61 #define SR_BUSY (1 << 0) 62 #define SR_TF_NOT_FULL (1 << 1) 63 #define SR_TF_EMPT (1 << 2) 64 #define SR_RF_NOT_EMPT (1 << 3) 65 #define SR_RF_FULL (1 << 4) 66 #define SR_TX_ERR (1 << 5) 67 #define SR_DCOL (1 << 6) 68 69 /* Bit fields in ISR, IMR, RISR, 7 bits */ 70 #define SPI_INT_TXEI (1 << 0) 71 #define SPI_INT_TXOI (1 << 1) 72 #define SPI_INT_RXUI (1 << 2) 73 #define SPI_INT_RXOI (1 << 3) 74 #define SPI_INT_RXFI (1 << 4) 75 #define SPI_INT_MSTI (1 << 5) 76 77 /* Bit fields in DMACR */ 78 #define SPI_DMA_RDMAE (1 << 0) 79 #define SPI_DMA_TDMAE (1 << 1) 80 81 /* TX RX interrupt level threshold, max can be 256 */ 82 #define SPI_INT_THRESHOLD 32 83 84 enum dw_ssi_type { 85 SSI_MOTO_SPI = 0, 86 SSI_TI_SSP, 87 SSI_NS_MICROWIRE, 88 }; 89 90 struct dw_spi; 91 struct dw_spi_dma_ops { 92 int (*dma_init)(struct dw_spi *dws); 93 void (*dma_exit)(struct dw_spi *dws); 94 int (*dma_transfer)(struct dw_spi *dws, int cs_change); 95 }; 96 97 struct dw_spi { 98 struct spi_master *master; 99 enum dw_ssi_type type; 100 char name[16]; 101 102 void __iomem *regs; 103 unsigned long paddr; 104 int irq; 105 u32 fifo_len; /* depth of the FIFO buffer */ 106 u32 max_freq; /* max bus freq supported */ 107 108 u16 bus_num; 109 u16 num_cs; /* supported slave numbers */ 110 111 /* Current message transfer state info */ 112 struct chip_data *prev_chip; 113 size_t len; 114 void *tx; 115 void *tx_end; 116 void *rx; 117 void *rx_end; 118 int dma_mapped; 119 dma_addr_t rx_dma; 120 dma_addr_t tx_dma; 121 size_t rx_map_len; 122 size_t tx_map_len; 123 u8 n_bytes; /* current is a 1/2 bytes op */ 124 u32 dma_width; 125 irqreturn_t (*transfer_handler)(struct dw_spi *dws); 126 127 /* Dma info */ 128 int dma_inited; 129 struct dma_chan *txchan; 130 struct scatterlist tx_sgl; 131 struct dma_chan *rxchan; 132 struct scatterlist rx_sgl; 133 unsigned long dma_chan_busy; 134 struct device *dma_dev; 135 dma_addr_t dma_addr; /* phy address of the Data register */ 136 struct dw_spi_dma_ops *dma_ops; 137 void *dma_priv; /* platform relate info */ 138 139 /* Bus interface info */ 140 void *priv; 141 #ifdef CONFIG_DEBUG_FS 142 struct dentry *debugfs; 143 #endif 144 }; 145 146 static inline u32 dw_readl(struct dw_spi *dws, u32 offset) 147 { 148 return __raw_readl(dws->regs + offset); 149 } 150 151 static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val) 152 { 153 __raw_writel(val, dws->regs + offset); 154 } 155 156 static inline u16 dw_readw(struct dw_spi *dws, u32 offset) 157 { 158 return __raw_readw(dws->regs + offset); 159 } 160 161 static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val) 162 { 163 __raw_writew(val, dws->regs + offset); 164 } 165 166 static inline void spi_enable_chip(struct dw_spi *dws, int enable) 167 { 168 dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0)); 169 } 170 171 static inline void spi_set_clk(struct dw_spi *dws, u16 div) 172 { 173 dw_writel(dws, DW_SPI_BAUDR, div); 174 } 175 176 /* Disable IRQ bits */ 177 static inline void spi_mask_intr(struct dw_spi *dws, u32 mask) 178 { 179 u32 new_mask; 180 181 new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask; 182 dw_writel(dws, DW_SPI_IMR, new_mask); 183 } 184 185 /* Enable IRQ bits */ 186 static inline void spi_umask_intr(struct dw_spi *dws, u32 mask) 187 { 188 u32 new_mask; 189 190 new_mask = dw_readl(dws, DW_SPI_IMR) | mask; 191 dw_writel(dws, DW_SPI_IMR, new_mask); 192 } 193 194 /* 195 * This does disable the SPI controller, interrupts, and re-enable the 196 * controller back. Transmit and receive FIFO buffers are cleared when the 197 * device is disabled. 198 */ 199 static inline void spi_reset_chip(struct dw_spi *dws) 200 { 201 spi_enable_chip(dws, 0); 202 spi_mask_intr(dws, 0xff); 203 spi_enable_chip(dws, 1); 204 } 205 206 /* 207 * Each SPI slave device to work with dw_api controller should 208 * has such a structure claiming its working mode (PIO/DMA etc), 209 * which can be save in the "controller_data" member of the 210 * struct spi_device. 211 */ 212 struct dw_spi_chip { 213 u8 poll_mode; /* 1 for controller polling mode */ 214 u8 type; /* SPI/SSP/MicroWire */ 215 u8 enable_dma; 216 void (*cs_control)(u32 command); 217 }; 218 219 extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws); 220 extern void dw_spi_remove_host(struct dw_spi *dws); 221 extern int dw_spi_suspend_host(struct dw_spi *dws); 222 extern int dw_spi_resume_host(struct dw_spi *dws); 223 224 /* platform related setup */ 225 extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */ 226 #endif /* DW_SPI_HEADER_H */ 227