1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __SPI_DW_H__ 3 #define __SPI_DW_H__ 4 5 #include <linux/bits.h> 6 #include <linux/completion.h> 7 #include <linux/debugfs.h> 8 #include <linux/irqreturn.h> 9 #include <linux/io.h> 10 #include <linux/scatterlist.h> 11 #include <linux/spi/spi-mem.h> 12 #include <linux/bitfield.h> 13 14 /* Synopsys DW SSI IP-core virtual IDs */ 15 #define DW_PSSI_ID 0 16 #define DW_HSSI_ID 1 17 18 /* Synopsys DW SSI component versions (FourCC sequence) */ 19 #define DW_HSSI_102A 0x3130322a 20 21 /* DW SSI IP-core ID and version check helpers */ 22 #define dw_spi_ip_is(_dws, _ip) \ 23 ((_dws)->ip == DW_ ## _ip ## _ID) 24 25 #define __dw_spi_ver_cmp(_dws, _ip, _ver, _op) \ 26 (dw_spi_ip_is(_dws, _ip) && (_dws)->ver _op DW_ ## _ip ## _ver) 27 28 #define dw_spi_ver_is(_dws, _ip, _ver) __dw_spi_ver_cmp(_dws, _ip, _ver, ==) 29 30 #define dw_spi_ver_is_ge(_dws, _ip, _ver) __dw_spi_ver_cmp(_dws, _ip, _ver, >=) 31 32 /* DW SPI controller capabilities */ 33 #define DW_SPI_CAP_CS_OVERRIDE BIT(0) 34 #define DW_SPI_CAP_KEEMBAY_MST BIT(1) 35 #define DW_SPI_CAP_DFS32 BIT(2) 36 37 /* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */ 38 #define DW_SPI_CTRLR0 0x00 39 #define DW_SPI_CTRLR1 0x04 40 #define DW_SPI_SSIENR 0x08 41 #define DW_SPI_MWCR 0x0c 42 #define DW_SPI_SER 0x10 43 #define DW_SPI_BAUDR 0x14 44 #define DW_SPI_TXFTLR 0x18 45 #define DW_SPI_RXFTLR 0x1c 46 #define DW_SPI_TXFLR 0x20 47 #define DW_SPI_RXFLR 0x24 48 #define DW_SPI_SR 0x28 49 #define DW_SPI_IMR 0x2c 50 #define DW_SPI_ISR 0x30 51 #define DW_SPI_RISR 0x34 52 #define DW_SPI_TXOICR 0x38 53 #define DW_SPI_RXOICR 0x3c 54 #define DW_SPI_RXUICR 0x40 55 #define DW_SPI_MSTICR 0x44 56 #define DW_SPI_ICR 0x48 57 #define DW_SPI_DMACR 0x4c 58 #define DW_SPI_DMATDLR 0x50 59 #define DW_SPI_DMARDLR 0x54 60 #define DW_SPI_IDR 0x58 61 #define DW_SPI_VERSION 0x5c 62 #define DW_SPI_DR 0x60 63 #define DW_SPI_RX_SAMPLE_DLY 0xf0 64 #define DW_SPI_CS_OVERRIDE 0xf4 65 66 /* Bit fields in CTRLR0 (DWC APB SSI) */ 67 #define DW_PSSI_CTRLR0_DFS_MASK GENMASK(3, 0) 68 #define DW_PSSI_CTRLR0_DFS32_MASK GENMASK(20, 16) 69 70 #define DW_PSSI_CTRLR0_FRF_MASK GENMASK(5, 4) 71 #define DW_SPI_CTRLR0_FRF_MOTO_SPI 0x0 72 #define DW_SPI_CTRLR0_FRF_TI_SSP 0x1 73 #define DW_SPI_CTRLR0_FRF_NS_MICROWIRE 0x2 74 #define DW_SPI_CTRLR0_FRF_RESV 0x3 75 76 #define DW_PSSI_CTRLR0_MODE_MASK GENMASK(7, 6) 77 #define DW_PSSI_CTRLR0_SCPHA BIT(6) 78 #define DW_PSSI_CTRLR0_SCPOL BIT(7) 79 80 #define DW_PSSI_CTRLR0_TMOD_MASK GENMASK(9, 8) 81 #define DW_SPI_CTRLR0_TMOD_TR 0x0 /* xmit & recv */ 82 #define DW_SPI_CTRLR0_TMOD_TO 0x1 /* xmit only */ 83 #define DW_SPI_CTRLR0_TMOD_RO 0x2 /* recv only */ 84 #define DW_SPI_CTRLR0_TMOD_EPROMREAD 0x3 /* eeprom read mode */ 85 86 #define DW_PSSI_CTRLR0_SLV_OE BIT(10) 87 #define DW_PSSI_CTRLR0_SRL BIT(11) 88 #define DW_PSSI_CTRLR0_CFS BIT(12) 89 90 /* Bit fields in CTRLR0 (DWC SSI with AHB interface) */ 91 #define DW_HSSI_CTRLR0_DFS_MASK GENMASK(4, 0) 92 #define DW_HSSI_CTRLR0_FRF_MASK GENMASK(7, 6) 93 #define DW_HSSI_CTRLR0_SCPHA BIT(8) 94 #define DW_HSSI_CTRLR0_SCPOL BIT(9) 95 #define DW_HSSI_CTRLR0_TMOD_MASK GENMASK(11, 10) 96 #define DW_HSSI_CTRLR0_SRL BIT(13) 97 98 /* 99 * For Keem Bay, CTRLR0[31] is used to select controller mode. 100 * 0: SSI is slave 101 * 1: SSI is master 102 */ 103 #define DW_HSSI_CTRLR0_KEEMBAY_MST BIT(31) 104 105 /* Bit fields in CTRLR1 */ 106 #define DW_SPI_NDF_MASK GENMASK(15, 0) 107 108 /* Bit fields in SR, 7 bits */ 109 #define DW_SPI_SR_MASK GENMASK(6, 0) 110 #define DW_SPI_SR_BUSY BIT(0) 111 #define DW_SPI_SR_TF_NOT_FULL BIT(1) 112 #define DW_SPI_SR_TF_EMPT BIT(2) 113 #define DW_SPI_SR_RF_NOT_EMPT BIT(3) 114 #define DW_SPI_SR_RF_FULL BIT(4) 115 #define DW_SPI_SR_TX_ERR BIT(5) 116 #define DW_SPI_SR_DCOL BIT(6) 117 118 /* Bit fields in ISR, IMR, RISR, 7 bits */ 119 #define DW_SPI_INT_MASK GENMASK(5, 0) 120 #define DW_SPI_INT_TXEI BIT(0) 121 #define DW_SPI_INT_TXOI BIT(1) 122 #define DW_SPI_INT_RXUI BIT(2) 123 #define DW_SPI_INT_RXOI BIT(3) 124 #define DW_SPI_INT_RXFI BIT(4) 125 #define DW_SPI_INT_MSTI BIT(5) 126 127 /* Bit fields in DMACR */ 128 #define DW_SPI_DMACR_RDMAE BIT(0) 129 #define DW_SPI_DMACR_TDMAE BIT(1) 130 131 /* Mem/DMA operations helpers */ 132 #define DW_SPI_WAIT_RETRIES 5 133 #define DW_SPI_BUF_SIZE \ 134 (sizeof_field(struct spi_mem_op, cmd.opcode) + \ 135 sizeof_field(struct spi_mem_op, addr.val) + 256) 136 #define DW_SPI_GET_BYTE(_val, _idx) \ 137 ((_val) >> (BITS_PER_BYTE * (_idx)) & 0xff) 138 139 /* Slave spi_transfer/spi_mem_op related */ 140 struct dw_spi_cfg { 141 u8 tmode; 142 u8 dfs; 143 u32 ndf; 144 u32 freq; 145 }; 146 147 struct dw_spi; 148 struct dw_spi_dma_ops { 149 int (*dma_init)(struct device *dev, struct dw_spi *dws); 150 void (*dma_exit)(struct dw_spi *dws); 151 int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer); 152 bool (*can_dma)(struct spi_controller *master, struct spi_device *spi, 153 struct spi_transfer *xfer); 154 int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer); 155 void (*dma_stop)(struct dw_spi *dws); 156 }; 157 158 struct dw_spi { 159 struct spi_controller *master; 160 161 u32 ip; /* Synopsys DW SSI IP-core ID */ 162 u32 ver; /* Synopsys component version */ 163 u32 caps; /* DW SPI capabilities */ 164 165 void __iomem *regs; 166 unsigned long paddr; 167 int irq; 168 u32 fifo_len; /* depth of the FIFO buffer */ 169 unsigned int dfs_offset; /* CTRLR0 DFS field offset */ 170 u32 max_mem_freq; /* max mem-ops bus freq */ 171 u32 max_freq; /* max bus freq supported */ 172 173 u32 reg_io_width; /* DR I/O width in bytes */ 174 u16 bus_num; 175 u16 num_cs; /* supported slave numbers */ 176 void (*set_cs)(struct spi_device *spi, bool enable); 177 178 /* Current message transfer state info */ 179 void *tx; 180 unsigned int tx_len; 181 void *rx; 182 unsigned int rx_len; 183 u8 buf[DW_SPI_BUF_SIZE]; 184 int dma_mapped; 185 u8 n_bytes; /* current is a 1/2 bytes op */ 186 irqreturn_t (*transfer_handler)(struct dw_spi *dws); 187 u32 current_freq; /* frequency in hz */ 188 u32 cur_rx_sample_dly; 189 u32 def_rx_sample_dly_ns; 190 191 /* Custom memory operations */ 192 struct spi_controller_mem_ops mem_ops; 193 194 /* DMA info */ 195 struct dma_chan *txchan; 196 u32 txburst; 197 struct dma_chan *rxchan; 198 u32 rxburst; 199 u32 dma_sg_burst; 200 unsigned long dma_chan_busy; 201 dma_addr_t dma_addr; /* phy address of the Data register */ 202 const struct dw_spi_dma_ops *dma_ops; 203 struct completion dma_completion; 204 205 #ifdef CONFIG_DEBUG_FS 206 struct dentry *debugfs; 207 struct debugfs_regset32 regset; 208 #endif 209 }; 210 211 static inline u32 dw_readl(struct dw_spi *dws, u32 offset) 212 { 213 return __raw_readl(dws->regs + offset); 214 } 215 216 static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val) 217 { 218 __raw_writel(val, dws->regs + offset); 219 } 220 221 static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset) 222 { 223 switch (dws->reg_io_width) { 224 case 2: 225 return readw_relaxed(dws->regs + offset); 226 case 4: 227 default: 228 return readl_relaxed(dws->regs + offset); 229 } 230 } 231 232 static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val) 233 { 234 switch (dws->reg_io_width) { 235 case 2: 236 writew_relaxed(val, dws->regs + offset); 237 break; 238 case 4: 239 default: 240 writel_relaxed(val, dws->regs + offset); 241 break; 242 } 243 } 244 245 static inline void dw_spi_enable_chip(struct dw_spi *dws, int enable) 246 { 247 dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0)); 248 } 249 250 static inline void dw_spi_set_clk(struct dw_spi *dws, u16 div) 251 { 252 dw_writel(dws, DW_SPI_BAUDR, div); 253 } 254 255 /* Disable IRQ bits */ 256 static inline void dw_spi_mask_intr(struct dw_spi *dws, u32 mask) 257 { 258 u32 new_mask; 259 260 new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask; 261 dw_writel(dws, DW_SPI_IMR, new_mask); 262 } 263 264 /* Enable IRQ bits */ 265 static inline void dw_spi_umask_intr(struct dw_spi *dws, u32 mask) 266 { 267 u32 new_mask; 268 269 new_mask = dw_readl(dws, DW_SPI_IMR) | mask; 270 dw_writel(dws, DW_SPI_IMR, new_mask); 271 } 272 273 /* 274 * This disables the SPI controller, interrupts, clears the interrupts status 275 * and CS, then re-enables the controller back. Transmit and receive FIFO 276 * buffers are cleared when the device is disabled. 277 */ 278 static inline void dw_spi_reset_chip(struct dw_spi *dws) 279 { 280 dw_spi_enable_chip(dws, 0); 281 dw_spi_mask_intr(dws, 0xff); 282 dw_readl(dws, DW_SPI_ICR); 283 dw_writel(dws, DW_SPI_SER, 0); 284 dw_spi_enable_chip(dws, 1); 285 } 286 287 static inline void dw_spi_shutdown_chip(struct dw_spi *dws) 288 { 289 dw_spi_enable_chip(dws, 0); 290 dw_spi_set_clk(dws, 0); 291 } 292 293 extern void dw_spi_set_cs(struct spi_device *spi, bool enable); 294 extern void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi, 295 struct dw_spi_cfg *cfg); 296 extern int dw_spi_check_status(struct dw_spi *dws, bool raw); 297 extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws); 298 extern void dw_spi_remove_host(struct dw_spi *dws); 299 extern int dw_spi_suspend_host(struct dw_spi *dws); 300 extern int dw_spi_resume_host(struct dw_spi *dws); 301 302 #ifdef CONFIG_SPI_DW_DMA 303 304 extern void dw_spi_dma_setup_mfld(struct dw_spi *dws); 305 extern void dw_spi_dma_setup_generic(struct dw_spi *dws); 306 307 #else 308 309 static inline void dw_spi_dma_setup_mfld(struct dw_spi *dws) {} 310 static inline void dw_spi_dma_setup_generic(struct dw_spi *dws) {} 311 312 #endif /* !CONFIG_SPI_DW_DMA */ 313 314 #endif /* __SPI_DW_H__ */ 315