1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef DW_SPI_HEADER_H 3 #define DW_SPI_HEADER_H 4 5 #include <linux/bits.h> 6 #include <linux/completion.h> 7 #include <linux/debugfs.h> 8 #include <linux/irqreturn.h> 9 #include <linux/io.h> 10 #include <linux/scatterlist.h> 11 12 /* Register offsets */ 13 #define DW_SPI_CTRLR0 0x00 14 #define DW_SPI_CTRLR1 0x04 15 #define DW_SPI_SSIENR 0x08 16 #define DW_SPI_MWCR 0x0c 17 #define DW_SPI_SER 0x10 18 #define DW_SPI_BAUDR 0x14 19 #define DW_SPI_TXFTLR 0x18 20 #define DW_SPI_RXFTLR 0x1c 21 #define DW_SPI_TXFLR 0x20 22 #define DW_SPI_RXFLR 0x24 23 #define DW_SPI_SR 0x28 24 #define DW_SPI_IMR 0x2c 25 #define DW_SPI_ISR 0x30 26 #define DW_SPI_RISR 0x34 27 #define DW_SPI_TXOICR 0x38 28 #define DW_SPI_RXOICR 0x3c 29 #define DW_SPI_RXUICR 0x40 30 #define DW_SPI_MSTICR 0x44 31 #define DW_SPI_ICR 0x48 32 #define DW_SPI_DMACR 0x4c 33 #define DW_SPI_DMATDLR 0x50 34 #define DW_SPI_DMARDLR 0x54 35 #define DW_SPI_IDR 0x58 36 #define DW_SPI_VERSION 0x5c 37 #define DW_SPI_DR 0x60 38 #define DW_SPI_RX_SAMPLE_DLY 0xf0 39 #define DW_SPI_CS_OVERRIDE 0xf4 40 41 /* Bit fields in CTRLR0 */ 42 #define SPI_DFS_OFFSET 0 43 44 #define SPI_FRF_OFFSET 4 45 #define SPI_FRF_SPI 0x0 46 #define SPI_FRF_SSP 0x1 47 #define SPI_FRF_MICROWIRE 0x2 48 #define SPI_FRF_RESV 0x3 49 50 #define SPI_MODE_OFFSET 6 51 #define SPI_SCPH_OFFSET 6 52 #define SPI_SCOL_OFFSET 7 53 54 #define SPI_TMOD_OFFSET 8 55 #define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET) 56 #define SPI_TMOD_TR 0x0 /* xmit & recv */ 57 #define SPI_TMOD_TO 0x1 /* xmit only */ 58 #define SPI_TMOD_RO 0x2 /* recv only */ 59 #define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */ 60 61 #define SPI_SLVOE_OFFSET 10 62 #define SPI_SRL_OFFSET 11 63 #define SPI_CFS_OFFSET 12 64 65 /* Bit fields in CTRLR0 based on DWC_ssi_databook.pdf v1.01a */ 66 #define DWC_SSI_CTRLR0_SRL_OFFSET 13 67 #define DWC_SSI_CTRLR0_TMOD_OFFSET 10 68 #define DWC_SSI_CTRLR0_TMOD_MASK GENMASK(11, 10) 69 #define DWC_SSI_CTRLR0_SCPOL_OFFSET 9 70 #define DWC_SSI_CTRLR0_SCPH_OFFSET 8 71 #define DWC_SSI_CTRLR0_FRF_OFFSET 6 72 #define DWC_SSI_CTRLR0_DFS_OFFSET 0 73 74 /* 75 * For Keem Bay, CTRLR0[31] is used to select controller mode. 76 * 0: SSI is slave 77 * 1: SSI is master 78 */ 79 #define DWC_SSI_CTRLR0_KEEMBAY_MST BIT(31) 80 81 /* Bit fields in SR, 7 bits */ 82 #define SR_MASK 0x7f /* cover 7 bits */ 83 #define SR_BUSY (1 << 0) 84 #define SR_TF_NOT_FULL (1 << 1) 85 #define SR_TF_EMPT (1 << 2) 86 #define SR_RF_NOT_EMPT (1 << 3) 87 #define SR_RF_FULL (1 << 4) 88 #define SR_TX_ERR (1 << 5) 89 #define SR_DCOL (1 << 6) 90 91 /* Bit fields in ISR, IMR, RISR, 7 bits */ 92 #define SPI_INT_TXEI (1 << 0) 93 #define SPI_INT_TXOI (1 << 1) 94 #define SPI_INT_RXUI (1 << 2) 95 #define SPI_INT_RXOI (1 << 3) 96 #define SPI_INT_RXFI (1 << 4) 97 #define SPI_INT_MSTI (1 << 5) 98 99 /* Bit fields in DMACR */ 100 #define SPI_DMA_RDMAE (1 << 0) 101 #define SPI_DMA_TDMAE (1 << 1) 102 103 enum dw_ssi_type { 104 SSI_MOTO_SPI = 0, 105 SSI_TI_SSP, 106 SSI_NS_MICROWIRE, 107 }; 108 109 /* DW SPI capabilities */ 110 #define DW_SPI_CAP_CS_OVERRIDE BIT(0) 111 #define DW_SPI_CAP_KEEMBAY_MST BIT(1) 112 113 struct dw_spi; 114 struct dw_spi_dma_ops { 115 int (*dma_init)(struct device *dev, struct dw_spi *dws); 116 void (*dma_exit)(struct dw_spi *dws); 117 int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer); 118 bool (*can_dma)(struct spi_controller *master, struct spi_device *spi, 119 struct spi_transfer *xfer); 120 int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer); 121 void (*dma_stop)(struct dw_spi *dws); 122 }; 123 124 struct dw_spi { 125 struct spi_controller *master; 126 127 void __iomem *regs; 128 unsigned long paddr; 129 int irq; 130 u32 fifo_len; /* depth of the FIFO buffer */ 131 u32 max_freq; /* max bus freq supported */ 132 133 u32 caps; /* DW SPI capabilities */ 134 135 u32 reg_io_width; /* DR I/O width in bytes */ 136 u16 bus_num; 137 u16 num_cs; /* supported slave numbers */ 138 void (*set_cs)(struct spi_device *spi, bool enable); 139 u32 (*update_cr0)(struct spi_controller *master, struct spi_device *spi, 140 struct spi_transfer *transfer); 141 142 /* Current message transfer state info */ 143 size_t len; 144 void *tx; 145 void *tx_end; 146 void *rx; 147 void *rx_end; 148 int dma_mapped; 149 u8 n_bytes; /* current is a 1/2 bytes op */ 150 irqreturn_t (*transfer_handler)(struct dw_spi *dws); 151 u32 current_freq; /* frequency in hz */ 152 u32 cur_rx_sample_dly; 153 u32 def_rx_sample_dly_ns; 154 155 /* DMA info */ 156 struct dma_chan *txchan; 157 u32 txburst; 158 struct dma_chan *rxchan; 159 u32 rxburst; 160 unsigned long dma_chan_busy; 161 dma_addr_t dma_addr; /* phy address of the Data register */ 162 const struct dw_spi_dma_ops *dma_ops; 163 struct completion dma_completion; 164 165 #ifdef CONFIG_DEBUG_FS 166 struct dentry *debugfs; 167 struct debugfs_regset32 regset; 168 #endif 169 }; 170 171 static inline u32 dw_readl(struct dw_spi *dws, u32 offset) 172 { 173 return __raw_readl(dws->regs + offset); 174 } 175 176 static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val) 177 { 178 __raw_writel(val, dws->regs + offset); 179 } 180 181 static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset) 182 { 183 switch (dws->reg_io_width) { 184 case 2: 185 return readw_relaxed(dws->regs + offset); 186 case 4: 187 default: 188 return readl_relaxed(dws->regs + offset); 189 } 190 } 191 192 static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val) 193 { 194 switch (dws->reg_io_width) { 195 case 2: 196 writew_relaxed(val, dws->regs + offset); 197 break; 198 case 4: 199 default: 200 writel_relaxed(val, dws->regs + offset); 201 break; 202 } 203 } 204 205 static inline void spi_enable_chip(struct dw_spi *dws, int enable) 206 { 207 dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0)); 208 } 209 210 static inline void spi_set_clk(struct dw_spi *dws, u16 div) 211 { 212 dw_writel(dws, DW_SPI_BAUDR, div); 213 } 214 215 /* Disable IRQ bits */ 216 static inline void spi_mask_intr(struct dw_spi *dws, u32 mask) 217 { 218 u32 new_mask; 219 220 new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask; 221 dw_writel(dws, DW_SPI_IMR, new_mask); 222 } 223 224 /* Enable IRQ bits */ 225 static inline void spi_umask_intr(struct dw_spi *dws, u32 mask) 226 { 227 u32 new_mask; 228 229 new_mask = dw_readl(dws, DW_SPI_IMR) | mask; 230 dw_writel(dws, DW_SPI_IMR, new_mask); 231 } 232 233 /* 234 * This disables the SPI controller, interrupts, clears the interrupts status, 235 * and re-enable the controller back. Transmit and receive FIFO buffers are 236 * cleared when the device is disabled. 237 */ 238 static inline void spi_reset_chip(struct dw_spi *dws) 239 { 240 spi_enable_chip(dws, 0); 241 spi_mask_intr(dws, 0xff); 242 dw_readl(dws, DW_SPI_ICR); 243 spi_enable_chip(dws, 1); 244 } 245 246 static inline void spi_shutdown_chip(struct dw_spi *dws) 247 { 248 spi_enable_chip(dws, 0); 249 spi_set_clk(dws, 0); 250 } 251 252 extern void dw_spi_set_cs(struct spi_device *spi, bool enable); 253 extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws); 254 extern void dw_spi_remove_host(struct dw_spi *dws); 255 extern int dw_spi_suspend_host(struct dw_spi *dws); 256 extern int dw_spi_resume_host(struct dw_spi *dws); 257 extern u32 dw_spi_update_cr0(struct spi_controller *master, 258 struct spi_device *spi, 259 struct spi_transfer *transfer); 260 extern u32 dw_spi_update_cr0_v1_01a(struct spi_controller *master, 261 struct spi_device *spi, 262 struct spi_transfer *transfer); 263 264 #ifdef CONFIG_SPI_DW_DMA 265 266 extern void dw_spi_dma_setup_mfld(struct dw_spi *dws); 267 extern void dw_spi_dma_setup_generic(struct dw_spi *dws); 268 269 #else 270 271 static inline void dw_spi_dma_setup_mfld(struct dw_spi *dws) {} 272 static inline void dw_spi_dma_setup_generic(struct dw_spi *dws) {} 273 274 #endif /* !CONFIG_SPI_DW_DMA */ 275 276 #endif /* DW_SPI_HEADER_H */ 277