1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Memory-mapped interface driver for DW SPI Core 4 * 5 * Copyright (c) 2010, Octasic semiconductor. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/err.h> 10 #include <linux/platform_device.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/slab.h> 13 #include <linux/spi/spi.h> 14 #include <linux/scatterlist.h> 15 #include <linux/mfd/syscon.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/of_platform.h> 19 #include <linux/acpi.h> 20 #include <linux/property.h> 21 #include <linux/regmap.h> 22 #include <linux/reset.h> 23 24 #include "spi-dw.h" 25 26 #define DRIVER_NAME "dw_spi_mmio" 27 28 struct dw_spi_mmio { 29 struct dw_spi dws; 30 struct clk *clk; 31 struct clk *pclk; 32 void *priv; 33 struct reset_control *rstc; 34 }; 35 36 #define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24 37 #define OCELOT_IF_SI_OWNER_OFFSET 4 38 #define JAGUAR2_IF_SI_OWNER_OFFSET 6 39 #define MSCC_IF_SI_OWNER_MASK GENMASK(1, 0) 40 #define MSCC_IF_SI_OWNER_SISL 0 41 #define MSCC_IF_SI_OWNER_SIBM 1 42 #define MSCC_IF_SI_OWNER_SIMC 2 43 44 #define MSCC_SPI_MST_SW_MODE 0x14 45 #define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE BIT(13) 46 #define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x) (x << 5) 47 48 /* 49 * For Keem Bay, CTRLR0[31] is used to select controller mode. 50 * 0: SSI is slave 51 * 1: SSI is master 52 */ 53 #define KEEMBAY_CTRLR0_SSIC_IS_MST BIT(31) 54 55 struct dw_spi_mscc { 56 struct regmap *syscon; 57 void __iomem *spi_mst; 58 }; 59 60 /* 61 * The Designware SPI controller (referred to as master in the documentation) 62 * automatically deasserts chip select when the tx fifo is empty. The chip 63 * selects then needs to be either driven as GPIOs or, for the first 4 using the 64 * the SPI boot controller registers. the final chip select is an OR gate 65 * between the Designware SPI controller and the SPI boot controller. 66 */ 67 static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable) 68 { 69 struct dw_spi *dws = spi_master_get_devdata(spi->master); 70 struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws); 71 struct dw_spi_mscc *dwsmscc = dwsmmio->priv; 72 u32 cs = spi->chip_select; 73 74 if (cs < 4) { 75 u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE; 76 77 if (!enable) 78 sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs)); 79 80 writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE); 81 } 82 83 dw_spi_set_cs(spi, enable); 84 } 85 86 static int dw_spi_mscc_init(struct platform_device *pdev, 87 struct dw_spi_mmio *dwsmmio, 88 const char *cpu_syscon, u32 if_si_owner_offset) 89 { 90 struct dw_spi_mscc *dwsmscc; 91 92 dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL); 93 if (!dwsmscc) 94 return -ENOMEM; 95 96 dwsmscc->spi_mst = devm_platform_ioremap_resource(pdev, 1); 97 if (IS_ERR(dwsmscc->spi_mst)) { 98 dev_err(&pdev->dev, "SPI_MST region map failed\n"); 99 return PTR_ERR(dwsmscc->spi_mst); 100 } 101 102 dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon); 103 if (IS_ERR(dwsmscc->syscon)) 104 return PTR_ERR(dwsmscc->syscon); 105 106 /* Deassert all CS */ 107 writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE); 108 109 /* Select the owner of the SI interface */ 110 regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL, 111 MSCC_IF_SI_OWNER_MASK << if_si_owner_offset, 112 MSCC_IF_SI_OWNER_SIMC << if_si_owner_offset); 113 114 dwsmmio->dws.set_cs = dw_spi_mscc_set_cs; 115 dwsmmio->priv = dwsmscc; 116 117 /* Register hook to configure CTRLR0 */ 118 dwsmmio->dws.update_cr0 = dw_spi_update_cr0; 119 120 return 0; 121 } 122 123 static int dw_spi_mscc_ocelot_init(struct platform_device *pdev, 124 struct dw_spi_mmio *dwsmmio) 125 { 126 return dw_spi_mscc_init(pdev, dwsmmio, "mscc,ocelot-cpu-syscon", 127 OCELOT_IF_SI_OWNER_OFFSET); 128 } 129 130 static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev, 131 struct dw_spi_mmio *dwsmmio) 132 { 133 return dw_spi_mscc_init(pdev, dwsmmio, "mscc,jaguar2-cpu-syscon", 134 JAGUAR2_IF_SI_OWNER_OFFSET); 135 } 136 137 static int dw_spi_alpine_init(struct platform_device *pdev, 138 struct dw_spi_mmio *dwsmmio) 139 { 140 dwsmmio->dws.cs_override = 1; 141 142 /* Register hook to configure CTRLR0 */ 143 dwsmmio->dws.update_cr0 = dw_spi_update_cr0; 144 145 return 0; 146 } 147 148 static int dw_spi_dw_apb_init(struct platform_device *pdev, 149 struct dw_spi_mmio *dwsmmio) 150 { 151 /* Register hook to configure CTRLR0 */ 152 dwsmmio->dws.update_cr0 = dw_spi_update_cr0; 153 154 dw_spi_dma_setup_generic(&dwsmmio->dws); 155 156 return 0; 157 } 158 159 static int dw_spi_dwc_ssi_init(struct platform_device *pdev, 160 struct dw_spi_mmio *dwsmmio) 161 { 162 /* Register hook to configure CTRLR0 */ 163 dwsmmio->dws.update_cr0 = dw_spi_update_cr0_v1_01a; 164 165 dw_spi_dma_setup_generic(&dwsmmio->dws); 166 167 return 0; 168 } 169 170 static u32 dw_spi_update_cr0_keembay(struct spi_controller *master, 171 struct spi_device *spi, 172 struct spi_transfer *transfer) 173 { 174 u32 cr0 = dw_spi_update_cr0_v1_01a(master, spi, transfer); 175 176 return cr0 | KEEMBAY_CTRLR0_SSIC_IS_MST; 177 } 178 179 static int dw_spi_keembay_init(struct platform_device *pdev, 180 struct dw_spi_mmio *dwsmmio) 181 { 182 /* Register hook to configure CTRLR0 */ 183 dwsmmio->dws.update_cr0 = dw_spi_update_cr0_keembay; 184 185 return 0; 186 } 187 188 static int dw_spi_mmio_probe(struct platform_device *pdev) 189 { 190 int (*init_func)(struct platform_device *pdev, 191 struct dw_spi_mmio *dwsmmio); 192 struct dw_spi_mmio *dwsmmio; 193 struct resource *mem; 194 struct dw_spi *dws; 195 int ret; 196 int num_cs; 197 198 dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio), 199 GFP_KERNEL); 200 if (!dwsmmio) 201 return -ENOMEM; 202 203 dws = &dwsmmio->dws; 204 205 /* Get basic io resource and map it */ 206 dws->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); 207 if (IS_ERR(dws->regs)) 208 return PTR_ERR(dws->regs); 209 210 dws->paddr = mem->start; 211 212 dws->irq = platform_get_irq(pdev, 0); 213 if (dws->irq < 0) 214 return dws->irq; /* -ENXIO */ 215 216 dwsmmio->clk = devm_clk_get(&pdev->dev, NULL); 217 if (IS_ERR(dwsmmio->clk)) 218 return PTR_ERR(dwsmmio->clk); 219 ret = clk_prepare_enable(dwsmmio->clk); 220 if (ret) 221 return ret; 222 223 /* Optional clock needed to access the registers */ 224 dwsmmio->pclk = devm_clk_get_optional(&pdev->dev, "pclk"); 225 if (IS_ERR(dwsmmio->pclk)) { 226 ret = PTR_ERR(dwsmmio->pclk); 227 goto out_clk; 228 } 229 ret = clk_prepare_enable(dwsmmio->pclk); 230 if (ret) 231 goto out_clk; 232 233 /* find an optional reset controller */ 234 dwsmmio->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, "spi"); 235 if (IS_ERR(dwsmmio->rstc)) { 236 ret = PTR_ERR(dwsmmio->rstc); 237 goto out_clk; 238 } 239 reset_control_deassert(dwsmmio->rstc); 240 241 dws->bus_num = pdev->id; 242 243 dws->max_freq = clk_get_rate(dwsmmio->clk); 244 245 device_property_read_u32(&pdev->dev, "reg-io-width", &dws->reg_io_width); 246 247 num_cs = 4; 248 249 device_property_read_u32(&pdev->dev, "num-cs", &num_cs); 250 251 dws->num_cs = num_cs; 252 253 init_func = device_get_match_data(&pdev->dev); 254 if (init_func) { 255 ret = init_func(pdev, dwsmmio); 256 if (ret) 257 goto out; 258 } 259 260 pm_runtime_enable(&pdev->dev); 261 262 ret = dw_spi_add_host(&pdev->dev, dws); 263 if (ret) 264 goto out; 265 266 platform_set_drvdata(pdev, dwsmmio); 267 return 0; 268 269 out: 270 pm_runtime_disable(&pdev->dev); 271 clk_disable_unprepare(dwsmmio->pclk); 272 out_clk: 273 clk_disable_unprepare(dwsmmio->clk); 274 reset_control_assert(dwsmmio->rstc); 275 276 return ret; 277 } 278 279 static int dw_spi_mmio_remove(struct platform_device *pdev) 280 { 281 struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev); 282 283 dw_spi_remove_host(&dwsmmio->dws); 284 pm_runtime_disable(&pdev->dev); 285 clk_disable_unprepare(dwsmmio->pclk); 286 clk_disable_unprepare(dwsmmio->clk); 287 reset_control_assert(dwsmmio->rstc); 288 289 return 0; 290 } 291 292 static const struct of_device_id dw_spi_mmio_of_match[] = { 293 { .compatible = "snps,dw-apb-ssi", .data = dw_spi_dw_apb_init}, 294 { .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init}, 295 { .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init}, 296 { .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init}, 297 { .compatible = "renesas,rzn1-spi", .data = dw_spi_dw_apb_init}, 298 { .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_dwc_ssi_init}, 299 { .compatible = "intel,keembay-ssi", .data = dw_spi_keembay_init}, 300 { /* end of table */} 301 }; 302 MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match); 303 304 #ifdef CONFIG_ACPI 305 static const struct acpi_device_id dw_spi_mmio_acpi_match[] = { 306 {"HISI0173", (kernel_ulong_t)dw_spi_dw_apb_init}, 307 {}, 308 }; 309 MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match); 310 #endif 311 312 static struct platform_driver dw_spi_mmio_driver = { 313 .probe = dw_spi_mmio_probe, 314 .remove = dw_spi_mmio_remove, 315 .driver = { 316 .name = DRIVER_NAME, 317 .of_match_table = dw_spi_mmio_of_match, 318 .acpi_match_table = ACPI_PTR(dw_spi_mmio_acpi_match), 319 }, 320 }; 321 module_platform_driver(dw_spi_mmio_driver); 322 323 MODULE_AUTHOR("Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>"); 324 MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core"); 325 MODULE_LICENSE("GPL v2"); 326