1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Memory-mapped interface driver for DW SPI Core 4 * 5 * Copyright (c) 2010, Octasic semiconductor. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/err.h> 10 #include <linux/interrupt.h> 11 #include <linux/platform_device.h> 12 #include <linux/slab.h> 13 #include <linux/spi/spi.h> 14 #include <linux/scatterlist.h> 15 #include <linux/mfd/syscon.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/of_platform.h> 19 #include <linux/acpi.h> 20 #include <linux/property.h> 21 #include <linux/regmap.h> 22 23 #include "spi-dw.h" 24 25 #define DRIVER_NAME "dw_spi_mmio" 26 27 struct dw_spi_mmio { 28 struct dw_spi dws; 29 struct clk *clk; 30 struct clk *pclk; 31 void *priv; 32 }; 33 34 #define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24 35 #define OCELOT_IF_SI_OWNER_OFFSET 4 36 #define JAGUAR2_IF_SI_OWNER_OFFSET 6 37 #define MSCC_IF_SI_OWNER_MASK GENMASK(1, 0) 38 #define MSCC_IF_SI_OWNER_SISL 0 39 #define MSCC_IF_SI_OWNER_SIBM 1 40 #define MSCC_IF_SI_OWNER_SIMC 2 41 42 #define MSCC_SPI_MST_SW_MODE 0x14 43 #define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE BIT(13) 44 #define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x) (x << 5) 45 46 struct dw_spi_mscc { 47 struct regmap *syscon; 48 void __iomem *spi_mst; 49 }; 50 51 /* 52 * The Designware SPI controller (referred to as master in the documentation) 53 * automatically deasserts chip select when the tx fifo is empty. The chip 54 * selects then needs to be either driven as GPIOs or, for the first 4 using the 55 * the SPI boot controller registers. the final chip select is an OR gate 56 * between the Designware SPI controller and the SPI boot controller. 57 */ 58 static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable) 59 { 60 struct dw_spi *dws = spi_master_get_devdata(spi->master); 61 struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws); 62 struct dw_spi_mscc *dwsmscc = dwsmmio->priv; 63 u32 cs = spi->chip_select; 64 65 if (cs < 4) { 66 u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE; 67 68 if (!enable) 69 sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs)); 70 71 writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE); 72 } 73 74 dw_spi_set_cs(spi, enable); 75 } 76 77 static int dw_spi_mscc_init(struct platform_device *pdev, 78 struct dw_spi_mmio *dwsmmio, 79 const char *cpu_syscon, u32 if_si_owner_offset) 80 { 81 struct dw_spi_mscc *dwsmscc; 82 struct resource *res; 83 84 dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL); 85 if (!dwsmscc) 86 return -ENOMEM; 87 88 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 89 dwsmscc->spi_mst = devm_ioremap_resource(&pdev->dev, res); 90 if (IS_ERR(dwsmscc->spi_mst)) { 91 dev_err(&pdev->dev, "SPI_MST region map failed\n"); 92 return PTR_ERR(dwsmscc->spi_mst); 93 } 94 95 dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon); 96 if (IS_ERR(dwsmscc->syscon)) 97 return PTR_ERR(dwsmscc->syscon); 98 99 /* Deassert all CS */ 100 writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE); 101 102 /* Select the owner of the SI interface */ 103 regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL, 104 MSCC_IF_SI_OWNER_MASK << if_si_owner_offset, 105 MSCC_IF_SI_OWNER_SIMC << if_si_owner_offset); 106 107 dwsmmio->dws.set_cs = dw_spi_mscc_set_cs; 108 dwsmmio->priv = dwsmscc; 109 110 return 0; 111 } 112 113 static int dw_spi_mscc_ocelot_init(struct platform_device *pdev, 114 struct dw_spi_mmio *dwsmmio) 115 { 116 return dw_spi_mscc_init(pdev, dwsmmio, "mscc,ocelot-cpu-syscon", 117 OCELOT_IF_SI_OWNER_OFFSET); 118 } 119 120 static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev, 121 struct dw_spi_mmio *dwsmmio) 122 { 123 return dw_spi_mscc_init(pdev, dwsmmio, "mscc,jaguar2-cpu-syscon", 124 JAGUAR2_IF_SI_OWNER_OFFSET); 125 } 126 127 static int dw_spi_alpine_init(struct platform_device *pdev, 128 struct dw_spi_mmio *dwsmmio) 129 { 130 dwsmmio->dws.cs_override = 1; 131 132 return 0; 133 } 134 135 static int dw_spi_mmio_probe(struct platform_device *pdev) 136 { 137 int (*init_func)(struct platform_device *pdev, 138 struct dw_spi_mmio *dwsmmio); 139 struct dw_spi_mmio *dwsmmio; 140 struct dw_spi *dws; 141 struct resource *mem; 142 int ret; 143 int num_cs; 144 145 dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio), 146 GFP_KERNEL); 147 if (!dwsmmio) 148 return -ENOMEM; 149 150 dws = &dwsmmio->dws; 151 152 /* Get basic io resource and map it */ 153 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 154 dws->regs = devm_ioremap_resource(&pdev->dev, mem); 155 if (IS_ERR(dws->regs)) { 156 dev_err(&pdev->dev, "SPI region map failed\n"); 157 return PTR_ERR(dws->regs); 158 } 159 160 dws->irq = platform_get_irq(pdev, 0); 161 if (dws->irq < 0) { 162 dev_err(&pdev->dev, "no irq resource?\n"); 163 return dws->irq; /* -ENXIO */ 164 } 165 166 dwsmmio->clk = devm_clk_get(&pdev->dev, NULL); 167 if (IS_ERR(dwsmmio->clk)) 168 return PTR_ERR(dwsmmio->clk); 169 ret = clk_prepare_enable(dwsmmio->clk); 170 if (ret) 171 return ret; 172 173 /* Optional clock needed to access the registers */ 174 dwsmmio->pclk = devm_clk_get_optional(&pdev->dev, "pclk"); 175 if (IS_ERR(dwsmmio->pclk)) 176 return PTR_ERR(dwsmmio->pclk); 177 ret = clk_prepare_enable(dwsmmio->pclk); 178 if (ret) 179 goto out_clk; 180 181 dws->bus_num = pdev->id; 182 183 dws->max_freq = clk_get_rate(dwsmmio->clk); 184 185 device_property_read_u32(&pdev->dev, "reg-io-width", &dws->reg_io_width); 186 187 num_cs = 4; 188 189 device_property_read_u32(&pdev->dev, "num-cs", &num_cs); 190 191 dws->num_cs = num_cs; 192 193 init_func = device_get_match_data(&pdev->dev); 194 if (init_func) { 195 ret = init_func(pdev, dwsmmio); 196 if (ret) 197 goto out; 198 } 199 200 ret = dw_spi_add_host(&pdev->dev, dws); 201 if (ret) 202 goto out; 203 204 platform_set_drvdata(pdev, dwsmmio); 205 return 0; 206 207 out: 208 clk_disable_unprepare(dwsmmio->pclk); 209 out_clk: 210 clk_disable_unprepare(dwsmmio->clk); 211 return ret; 212 } 213 214 static int dw_spi_mmio_remove(struct platform_device *pdev) 215 { 216 struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev); 217 218 dw_spi_remove_host(&dwsmmio->dws); 219 clk_disable_unprepare(dwsmmio->pclk); 220 clk_disable_unprepare(dwsmmio->clk); 221 222 return 0; 223 } 224 225 static const struct of_device_id dw_spi_mmio_of_match[] = { 226 { .compatible = "snps,dw-apb-ssi", }, 227 { .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init}, 228 { .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init}, 229 { .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init}, 230 { /* end of table */} 231 }; 232 MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match); 233 234 static const struct acpi_device_id dw_spi_mmio_acpi_match[] = { 235 {"HISI0173", 0}, 236 {}, 237 }; 238 MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match); 239 240 static struct platform_driver dw_spi_mmio_driver = { 241 .probe = dw_spi_mmio_probe, 242 .remove = dw_spi_mmio_remove, 243 .driver = { 244 .name = DRIVER_NAME, 245 .of_match_table = dw_spi_mmio_of_match, 246 .acpi_match_table = ACPI_PTR(dw_spi_mmio_acpi_match), 247 }, 248 }; 249 module_platform_driver(dw_spi_mmio_driver); 250 251 MODULE_AUTHOR("Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>"); 252 MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core"); 253 MODULE_LICENSE("GPL v2"); 254