1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Special handling for DW DMA core 4 * 5 * Copyright (c) 2009, 2014 Intel Corporation. 6 */ 7 8 #include <linux/completion.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/dmaengine.h> 11 #include <linux/irqreturn.h> 12 #include <linux/jiffies.h> 13 #include <linux/module.h> 14 #include <linux/pci.h> 15 #include <linux/platform_data/dma-dw.h> 16 #include <linux/spi/spi.h> 17 #include <linux/types.h> 18 19 #include "spi-dw.h" 20 21 #define DW_SPI_RX_BUSY 0 22 #define DW_SPI_RX_BURST_LEVEL 16 23 #define DW_SPI_TX_BUSY 1 24 #define DW_SPI_TX_BURST_LEVEL 16 25 26 static bool dw_spi_dma_chan_filter(struct dma_chan *chan, void *param) 27 { 28 struct dw_dma_slave *s = param; 29 30 if (s->dma_dev != chan->device->dev) 31 return false; 32 33 chan->private = s; 34 return true; 35 } 36 37 static void dw_spi_dma_maxburst_init(struct dw_spi *dws) 38 { 39 struct dma_slave_caps caps; 40 u32 max_burst, def_burst; 41 int ret; 42 43 def_burst = dws->fifo_len / 2; 44 45 ret = dma_get_slave_caps(dws->rxchan, &caps); 46 if (!ret && caps.max_burst) 47 max_burst = caps.max_burst; 48 else 49 max_burst = DW_SPI_RX_BURST_LEVEL; 50 51 dws->rxburst = min(max_burst, def_burst); 52 dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1); 53 54 ret = dma_get_slave_caps(dws->txchan, &caps); 55 if (!ret && caps.max_burst) 56 max_burst = caps.max_burst; 57 else 58 max_burst = DW_SPI_TX_BURST_LEVEL; 59 60 /* 61 * Having a Rx DMA channel serviced with higher priority than a Tx DMA 62 * channel might not be enough to provide a well balanced DMA-based 63 * SPI transfer interface. There might still be moments when the Tx DMA 64 * channel is occasionally handled faster than the Rx DMA channel. 65 * That in its turn will eventually cause the SPI Rx FIFO overflow if 66 * SPI bus speed is high enough to fill the SPI Rx FIFO in before it's 67 * cleared by the Rx DMA channel. In order to fix the problem the Tx 68 * DMA activity is intentionally slowed down by limiting the SPI Tx 69 * FIFO depth with a value twice bigger than the Tx burst length. 70 */ 71 dws->txburst = min(max_burst, def_burst); 72 dw_writel(dws, DW_SPI_DMATDLR, dws->txburst); 73 } 74 75 static void dw_spi_dma_sg_burst_init(struct dw_spi *dws) 76 { 77 struct dma_slave_caps tx = {0}, rx = {0}; 78 79 dma_get_slave_caps(dws->txchan, &tx); 80 dma_get_slave_caps(dws->rxchan, &rx); 81 82 if (tx.max_sg_burst > 0 && rx.max_sg_burst > 0) 83 dws->dma_sg_burst = min(tx.max_sg_burst, rx.max_sg_burst); 84 else if (tx.max_sg_burst > 0) 85 dws->dma_sg_burst = tx.max_sg_burst; 86 else if (rx.max_sg_burst > 0) 87 dws->dma_sg_burst = rx.max_sg_burst; 88 else 89 dws->dma_sg_burst = 0; 90 } 91 92 static int dw_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws) 93 { 94 struct dw_dma_slave dma_tx = { .dst_id = 1 }, *tx = &dma_tx; 95 struct dw_dma_slave dma_rx = { .src_id = 0 }, *rx = &dma_rx; 96 struct pci_dev *dma_dev; 97 dma_cap_mask_t mask; 98 99 /* 100 * Get pci device for DMA controller, currently it could only 101 * be the DMA controller of Medfield 102 */ 103 dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL); 104 if (!dma_dev) 105 return -ENODEV; 106 107 dma_cap_zero(mask); 108 dma_cap_set(DMA_SLAVE, mask); 109 110 /* 1. Init rx channel */ 111 rx->dma_dev = &dma_dev->dev; 112 dws->rxchan = dma_request_channel(mask, dw_spi_dma_chan_filter, rx); 113 if (!dws->rxchan) 114 goto err_exit; 115 116 /* 2. Init tx channel */ 117 tx->dma_dev = &dma_dev->dev; 118 dws->txchan = dma_request_channel(mask, dw_spi_dma_chan_filter, tx); 119 if (!dws->txchan) 120 goto free_rxchan; 121 122 dws->master->dma_rx = dws->rxchan; 123 dws->master->dma_tx = dws->txchan; 124 125 init_completion(&dws->dma_completion); 126 127 dw_spi_dma_maxburst_init(dws); 128 129 dw_spi_dma_sg_burst_init(dws); 130 131 return 0; 132 133 free_rxchan: 134 dma_release_channel(dws->rxchan); 135 dws->rxchan = NULL; 136 err_exit: 137 return -EBUSY; 138 } 139 140 static int dw_spi_dma_init_generic(struct device *dev, struct dw_spi *dws) 141 { 142 int ret; 143 144 dws->rxchan = dma_request_chan(dev, "rx"); 145 if (IS_ERR(dws->rxchan)) { 146 ret = PTR_ERR(dws->rxchan); 147 dws->rxchan = NULL; 148 goto err_exit; 149 } 150 151 dws->txchan = dma_request_chan(dev, "tx"); 152 if (IS_ERR(dws->txchan)) { 153 ret = PTR_ERR(dws->txchan); 154 dws->txchan = NULL; 155 goto free_rxchan; 156 } 157 158 dws->master->dma_rx = dws->rxchan; 159 dws->master->dma_tx = dws->txchan; 160 161 init_completion(&dws->dma_completion); 162 163 dw_spi_dma_maxburst_init(dws); 164 165 dw_spi_dma_sg_burst_init(dws); 166 167 return 0; 168 169 free_rxchan: 170 dma_release_channel(dws->rxchan); 171 dws->rxchan = NULL; 172 err_exit: 173 return ret; 174 } 175 176 static void dw_spi_dma_exit(struct dw_spi *dws) 177 { 178 if (dws->txchan) { 179 dmaengine_terminate_sync(dws->txchan); 180 dma_release_channel(dws->txchan); 181 } 182 183 if (dws->rxchan) { 184 dmaengine_terminate_sync(dws->rxchan); 185 dma_release_channel(dws->rxchan); 186 } 187 } 188 189 static irqreturn_t dw_spi_dma_transfer_handler(struct dw_spi *dws) 190 { 191 dw_spi_check_status(dws, false); 192 193 complete(&dws->dma_completion); 194 195 return IRQ_HANDLED; 196 } 197 198 static bool dw_spi_can_dma(struct spi_controller *master, 199 struct spi_device *spi, struct spi_transfer *xfer) 200 { 201 struct dw_spi *dws = spi_controller_get_devdata(master); 202 203 return xfer->len > dws->fifo_len; 204 } 205 206 static enum dma_slave_buswidth dw_spi_dma_convert_width(u8 n_bytes) 207 { 208 if (n_bytes == 1) 209 return DMA_SLAVE_BUSWIDTH_1_BYTE; 210 else if (n_bytes == 2) 211 return DMA_SLAVE_BUSWIDTH_2_BYTES; 212 213 return DMA_SLAVE_BUSWIDTH_UNDEFINED; 214 } 215 216 static int dw_spi_dma_wait(struct dw_spi *dws, unsigned int len, u32 speed) 217 { 218 unsigned long long ms; 219 220 ms = len * MSEC_PER_SEC * BITS_PER_BYTE; 221 do_div(ms, speed); 222 ms += ms + 200; 223 224 if (ms > UINT_MAX) 225 ms = UINT_MAX; 226 227 ms = wait_for_completion_timeout(&dws->dma_completion, 228 msecs_to_jiffies(ms)); 229 230 if (ms == 0) { 231 dev_err(&dws->master->cur_msg->spi->dev, 232 "DMA transaction timed out\n"); 233 return -ETIMEDOUT; 234 } 235 236 return 0; 237 } 238 239 static inline bool dw_spi_dma_tx_busy(struct dw_spi *dws) 240 { 241 return !(dw_readl(dws, DW_SPI_SR) & DW_SPI_SR_TF_EMPT); 242 } 243 244 static int dw_spi_dma_wait_tx_done(struct dw_spi *dws, 245 struct spi_transfer *xfer) 246 { 247 int retry = DW_SPI_WAIT_RETRIES; 248 struct spi_delay delay; 249 u32 nents; 250 251 nents = dw_readl(dws, DW_SPI_TXFLR); 252 delay.unit = SPI_DELAY_UNIT_SCK; 253 delay.value = nents * dws->n_bytes * BITS_PER_BYTE; 254 255 while (dw_spi_dma_tx_busy(dws) && retry--) 256 spi_delay_exec(&delay, xfer); 257 258 if (retry < 0) { 259 dev_err(&dws->master->dev, "Tx hanged up\n"); 260 return -EIO; 261 } 262 263 return 0; 264 } 265 266 /* 267 * dws->dma_chan_busy is set before the dma transfer starts, callback for tx 268 * channel will clear a corresponding bit. 269 */ 270 static void dw_spi_dma_tx_done(void *arg) 271 { 272 struct dw_spi *dws = arg; 273 274 clear_bit(DW_SPI_TX_BUSY, &dws->dma_chan_busy); 275 if (test_bit(DW_SPI_RX_BUSY, &dws->dma_chan_busy)) 276 return; 277 278 complete(&dws->dma_completion); 279 } 280 281 static int dw_spi_dma_config_tx(struct dw_spi *dws) 282 { 283 struct dma_slave_config txconf; 284 285 memset(&txconf, 0, sizeof(txconf)); 286 txconf.direction = DMA_MEM_TO_DEV; 287 txconf.dst_addr = dws->dma_addr; 288 txconf.dst_maxburst = dws->txburst; 289 txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 290 txconf.dst_addr_width = dw_spi_dma_convert_width(dws->n_bytes); 291 txconf.device_fc = false; 292 293 return dmaengine_slave_config(dws->txchan, &txconf); 294 } 295 296 static int dw_spi_dma_submit_tx(struct dw_spi *dws, struct scatterlist *sgl, 297 unsigned int nents) 298 { 299 struct dma_async_tx_descriptor *txdesc; 300 dma_cookie_t cookie; 301 int ret; 302 303 txdesc = dmaengine_prep_slave_sg(dws->txchan, sgl, nents, 304 DMA_MEM_TO_DEV, 305 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 306 if (!txdesc) 307 return -ENOMEM; 308 309 txdesc->callback = dw_spi_dma_tx_done; 310 txdesc->callback_param = dws; 311 312 cookie = dmaengine_submit(txdesc); 313 ret = dma_submit_error(cookie); 314 if (ret) { 315 dmaengine_terminate_sync(dws->txchan); 316 return ret; 317 } 318 319 set_bit(DW_SPI_TX_BUSY, &dws->dma_chan_busy); 320 321 return 0; 322 } 323 324 static inline bool dw_spi_dma_rx_busy(struct dw_spi *dws) 325 { 326 return !!(dw_readl(dws, DW_SPI_SR) & DW_SPI_SR_RF_NOT_EMPT); 327 } 328 329 static int dw_spi_dma_wait_rx_done(struct dw_spi *dws) 330 { 331 int retry = DW_SPI_WAIT_RETRIES; 332 struct spi_delay delay; 333 unsigned long ns, us; 334 u32 nents; 335 336 /* 337 * It's unlikely that DMA engine is still doing the data fetching, but 338 * if it's let's give it some reasonable time. The timeout calculation 339 * is based on the synchronous APB/SSI reference clock rate, on a 340 * number of data entries left in the Rx FIFO, times a number of clock 341 * periods normally needed for a single APB read/write transaction 342 * without PREADY signal utilized (which is true for the DW APB SSI 343 * controller). 344 */ 345 nents = dw_readl(dws, DW_SPI_RXFLR); 346 ns = 4U * NSEC_PER_SEC / dws->max_freq * nents; 347 if (ns <= NSEC_PER_USEC) { 348 delay.unit = SPI_DELAY_UNIT_NSECS; 349 delay.value = ns; 350 } else { 351 us = DIV_ROUND_UP(ns, NSEC_PER_USEC); 352 delay.unit = SPI_DELAY_UNIT_USECS; 353 delay.value = clamp_val(us, 0, USHRT_MAX); 354 } 355 356 while (dw_spi_dma_rx_busy(dws) && retry--) 357 spi_delay_exec(&delay, NULL); 358 359 if (retry < 0) { 360 dev_err(&dws->master->dev, "Rx hanged up\n"); 361 return -EIO; 362 } 363 364 return 0; 365 } 366 367 /* 368 * dws->dma_chan_busy is set before the dma transfer starts, callback for rx 369 * channel will clear a corresponding bit. 370 */ 371 static void dw_spi_dma_rx_done(void *arg) 372 { 373 struct dw_spi *dws = arg; 374 375 clear_bit(DW_SPI_RX_BUSY, &dws->dma_chan_busy); 376 if (test_bit(DW_SPI_TX_BUSY, &dws->dma_chan_busy)) 377 return; 378 379 complete(&dws->dma_completion); 380 } 381 382 static int dw_spi_dma_config_rx(struct dw_spi *dws) 383 { 384 struct dma_slave_config rxconf; 385 386 memset(&rxconf, 0, sizeof(rxconf)); 387 rxconf.direction = DMA_DEV_TO_MEM; 388 rxconf.src_addr = dws->dma_addr; 389 rxconf.src_maxburst = dws->rxburst; 390 rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 391 rxconf.src_addr_width = dw_spi_dma_convert_width(dws->n_bytes); 392 rxconf.device_fc = false; 393 394 return dmaengine_slave_config(dws->rxchan, &rxconf); 395 } 396 397 static int dw_spi_dma_submit_rx(struct dw_spi *dws, struct scatterlist *sgl, 398 unsigned int nents) 399 { 400 struct dma_async_tx_descriptor *rxdesc; 401 dma_cookie_t cookie; 402 int ret; 403 404 rxdesc = dmaengine_prep_slave_sg(dws->rxchan, sgl, nents, 405 DMA_DEV_TO_MEM, 406 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 407 if (!rxdesc) 408 return -ENOMEM; 409 410 rxdesc->callback = dw_spi_dma_rx_done; 411 rxdesc->callback_param = dws; 412 413 cookie = dmaengine_submit(rxdesc); 414 ret = dma_submit_error(cookie); 415 if (ret) { 416 dmaengine_terminate_sync(dws->rxchan); 417 return ret; 418 } 419 420 set_bit(DW_SPI_RX_BUSY, &dws->dma_chan_busy); 421 422 return 0; 423 } 424 425 static int dw_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer) 426 { 427 u16 imr, dma_ctrl; 428 int ret; 429 430 if (!xfer->tx_buf) 431 return -EINVAL; 432 433 /* Setup DMA channels */ 434 ret = dw_spi_dma_config_tx(dws); 435 if (ret) 436 return ret; 437 438 if (xfer->rx_buf) { 439 ret = dw_spi_dma_config_rx(dws); 440 if (ret) 441 return ret; 442 } 443 444 /* Set the DMA handshaking interface */ 445 dma_ctrl = DW_SPI_DMACR_TDMAE; 446 if (xfer->rx_buf) 447 dma_ctrl |= DW_SPI_DMACR_RDMAE; 448 dw_writel(dws, DW_SPI_DMACR, dma_ctrl); 449 450 /* Set the interrupt mask */ 451 imr = DW_SPI_INT_TXOI; 452 if (xfer->rx_buf) 453 imr |= DW_SPI_INT_RXUI | DW_SPI_INT_RXOI; 454 dw_spi_umask_intr(dws, imr); 455 456 reinit_completion(&dws->dma_completion); 457 458 dws->transfer_handler = dw_spi_dma_transfer_handler; 459 460 return 0; 461 } 462 463 static int dw_spi_dma_transfer_all(struct dw_spi *dws, 464 struct spi_transfer *xfer) 465 { 466 int ret; 467 468 /* Submit the DMA Tx transfer */ 469 ret = dw_spi_dma_submit_tx(dws, xfer->tx_sg.sgl, xfer->tx_sg.nents); 470 if (ret) 471 goto err_clear_dmac; 472 473 /* Submit the DMA Rx transfer if required */ 474 if (xfer->rx_buf) { 475 ret = dw_spi_dma_submit_rx(dws, xfer->rx_sg.sgl, 476 xfer->rx_sg.nents); 477 if (ret) 478 goto err_clear_dmac; 479 480 /* rx must be started before tx due to spi instinct */ 481 dma_async_issue_pending(dws->rxchan); 482 } 483 484 dma_async_issue_pending(dws->txchan); 485 486 ret = dw_spi_dma_wait(dws, xfer->len, xfer->effective_speed_hz); 487 488 err_clear_dmac: 489 dw_writel(dws, DW_SPI_DMACR, 0); 490 491 return ret; 492 } 493 494 /* 495 * In case if at least one of the requested DMA channels doesn't support the 496 * hardware accelerated SG list entries traverse, the DMA driver will most 497 * likely work that around by performing the IRQ-based SG list entries 498 * resubmission. That might and will cause a problem if the DMA Tx channel is 499 * recharged and re-executed before the Rx DMA channel. Due to 500 * non-deterministic IRQ-handler execution latency the DMA Tx channel will 501 * start pushing data to the SPI bus before the Rx DMA channel is even 502 * reinitialized with the next inbound SG list entry. By doing so the DMA Tx 503 * channel will implicitly start filling the DW APB SSI Rx FIFO up, which while 504 * the DMA Rx channel being recharged and re-executed will eventually be 505 * overflown. 506 * 507 * In order to solve the problem we have to feed the DMA engine with SG list 508 * entries one-by-one. It shall keep the DW APB SSI Tx and Rx FIFOs 509 * synchronized and prevent the Rx FIFO overflow. Since in general the tx_sg 510 * and rx_sg lists may have different number of entries of different lengths 511 * (though total length should match) let's virtually split the SG-lists to the 512 * set of DMA transfers, which length is a minimum of the ordered SG-entries 513 * lengths. An ASCII-sketch of the implemented algo is following: 514 * xfer->len 515 * |___________| 516 * tx_sg list: |___|____|__| 517 * rx_sg list: |_|____|____| 518 * DMA transfers: |_|_|__|_|__| 519 * 520 * Note in order to have this workaround solving the denoted problem the DMA 521 * engine driver should properly initialize the max_sg_burst capability and set 522 * the DMA device max segment size parameter with maximum data block size the 523 * DMA engine supports. 524 */ 525 526 static int dw_spi_dma_transfer_one(struct dw_spi *dws, 527 struct spi_transfer *xfer) 528 { 529 struct scatterlist *tx_sg = NULL, *rx_sg = NULL, tx_tmp, rx_tmp; 530 unsigned int tx_len = 0, rx_len = 0; 531 unsigned int base, len; 532 int ret; 533 534 sg_init_table(&tx_tmp, 1); 535 sg_init_table(&rx_tmp, 1); 536 537 for (base = 0, len = 0; base < xfer->len; base += len) { 538 /* Fetch next Tx DMA data chunk */ 539 if (!tx_len) { 540 tx_sg = !tx_sg ? &xfer->tx_sg.sgl[0] : sg_next(tx_sg); 541 sg_dma_address(&tx_tmp) = sg_dma_address(tx_sg); 542 tx_len = sg_dma_len(tx_sg); 543 } 544 545 /* Fetch next Rx DMA data chunk */ 546 if (!rx_len) { 547 rx_sg = !rx_sg ? &xfer->rx_sg.sgl[0] : sg_next(rx_sg); 548 sg_dma_address(&rx_tmp) = sg_dma_address(rx_sg); 549 rx_len = sg_dma_len(rx_sg); 550 } 551 552 len = min(tx_len, rx_len); 553 554 sg_dma_len(&tx_tmp) = len; 555 sg_dma_len(&rx_tmp) = len; 556 557 /* Submit DMA Tx transfer */ 558 ret = dw_spi_dma_submit_tx(dws, &tx_tmp, 1); 559 if (ret) 560 break; 561 562 /* Submit DMA Rx transfer */ 563 ret = dw_spi_dma_submit_rx(dws, &rx_tmp, 1); 564 if (ret) 565 break; 566 567 /* Rx must be started before Tx due to SPI instinct */ 568 dma_async_issue_pending(dws->rxchan); 569 570 dma_async_issue_pending(dws->txchan); 571 572 /* 573 * Here we only need to wait for the DMA transfer to be 574 * finished since SPI controller is kept enabled during the 575 * procedure this loop implements and there is no risk to lose 576 * data left in the Tx/Rx FIFOs. 577 */ 578 ret = dw_spi_dma_wait(dws, len, xfer->effective_speed_hz); 579 if (ret) 580 break; 581 582 reinit_completion(&dws->dma_completion); 583 584 sg_dma_address(&tx_tmp) += len; 585 sg_dma_address(&rx_tmp) += len; 586 tx_len -= len; 587 rx_len -= len; 588 } 589 590 dw_writel(dws, DW_SPI_DMACR, 0); 591 592 return ret; 593 } 594 595 static int dw_spi_dma_transfer(struct dw_spi *dws, struct spi_transfer *xfer) 596 { 597 unsigned int nents; 598 int ret; 599 600 nents = max(xfer->tx_sg.nents, xfer->rx_sg.nents); 601 602 /* 603 * Execute normal DMA-based transfer (which submits the Rx and Tx SG 604 * lists directly to the DMA engine at once) if either full hardware 605 * accelerated SG list traverse is supported by both channels, or the 606 * Tx-only SPI transfer is requested, or the DMA engine is capable to 607 * handle both SG lists on hardware accelerated basis. 608 */ 609 if (!dws->dma_sg_burst || !xfer->rx_buf || nents <= dws->dma_sg_burst) 610 ret = dw_spi_dma_transfer_all(dws, xfer); 611 else 612 ret = dw_spi_dma_transfer_one(dws, xfer); 613 if (ret) 614 return ret; 615 616 if (dws->master->cur_msg->status == -EINPROGRESS) { 617 ret = dw_spi_dma_wait_tx_done(dws, xfer); 618 if (ret) 619 return ret; 620 } 621 622 if (xfer->rx_buf && dws->master->cur_msg->status == -EINPROGRESS) 623 ret = dw_spi_dma_wait_rx_done(dws); 624 625 return ret; 626 } 627 628 static void dw_spi_dma_stop(struct dw_spi *dws) 629 { 630 if (test_bit(DW_SPI_TX_BUSY, &dws->dma_chan_busy)) { 631 dmaengine_terminate_sync(dws->txchan); 632 clear_bit(DW_SPI_TX_BUSY, &dws->dma_chan_busy); 633 } 634 if (test_bit(DW_SPI_RX_BUSY, &dws->dma_chan_busy)) { 635 dmaengine_terminate_sync(dws->rxchan); 636 clear_bit(DW_SPI_RX_BUSY, &dws->dma_chan_busy); 637 } 638 } 639 640 static const struct dw_spi_dma_ops dw_spi_dma_mfld_ops = { 641 .dma_init = dw_spi_dma_init_mfld, 642 .dma_exit = dw_spi_dma_exit, 643 .dma_setup = dw_spi_dma_setup, 644 .can_dma = dw_spi_can_dma, 645 .dma_transfer = dw_spi_dma_transfer, 646 .dma_stop = dw_spi_dma_stop, 647 }; 648 649 void dw_spi_dma_setup_mfld(struct dw_spi *dws) 650 { 651 dws->dma_ops = &dw_spi_dma_mfld_ops; 652 } 653 EXPORT_SYMBOL_NS_GPL(dw_spi_dma_setup_mfld, SPI_DW_CORE); 654 655 static const struct dw_spi_dma_ops dw_spi_dma_generic_ops = { 656 .dma_init = dw_spi_dma_init_generic, 657 .dma_exit = dw_spi_dma_exit, 658 .dma_setup = dw_spi_dma_setup, 659 .can_dma = dw_spi_can_dma, 660 .dma_transfer = dw_spi_dma_transfer, 661 .dma_stop = dw_spi_dma_stop, 662 }; 663 664 void dw_spi_dma_setup_generic(struct dw_spi *dws) 665 { 666 dws->dma_ops = &dw_spi_dma_generic_ops; 667 } 668 EXPORT_SYMBOL_NS_GPL(dw_spi_dma_setup_generic, SPI_DW_CORE); 669