1 /* 2 * Driver for the Diolan DLN-2 USB-SPI adapter 3 * 4 * Copyright (c) 2014 Intel Corporation 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation, version 2. 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/mfd/dln2.h> 15 #include <linux/spi/spi.h> 16 #include <linux/pm_runtime.h> 17 #include <asm/unaligned.h> 18 19 #define DLN2_SPI_MODULE_ID 0x02 20 #define DLN2_SPI_CMD(cmd) DLN2_CMD(cmd, DLN2_SPI_MODULE_ID) 21 22 /* SPI commands */ 23 #define DLN2_SPI_GET_PORT_COUNT DLN2_SPI_CMD(0x00) 24 #define DLN2_SPI_ENABLE DLN2_SPI_CMD(0x11) 25 #define DLN2_SPI_DISABLE DLN2_SPI_CMD(0x12) 26 #define DLN2_SPI_IS_ENABLED DLN2_SPI_CMD(0x13) 27 #define DLN2_SPI_SET_MODE DLN2_SPI_CMD(0x14) 28 #define DLN2_SPI_GET_MODE DLN2_SPI_CMD(0x15) 29 #define DLN2_SPI_SET_FRAME_SIZE DLN2_SPI_CMD(0x16) 30 #define DLN2_SPI_GET_FRAME_SIZE DLN2_SPI_CMD(0x17) 31 #define DLN2_SPI_SET_FREQUENCY DLN2_SPI_CMD(0x18) 32 #define DLN2_SPI_GET_FREQUENCY DLN2_SPI_CMD(0x19) 33 #define DLN2_SPI_READ_WRITE DLN2_SPI_CMD(0x1A) 34 #define DLN2_SPI_READ DLN2_SPI_CMD(0x1B) 35 #define DLN2_SPI_WRITE DLN2_SPI_CMD(0x1C) 36 #define DLN2_SPI_SET_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x20) 37 #define DLN2_SPI_GET_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x21) 38 #define DLN2_SPI_SET_DELAY_AFTER_SS DLN2_SPI_CMD(0x22) 39 #define DLN2_SPI_GET_DELAY_AFTER_SS DLN2_SPI_CMD(0x23) 40 #define DLN2_SPI_SET_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x24) 41 #define DLN2_SPI_GET_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x25) 42 #define DLN2_SPI_SET_SS DLN2_SPI_CMD(0x26) 43 #define DLN2_SPI_GET_SS DLN2_SPI_CMD(0x27) 44 #define DLN2_SPI_RELEASE_SS DLN2_SPI_CMD(0x28) 45 #define DLN2_SPI_SS_VARIABLE_ENABLE DLN2_SPI_CMD(0x2B) 46 #define DLN2_SPI_SS_VARIABLE_DISABLE DLN2_SPI_CMD(0x2C) 47 #define DLN2_SPI_SS_VARIABLE_IS_ENABLED DLN2_SPI_CMD(0x2D) 48 #define DLN2_SPI_SS_AAT_ENABLE DLN2_SPI_CMD(0x2E) 49 #define DLN2_SPI_SS_AAT_DISABLE DLN2_SPI_CMD(0x2F) 50 #define DLN2_SPI_SS_AAT_IS_ENABLED DLN2_SPI_CMD(0x30) 51 #define DLN2_SPI_SS_BETWEEN_FRAMES_ENABLE DLN2_SPI_CMD(0x31) 52 #define DLN2_SPI_SS_BETWEEN_FRAMES_DISABLE DLN2_SPI_CMD(0x32) 53 #define DLN2_SPI_SS_BETWEEN_FRAMES_IS_ENABLED DLN2_SPI_CMD(0x33) 54 #define DLN2_SPI_SET_CPHA DLN2_SPI_CMD(0x34) 55 #define DLN2_SPI_GET_CPHA DLN2_SPI_CMD(0x35) 56 #define DLN2_SPI_SET_CPOL DLN2_SPI_CMD(0x36) 57 #define DLN2_SPI_GET_CPOL DLN2_SPI_CMD(0x37) 58 #define DLN2_SPI_SS_MULTI_ENABLE DLN2_SPI_CMD(0x38) 59 #define DLN2_SPI_SS_MULTI_DISABLE DLN2_SPI_CMD(0x39) 60 #define DLN2_SPI_SS_MULTI_IS_ENABLED DLN2_SPI_CMD(0x3A) 61 #define DLN2_SPI_GET_SUPPORTED_MODES DLN2_SPI_CMD(0x40) 62 #define DLN2_SPI_GET_SUPPORTED_CPHA_VALUES DLN2_SPI_CMD(0x41) 63 #define DLN2_SPI_GET_SUPPORTED_CPOL_VALUES DLN2_SPI_CMD(0x42) 64 #define DLN2_SPI_GET_SUPPORTED_FRAME_SIZES DLN2_SPI_CMD(0x43) 65 #define DLN2_SPI_GET_SS_COUNT DLN2_SPI_CMD(0x44) 66 #define DLN2_SPI_GET_MIN_FREQUENCY DLN2_SPI_CMD(0x45) 67 #define DLN2_SPI_GET_MAX_FREQUENCY DLN2_SPI_CMD(0x46) 68 #define DLN2_SPI_GET_MIN_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x47) 69 #define DLN2_SPI_GET_MAX_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x48) 70 #define DLN2_SPI_GET_MIN_DELAY_AFTER_SS DLN2_SPI_CMD(0x49) 71 #define DLN2_SPI_GET_MAX_DELAY_AFTER_SS DLN2_SPI_CMD(0x4A) 72 #define DLN2_SPI_GET_MIN_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x4B) 73 #define DLN2_SPI_GET_MAX_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x4C) 74 75 #define DLN2_SPI_MAX_XFER_SIZE 256 76 #define DLN2_SPI_BUF_SIZE (DLN2_SPI_MAX_XFER_SIZE + 16) 77 #define DLN2_SPI_ATTR_LEAVE_SS_LOW BIT(0) 78 #define DLN2_TRANSFERS_WAIT_COMPLETE 1 79 #define DLN2_TRANSFERS_CANCEL 0 80 #define DLN2_RPM_AUTOSUSPEND_TIMEOUT 2000 81 82 struct dln2_spi { 83 struct platform_device *pdev; 84 struct spi_master *master; 85 u8 port; 86 87 /* 88 * This buffer will be used mainly for read/write operations. Since 89 * they're quite large, we cannot use the stack. Protection is not 90 * needed because all SPI communication is serialized by the SPI core. 91 */ 92 void *buf; 93 94 u8 bpw; 95 u32 speed; 96 u16 mode; 97 u8 cs; 98 }; 99 100 /* 101 * Enable/Disable SPI module. The disable command will wait for transfers to 102 * complete first. 103 */ 104 static int dln2_spi_enable(struct dln2_spi *dln2, bool enable) 105 { 106 u16 cmd; 107 struct { 108 u8 port; 109 u8 wait_for_completion; 110 } tx; 111 unsigned len = sizeof(tx); 112 113 tx.port = dln2->port; 114 115 if (enable) { 116 cmd = DLN2_SPI_ENABLE; 117 len -= sizeof(tx.wait_for_completion); 118 } else { 119 tx.wait_for_completion = DLN2_TRANSFERS_WAIT_COMPLETE; 120 cmd = DLN2_SPI_DISABLE; 121 } 122 123 return dln2_transfer_tx(dln2->pdev, cmd, &tx, len); 124 } 125 126 /* 127 * Select/unselect multiple CS lines. The selected lines will be automatically 128 * toggled LOW/HIGH by the board firmware during transfers, provided they're 129 * enabled first. 130 * 131 * Ex: cs_mask = 0x03 -> CS0 & CS1 will be selected and the next WR/RD operation 132 * will toggle the lines LOW/HIGH automatically. 133 */ 134 static int dln2_spi_cs_set(struct dln2_spi *dln2, u8 cs_mask) 135 { 136 struct { 137 u8 port; 138 u8 cs; 139 } tx; 140 141 tx.port = dln2->port; 142 143 /* 144 * According to Diolan docs, "a slave device can be selected by changing 145 * the corresponding bit value to 0". The rest must be set to 1. Hence 146 * the bitwise NOT in front. 147 */ 148 tx.cs = ~cs_mask; 149 150 return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_SS, &tx, sizeof(tx)); 151 } 152 153 /* 154 * Select one CS line. The other lines will be un-selected. 155 */ 156 static int dln2_spi_cs_set_one(struct dln2_spi *dln2, u8 cs) 157 { 158 return dln2_spi_cs_set(dln2, BIT(cs)); 159 } 160 161 /* 162 * Enable/disable CS lines for usage. The module has to be disabled first. 163 */ 164 static int dln2_spi_cs_enable(struct dln2_spi *dln2, u8 cs_mask, bool enable) 165 { 166 struct { 167 u8 port; 168 u8 cs; 169 } tx; 170 u16 cmd; 171 172 tx.port = dln2->port; 173 tx.cs = cs_mask; 174 cmd = enable ? DLN2_SPI_SS_MULTI_ENABLE : DLN2_SPI_SS_MULTI_DISABLE; 175 176 return dln2_transfer_tx(dln2->pdev, cmd, &tx, sizeof(tx)); 177 } 178 179 static int dln2_spi_cs_enable_all(struct dln2_spi *dln2, bool enable) 180 { 181 u8 cs_mask = GENMASK(dln2->master->num_chipselect - 1, 0); 182 183 return dln2_spi_cs_enable(dln2, cs_mask, enable); 184 } 185 186 static int dln2_spi_get_cs_num(struct dln2_spi *dln2, u16 *cs_num) 187 { 188 int ret; 189 struct { 190 u8 port; 191 } tx; 192 struct { 193 __le16 cs_count; 194 } rx; 195 unsigned rx_len = sizeof(rx); 196 197 tx.port = dln2->port; 198 ret = dln2_transfer(dln2->pdev, DLN2_SPI_GET_SS_COUNT, &tx, sizeof(tx), 199 &rx, &rx_len); 200 if (ret < 0) 201 return ret; 202 if (rx_len < sizeof(rx)) 203 return -EPROTO; 204 205 *cs_num = le16_to_cpu(rx.cs_count); 206 207 dev_dbg(&dln2->pdev->dev, "cs_num = %d\n", *cs_num); 208 209 return 0; 210 } 211 212 static int dln2_spi_get_speed(struct dln2_spi *dln2, u16 cmd, u32 *freq) 213 { 214 int ret; 215 struct { 216 u8 port; 217 } tx; 218 struct { 219 __le32 speed; 220 } rx; 221 unsigned rx_len = sizeof(rx); 222 223 tx.port = dln2->port; 224 225 ret = dln2_transfer(dln2->pdev, cmd, &tx, sizeof(tx), &rx, &rx_len); 226 if (ret < 0) 227 return ret; 228 if (rx_len < sizeof(rx)) 229 return -EPROTO; 230 231 *freq = le32_to_cpu(rx.speed); 232 233 return 0; 234 } 235 236 /* 237 * Get bus min/max frequencies. 238 */ 239 static int dln2_spi_get_speed_range(struct dln2_spi *dln2, u32 *fmin, u32 *fmax) 240 { 241 int ret; 242 243 ret = dln2_spi_get_speed(dln2, DLN2_SPI_GET_MIN_FREQUENCY, fmin); 244 if (ret < 0) 245 return ret; 246 247 ret = dln2_spi_get_speed(dln2, DLN2_SPI_GET_MAX_FREQUENCY, fmax); 248 if (ret < 0) 249 return ret; 250 251 dev_dbg(&dln2->pdev->dev, "freq_min = %d, freq_max = %d\n", 252 *fmin, *fmax); 253 254 return 0; 255 } 256 257 /* 258 * Set the bus speed. The module will automatically round down to the closest 259 * available frequency and returns it. The module has to be disabled first. 260 */ 261 static int dln2_spi_set_speed(struct dln2_spi *dln2, u32 speed) 262 { 263 int ret; 264 struct { 265 u8 port; 266 __le32 speed; 267 } __packed tx; 268 struct { 269 __le32 speed; 270 } rx; 271 int rx_len = sizeof(rx); 272 273 tx.port = dln2->port; 274 tx.speed = cpu_to_le32(speed); 275 276 ret = dln2_transfer(dln2->pdev, DLN2_SPI_SET_FREQUENCY, &tx, sizeof(tx), 277 &rx, &rx_len); 278 if (ret < 0) 279 return ret; 280 if (rx_len < sizeof(rx)) 281 return -EPROTO; 282 283 return 0; 284 } 285 286 /* 287 * Change CPOL & CPHA. The module has to be disabled first. 288 */ 289 static int dln2_spi_set_mode(struct dln2_spi *dln2, u8 mode) 290 { 291 struct { 292 u8 port; 293 u8 mode; 294 } tx; 295 296 tx.port = dln2->port; 297 tx.mode = mode; 298 299 return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_MODE, &tx, sizeof(tx)); 300 } 301 302 /* 303 * Change frame size. The module has to be disabled first. 304 */ 305 static int dln2_spi_set_bpw(struct dln2_spi *dln2, u8 bpw) 306 { 307 struct { 308 u8 port; 309 u8 bpw; 310 } tx; 311 312 tx.port = dln2->port; 313 tx.bpw = bpw; 314 315 return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_FRAME_SIZE, 316 &tx, sizeof(tx)); 317 } 318 319 static int dln2_spi_get_supported_frame_sizes(struct dln2_spi *dln2, 320 u32 *bpw_mask) 321 { 322 int ret; 323 struct { 324 u8 port; 325 } tx; 326 struct { 327 u8 count; 328 u8 frame_sizes[36]; 329 } *rx = dln2->buf; 330 unsigned rx_len = sizeof(*rx); 331 int i; 332 333 tx.port = dln2->port; 334 335 ret = dln2_transfer(dln2->pdev, DLN2_SPI_GET_SUPPORTED_FRAME_SIZES, 336 &tx, sizeof(tx), rx, &rx_len); 337 if (ret < 0) 338 return ret; 339 if (rx_len < sizeof(*rx)) 340 return -EPROTO; 341 if (rx->count > ARRAY_SIZE(rx->frame_sizes)) 342 return -EPROTO; 343 344 *bpw_mask = 0; 345 for (i = 0; i < rx->count; i++) 346 *bpw_mask |= BIT(rx->frame_sizes[i] - 1); 347 348 dev_dbg(&dln2->pdev->dev, "bpw_mask = 0x%X\n", *bpw_mask); 349 350 return 0; 351 } 352 353 /* 354 * Copy the data to DLN2 buffer and change the byte order to LE, requested by 355 * DLN2 module. SPI core makes sure that the data length is a multiple of word 356 * size. 357 */ 358 static int dln2_spi_copy_to_buf(u8 *dln2_buf, const u8 *src, u16 len, u8 bpw) 359 { 360 #ifdef __LITTLE_ENDIAN 361 memcpy(dln2_buf, src, len); 362 #else 363 if (bpw <= 8) { 364 memcpy(dln2_buf, src, len); 365 } else if (bpw <= 16) { 366 __le16 *d = (__le16 *)dln2_buf; 367 u16 *s = (u16 *)src; 368 369 len = len / 2; 370 while (len--) 371 *d++ = cpu_to_le16p(s++); 372 } else { 373 __le32 *d = (__le32 *)dln2_buf; 374 u32 *s = (u32 *)src; 375 376 len = len / 4; 377 while (len--) 378 *d++ = cpu_to_le32p(s++); 379 } 380 #endif 381 382 return 0; 383 } 384 385 /* 386 * Copy the data from DLN2 buffer and convert to CPU byte order since the DLN2 387 * buffer is LE ordered. SPI core makes sure that the data length is a multiple 388 * of word size. The RX dln2_buf is 2 byte aligned so, for BE, we have to make 389 * sure we avoid unaligned accesses for 32 bit case. 390 */ 391 static int dln2_spi_copy_from_buf(u8 *dest, const u8 *dln2_buf, u16 len, u8 bpw) 392 { 393 #ifdef __LITTLE_ENDIAN 394 memcpy(dest, dln2_buf, len); 395 #else 396 if (bpw <= 8) { 397 memcpy(dest, dln2_buf, len); 398 } else if (bpw <= 16) { 399 u16 *d = (u16 *)dest; 400 __le16 *s = (__le16 *)dln2_buf; 401 402 len = len / 2; 403 while (len--) 404 *d++ = le16_to_cpup(s++); 405 } else { 406 u32 *d = (u32 *)dest; 407 __le32 *s = (__le32 *)dln2_buf; 408 409 len = len / 4; 410 while (len--) 411 *d++ = get_unaligned_le32(s++); 412 } 413 #endif 414 415 return 0; 416 } 417 418 /* 419 * Perform one write operation. 420 */ 421 static int dln2_spi_write_one(struct dln2_spi *dln2, const u8 *data, 422 u16 data_len, u8 attr) 423 { 424 struct { 425 u8 port; 426 __le16 size; 427 u8 attr; 428 u8 buf[DLN2_SPI_MAX_XFER_SIZE]; 429 } __packed *tx = dln2->buf; 430 unsigned tx_len; 431 432 BUILD_BUG_ON(sizeof(*tx) > DLN2_SPI_BUF_SIZE); 433 434 if (data_len > DLN2_SPI_MAX_XFER_SIZE) 435 return -EINVAL; 436 437 tx->port = dln2->port; 438 tx->size = cpu_to_le16(data_len); 439 tx->attr = attr; 440 441 dln2_spi_copy_to_buf(tx->buf, data, data_len, dln2->bpw); 442 443 tx_len = sizeof(*tx) + data_len - DLN2_SPI_MAX_XFER_SIZE; 444 return dln2_transfer_tx(dln2->pdev, DLN2_SPI_WRITE, tx, tx_len); 445 } 446 447 /* 448 * Perform one read operation. 449 */ 450 static int dln2_spi_read_one(struct dln2_spi *dln2, u8 *data, 451 u16 data_len, u8 attr) 452 { 453 int ret; 454 struct { 455 u8 port; 456 __le16 size; 457 u8 attr; 458 } __packed tx; 459 struct { 460 __le16 size; 461 u8 buf[DLN2_SPI_MAX_XFER_SIZE]; 462 } __packed *rx = dln2->buf; 463 unsigned rx_len = sizeof(*rx); 464 465 BUILD_BUG_ON(sizeof(*rx) > DLN2_SPI_BUF_SIZE); 466 467 if (data_len > DLN2_SPI_MAX_XFER_SIZE) 468 return -EINVAL; 469 470 tx.port = dln2->port; 471 tx.size = cpu_to_le16(data_len); 472 tx.attr = attr; 473 474 ret = dln2_transfer(dln2->pdev, DLN2_SPI_READ, &tx, sizeof(tx), 475 rx, &rx_len); 476 if (ret < 0) 477 return ret; 478 if (rx_len < sizeof(rx->size) + data_len) 479 return -EPROTO; 480 if (le16_to_cpu(rx->size) != data_len) 481 return -EPROTO; 482 483 dln2_spi_copy_from_buf(data, rx->buf, data_len, dln2->bpw); 484 485 return 0; 486 } 487 488 /* 489 * Perform one write & read operation. 490 */ 491 static int dln2_spi_read_write_one(struct dln2_spi *dln2, const u8 *tx_data, 492 u8 *rx_data, u16 data_len, u8 attr) 493 { 494 int ret; 495 struct { 496 u8 port; 497 __le16 size; 498 u8 attr; 499 u8 buf[DLN2_SPI_MAX_XFER_SIZE]; 500 } __packed *tx; 501 struct { 502 __le16 size; 503 u8 buf[DLN2_SPI_MAX_XFER_SIZE]; 504 } __packed *rx; 505 unsigned tx_len, rx_len; 506 507 BUILD_BUG_ON(sizeof(*tx) > DLN2_SPI_BUF_SIZE || 508 sizeof(*rx) > DLN2_SPI_BUF_SIZE); 509 510 if (data_len > DLN2_SPI_MAX_XFER_SIZE) 511 return -EINVAL; 512 513 /* 514 * Since this is a pseudo full-duplex communication, we're perfectly 515 * safe to use the same buffer for both tx and rx. When DLN2 sends the 516 * response back, with the rx data, we don't need the tx buffer anymore. 517 */ 518 tx = dln2->buf; 519 rx = dln2->buf; 520 521 tx->port = dln2->port; 522 tx->size = cpu_to_le16(data_len); 523 tx->attr = attr; 524 525 dln2_spi_copy_to_buf(tx->buf, tx_data, data_len, dln2->bpw); 526 527 tx_len = sizeof(*tx) + data_len - DLN2_SPI_MAX_XFER_SIZE; 528 rx_len = sizeof(*rx); 529 530 ret = dln2_transfer(dln2->pdev, DLN2_SPI_READ_WRITE, tx, tx_len, 531 rx, &rx_len); 532 if (ret < 0) 533 return ret; 534 if (rx_len < sizeof(rx->size) + data_len) 535 return -EPROTO; 536 if (le16_to_cpu(rx->size) != data_len) 537 return -EPROTO; 538 539 dln2_spi_copy_from_buf(rx_data, rx->buf, data_len, dln2->bpw); 540 541 return 0; 542 } 543 544 /* 545 * Read/Write wrapper. It will automatically split an operation into multiple 546 * single ones due to device buffer constraints. 547 */ 548 static int dln2_spi_rdwr(struct dln2_spi *dln2, const u8 *tx_data, 549 u8 *rx_data, u16 data_len, u8 attr) { 550 int ret; 551 u16 len; 552 u8 temp_attr; 553 u16 remaining = data_len; 554 u16 offset; 555 556 do { 557 if (remaining > DLN2_SPI_MAX_XFER_SIZE) { 558 len = DLN2_SPI_MAX_XFER_SIZE; 559 temp_attr = DLN2_SPI_ATTR_LEAVE_SS_LOW; 560 } else { 561 len = remaining; 562 temp_attr = attr; 563 } 564 565 offset = data_len - remaining; 566 567 if (tx_data && rx_data) { 568 ret = dln2_spi_read_write_one(dln2, 569 tx_data + offset, 570 rx_data + offset, 571 len, temp_attr); 572 } else if (tx_data) { 573 ret = dln2_spi_write_one(dln2, 574 tx_data + offset, 575 len, temp_attr); 576 } else if (rx_data) { 577 ret = dln2_spi_read_one(dln2, 578 rx_data + offset, 579 len, temp_attr); 580 } else { 581 return -EINVAL; 582 } 583 584 if (ret < 0) 585 return ret; 586 587 remaining -= len; 588 } while (remaining); 589 590 return 0; 591 } 592 593 static int dln2_spi_prepare_message(struct spi_master *master, 594 struct spi_message *message) 595 { 596 int ret; 597 struct dln2_spi *dln2 = spi_master_get_devdata(master); 598 struct spi_device *spi = message->spi; 599 600 if (dln2->cs != spi->chip_select) { 601 ret = dln2_spi_cs_set_one(dln2, spi->chip_select); 602 if (ret < 0) 603 return ret; 604 605 dln2->cs = spi->chip_select; 606 } 607 608 return 0; 609 } 610 611 static int dln2_spi_transfer_setup(struct dln2_spi *dln2, u32 speed, 612 u8 bpw, u8 mode) 613 { 614 int ret; 615 bool bus_setup_change; 616 617 bus_setup_change = dln2->speed != speed || dln2->mode != mode || 618 dln2->bpw != bpw; 619 620 if (!bus_setup_change) 621 return 0; 622 623 ret = dln2_spi_enable(dln2, false); 624 if (ret < 0) 625 return ret; 626 627 if (dln2->speed != speed) { 628 ret = dln2_spi_set_speed(dln2, speed); 629 if (ret < 0) 630 return ret; 631 632 dln2->speed = speed; 633 } 634 635 if (dln2->mode != mode) { 636 ret = dln2_spi_set_mode(dln2, mode & 0x3); 637 if (ret < 0) 638 return ret; 639 640 dln2->mode = mode; 641 } 642 643 if (dln2->bpw != bpw) { 644 ret = dln2_spi_set_bpw(dln2, bpw); 645 if (ret < 0) 646 return ret; 647 648 dln2->bpw = bpw; 649 } 650 651 return dln2_spi_enable(dln2, true); 652 } 653 654 static int dln2_spi_transfer_one(struct spi_master *master, 655 struct spi_device *spi, 656 struct spi_transfer *xfer) 657 { 658 struct dln2_spi *dln2 = spi_master_get_devdata(master); 659 int status; 660 u8 attr = 0; 661 662 status = dln2_spi_transfer_setup(dln2, xfer->speed_hz, 663 xfer->bits_per_word, 664 spi->mode); 665 if (status < 0) { 666 dev_err(&dln2->pdev->dev, "Cannot setup transfer\n"); 667 return status; 668 } 669 670 if (!xfer->cs_change && !spi_transfer_is_last(master, xfer)) 671 attr = DLN2_SPI_ATTR_LEAVE_SS_LOW; 672 673 status = dln2_spi_rdwr(dln2, xfer->tx_buf, xfer->rx_buf, 674 xfer->len, attr); 675 if (status < 0) 676 dev_err(&dln2->pdev->dev, "write/read failed!\n"); 677 678 return status; 679 } 680 681 static int dln2_spi_probe(struct platform_device *pdev) 682 { 683 struct spi_master *master; 684 struct dln2_spi *dln2; 685 struct dln2_platform_data *pdata = dev_get_platdata(&pdev->dev); 686 struct device *dev = &pdev->dev; 687 int ret; 688 689 master = spi_alloc_master(&pdev->dev, sizeof(*dln2)); 690 if (!master) 691 return -ENOMEM; 692 693 platform_set_drvdata(pdev, master); 694 695 dln2 = spi_master_get_devdata(master); 696 697 dln2->buf = devm_kmalloc(&pdev->dev, DLN2_SPI_BUF_SIZE, GFP_KERNEL); 698 if (!dln2->buf) { 699 ret = -ENOMEM; 700 goto exit_free_master; 701 } 702 703 dln2->master = master; 704 dln2->master->dev.of_node = dev->of_node; 705 dln2->pdev = pdev; 706 dln2->port = pdata->port; 707 /* cs/mode can never be 0xff, so the first transfer will set them */ 708 dln2->cs = 0xff; 709 dln2->mode = 0xff; 710 711 /* disable SPI module before continuing with the setup */ 712 ret = dln2_spi_enable(dln2, false); 713 if (ret < 0) { 714 dev_err(&pdev->dev, "Failed to disable SPI module\n"); 715 goto exit_free_master; 716 } 717 718 ret = dln2_spi_get_cs_num(dln2, &master->num_chipselect); 719 if (ret < 0) { 720 dev_err(&pdev->dev, "Failed to get number of CS pins\n"); 721 goto exit_free_master; 722 } 723 724 ret = dln2_spi_get_speed_range(dln2, 725 &master->min_speed_hz, 726 &master->max_speed_hz); 727 if (ret < 0) { 728 dev_err(&pdev->dev, "Failed to read bus min/max freqs\n"); 729 goto exit_free_master; 730 } 731 732 ret = dln2_spi_get_supported_frame_sizes(dln2, 733 &master->bits_per_word_mask); 734 if (ret < 0) { 735 dev_err(&pdev->dev, "Failed to read supported frame sizes\n"); 736 goto exit_free_master; 737 } 738 739 ret = dln2_spi_cs_enable_all(dln2, true); 740 if (ret < 0) { 741 dev_err(&pdev->dev, "Failed to enable CS pins\n"); 742 goto exit_free_master; 743 } 744 745 master->bus_num = -1; 746 master->mode_bits = SPI_CPOL | SPI_CPHA; 747 master->prepare_message = dln2_spi_prepare_message; 748 master->transfer_one = dln2_spi_transfer_one; 749 master->auto_runtime_pm = true; 750 751 /* enable SPI module, we're good to go */ 752 ret = dln2_spi_enable(dln2, true); 753 if (ret < 0) { 754 dev_err(&pdev->dev, "Failed to enable SPI module\n"); 755 goto exit_free_master; 756 } 757 758 pm_runtime_set_autosuspend_delay(&pdev->dev, 759 DLN2_RPM_AUTOSUSPEND_TIMEOUT); 760 pm_runtime_use_autosuspend(&pdev->dev); 761 pm_runtime_set_active(&pdev->dev); 762 pm_runtime_enable(&pdev->dev); 763 764 ret = devm_spi_register_master(&pdev->dev, master); 765 if (ret < 0) { 766 dev_err(&pdev->dev, "Failed to register master\n"); 767 goto exit_register; 768 } 769 770 return ret; 771 772 exit_register: 773 pm_runtime_disable(&pdev->dev); 774 pm_runtime_set_suspended(&pdev->dev); 775 776 if (dln2_spi_enable(dln2, false) < 0) 777 dev_err(&pdev->dev, "Failed to disable SPI module\n"); 778 exit_free_master: 779 spi_master_put(master); 780 781 return ret; 782 } 783 784 static int dln2_spi_remove(struct platform_device *pdev) 785 { 786 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); 787 struct dln2_spi *dln2 = spi_master_get_devdata(master); 788 789 pm_runtime_disable(&pdev->dev); 790 791 if (dln2_spi_enable(dln2, false) < 0) 792 dev_err(&pdev->dev, "Failed to disable SPI module\n"); 793 794 return 0; 795 } 796 797 #ifdef CONFIG_PM_SLEEP 798 static int dln2_spi_suspend(struct device *dev) 799 { 800 int ret; 801 struct spi_master *master = dev_get_drvdata(dev); 802 struct dln2_spi *dln2 = spi_master_get_devdata(master); 803 804 ret = spi_master_suspend(master); 805 if (ret < 0) 806 return ret; 807 808 if (!pm_runtime_suspended(dev)) { 809 ret = dln2_spi_enable(dln2, false); 810 if (ret < 0) 811 return ret; 812 } 813 814 /* 815 * USB power may be cut off during sleep. Resetting the following 816 * parameters will force the board to be set up before first transfer. 817 */ 818 dln2->cs = 0xff; 819 dln2->speed = 0; 820 dln2->bpw = 0; 821 dln2->mode = 0xff; 822 823 return 0; 824 } 825 826 static int dln2_spi_resume(struct device *dev) 827 { 828 int ret; 829 struct spi_master *master = dev_get_drvdata(dev); 830 struct dln2_spi *dln2 = spi_master_get_devdata(master); 831 832 if (!pm_runtime_suspended(dev)) { 833 ret = dln2_spi_cs_enable_all(dln2, true); 834 if (ret < 0) 835 return ret; 836 837 ret = dln2_spi_enable(dln2, true); 838 if (ret < 0) 839 return ret; 840 } 841 842 return spi_master_resume(master); 843 } 844 #endif /* CONFIG_PM_SLEEP */ 845 846 #ifdef CONFIG_PM 847 static int dln2_spi_runtime_suspend(struct device *dev) 848 { 849 struct spi_master *master = dev_get_drvdata(dev); 850 struct dln2_spi *dln2 = spi_master_get_devdata(master); 851 852 return dln2_spi_enable(dln2, false); 853 } 854 855 static int dln2_spi_runtime_resume(struct device *dev) 856 { 857 struct spi_master *master = dev_get_drvdata(dev); 858 struct dln2_spi *dln2 = spi_master_get_devdata(master); 859 860 return dln2_spi_enable(dln2, true); 861 } 862 #endif /* CONFIG_PM */ 863 864 static const struct dev_pm_ops dln2_spi_pm = { 865 SET_SYSTEM_SLEEP_PM_OPS(dln2_spi_suspend, dln2_spi_resume) 866 SET_RUNTIME_PM_OPS(dln2_spi_runtime_suspend, 867 dln2_spi_runtime_resume, NULL) 868 }; 869 870 static struct platform_driver spi_dln2_driver = { 871 .driver = { 872 .name = "dln2-spi", 873 .pm = &dln2_spi_pm, 874 }, 875 .probe = dln2_spi_probe, 876 .remove = dln2_spi_remove, 877 }; 878 module_platform_driver(spi_dln2_driver); 879 880 MODULE_DESCRIPTION("Driver for the Diolan DLN2 SPI master interface"); 881 MODULE_AUTHOR("Laurentiu Palcu <laurentiu.palcu@intel.com>"); 882 MODULE_LICENSE("GPL v2"); 883 MODULE_ALIAS("platform:dln2-spi"); 884