xref: /openbmc/linux/drivers/spi/spi-davinci.c (revision d58f75de)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (C) 2009 Texas Instruments.
4  * Copyright (C) 2010 EF Johnson Technologies
5  */
6 
7 #include <linux/interrupt.h>
8 #include <linux/io.h>
9 #include <linux/gpio/consumer.h>
10 #include <linux/module.h>
11 #include <linux/delay.h>
12 #include <linux/platform_device.h>
13 #include <linux/err.h>
14 #include <linux/clk.h>
15 #include <linux/dmaengine.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/of.h>
18 #include <linux/of_device.h>
19 #include <linux/spi/spi.h>
20 #include <linux/spi/spi_bitbang.h>
21 #include <linux/slab.h>
22 
23 #include <linux/platform_data/spi-davinci.h>
24 
25 #define CS_DEFAULT	0xFF
26 
27 #define SPIFMT_PHASE_MASK	BIT(16)
28 #define SPIFMT_POLARITY_MASK	BIT(17)
29 #define SPIFMT_DISTIMER_MASK	BIT(18)
30 #define SPIFMT_SHIFTDIR_MASK	BIT(20)
31 #define SPIFMT_WAITENA_MASK	BIT(21)
32 #define SPIFMT_PARITYENA_MASK	BIT(22)
33 #define SPIFMT_ODD_PARITY_MASK	BIT(23)
34 #define SPIFMT_WDELAY_MASK	0x3f000000u
35 #define SPIFMT_WDELAY_SHIFT	24
36 #define SPIFMT_PRESCALE_SHIFT	8
37 
38 /* SPIPC0 */
39 #define SPIPC0_DIFUN_MASK	BIT(11)		/* MISO */
40 #define SPIPC0_DOFUN_MASK	BIT(10)		/* MOSI */
41 #define SPIPC0_CLKFUN_MASK	BIT(9)		/* CLK */
42 #define SPIPC0_SPIENA_MASK	BIT(8)		/* nREADY */
43 
44 #define SPIINT_MASKALL		0x0101035F
45 #define SPIINT_MASKINT		0x0000015F
46 #define SPI_INTLVL_1		0x000001FF
47 #define SPI_INTLVL_0		0x00000000
48 
49 /* SPIDAT1 (upper 16 bit defines) */
50 #define SPIDAT1_CSHOLD_MASK	BIT(12)
51 #define SPIDAT1_WDEL		BIT(10)
52 
53 /* SPIGCR1 */
54 #define SPIGCR1_CLKMOD_MASK	BIT(1)
55 #define SPIGCR1_MASTER_MASK     BIT(0)
56 #define SPIGCR1_POWERDOWN_MASK	BIT(8)
57 #define SPIGCR1_LOOPBACK_MASK	BIT(16)
58 #define SPIGCR1_SPIENA_MASK	BIT(24)
59 
60 /* SPIBUF */
61 #define SPIBUF_TXFULL_MASK	BIT(29)
62 #define SPIBUF_RXEMPTY_MASK	BIT(31)
63 
64 /* SPIDELAY */
65 #define SPIDELAY_C2TDELAY_SHIFT 24
66 #define SPIDELAY_C2TDELAY_MASK  (0xFF << SPIDELAY_C2TDELAY_SHIFT)
67 #define SPIDELAY_T2CDELAY_SHIFT 16
68 #define SPIDELAY_T2CDELAY_MASK  (0xFF << SPIDELAY_T2CDELAY_SHIFT)
69 #define SPIDELAY_T2EDELAY_SHIFT 8
70 #define SPIDELAY_T2EDELAY_MASK  (0xFF << SPIDELAY_T2EDELAY_SHIFT)
71 #define SPIDELAY_C2EDELAY_SHIFT 0
72 #define SPIDELAY_C2EDELAY_MASK  0xFF
73 
74 /* Error Masks */
75 #define SPIFLG_DLEN_ERR_MASK		BIT(0)
76 #define SPIFLG_TIMEOUT_MASK		BIT(1)
77 #define SPIFLG_PARERR_MASK		BIT(2)
78 #define SPIFLG_DESYNC_MASK		BIT(3)
79 #define SPIFLG_BITERR_MASK		BIT(4)
80 #define SPIFLG_OVRRUN_MASK		BIT(6)
81 #define SPIFLG_BUF_INIT_ACTIVE_MASK	BIT(24)
82 #define SPIFLG_ERROR_MASK		(SPIFLG_DLEN_ERR_MASK \
83 				| SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
84 				| SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
85 				| SPIFLG_OVRRUN_MASK)
86 
87 #define SPIINT_DMA_REQ_EN	BIT(16)
88 
89 /* SPI Controller registers */
90 #define SPIGCR0		0x00
91 #define SPIGCR1		0x04
92 #define SPIINT		0x08
93 #define SPILVL		0x0c
94 #define SPIFLG		0x10
95 #define SPIPC0		0x14
96 #define SPIDAT1		0x3c
97 #define SPIBUF		0x40
98 #define SPIDELAY	0x48
99 #define SPIDEF		0x4c
100 #define SPIFMT0		0x50
101 
102 #define DMA_MIN_BYTES	16
103 
104 /* SPI Controller driver's private data. */
105 struct davinci_spi {
106 	struct spi_bitbang	bitbang;
107 	struct clk		*clk;
108 
109 	u8			version;
110 	resource_size_t		pbase;
111 	void __iomem		*base;
112 	u32			irq;
113 	struct completion	done;
114 
115 	const void		*tx;
116 	void			*rx;
117 	int			rcount;
118 	int			wcount;
119 
120 	struct dma_chan		*dma_rx;
121 	struct dma_chan		*dma_tx;
122 
123 	struct davinci_spi_platform_data pdata;
124 
125 	void			(*get_rx)(u32 rx_data, struct davinci_spi *);
126 	u32			(*get_tx)(struct davinci_spi *);
127 
128 	u8			*bytes_per_word;
129 
130 	u8			prescaler_limit;
131 };
132 
133 static struct davinci_spi_config davinci_spi_default_cfg;
134 
135 static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi)
136 {
137 	if (dspi->rx) {
138 		u8 *rx = dspi->rx;
139 		*rx++ = (u8)data;
140 		dspi->rx = rx;
141 	}
142 }
143 
144 static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi)
145 {
146 	if (dspi->rx) {
147 		u16 *rx = dspi->rx;
148 		*rx++ = (u16)data;
149 		dspi->rx = rx;
150 	}
151 }
152 
153 static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)
154 {
155 	u32 data = 0;
156 
157 	if (dspi->tx) {
158 		const u8 *tx = dspi->tx;
159 
160 		data = *tx++;
161 		dspi->tx = tx;
162 	}
163 	return data;
164 }
165 
166 static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi)
167 {
168 	u32 data = 0;
169 
170 	if (dspi->tx) {
171 		const u16 *tx = dspi->tx;
172 
173 		data = *tx++;
174 		dspi->tx = tx;
175 	}
176 	return data;
177 }
178 
179 static inline void set_io_bits(void __iomem *addr, u32 bits)
180 {
181 	u32 v = ioread32(addr);
182 
183 	v |= bits;
184 	iowrite32(v, addr);
185 }
186 
187 static inline void clear_io_bits(void __iomem *addr, u32 bits)
188 {
189 	u32 v = ioread32(addr);
190 
191 	v &= ~bits;
192 	iowrite32(v, addr);
193 }
194 
195 /*
196  * Interface to control the chip select signal
197  */
198 static void davinci_spi_chipselect(struct spi_device *spi, int value)
199 {
200 	struct davinci_spi *dspi;
201 	struct davinci_spi_config *spicfg = spi->controller_data;
202 	u8 chip_sel = spi->chip_select;
203 	u16 spidat1 = CS_DEFAULT;
204 
205 	dspi = spi_master_get_devdata(spi->master);
206 
207 	/* program delay transfers if tx_delay is non zero */
208 	if (spicfg && spicfg->wdelay)
209 		spidat1 |= SPIDAT1_WDEL;
210 
211 	/*
212 	 * Board specific chip select logic decides the polarity and cs
213 	 * line for the controller
214 	 */
215 	if (spi->cs_gpiod) {
216 		/*
217 		 * FIXME: is this code ever executed? This host does not
218 		 * set SPI_MASTER_GPIO_SS so this chipselect callback should
219 		 * not get called from the SPI core when we are using
220 		 * GPIOs for chip select.
221 		 */
222 		if (value == BITBANG_CS_ACTIVE)
223 			gpiod_set_value(spi->cs_gpiod, 1);
224 		else
225 			gpiod_set_value(spi->cs_gpiod, 0);
226 	} else {
227 		if (value == BITBANG_CS_ACTIVE) {
228 			if (!(spi->mode & SPI_CS_WORD))
229 				spidat1 |= SPIDAT1_CSHOLD_MASK;
230 			spidat1 &= ~(0x1 << chip_sel);
231 		}
232 	}
233 
234 	iowrite16(spidat1, dspi->base + SPIDAT1 + 2);
235 }
236 
237 /**
238  * davinci_spi_get_prescale - Calculates the correct prescale value
239  * @dspi: the controller data
240  * @max_speed_hz: the maximum rate the SPI clock can run at
241  *
242  * This function calculates the prescale value that generates a clock rate
243  * less than or equal to the specified maximum.
244  *
245  * Returns: calculated prescale value for easy programming into SPI registers
246  * or negative error number if valid prescalar cannot be updated.
247  */
248 static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
249 							u32 max_speed_hz)
250 {
251 	int ret;
252 
253 	/* Subtract 1 to match what will be programmed into SPI register. */
254 	ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz) - 1;
255 
256 	if (ret < dspi->prescaler_limit || ret > 255)
257 		return -EINVAL;
258 
259 	return ret;
260 }
261 
262 /**
263  * davinci_spi_setup_transfer - This functions will determine transfer method
264  * @spi: spi device on which data transfer to be done
265  * @t: spi transfer in which transfer info is filled
266  *
267  * This function determines data transfer method (8/16/32 bit transfer).
268  * It will also set the SPI Clock Control register according to
269  * SPI slave device freq.
270  */
271 static int davinci_spi_setup_transfer(struct spi_device *spi,
272 		struct spi_transfer *t)
273 {
274 
275 	struct davinci_spi *dspi;
276 	struct davinci_spi_config *spicfg;
277 	u8 bits_per_word = 0;
278 	u32 hz = 0, spifmt = 0;
279 	int prescale;
280 
281 	dspi = spi_master_get_devdata(spi->master);
282 	spicfg = spi->controller_data;
283 	if (!spicfg)
284 		spicfg = &davinci_spi_default_cfg;
285 
286 	if (t) {
287 		bits_per_word = t->bits_per_word;
288 		hz = t->speed_hz;
289 	}
290 
291 	/* if bits_per_word is not set then set it default */
292 	if (!bits_per_word)
293 		bits_per_word = spi->bits_per_word;
294 
295 	/*
296 	 * Assign function pointer to appropriate transfer method
297 	 * 8bit, 16bit or 32bit transfer
298 	 */
299 	if (bits_per_word <= 8) {
300 		dspi->get_rx = davinci_spi_rx_buf_u8;
301 		dspi->get_tx = davinci_spi_tx_buf_u8;
302 		dspi->bytes_per_word[spi->chip_select] = 1;
303 	} else {
304 		dspi->get_rx = davinci_spi_rx_buf_u16;
305 		dspi->get_tx = davinci_spi_tx_buf_u16;
306 		dspi->bytes_per_word[spi->chip_select] = 2;
307 	}
308 
309 	if (!hz)
310 		hz = spi->max_speed_hz;
311 
312 	/* Set up SPIFMTn register, unique to this chipselect. */
313 
314 	prescale = davinci_spi_get_prescale(dspi, hz);
315 	if (prescale < 0)
316 		return prescale;
317 
318 	spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);
319 
320 	if (spi->mode & SPI_LSB_FIRST)
321 		spifmt |= SPIFMT_SHIFTDIR_MASK;
322 
323 	if (spi->mode & SPI_CPOL)
324 		spifmt |= SPIFMT_POLARITY_MASK;
325 
326 	if (!(spi->mode & SPI_CPHA))
327 		spifmt |= SPIFMT_PHASE_MASK;
328 
329 	/*
330 	* Assume wdelay is used only on SPI peripherals that has this field
331 	* in SPIFMTn register and when it's configured from board file or DT.
332 	*/
333 	if (spicfg->wdelay)
334 		spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
335 				& SPIFMT_WDELAY_MASK);
336 
337 	/*
338 	 * Version 1 hardware supports two basic SPI modes:
339 	 *  - Standard SPI mode uses 4 pins, with chipselect
340 	 *  - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
341 	 *	(distinct from SPI_3WIRE, with just one data wire;
342 	 *	or similar variants without MOSI or without MISO)
343 	 *
344 	 * Version 2 hardware supports an optional handshaking signal,
345 	 * so it can support two more modes:
346 	 *  - 5 pin SPI variant is standard SPI plus SPI_READY
347 	 *  - 4 pin with enable is (SPI_READY | SPI_NO_CS)
348 	 */
349 
350 	if (dspi->version == SPI_VERSION_2) {
351 
352 		u32 delay = 0;
353 
354 		if (spicfg->odd_parity)
355 			spifmt |= SPIFMT_ODD_PARITY_MASK;
356 
357 		if (spicfg->parity_enable)
358 			spifmt |= SPIFMT_PARITYENA_MASK;
359 
360 		if (spicfg->timer_disable) {
361 			spifmt |= SPIFMT_DISTIMER_MASK;
362 		} else {
363 			delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)
364 						& SPIDELAY_C2TDELAY_MASK;
365 			delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)
366 						& SPIDELAY_T2CDELAY_MASK;
367 		}
368 
369 		if (spi->mode & SPI_READY) {
370 			spifmt |= SPIFMT_WAITENA_MASK;
371 			delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)
372 						& SPIDELAY_T2EDELAY_MASK;
373 			delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)
374 						& SPIDELAY_C2EDELAY_MASK;
375 		}
376 
377 		iowrite32(delay, dspi->base + SPIDELAY);
378 	}
379 
380 	iowrite32(spifmt, dspi->base + SPIFMT0);
381 
382 	return 0;
383 }
384 
385 static int davinci_spi_of_setup(struct spi_device *spi)
386 {
387 	struct davinci_spi_config *spicfg = spi->controller_data;
388 	struct device_node *np = spi->dev.of_node;
389 	struct davinci_spi *dspi = spi_master_get_devdata(spi->master);
390 	u32 prop;
391 
392 	if (spicfg == NULL && np) {
393 		spicfg = kzalloc(sizeof(*spicfg), GFP_KERNEL);
394 		if (!spicfg)
395 			return -ENOMEM;
396 		*spicfg = davinci_spi_default_cfg;
397 		/* override with dt configured values */
398 		if (!of_property_read_u32(np, "ti,spi-wdelay", &prop))
399 			spicfg->wdelay = (u8)prop;
400 		spi->controller_data = spicfg;
401 
402 		if (dspi->dma_rx && dspi->dma_tx)
403 			spicfg->io_type = SPI_IO_TYPE_DMA;
404 	}
405 
406 	return 0;
407 }
408 
409 /**
410  * davinci_spi_setup - This functions will set default transfer method
411  * @spi: spi device on which data transfer to be done
412  *
413  * This functions sets the default transfer method.
414  */
415 static int davinci_spi_setup(struct spi_device *spi)
416 {
417 	struct davinci_spi *dspi;
418 	struct device_node *np = spi->dev.of_node;
419 	bool internal_cs = true;
420 
421 	dspi = spi_master_get_devdata(spi->master);
422 
423 	if (!(spi->mode & SPI_NO_CS)) {
424 		if (np && spi->cs_gpiod)
425 			internal_cs = false;
426 
427 		if (internal_cs)
428 			set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
429 	}
430 
431 	if (spi->mode & SPI_READY)
432 		set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
433 
434 	if (spi->mode & SPI_LOOP)
435 		set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
436 	else
437 		clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
438 
439 	return davinci_spi_of_setup(spi);
440 }
441 
442 static void davinci_spi_cleanup(struct spi_device *spi)
443 {
444 	struct davinci_spi_config *spicfg = spi->controller_data;
445 
446 	spi->controller_data = NULL;
447 	if (spi->dev.of_node)
448 		kfree(spicfg);
449 }
450 
451 static bool davinci_spi_can_dma(struct spi_master *master,
452 				struct spi_device *spi,
453 				struct spi_transfer *xfer)
454 {
455 	struct davinci_spi_config *spicfg = spi->controller_data;
456 	bool can_dma = false;
457 
458 	if (spicfg)
459 		can_dma = (spicfg->io_type == SPI_IO_TYPE_DMA) &&
460 			(xfer->len >= DMA_MIN_BYTES) &&
461 			!is_vmalloc_addr(xfer->rx_buf) &&
462 			!is_vmalloc_addr(xfer->tx_buf);
463 
464 	return can_dma;
465 }
466 
467 static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
468 {
469 	struct device *sdev = dspi->bitbang.master->dev.parent;
470 
471 	if (int_status & SPIFLG_TIMEOUT_MASK) {
472 		dev_err(sdev, "SPI Time-out Error\n");
473 		return -ETIMEDOUT;
474 	}
475 	if (int_status & SPIFLG_DESYNC_MASK) {
476 		dev_err(sdev, "SPI Desynchronization Error\n");
477 		return -EIO;
478 	}
479 	if (int_status & SPIFLG_BITERR_MASK) {
480 		dev_err(sdev, "SPI Bit error\n");
481 		return -EIO;
482 	}
483 
484 	if (dspi->version == SPI_VERSION_2) {
485 		if (int_status & SPIFLG_DLEN_ERR_MASK) {
486 			dev_err(sdev, "SPI Data Length Error\n");
487 			return -EIO;
488 		}
489 		if (int_status & SPIFLG_PARERR_MASK) {
490 			dev_err(sdev, "SPI Parity Error\n");
491 			return -EIO;
492 		}
493 		if (int_status & SPIFLG_OVRRUN_MASK) {
494 			dev_err(sdev, "SPI Data Overrun error\n");
495 			return -EIO;
496 		}
497 		if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
498 			dev_err(sdev, "SPI Buffer Init Active\n");
499 			return -EBUSY;
500 		}
501 	}
502 
503 	return 0;
504 }
505 
506 /**
507  * davinci_spi_process_events - check for and handle any SPI controller events
508  * @dspi: the controller data
509  *
510  * This function will check the SPIFLG register and handle any events that are
511  * detected there
512  */
513 static int davinci_spi_process_events(struct davinci_spi *dspi)
514 {
515 	u32 buf, status, errors = 0, spidat1;
516 
517 	buf = ioread32(dspi->base + SPIBUF);
518 
519 	if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
520 		dspi->get_rx(buf & 0xFFFF, dspi);
521 		dspi->rcount--;
522 	}
523 
524 	status = ioread32(dspi->base + SPIFLG);
525 
526 	if (unlikely(status & SPIFLG_ERROR_MASK)) {
527 		errors = status & SPIFLG_ERROR_MASK;
528 		goto out;
529 	}
530 
531 	if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
532 		spidat1 = ioread32(dspi->base + SPIDAT1);
533 		dspi->wcount--;
534 		spidat1 &= ~0xFFFF;
535 		spidat1 |= 0xFFFF & dspi->get_tx(dspi);
536 		iowrite32(spidat1, dspi->base + SPIDAT1);
537 	}
538 
539 out:
540 	return errors;
541 }
542 
543 static void davinci_spi_dma_rx_callback(void *data)
544 {
545 	struct davinci_spi *dspi = (struct davinci_spi *)data;
546 
547 	dspi->rcount = 0;
548 
549 	if (!dspi->wcount && !dspi->rcount)
550 		complete(&dspi->done);
551 }
552 
553 static void davinci_spi_dma_tx_callback(void *data)
554 {
555 	struct davinci_spi *dspi = (struct davinci_spi *)data;
556 
557 	dspi->wcount = 0;
558 
559 	if (!dspi->wcount && !dspi->rcount)
560 		complete(&dspi->done);
561 }
562 
563 /**
564  * davinci_spi_bufs - functions which will handle transfer data
565  * @spi: spi device on which data transfer to be done
566  * @t: spi transfer in which transfer info is filled
567  *
568  * This function will put data to be transferred into data register
569  * of SPI controller and then wait until the completion will be marked
570  * by the IRQ Handler.
571  */
572 static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
573 {
574 	struct davinci_spi *dspi;
575 	int data_type, ret = -ENOMEM;
576 	u32 tx_data, spidat1;
577 	u32 errors = 0;
578 	struct davinci_spi_config *spicfg;
579 	struct davinci_spi_platform_data *pdata;
580 
581 	dspi = spi_master_get_devdata(spi->master);
582 	pdata = &dspi->pdata;
583 	spicfg = (struct davinci_spi_config *)spi->controller_data;
584 	if (!spicfg)
585 		spicfg = &davinci_spi_default_cfg;
586 
587 	/* convert len to words based on bits_per_word */
588 	data_type = dspi->bytes_per_word[spi->chip_select];
589 
590 	dspi->tx = t->tx_buf;
591 	dspi->rx = t->rx_buf;
592 	dspi->wcount = t->len / data_type;
593 	dspi->rcount = dspi->wcount;
594 
595 	spidat1 = ioread32(dspi->base + SPIDAT1);
596 
597 	clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
598 	set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
599 
600 	reinit_completion(&dspi->done);
601 
602 	if (!davinci_spi_can_dma(spi->master, spi, t)) {
603 		if (spicfg->io_type != SPI_IO_TYPE_POLL)
604 			set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
605 		/* start the transfer */
606 		dspi->wcount--;
607 		tx_data = dspi->get_tx(dspi);
608 		spidat1 &= 0xFFFF0000;
609 		spidat1 |= tx_data & 0xFFFF;
610 		iowrite32(spidat1, dspi->base + SPIDAT1);
611 	} else {
612 		struct dma_slave_config dma_rx_conf = {
613 			.direction = DMA_DEV_TO_MEM,
614 			.src_addr = (unsigned long)dspi->pbase + SPIBUF,
615 			.src_addr_width = data_type,
616 			.src_maxburst = 1,
617 		};
618 		struct dma_slave_config dma_tx_conf = {
619 			.direction = DMA_MEM_TO_DEV,
620 			.dst_addr = (unsigned long)dspi->pbase + SPIDAT1,
621 			.dst_addr_width = data_type,
622 			.dst_maxburst = 1,
623 		};
624 		struct dma_async_tx_descriptor *rxdesc;
625 		struct dma_async_tx_descriptor *txdesc;
626 
627 		dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf);
628 		dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf);
629 
630 		rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx,
631 				t->rx_sg.sgl, t->rx_sg.nents, DMA_DEV_TO_MEM,
632 				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
633 		if (!rxdesc)
634 			goto err_desc;
635 
636 		if (!t->tx_buf) {
637 			/* To avoid errors when doing rx-only transfers with
638 			 * many SG entries (> 20), use the rx buffer as the
639 			 * dummy tx buffer so that dma reloads are done at the
640 			 * same time for rx and tx.
641 			 */
642 			t->tx_sg.sgl = t->rx_sg.sgl;
643 			t->tx_sg.nents = t->rx_sg.nents;
644 		}
645 
646 		txdesc = dmaengine_prep_slave_sg(dspi->dma_tx,
647 				t->tx_sg.sgl, t->tx_sg.nents, DMA_MEM_TO_DEV,
648 				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
649 		if (!txdesc)
650 			goto err_desc;
651 
652 		rxdesc->callback = davinci_spi_dma_rx_callback;
653 		rxdesc->callback_param = (void *)dspi;
654 		txdesc->callback = davinci_spi_dma_tx_callback;
655 		txdesc->callback_param = (void *)dspi;
656 
657 		if (pdata->cshold_bug)
658 			iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
659 
660 		dmaengine_submit(rxdesc);
661 		dmaengine_submit(txdesc);
662 
663 		dma_async_issue_pending(dspi->dma_rx);
664 		dma_async_issue_pending(dspi->dma_tx);
665 
666 		set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
667 	}
668 
669 	/* Wait for the transfer to complete */
670 	if (spicfg->io_type != SPI_IO_TYPE_POLL) {
671 		if (wait_for_completion_timeout(&dspi->done, HZ) == 0)
672 			errors = SPIFLG_TIMEOUT_MASK;
673 	} else {
674 		while (dspi->rcount > 0 || dspi->wcount > 0) {
675 			errors = davinci_spi_process_events(dspi);
676 			if (errors)
677 				break;
678 			cpu_relax();
679 		}
680 	}
681 
682 	clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
683 	if (davinci_spi_can_dma(spi->master, spi, t))
684 		clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
685 
686 	clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
687 	set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
688 
689 	/*
690 	 * Check for bit error, desync error,parity error,timeout error and
691 	 * receive overflow errors
692 	 */
693 	if (errors) {
694 		ret = davinci_spi_check_error(dspi, errors);
695 		WARN(!ret, "%s: error reported but no error found!\n",
696 							dev_name(&spi->dev));
697 		return ret;
698 	}
699 
700 	if (dspi->rcount != 0 || dspi->wcount != 0) {
701 		dev_err(&spi->dev, "SPI data transfer error\n");
702 		return -EIO;
703 	}
704 
705 	return t->len;
706 
707 err_desc:
708 	return ret;
709 }
710 
711 /**
712  * dummy_thread_fn - dummy thread function
713  * @irq: IRQ number for this SPI Master
714  * @data: structure for SPI Master controller davinci_spi
715  *
716  * This is to satisfy the request_threaded_irq() API so that the irq
717  * handler is called in interrupt context.
718  */
719 static irqreturn_t dummy_thread_fn(s32 irq, void *data)
720 {
721 	return IRQ_HANDLED;
722 }
723 
724 /**
725  * davinci_spi_irq - Interrupt handler for SPI Master Controller
726  * @irq: IRQ number for this SPI Master
727  * @data: structure for SPI Master controller davinci_spi
728  *
729  * ISR will determine that interrupt arrives either for READ or WRITE command.
730  * According to command it will do the appropriate action. It will check
731  * transfer length and if it is not zero then dispatch transfer command again.
732  * If transfer length is zero then it will indicate the COMPLETION so that
733  * davinci_spi_bufs function can go ahead.
734  */
735 static irqreturn_t davinci_spi_irq(s32 irq, void *data)
736 {
737 	struct davinci_spi *dspi = data;
738 	int status;
739 
740 	status = davinci_spi_process_events(dspi);
741 	if (unlikely(status != 0))
742 		clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
743 
744 	if ((!dspi->rcount && !dspi->wcount) || status)
745 		complete(&dspi->done);
746 
747 	return IRQ_HANDLED;
748 }
749 
750 static int davinci_spi_request_dma(struct davinci_spi *dspi)
751 {
752 	struct device *sdev = dspi->bitbang.master->dev.parent;
753 
754 	dspi->dma_rx = dma_request_chan(sdev, "rx");
755 	if (IS_ERR(dspi->dma_rx))
756 		return PTR_ERR(dspi->dma_rx);
757 
758 	dspi->dma_tx = dma_request_chan(sdev, "tx");
759 	if (IS_ERR(dspi->dma_tx)) {
760 		dma_release_channel(dspi->dma_rx);
761 		return PTR_ERR(dspi->dma_tx);
762 	}
763 
764 	return 0;
765 }
766 
767 #if defined(CONFIG_OF)
768 
769 /* OF SPI data structure */
770 struct davinci_spi_of_data {
771 	u8	version;
772 	u8	prescaler_limit;
773 };
774 
775 static const struct davinci_spi_of_data dm6441_spi_data = {
776 	.version = SPI_VERSION_1,
777 	.prescaler_limit = 2,
778 };
779 
780 static const struct davinci_spi_of_data da830_spi_data = {
781 	.version = SPI_VERSION_2,
782 	.prescaler_limit = 2,
783 };
784 
785 static const struct davinci_spi_of_data keystone_spi_data = {
786 	.version = SPI_VERSION_1,
787 	.prescaler_limit = 0,
788 };
789 
790 static const struct of_device_id davinci_spi_of_match[] = {
791 	{
792 		.compatible = "ti,dm6441-spi",
793 		.data = &dm6441_spi_data,
794 	},
795 	{
796 		.compatible = "ti,da830-spi",
797 		.data = &da830_spi_data,
798 	},
799 	{
800 		.compatible = "ti,keystone-spi",
801 		.data = &keystone_spi_data,
802 	},
803 	{ },
804 };
805 MODULE_DEVICE_TABLE(of, davinci_spi_of_match);
806 
807 /**
808  * spi_davinci_get_pdata - Get platform data from DTS binding
809  * @pdev: ptr to platform data
810  * @dspi: ptr to driver data
811  *
812  * Parses and populates pdata in dspi from device tree bindings.
813  *
814  * NOTE: Not all platform data params are supported currently.
815  */
816 static int spi_davinci_get_pdata(struct platform_device *pdev,
817 			struct davinci_spi *dspi)
818 {
819 	struct device_node *node = pdev->dev.of_node;
820 	const struct davinci_spi_of_data *spi_data;
821 	struct davinci_spi_platform_data *pdata;
822 	unsigned int num_cs, intr_line = 0;
823 
824 	pdata = &dspi->pdata;
825 
826 	spi_data = device_get_match_data(&pdev->dev);
827 
828 	pdata->version = spi_data->version;
829 	pdata->prescaler_limit = spi_data->prescaler_limit;
830 	/*
831 	 * default num_cs is 1 and all chipsel are internal to the chip
832 	 * indicated by chip_sel being NULL or cs_gpios being NULL or
833 	 * set to -ENOENT. num-cs includes internal as well as gpios.
834 	 * indicated by chip_sel being NULL. GPIO based CS is not
835 	 * supported yet in DT bindings.
836 	 */
837 	num_cs = 1;
838 	of_property_read_u32(node, "num-cs", &num_cs);
839 	pdata->num_chipselect = num_cs;
840 	of_property_read_u32(node, "ti,davinci-spi-intr-line", &intr_line);
841 	pdata->intr_line = intr_line;
842 	return 0;
843 }
844 #else
845 static int spi_davinci_get_pdata(struct platform_device *pdev,
846 			struct davinci_spi *dspi)
847 {
848 	return -ENODEV;
849 }
850 #endif
851 
852 /**
853  * davinci_spi_probe - probe function for SPI Master Controller
854  * @pdev: platform_device structure which contains plateform specific data
855  *
856  * According to Linux Device Model this function will be invoked by Linux
857  * with platform_device struct which contains the device specific info.
858  * This function will map the SPI controller's memory, register IRQ,
859  * Reset SPI controller and setting its registers to default value.
860  * It will invoke spi_bitbang_start to create work queue so that client driver
861  * can register transfer method to work queue.
862  */
863 static int davinci_spi_probe(struct platform_device *pdev)
864 {
865 	struct spi_master *master;
866 	struct davinci_spi *dspi;
867 	struct davinci_spi_platform_data *pdata;
868 	struct resource *r;
869 	int ret = 0;
870 	u32 spipc0;
871 
872 	master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
873 	if (master == NULL) {
874 		ret = -ENOMEM;
875 		goto err;
876 	}
877 
878 	platform_set_drvdata(pdev, master);
879 
880 	dspi = spi_master_get_devdata(master);
881 
882 	if (dev_get_platdata(&pdev->dev)) {
883 		pdata = dev_get_platdata(&pdev->dev);
884 		dspi->pdata = *pdata;
885 	} else {
886 		/* update dspi pdata with that from the DT */
887 		ret = spi_davinci_get_pdata(pdev, dspi);
888 		if (ret < 0)
889 			goto free_master;
890 	}
891 
892 	/* pdata in dspi is now updated and point pdata to that */
893 	pdata = &dspi->pdata;
894 
895 	dspi->bytes_per_word = devm_kcalloc(&pdev->dev,
896 					    pdata->num_chipselect,
897 					    sizeof(*dspi->bytes_per_word),
898 					    GFP_KERNEL);
899 	if (dspi->bytes_per_word == NULL) {
900 		ret = -ENOMEM;
901 		goto free_master;
902 	}
903 
904 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
905 	if (r == NULL) {
906 		ret = -ENOENT;
907 		goto free_master;
908 	}
909 
910 	dspi->pbase = r->start;
911 
912 	dspi->base = devm_ioremap_resource(&pdev->dev, r);
913 	if (IS_ERR(dspi->base)) {
914 		ret = PTR_ERR(dspi->base);
915 		goto free_master;
916 	}
917 
918 	init_completion(&dspi->done);
919 
920 	ret = platform_get_irq(pdev, 0);
921 	if (ret == 0)
922 		ret = -EINVAL;
923 	if (ret < 0)
924 		goto free_master;
925 	dspi->irq = ret;
926 
927 	ret = devm_request_threaded_irq(&pdev->dev, dspi->irq, davinci_spi_irq,
928 				dummy_thread_fn, 0, dev_name(&pdev->dev), dspi);
929 	if (ret)
930 		goto free_master;
931 
932 	dspi->bitbang.master = master;
933 
934 	dspi->clk = devm_clk_get(&pdev->dev, NULL);
935 	if (IS_ERR(dspi->clk)) {
936 		ret = -ENODEV;
937 		goto free_master;
938 	}
939 	ret = clk_prepare_enable(dspi->clk);
940 	if (ret)
941 		goto free_master;
942 
943 	master->use_gpio_descriptors = true;
944 	master->dev.of_node = pdev->dev.of_node;
945 	master->bus_num = pdev->id;
946 	master->num_chipselect = pdata->num_chipselect;
947 	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16);
948 	master->flags = SPI_MASTER_MUST_RX;
949 	master->setup = davinci_spi_setup;
950 	master->cleanup = davinci_spi_cleanup;
951 	master->can_dma = davinci_spi_can_dma;
952 
953 	dspi->bitbang.chipselect = davinci_spi_chipselect;
954 	dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;
955 	dspi->prescaler_limit = pdata->prescaler_limit;
956 	dspi->version = pdata->version;
957 
958 	dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_WORD;
959 	if (dspi->version == SPI_VERSION_2)
960 		dspi->bitbang.flags |= SPI_READY;
961 
962 	dspi->bitbang.txrx_bufs = davinci_spi_bufs;
963 
964 	ret = davinci_spi_request_dma(dspi);
965 	if (ret == -EPROBE_DEFER) {
966 		goto free_clk;
967 	} else if (ret) {
968 		dev_info(&pdev->dev, "DMA is not supported (%d)\n", ret);
969 		dspi->dma_rx = NULL;
970 		dspi->dma_tx = NULL;
971 	}
972 
973 	dspi->get_rx = davinci_spi_rx_buf_u8;
974 	dspi->get_tx = davinci_spi_tx_buf_u8;
975 
976 	/* Reset In/OUT SPI module */
977 	iowrite32(0, dspi->base + SPIGCR0);
978 	udelay(100);
979 	iowrite32(1, dspi->base + SPIGCR0);
980 
981 	/* Set up SPIPC0.  CS and ENA init is done in davinci_spi_setup */
982 	spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
983 	iowrite32(spipc0, dspi->base + SPIPC0);
984 
985 	if (pdata->intr_line)
986 		iowrite32(SPI_INTLVL_1, dspi->base + SPILVL);
987 	else
988 		iowrite32(SPI_INTLVL_0, dspi->base + SPILVL);
989 
990 	iowrite32(CS_DEFAULT, dspi->base + SPIDEF);
991 
992 	/* master mode default */
993 	set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);
994 	set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
995 	set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
996 
997 	ret = spi_bitbang_start(&dspi->bitbang);
998 	if (ret)
999 		goto free_dma;
1000 
1001 	dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base);
1002 
1003 	return ret;
1004 
1005 free_dma:
1006 	if (dspi->dma_rx) {
1007 		dma_release_channel(dspi->dma_rx);
1008 		dma_release_channel(dspi->dma_tx);
1009 	}
1010 free_clk:
1011 	clk_disable_unprepare(dspi->clk);
1012 free_master:
1013 	spi_master_put(master);
1014 err:
1015 	return ret;
1016 }
1017 
1018 /**
1019  * davinci_spi_remove - remove function for SPI Master Controller
1020  * @pdev: platform_device structure which contains plateform specific data
1021  *
1022  * This function will do the reverse action of davinci_spi_probe function
1023  * It will free the IRQ and SPI controller's memory region.
1024  * It will also call spi_bitbang_stop to destroy the work queue which was
1025  * created by spi_bitbang_start.
1026  */
1027 static int davinci_spi_remove(struct platform_device *pdev)
1028 {
1029 	struct davinci_spi *dspi;
1030 	struct spi_master *master;
1031 
1032 	master = platform_get_drvdata(pdev);
1033 	dspi = spi_master_get_devdata(master);
1034 
1035 	spi_bitbang_stop(&dspi->bitbang);
1036 
1037 	clk_disable_unprepare(dspi->clk);
1038 
1039 	if (dspi->dma_rx) {
1040 		dma_release_channel(dspi->dma_rx);
1041 		dma_release_channel(dspi->dma_tx);
1042 	}
1043 
1044 	spi_master_put(master);
1045 	return 0;
1046 }
1047 
1048 static struct platform_driver davinci_spi_driver = {
1049 	.driver = {
1050 		.name = "spi_davinci",
1051 		.of_match_table = of_match_ptr(davinci_spi_of_match),
1052 	},
1053 	.probe = davinci_spi_probe,
1054 	.remove = davinci_spi_remove,
1055 };
1056 module_platform_driver(davinci_spi_driver);
1057 
1058 MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
1059 MODULE_LICENSE("GPL");
1060