1 /* 2 * Copyright (C) 2009 Texas Instruments. 3 * Copyright (C) 2010 EF Johnson Technologies 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/gpio.h> 19 #include <linux/module.h> 20 #include <linux/delay.h> 21 #include <linux/platform_device.h> 22 #include <linux/err.h> 23 #include <linux/clk.h> 24 #include <linux/dmaengine.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/edma.h> 27 #include <linux/of.h> 28 #include <linux/of_device.h> 29 #include <linux/of_gpio.h> 30 #include <linux/spi/spi.h> 31 #include <linux/spi/spi_bitbang.h> 32 #include <linux/slab.h> 33 34 #include <linux/platform_data/spi-davinci.h> 35 36 #define SPI_NO_RESOURCE ((resource_size_t)-1) 37 38 #define CS_DEFAULT 0xFF 39 40 #define SPIFMT_PHASE_MASK BIT(16) 41 #define SPIFMT_POLARITY_MASK BIT(17) 42 #define SPIFMT_DISTIMER_MASK BIT(18) 43 #define SPIFMT_SHIFTDIR_MASK BIT(20) 44 #define SPIFMT_WAITENA_MASK BIT(21) 45 #define SPIFMT_PARITYENA_MASK BIT(22) 46 #define SPIFMT_ODD_PARITY_MASK BIT(23) 47 #define SPIFMT_WDELAY_MASK 0x3f000000u 48 #define SPIFMT_WDELAY_SHIFT 24 49 #define SPIFMT_PRESCALE_SHIFT 8 50 51 /* SPIPC0 */ 52 #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ 53 #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ 54 #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ 55 #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ 56 57 #define SPIINT_MASKALL 0x0101035F 58 #define SPIINT_MASKINT 0x0000015F 59 #define SPI_INTLVL_1 0x000001FF 60 #define SPI_INTLVL_0 0x00000000 61 62 /* SPIDAT1 (upper 16 bit defines) */ 63 #define SPIDAT1_CSHOLD_MASK BIT(12) 64 #define SPIDAT1_WDEL BIT(10) 65 66 /* SPIGCR1 */ 67 #define SPIGCR1_CLKMOD_MASK BIT(1) 68 #define SPIGCR1_MASTER_MASK BIT(0) 69 #define SPIGCR1_POWERDOWN_MASK BIT(8) 70 #define SPIGCR1_LOOPBACK_MASK BIT(16) 71 #define SPIGCR1_SPIENA_MASK BIT(24) 72 73 /* SPIBUF */ 74 #define SPIBUF_TXFULL_MASK BIT(29) 75 #define SPIBUF_RXEMPTY_MASK BIT(31) 76 77 /* SPIDELAY */ 78 #define SPIDELAY_C2TDELAY_SHIFT 24 79 #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT) 80 #define SPIDELAY_T2CDELAY_SHIFT 16 81 #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT) 82 #define SPIDELAY_T2EDELAY_SHIFT 8 83 #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT) 84 #define SPIDELAY_C2EDELAY_SHIFT 0 85 #define SPIDELAY_C2EDELAY_MASK 0xFF 86 87 /* Error Masks */ 88 #define SPIFLG_DLEN_ERR_MASK BIT(0) 89 #define SPIFLG_TIMEOUT_MASK BIT(1) 90 #define SPIFLG_PARERR_MASK BIT(2) 91 #define SPIFLG_DESYNC_MASK BIT(3) 92 #define SPIFLG_BITERR_MASK BIT(4) 93 #define SPIFLG_OVRRUN_MASK BIT(6) 94 #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) 95 #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ 96 | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ 97 | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ 98 | SPIFLG_OVRRUN_MASK) 99 100 #define SPIINT_DMA_REQ_EN BIT(16) 101 102 /* SPI Controller registers */ 103 #define SPIGCR0 0x00 104 #define SPIGCR1 0x04 105 #define SPIINT 0x08 106 #define SPILVL 0x0c 107 #define SPIFLG 0x10 108 #define SPIPC0 0x14 109 #define SPIDAT1 0x3c 110 #define SPIBUF 0x40 111 #define SPIDELAY 0x48 112 #define SPIDEF 0x4c 113 #define SPIFMT0 0x50 114 115 /* SPI Controller driver's private data. */ 116 struct davinci_spi { 117 struct spi_bitbang bitbang; 118 struct clk *clk; 119 120 u8 version; 121 resource_size_t pbase; 122 void __iomem *base; 123 u32 irq; 124 struct completion done; 125 126 const void *tx; 127 void *rx; 128 int rcount; 129 int wcount; 130 131 struct dma_chan *dma_rx; 132 struct dma_chan *dma_tx; 133 int dma_rx_chnum; 134 int dma_tx_chnum; 135 136 struct davinci_spi_platform_data pdata; 137 138 void (*get_rx)(u32 rx_data, struct davinci_spi *); 139 u32 (*get_tx)(struct davinci_spi *); 140 141 u8 *bytes_per_word; 142 143 u8 prescaler_limit; 144 }; 145 146 static struct davinci_spi_config davinci_spi_default_cfg; 147 148 static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi) 149 { 150 if (dspi->rx) { 151 u8 *rx = dspi->rx; 152 *rx++ = (u8)data; 153 dspi->rx = rx; 154 } 155 } 156 157 static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi) 158 { 159 if (dspi->rx) { 160 u16 *rx = dspi->rx; 161 *rx++ = (u16)data; 162 dspi->rx = rx; 163 } 164 } 165 166 static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi) 167 { 168 u32 data = 0; 169 170 if (dspi->tx) { 171 const u8 *tx = dspi->tx; 172 173 data = *tx++; 174 dspi->tx = tx; 175 } 176 return data; 177 } 178 179 static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi) 180 { 181 u32 data = 0; 182 183 if (dspi->tx) { 184 const u16 *tx = dspi->tx; 185 186 data = *tx++; 187 dspi->tx = tx; 188 } 189 return data; 190 } 191 192 static inline void set_io_bits(void __iomem *addr, u32 bits) 193 { 194 u32 v = ioread32(addr); 195 196 v |= bits; 197 iowrite32(v, addr); 198 } 199 200 static inline void clear_io_bits(void __iomem *addr, u32 bits) 201 { 202 u32 v = ioread32(addr); 203 204 v &= ~bits; 205 iowrite32(v, addr); 206 } 207 208 /* 209 * Interface to control the chip select signal 210 */ 211 static void davinci_spi_chipselect(struct spi_device *spi, int value) 212 { 213 struct davinci_spi *dspi; 214 struct davinci_spi_platform_data *pdata; 215 struct davinci_spi_config *spicfg = spi->controller_data; 216 u8 chip_sel = spi->chip_select; 217 u16 spidat1 = CS_DEFAULT; 218 bool gpio_chipsel = false; 219 int gpio; 220 221 dspi = spi_master_get_devdata(spi->master); 222 pdata = &dspi->pdata; 223 224 if (spi->cs_gpio >= 0) { 225 /* SPI core parse and update master->cs_gpio */ 226 gpio_chipsel = true; 227 gpio = spi->cs_gpio; 228 } 229 230 /* program delay transfers if tx_delay is non zero */ 231 if (spicfg->wdelay) 232 spidat1 |= SPIDAT1_WDEL; 233 234 /* 235 * Board specific chip select logic decides the polarity and cs 236 * line for the controller 237 */ 238 if (gpio_chipsel) { 239 if (value == BITBANG_CS_ACTIVE) 240 gpio_set_value(gpio, spi->mode & SPI_CS_HIGH); 241 else 242 gpio_set_value(gpio, !(spi->mode & SPI_CS_HIGH)); 243 } else { 244 if (value == BITBANG_CS_ACTIVE) { 245 spidat1 |= SPIDAT1_CSHOLD_MASK; 246 spidat1 &= ~(0x1 << chip_sel); 247 } 248 } 249 250 iowrite16(spidat1, dspi->base + SPIDAT1 + 2); 251 } 252 253 /** 254 * davinci_spi_get_prescale - Calculates the correct prescale value 255 * @maxspeed_hz: the maximum rate the SPI clock can run at 256 * 257 * This function calculates the prescale value that generates a clock rate 258 * less than or equal to the specified maximum. 259 * 260 * Returns: calculated prescale value for easy programming into SPI registers 261 * or negative error number if valid prescalar cannot be updated. 262 */ 263 static inline int davinci_spi_get_prescale(struct davinci_spi *dspi, 264 u32 max_speed_hz) 265 { 266 int ret; 267 268 /* Subtract 1 to match what will be programmed into SPI register. */ 269 ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz) - 1; 270 271 if (ret < dspi->prescaler_limit || ret > 255) 272 return -EINVAL; 273 274 return ret; 275 } 276 277 /** 278 * davinci_spi_setup_transfer - This functions will determine transfer method 279 * @spi: spi device on which data transfer to be done 280 * @t: spi transfer in which transfer info is filled 281 * 282 * This function determines data transfer method (8/16/32 bit transfer). 283 * It will also set the SPI Clock Control register according to 284 * SPI slave device freq. 285 */ 286 static int davinci_spi_setup_transfer(struct spi_device *spi, 287 struct spi_transfer *t) 288 { 289 290 struct davinci_spi *dspi; 291 struct davinci_spi_config *spicfg; 292 u8 bits_per_word = 0; 293 u32 hz = 0, spifmt = 0; 294 int prescale; 295 296 dspi = spi_master_get_devdata(spi->master); 297 spicfg = spi->controller_data; 298 if (!spicfg) 299 spicfg = &davinci_spi_default_cfg; 300 301 if (t) { 302 bits_per_word = t->bits_per_word; 303 hz = t->speed_hz; 304 } 305 306 /* if bits_per_word is not set then set it default */ 307 if (!bits_per_word) 308 bits_per_word = spi->bits_per_word; 309 310 /* 311 * Assign function pointer to appropriate transfer method 312 * 8bit, 16bit or 32bit transfer 313 */ 314 if (bits_per_word <= 8) { 315 dspi->get_rx = davinci_spi_rx_buf_u8; 316 dspi->get_tx = davinci_spi_tx_buf_u8; 317 dspi->bytes_per_word[spi->chip_select] = 1; 318 } else { 319 dspi->get_rx = davinci_spi_rx_buf_u16; 320 dspi->get_tx = davinci_spi_tx_buf_u16; 321 dspi->bytes_per_word[spi->chip_select] = 2; 322 } 323 324 if (!hz) 325 hz = spi->max_speed_hz; 326 327 /* Set up SPIFMTn register, unique to this chipselect. */ 328 329 prescale = davinci_spi_get_prescale(dspi, hz); 330 if (prescale < 0) 331 return prescale; 332 333 spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f); 334 335 if (spi->mode & SPI_LSB_FIRST) 336 spifmt |= SPIFMT_SHIFTDIR_MASK; 337 338 if (spi->mode & SPI_CPOL) 339 spifmt |= SPIFMT_POLARITY_MASK; 340 341 if (!(spi->mode & SPI_CPHA)) 342 spifmt |= SPIFMT_PHASE_MASK; 343 344 /* 345 * Assume wdelay is used only on SPI peripherals that has this field 346 * in SPIFMTn register and when it's configured from board file or DT. 347 */ 348 if (spicfg->wdelay) 349 spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT) 350 & SPIFMT_WDELAY_MASK); 351 352 /* 353 * Version 1 hardware supports two basic SPI modes: 354 * - Standard SPI mode uses 4 pins, with chipselect 355 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) 356 * (distinct from SPI_3WIRE, with just one data wire; 357 * or similar variants without MOSI or without MISO) 358 * 359 * Version 2 hardware supports an optional handshaking signal, 360 * so it can support two more modes: 361 * - 5 pin SPI variant is standard SPI plus SPI_READY 362 * - 4 pin with enable is (SPI_READY | SPI_NO_CS) 363 */ 364 365 if (dspi->version == SPI_VERSION_2) { 366 367 u32 delay = 0; 368 369 if (spicfg->odd_parity) 370 spifmt |= SPIFMT_ODD_PARITY_MASK; 371 372 if (spicfg->parity_enable) 373 spifmt |= SPIFMT_PARITYENA_MASK; 374 375 if (spicfg->timer_disable) { 376 spifmt |= SPIFMT_DISTIMER_MASK; 377 } else { 378 delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT) 379 & SPIDELAY_C2TDELAY_MASK; 380 delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT) 381 & SPIDELAY_T2CDELAY_MASK; 382 } 383 384 if (spi->mode & SPI_READY) { 385 spifmt |= SPIFMT_WAITENA_MASK; 386 delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT) 387 & SPIDELAY_T2EDELAY_MASK; 388 delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT) 389 & SPIDELAY_C2EDELAY_MASK; 390 } 391 392 iowrite32(delay, dspi->base + SPIDELAY); 393 } 394 395 iowrite32(spifmt, dspi->base + SPIFMT0); 396 397 return 0; 398 } 399 400 static int davinci_spi_of_setup(struct spi_device *spi) 401 { 402 struct davinci_spi_config *spicfg = spi->controller_data; 403 struct device_node *np = spi->dev.of_node; 404 u32 prop; 405 406 if (spicfg == NULL && np) { 407 spicfg = kzalloc(sizeof(*spicfg), GFP_KERNEL); 408 if (!spicfg) 409 return -ENOMEM; 410 *spicfg = davinci_spi_default_cfg; 411 /* override with dt configured values */ 412 if (!of_property_read_u32(np, "ti,spi-wdelay", &prop)) 413 spicfg->wdelay = (u8)prop; 414 spi->controller_data = spicfg; 415 } 416 417 return 0; 418 } 419 420 /** 421 * davinci_spi_setup - This functions will set default transfer method 422 * @spi: spi device on which data transfer to be done 423 * 424 * This functions sets the default transfer method. 425 */ 426 static int davinci_spi_setup(struct spi_device *spi) 427 { 428 int retval = 0; 429 struct davinci_spi *dspi; 430 struct davinci_spi_platform_data *pdata; 431 struct spi_master *master = spi->master; 432 struct device_node *np = spi->dev.of_node; 433 bool internal_cs = true; 434 435 dspi = spi_master_get_devdata(spi->master); 436 pdata = &dspi->pdata; 437 438 if (!(spi->mode & SPI_NO_CS)) { 439 if (np && (master->cs_gpios != NULL) && (spi->cs_gpio >= 0)) { 440 retval = gpio_direction_output( 441 spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); 442 internal_cs = false; 443 } else if (pdata->chip_sel && 444 spi->chip_select < pdata->num_chipselect && 445 pdata->chip_sel[spi->chip_select] != SPI_INTERN_CS) { 446 spi->cs_gpio = pdata->chip_sel[spi->chip_select]; 447 retval = gpio_direction_output( 448 spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); 449 internal_cs = false; 450 } 451 452 if (retval) { 453 dev_err(&spi->dev, "GPIO %d setup failed (%d)\n", 454 spi->cs_gpio, retval); 455 return retval; 456 } 457 458 if (internal_cs) 459 set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select); 460 } 461 462 if (spi->mode & SPI_READY) 463 set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK); 464 465 if (spi->mode & SPI_LOOP) 466 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); 467 else 468 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); 469 470 return davinci_spi_of_setup(spi); 471 } 472 473 static void davinci_spi_cleanup(struct spi_device *spi) 474 { 475 struct davinci_spi_config *spicfg = spi->controller_data; 476 477 spi->controller_data = NULL; 478 if (spi->dev.of_node) 479 kfree(spicfg); 480 } 481 482 static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status) 483 { 484 struct device *sdev = dspi->bitbang.master->dev.parent; 485 486 if (int_status & SPIFLG_TIMEOUT_MASK) { 487 dev_dbg(sdev, "SPI Time-out Error\n"); 488 return -ETIMEDOUT; 489 } 490 if (int_status & SPIFLG_DESYNC_MASK) { 491 dev_dbg(sdev, "SPI Desynchronization Error\n"); 492 return -EIO; 493 } 494 if (int_status & SPIFLG_BITERR_MASK) { 495 dev_dbg(sdev, "SPI Bit error\n"); 496 return -EIO; 497 } 498 499 if (dspi->version == SPI_VERSION_2) { 500 if (int_status & SPIFLG_DLEN_ERR_MASK) { 501 dev_dbg(sdev, "SPI Data Length Error\n"); 502 return -EIO; 503 } 504 if (int_status & SPIFLG_PARERR_MASK) { 505 dev_dbg(sdev, "SPI Parity Error\n"); 506 return -EIO; 507 } 508 if (int_status & SPIFLG_OVRRUN_MASK) { 509 dev_dbg(sdev, "SPI Data Overrun error\n"); 510 return -EIO; 511 } 512 if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) { 513 dev_dbg(sdev, "SPI Buffer Init Active\n"); 514 return -EBUSY; 515 } 516 } 517 518 return 0; 519 } 520 521 /** 522 * davinci_spi_process_events - check for and handle any SPI controller events 523 * @dspi: the controller data 524 * 525 * This function will check the SPIFLG register and handle any events that are 526 * detected there 527 */ 528 static int davinci_spi_process_events(struct davinci_spi *dspi) 529 { 530 u32 buf, status, errors = 0, spidat1; 531 532 buf = ioread32(dspi->base + SPIBUF); 533 534 if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) { 535 dspi->get_rx(buf & 0xFFFF, dspi); 536 dspi->rcount--; 537 } 538 539 status = ioread32(dspi->base + SPIFLG); 540 541 if (unlikely(status & SPIFLG_ERROR_MASK)) { 542 errors = status & SPIFLG_ERROR_MASK; 543 goto out; 544 } 545 546 if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) { 547 spidat1 = ioread32(dspi->base + SPIDAT1); 548 dspi->wcount--; 549 spidat1 &= ~0xFFFF; 550 spidat1 |= 0xFFFF & dspi->get_tx(dspi); 551 iowrite32(spidat1, dspi->base + SPIDAT1); 552 } 553 554 out: 555 return errors; 556 } 557 558 static void davinci_spi_dma_rx_callback(void *data) 559 { 560 struct davinci_spi *dspi = (struct davinci_spi *)data; 561 562 dspi->rcount = 0; 563 564 if (!dspi->wcount && !dspi->rcount) 565 complete(&dspi->done); 566 } 567 568 static void davinci_spi_dma_tx_callback(void *data) 569 { 570 struct davinci_spi *dspi = (struct davinci_spi *)data; 571 572 dspi->wcount = 0; 573 574 if (!dspi->wcount && !dspi->rcount) 575 complete(&dspi->done); 576 } 577 578 /** 579 * davinci_spi_bufs - functions which will handle transfer data 580 * @spi: spi device on which data transfer to be done 581 * @t: spi transfer in which transfer info is filled 582 * 583 * This function will put data to be transferred into data register 584 * of SPI controller and then wait until the completion will be marked 585 * by the IRQ Handler. 586 */ 587 static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) 588 { 589 struct davinci_spi *dspi; 590 int data_type, ret = -ENOMEM; 591 u32 tx_data, spidat1; 592 u32 errors = 0; 593 struct davinci_spi_config *spicfg; 594 struct davinci_spi_platform_data *pdata; 595 unsigned uninitialized_var(rx_buf_count); 596 void *dummy_buf = NULL; 597 struct scatterlist sg_rx, sg_tx; 598 599 dspi = spi_master_get_devdata(spi->master); 600 pdata = &dspi->pdata; 601 spicfg = (struct davinci_spi_config *)spi->controller_data; 602 if (!spicfg) 603 spicfg = &davinci_spi_default_cfg; 604 605 /* convert len to words based on bits_per_word */ 606 data_type = dspi->bytes_per_word[spi->chip_select]; 607 608 dspi->tx = t->tx_buf; 609 dspi->rx = t->rx_buf; 610 dspi->wcount = t->len / data_type; 611 dspi->rcount = dspi->wcount; 612 613 spidat1 = ioread32(dspi->base + SPIDAT1); 614 615 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); 616 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); 617 618 reinit_completion(&dspi->done); 619 620 if (spicfg->io_type == SPI_IO_TYPE_INTR) 621 set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); 622 623 if (spicfg->io_type != SPI_IO_TYPE_DMA) { 624 /* start the transfer */ 625 dspi->wcount--; 626 tx_data = dspi->get_tx(dspi); 627 spidat1 &= 0xFFFF0000; 628 spidat1 |= tx_data & 0xFFFF; 629 iowrite32(spidat1, dspi->base + SPIDAT1); 630 } else { 631 struct dma_slave_config dma_rx_conf = { 632 .direction = DMA_DEV_TO_MEM, 633 .src_addr = (unsigned long)dspi->pbase + SPIBUF, 634 .src_addr_width = data_type, 635 .src_maxburst = 1, 636 }; 637 struct dma_slave_config dma_tx_conf = { 638 .direction = DMA_MEM_TO_DEV, 639 .dst_addr = (unsigned long)dspi->pbase + SPIDAT1, 640 .dst_addr_width = data_type, 641 .dst_maxburst = 1, 642 }; 643 struct dma_async_tx_descriptor *rxdesc; 644 struct dma_async_tx_descriptor *txdesc; 645 void *buf; 646 647 dummy_buf = kzalloc(t->len, GFP_KERNEL); 648 if (!dummy_buf) 649 goto err_alloc_dummy_buf; 650 651 dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf); 652 dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf); 653 654 sg_init_table(&sg_rx, 1); 655 if (!t->rx_buf) 656 buf = dummy_buf; 657 else 658 buf = t->rx_buf; 659 t->rx_dma = dma_map_single(&spi->dev, buf, 660 t->len, DMA_FROM_DEVICE); 661 if (!t->rx_dma) { 662 ret = -EFAULT; 663 goto err_rx_map; 664 } 665 sg_dma_address(&sg_rx) = t->rx_dma; 666 sg_dma_len(&sg_rx) = t->len; 667 668 sg_init_table(&sg_tx, 1); 669 if (!t->tx_buf) 670 buf = dummy_buf; 671 else 672 buf = (void *)t->tx_buf; 673 t->tx_dma = dma_map_single(&spi->dev, buf, 674 t->len, DMA_TO_DEVICE); 675 if (!t->tx_dma) { 676 ret = -EFAULT; 677 goto err_tx_map; 678 } 679 sg_dma_address(&sg_tx) = t->tx_dma; 680 sg_dma_len(&sg_tx) = t->len; 681 682 rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx, 683 &sg_rx, 1, DMA_DEV_TO_MEM, 684 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 685 if (!rxdesc) 686 goto err_desc; 687 688 txdesc = dmaengine_prep_slave_sg(dspi->dma_tx, 689 &sg_tx, 1, DMA_MEM_TO_DEV, 690 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 691 if (!txdesc) 692 goto err_desc; 693 694 rxdesc->callback = davinci_spi_dma_rx_callback; 695 rxdesc->callback_param = (void *)dspi; 696 txdesc->callback = davinci_spi_dma_tx_callback; 697 txdesc->callback_param = (void *)dspi; 698 699 if (pdata->cshold_bug) 700 iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2); 701 702 dmaengine_submit(rxdesc); 703 dmaengine_submit(txdesc); 704 705 dma_async_issue_pending(dspi->dma_rx); 706 dma_async_issue_pending(dspi->dma_tx); 707 708 set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); 709 } 710 711 /* Wait for the transfer to complete */ 712 if (spicfg->io_type != SPI_IO_TYPE_POLL) { 713 wait_for_completion_interruptible(&(dspi->done)); 714 } else { 715 while (dspi->rcount > 0 || dspi->wcount > 0) { 716 errors = davinci_spi_process_events(dspi); 717 if (errors) 718 break; 719 cpu_relax(); 720 } 721 } 722 723 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL); 724 if (spicfg->io_type == SPI_IO_TYPE_DMA) { 725 clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); 726 727 dma_unmap_single(&spi->dev, t->rx_dma, 728 t->len, DMA_FROM_DEVICE); 729 dma_unmap_single(&spi->dev, t->tx_dma, 730 t->len, DMA_TO_DEVICE); 731 kfree(dummy_buf); 732 } 733 734 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); 735 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); 736 737 /* 738 * Check for bit error, desync error,parity error,timeout error and 739 * receive overflow errors 740 */ 741 if (errors) { 742 ret = davinci_spi_check_error(dspi, errors); 743 WARN(!ret, "%s: error reported but no error found!\n", 744 dev_name(&spi->dev)); 745 return ret; 746 } 747 748 if (dspi->rcount != 0 || dspi->wcount != 0) { 749 dev_err(&spi->dev, "SPI data transfer error\n"); 750 return -EIO; 751 } 752 753 return t->len; 754 755 err_desc: 756 dma_unmap_single(&spi->dev, t->tx_dma, t->len, DMA_TO_DEVICE); 757 err_tx_map: 758 dma_unmap_single(&spi->dev, t->rx_dma, t->len, DMA_FROM_DEVICE); 759 err_rx_map: 760 kfree(dummy_buf); 761 err_alloc_dummy_buf: 762 return ret; 763 } 764 765 /** 766 * dummy_thread_fn - dummy thread function 767 * @irq: IRQ number for this SPI Master 768 * @context_data: structure for SPI Master controller davinci_spi 769 * 770 * This is to satisfy the request_threaded_irq() API so that the irq 771 * handler is called in interrupt context. 772 */ 773 static irqreturn_t dummy_thread_fn(s32 irq, void *data) 774 { 775 return IRQ_HANDLED; 776 } 777 778 /** 779 * davinci_spi_irq - Interrupt handler for SPI Master Controller 780 * @irq: IRQ number for this SPI Master 781 * @context_data: structure for SPI Master controller davinci_spi 782 * 783 * ISR will determine that interrupt arrives either for READ or WRITE command. 784 * According to command it will do the appropriate action. It will check 785 * transfer length and if it is not zero then dispatch transfer command again. 786 * If transfer length is zero then it will indicate the COMPLETION so that 787 * davinci_spi_bufs function can go ahead. 788 */ 789 static irqreturn_t davinci_spi_irq(s32 irq, void *data) 790 { 791 struct davinci_spi *dspi = data; 792 int status; 793 794 status = davinci_spi_process_events(dspi); 795 if (unlikely(status != 0)) 796 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); 797 798 if ((!dspi->rcount && !dspi->wcount) || status) 799 complete(&dspi->done); 800 801 return IRQ_HANDLED; 802 } 803 804 static int davinci_spi_request_dma(struct davinci_spi *dspi) 805 { 806 dma_cap_mask_t mask; 807 struct device *sdev = dspi->bitbang.master->dev.parent; 808 int r; 809 810 dma_cap_zero(mask); 811 dma_cap_set(DMA_SLAVE, mask); 812 813 dspi->dma_rx = dma_request_channel(mask, edma_filter_fn, 814 &dspi->dma_rx_chnum); 815 if (!dspi->dma_rx) { 816 dev_err(sdev, "request RX DMA channel failed\n"); 817 r = -ENODEV; 818 goto rx_dma_failed; 819 } 820 821 dspi->dma_tx = dma_request_channel(mask, edma_filter_fn, 822 &dspi->dma_tx_chnum); 823 if (!dspi->dma_tx) { 824 dev_err(sdev, "request TX DMA channel failed\n"); 825 r = -ENODEV; 826 goto tx_dma_failed; 827 } 828 829 return 0; 830 831 tx_dma_failed: 832 dma_release_channel(dspi->dma_rx); 833 rx_dma_failed: 834 return r; 835 } 836 837 #if defined(CONFIG_OF) 838 839 /* OF SPI data structure */ 840 struct davinci_spi_of_data { 841 u8 version; 842 u8 prescaler_limit; 843 }; 844 845 static const struct davinci_spi_of_data dm6441_spi_data = { 846 .version = SPI_VERSION_1, 847 .prescaler_limit = 2, 848 }; 849 850 static const struct davinci_spi_of_data da830_spi_data = { 851 .version = SPI_VERSION_2, 852 .prescaler_limit = 2, 853 }; 854 855 static const struct davinci_spi_of_data keystone_spi_data = { 856 .version = SPI_VERSION_1, 857 .prescaler_limit = 0, 858 }; 859 860 static const struct of_device_id davinci_spi_of_match[] = { 861 { 862 .compatible = "ti,dm6441-spi", 863 .data = &dm6441_spi_data, 864 }, 865 { 866 .compatible = "ti,da830-spi", 867 .data = &da830_spi_data, 868 }, 869 { 870 .compatible = "ti,keystone-spi", 871 .data = &keystone_spi_data, 872 }, 873 { }, 874 }; 875 MODULE_DEVICE_TABLE(of, davinci_spi_of_match); 876 877 /** 878 * spi_davinci_get_pdata - Get platform data from DTS binding 879 * @pdev: ptr to platform data 880 * @dspi: ptr to driver data 881 * 882 * Parses and populates pdata in dspi from device tree bindings. 883 * 884 * NOTE: Not all platform data params are supported currently. 885 */ 886 static int spi_davinci_get_pdata(struct platform_device *pdev, 887 struct davinci_spi *dspi) 888 { 889 struct device_node *node = pdev->dev.of_node; 890 struct davinci_spi_of_data *spi_data; 891 struct davinci_spi_platform_data *pdata; 892 unsigned int num_cs, intr_line = 0; 893 const struct of_device_id *match; 894 895 pdata = &dspi->pdata; 896 897 match = of_match_device(davinci_spi_of_match, &pdev->dev); 898 if (!match) 899 return -ENODEV; 900 901 spi_data = (struct davinci_spi_of_data *)match->data; 902 903 pdata->version = spi_data->version; 904 pdata->prescaler_limit = spi_data->prescaler_limit; 905 /* 906 * default num_cs is 1 and all chipsel are internal to the chip 907 * indicated by chip_sel being NULL or cs_gpios being NULL or 908 * set to -ENOENT. num-cs includes internal as well as gpios. 909 * indicated by chip_sel being NULL. GPIO based CS is not 910 * supported yet in DT bindings. 911 */ 912 num_cs = 1; 913 of_property_read_u32(node, "num-cs", &num_cs); 914 pdata->num_chipselect = num_cs; 915 of_property_read_u32(node, "ti,davinci-spi-intr-line", &intr_line); 916 pdata->intr_line = intr_line; 917 return 0; 918 } 919 #else 920 static struct davinci_spi_platform_data 921 *spi_davinci_get_pdata(struct platform_device *pdev, 922 struct davinci_spi *dspi) 923 { 924 return -ENODEV; 925 } 926 #endif 927 928 /** 929 * davinci_spi_probe - probe function for SPI Master Controller 930 * @pdev: platform_device structure which contains plateform specific data 931 * 932 * According to Linux Device Model this function will be invoked by Linux 933 * with platform_device struct which contains the device specific info. 934 * This function will map the SPI controller's memory, register IRQ, 935 * Reset SPI controller and setting its registers to default value. 936 * It will invoke spi_bitbang_start to create work queue so that client driver 937 * can register transfer method to work queue. 938 */ 939 static int davinci_spi_probe(struct platform_device *pdev) 940 { 941 struct spi_master *master; 942 struct davinci_spi *dspi; 943 struct davinci_spi_platform_data *pdata; 944 struct resource *r; 945 resource_size_t dma_rx_chan = SPI_NO_RESOURCE; 946 resource_size_t dma_tx_chan = SPI_NO_RESOURCE; 947 int ret = 0; 948 u32 spipc0; 949 950 master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi)); 951 if (master == NULL) { 952 ret = -ENOMEM; 953 goto err; 954 } 955 956 platform_set_drvdata(pdev, master); 957 958 dspi = spi_master_get_devdata(master); 959 960 if (dev_get_platdata(&pdev->dev)) { 961 pdata = dev_get_platdata(&pdev->dev); 962 dspi->pdata = *pdata; 963 } else { 964 /* update dspi pdata with that from the DT */ 965 ret = spi_davinci_get_pdata(pdev, dspi); 966 if (ret < 0) 967 goto free_master; 968 } 969 970 /* pdata in dspi is now updated and point pdata to that */ 971 pdata = &dspi->pdata; 972 973 dspi->bytes_per_word = devm_kzalloc(&pdev->dev, 974 sizeof(*dspi->bytes_per_word) * 975 pdata->num_chipselect, GFP_KERNEL); 976 if (dspi->bytes_per_word == NULL) { 977 ret = -ENOMEM; 978 goto free_master; 979 } 980 981 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 982 if (r == NULL) { 983 ret = -ENOENT; 984 goto free_master; 985 } 986 987 dspi->pbase = r->start; 988 989 dspi->base = devm_ioremap_resource(&pdev->dev, r); 990 if (IS_ERR(dspi->base)) { 991 ret = PTR_ERR(dspi->base); 992 goto free_master; 993 } 994 995 dspi->irq = platform_get_irq(pdev, 0); 996 if (dspi->irq <= 0) { 997 ret = -EINVAL; 998 goto free_master; 999 } 1000 1001 ret = devm_request_threaded_irq(&pdev->dev, dspi->irq, davinci_spi_irq, 1002 dummy_thread_fn, 0, dev_name(&pdev->dev), dspi); 1003 if (ret) 1004 goto free_master; 1005 1006 dspi->bitbang.master = master; 1007 1008 dspi->clk = devm_clk_get(&pdev->dev, NULL); 1009 if (IS_ERR(dspi->clk)) { 1010 ret = -ENODEV; 1011 goto free_master; 1012 } 1013 clk_prepare_enable(dspi->clk); 1014 1015 master->dev.of_node = pdev->dev.of_node; 1016 master->bus_num = pdev->id; 1017 master->num_chipselect = pdata->num_chipselect; 1018 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16); 1019 master->setup = davinci_spi_setup; 1020 master->cleanup = davinci_spi_cleanup; 1021 1022 dspi->bitbang.chipselect = davinci_spi_chipselect; 1023 dspi->bitbang.setup_transfer = davinci_spi_setup_transfer; 1024 dspi->prescaler_limit = pdata->prescaler_limit; 1025 dspi->version = pdata->version; 1026 1027 dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP; 1028 if (dspi->version == SPI_VERSION_2) 1029 dspi->bitbang.flags |= SPI_READY; 1030 1031 if (pdev->dev.of_node) { 1032 int i; 1033 1034 for (i = 0; i < pdata->num_chipselect; i++) { 1035 int cs_gpio = of_get_named_gpio(pdev->dev.of_node, 1036 "cs-gpios", i); 1037 1038 if (cs_gpio == -EPROBE_DEFER) { 1039 ret = cs_gpio; 1040 goto free_clk; 1041 } 1042 1043 if (gpio_is_valid(cs_gpio)) { 1044 ret = devm_gpio_request(&pdev->dev, cs_gpio, 1045 dev_name(&pdev->dev)); 1046 if (ret) 1047 goto free_clk; 1048 } 1049 } 1050 } 1051 1052 r = platform_get_resource(pdev, IORESOURCE_DMA, 0); 1053 if (r) 1054 dma_rx_chan = r->start; 1055 r = platform_get_resource(pdev, IORESOURCE_DMA, 1); 1056 if (r) 1057 dma_tx_chan = r->start; 1058 1059 dspi->bitbang.txrx_bufs = davinci_spi_bufs; 1060 if (dma_rx_chan != SPI_NO_RESOURCE && 1061 dma_tx_chan != SPI_NO_RESOURCE) { 1062 dspi->dma_rx_chnum = dma_rx_chan; 1063 dspi->dma_tx_chnum = dma_tx_chan; 1064 1065 ret = davinci_spi_request_dma(dspi); 1066 if (ret) 1067 goto free_clk; 1068 1069 dev_info(&pdev->dev, "DMA: supported\n"); 1070 dev_info(&pdev->dev, "DMA: RX channel: %pa, TX channel: %pa, event queue: %d\n", 1071 &dma_rx_chan, &dma_tx_chan, 1072 pdata->dma_event_q); 1073 } 1074 1075 dspi->get_rx = davinci_spi_rx_buf_u8; 1076 dspi->get_tx = davinci_spi_tx_buf_u8; 1077 1078 init_completion(&dspi->done); 1079 1080 /* Reset In/OUT SPI module */ 1081 iowrite32(0, dspi->base + SPIGCR0); 1082 udelay(100); 1083 iowrite32(1, dspi->base + SPIGCR0); 1084 1085 /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ 1086 spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; 1087 iowrite32(spipc0, dspi->base + SPIPC0); 1088 1089 if (pdata->intr_line) 1090 iowrite32(SPI_INTLVL_1, dspi->base + SPILVL); 1091 else 1092 iowrite32(SPI_INTLVL_0, dspi->base + SPILVL); 1093 1094 iowrite32(CS_DEFAULT, dspi->base + SPIDEF); 1095 1096 /* master mode default */ 1097 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); 1098 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK); 1099 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); 1100 1101 ret = spi_bitbang_start(&dspi->bitbang); 1102 if (ret) 1103 goto free_dma; 1104 1105 dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base); 1106 1107 return ret; 1108 1109 free_dma: 1110 dma_release_channel(dspi->dma_rx); 1111 dma_release_channel(dspi->dma_tx); 1112 free_clk: 1113 clk_disable_unprepare(dspi->clk); 1114 free_master: 1115 spi_master_put(master); 1116 err: 1117 return ret; 1118 } 1119 1120 /** 1121 * davinci_spi_remove - remove function for SPI Master Controller 1122 * @pdev: platform_device structure which contains plateform specific data 1123 * 1124 * This function will do the reverse action of davinci_spi_probe function 1125 * It will free the IRQ and SPI controller's memory region. 1126 * It will also call spi_bitbang_stop to destroy the work queue which was 1127 * created by spi_bitbang_start. 1128 */ 1129 static int davinci_spi_remove(struct platform_device *pdev) 1130 { 1131 struct davinci_spi *dspi; 1132 struct spi_master *master; 1133 1134 master = platform_get_drvdata(pdev); 1135 dspi = spi_master_get_devdata(master); 1136 1137 spi_bitbang_stop(&dspi->bitbang); 1138 1139 clk_disable_unprepare(dspi->clk); 1140 spi_master_put(master); 1141 1142 return 0; 1143 } 1144 1145 static struct platform_driver davinci_spi_driver = { 1146 .driver = { 1147 .name = "spi_davinci", 1148 .of_match_table = of_match_ptr(davinci_spi_of_match), 1149 }, 1150 .probe = davinci_spi_probe, 1151 .remove = davinci_spi_remove, 1152 }; 1153 module_platform_driver(davinci_spi_driver); 1154 1155 MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver"); 1156 MODULE_LICENSE("GPL"); 1157