xref: /openbmc/linux/drivers/spi/spi-davinci.c (revision 9b9c2cd4)
1 /*
2  * Copyright (C) 2009 Texas Instruments.
3  * Copyright (C) 2010 EF Johnson Technologies
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation; either version 2 of the License, or
8  * (at your option) any later version.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15 
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/gpio.h>
19 #include <linux/module.h>
20 #include <linux/delay.h>
21 #include <linux/platform_device.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
24 #include <linux/dmaengine.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/edma.h>
27 #include <linux/of.h>
28 #include <linux/of_device.h>
29 #include <linux/of_gpio.h>
30 #include <linux/spi/spi.h>
31 #include <linux/spi/spi_bitbang.h>
32 #include <linux/slab.h>
33 
34 #include <linux/platform_data/spi-davinci.h>
35 
36 #define SPI_NO_RESOURCE		((resource_size_t)-1)
37 
38 #define CS_DEFAULT	0xFF
39 
40 #define SPIFMT_PHASE_MASK	BIT(16)
41 #define SPIFMT_POLARITY_MASK	BIT(17)
42 #define SPIFMT_DISTIMER_MASK	BIT(18)
43 #define SPIFMT_SHIFTDIR_MASK	BIT(20)
44 #define SPIFMT_WAITENA_MASK	BIT(21)
45 #define SPIFMT_PARITYENA_MASK	BIT(22)
46 #define SPIFMT_ODD_PARITY_MASK	BIT(23)
47 #define SPIFMT_WDELAY_MASK	0x3f000000u
48 #define SPIFMT_WDELAY_SHIFT	24
49 #define SPIFMT_PRESCALE_SHIFT	8
50 
51 /* SPIPC0 */
52 #define SPIPC0_DIFUN_MASK	BIT(11)		/* MISO */
53 #define SPIPC0_DOFUN_MASK	BIT(10)		/* MOSI */
54 #define SPIPC0_CLKFUN_MASK	BIT(9)		/* CLK */
55 #define SPIPC0_SPIENA_MASK	BIT(8)		/* nREADY */
56 
57 #define SPIINT_MASKALL		0x0101035F
58 #define SPIINT_MASKINT		0x0000015F
59 #define SPI_INTLVL_1		0x000001FF
60 #define SPI_INTLVL_0		0x00000000
61 
62 /* SPIDAT1 (upper 16 bit defines) */
63 #define SPIDAT1_CSHOLD_MASK	BIT(12)
64 #define SPIDAT1_WDEL		BIT(10)
65 
66 /* SPIGCR1 */
67 #define SPIGCR1_CLKMOD_MASK	BIT(1)
68 #define SPIGCR1_MASTER_MASK     BIT(0)
69 #define SPIGCR1_POWERDOWN_MASK	BIT(8)
70 #define SPIGCR1_LOOPBACK_MASK	BIT(16)
71 #define SPIGCR1_SPIENA_MASK	BIT(24)
72 
73 /* SPIBUF */
74 #define SPIBUF_TXFULL_MASK	BIT(29)
75 #define SPIBUF_RXEMPTY_MASK	BIT(31)
76 
77 /* SPIDELAY */
78 #define SPIDELAY_C2TDELAY_SHIFT 24
79 #define SPIDELAY_C2TDELAY_MASK  (0xFF << SPIDELAY_C2TDELAY_SHIFT)
80 #define SPIDELAY_T2CDELAY_SHIFT 16
81 #define SPIDELAY_T2CDELAY_MASK  (0xFF << SPIDELAY_T2CDELAY_SHIFT)
82 #define SPIDELAY_T2EDELAY_SHIFT 8
83 #define SPIDELAY_T2EDELAY_MASK  (0xFF << SPIDELAY_T2EDELAY_SHIFT)
84 #define SPIDELAY_C2EDELAY_SHIFT 0
85 #define SPIDELAY_C2EDELAY_MASK  0xFF
86 
87 /* Error Masks */
88 #define SPIFLG_DLEN_ERR_MASK		BIT(0)
89 #define SPIFLG_TIMEOUT_MASK		BIT(1)
90 #define SPIFLG_PARERR_MASK		BIT(2)
91 #define SPIFLG_DESYNC_MASK		BIT(3)
92 #define SPIFLG_BITERR_MASK		BIT(4)
93 #define SPIFLG_OVRRUN_MASK		BIT(6)
94 #define SPIFLG_BUF_INIT_ACTIVE_MASK	BIT(24)
95 #define SPIFLG_ERROR_MASK		(SPIFLG_DLEN_ERR_MASK \
96 				| SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
97 				| SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
98 				| SPIFLG_OVRRUN_MASK)
99 
100 #define SPIINT_DMA_REQ_EN	BIT(16)
101 
102 /* SPI Controller registers */
103 #define SPIGCR0		0x00
104 #define SPIGCR1		0x04
105 #define SPIINT		0x08
106 #define SPILVL		0x0c
107 #define SPIFLG		0x10
108 #define SPIPC0		0x14
109 #define SPIDAT1		0x3c
110 #define SPIBUF		0x40
111 #define SPIDELAY	0x48
112 #define SPIDEF		0x4c
113 #define SPIFMT0		0x50
114 
115 /* SPI Controller driver's private data. */
116 struct davinci_spi {
117 	struct spi_bitbang	bitbang;
118 	struct clk		*clk;
119 
120 	u8			version;
121 	resource_size_t		pbase;
122 	void __iomem		*base;
123 	u32			irq;
124 	struct completion	done;
125 
126 	const void		*tx;
127 	void			*rx;
128 	int			rcount;
129 	int			wcount;
130 
131 	struct dma_chan		*dma_rx;
132 	struct dma_chan		*dma_tx;
133 	int			dma_rx_chnum;
134 	int			dma_tx_chnum;
135 
136 	struct davinci_spi_platform_data pdata;
137 
138 	void			(*get_rx)(u32 rx_data, struct davinci_spi *);
139 	u32			(*get_tx)(struct davinci_spi *);
140 
141 	u8			*bytes_per_word;
142 
143 	u8			prescaler_limit;
144 };
145 
146 static struct davinci_spi_config davinci_spi_default_cfg;
147 
148 static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi)
149 {
150 	if (dspi->rx) {
151 		u8 *rx = dspi->rx;
152 		*rx++ = (u8)data;
153 		dspi->rx = rx;
154 	}
155 }
156 
157 static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi)
158 {
159 	if (dspi->rx) {
160 		u16 *rx = dspi->rx;
161 		*rx++ = (u16)data;
162 		dspi->rx = rx;
163 	}
164 }
165 
166 static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)
167 {
168 	u32 data = 0;
169 
170 	if (dspi->tx) {
171 		const u8 *tx = dspi->tx;
172 
173 		data = *tx++;
174 		dspi->tx = tx;
175 	}
176 	return data;
177 }
178 
179 static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi)
180 {
181 	u32 data = 0;
182 
183 	if (dspi->tx) {
184 		const u16 *tx = dspi->tx;
185 
186 		data = *tx++;
187 		dspi->tx = tx;
188 	}
189 	return data;
190 }
191 
192 static inline void set_io_bits(void __iomem *addr, u32 bits)
193 {
194 	u32 v = ioread32(addr);
195 
196 	v |= bits;
197 	iowrite32(v, addr);
198 }
199 
200 static inline void clear_io_bits(void __iomem *addr, u32 bits)
201 {
202 	u32 v = ioread32(addr);
203 
204 	v &= ~bits;
205 	iowrite32(v, addr);
206 }
207 
208 /*
209  * Interface to control the chip select signal
210  */
211 static void davinci_spi_chipselect(struct spi_device *spi, int value)
212 {
213 	struct davinci_spi *dspi;
214 	struct davinci_spi_platform_data *pdata;
215 	struct davinci_spi_config *spicfg = spi->controller_data;
216 	u8 chip_sel = spi->chip_select;
217 	u16 spidat1 = CS_DEFAULT;
218 
219 	dspi = spi_master_get_devdata(spi->master);
220 	pdata = &dspi->pdata;
221 
222 	/* program delay transfers if tx_delay is non zero */
223 	if (spicfg->wdelay)
224 		spidat1 |= SPIDAT1_WDEL;
225 
226 	/*
227 	 * Board specific chip select logic decides the polarity and cs
228 	 * line for the controller
229 	 */
230 	if (spi->cs_gpio >= 0) {
231 		if (value == BITBANG_CS_ACTIVE)
232 			gpio_set_value(spi->cs_gpio, spi->mode & SPI_CS_HIGH);
233 		else
234 			gpio_set_value(spi->cs_gpio,
235 				!(spi->mode & SPI_CS_HIGH));
236 	} else {
237 		if (value == BITBANG_CS_ACTIVE) {
238 			spidat1 |= SPIDAT1_CSHOLD_MASK;
239 			spidat1 &= ~(0x1 << chip_sel);
240 		}
241 	}
242 
243 	iowrite16(spidat1, dspi->base + SPIDAT1 + 2);
244 }
245 
246 /**
247  * davinci_spi_get_prescale - Calculates the correct prescale value
248  * @maxspeed_hz: the maximum rate the SPI clock can run at
249  *
250  * This function calculates the prescale value that generates a clock rate
251  * less than or equal to the specified maximum.
252  *
253  * Returns: calculated prescale value for easy programming into SPI registers
254  * or negative error number if valid prescalar cannot be updated.
255  */
256 static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
257 							u32 max_speed_hz)
258 {
259 	int ret;
260 
261 	/* Subtract 1 to match what will be programmed into SPI register. */
262 	ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz) - 1;
263 
264 	if (ret < dspi->prescaler_limit || ret > 255)
265 		return -EINVAL;
266 
267 	return ret;
268 }
269 
270 /**
271  * davinci_spi_setup_transfer - This functions will determine transfer method
272  * @spi: spi device on which data transfer to be done
273  * @t: spi transfer in which transfer info is filled
274  *
275  * This function determines data transfer method (8/16/32 bit transfer).
276  * It will also set the SPI Clock Control register according to
277  * SPI slave device freq.
278  */
279 static int davinci_spi_setup_transfer(struct spi_device *spi,
280 		struct spi_transfer *t)
281 {
282 
283 	struct davinci_spi *dspi;
284 	struct davinci_spi_config *spicfg;
285 	u8 bits_per_word = 0;
286 	u32 hz = 0, spifmt = 0;
287 	int prescale;
288 
289 	dspi = spi_master_get_devdata(spi->master);
290 	spicfg = spi->controller_data;
291 	if (!spicfg)
292 		spicfg = &davinci_spi_default_cfg;
293 
294 	if (t) {
295 		bits_per_word = t->bits_per_word;
296 		hz = t->speed_hz;
297 	}
298 
299 	/* if bits_per_word is not set then set it default */
300 	if (!bits_per_word)
301 		bits_per_word = spi->bits_per_word;
302 
303 	/*
304 	 * Assign function pointer to appropriate transfer method
305 	 * 8bit, 16bit or 32bit transfer
306 	 */
307 	if (bits_per_word <= 8) {
308 		dspi->get_rx = davinci_spi_rx_buf_u8;
309 		dspi->get_tx = davinci_spi_tx_buf_u8;
310 		dspi->bytes_per_word[spi->chip_select] = 1;
311 	} else {
312 		dspi->get_rx = davinci_spi_rx_buf_u16;
313 		dspi->get_tx = davinci_spi_tx_buf_u16;
314 		dspi->bytes_per_word[spi->chip_select] = 2;
315 	}
316 
317 	if (!hz)
318 		hz = spi->max_speed_hz;
319 
320 	/* Set up SPIFMTn register, unique to this chipselect. */
321 
322 	prescale = davinci_spi_get_prescale(dspi, hz);
323 	if (prescale < 0)
324 		return prescale;
325 
326 	spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);
327 
328 	if (spi->mode & SPI_LSB_FIRST)
329 		spifmt |= SPIFMT_SHIFTDIR_MASK;
330 
331 	if (spi->mode & SPI_CPOL)
332 		spifmt |= SPIFMT_POLARITY_MASK;
333 
334 	if (!(spi->mode & SPI_CPHA))
335 		spifmt |= SPIFMT_PHASE_MASK;
336 
337 	/*
338 	* Assume wdelay is used only on SPI peripherals that has this field
339 	* in SPIFMTn register and when it's configured from board file or DT.
340 	*/
341 	if (spicfg->wdelay)
342 		spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
343 				& SPIFMT_WDELAY_MASK);
344 
345 	/*
346 	 * Version 1 hardware supports two basic SPI modes:
347 	 *  - Standard SPI mode uses 4 pins, with chipselect
348 	 *  - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
349 	 *	(distinct from SPI_3WIRE, with just one data wire;
350 	 *	or similar variants without MOSI or without MISO)
351 	 *
352 	 * Version 2 hardware supports an optional handshaking signal,
353 	 * so it can support two more modes:
354 	 *  - 5 pin SPI variant is standard SPI plus SPI_READY
355 	 *  - 4 pin with enable is (SPI_READY | SPI_NO_CS)
356 	 */
357 
358 	if (dspi->version == SPI_VERSION_2) {
359 
360 		u32 delay = 0;
361 
362 		if (spicfg->odd_parity)
363 			spifmt |= SPIFMT_ODD_PARITY_MASK;
364 
365 		if (spicfg->parity_enable)
366 			spifmt |= SPIFMT_PARITYENA_MASK;
367 
368 		if (spicfg->timer_disable) {
369 			spifmt |= SPIFMT_DISTIMER_MASK;
370 		} else {
371 			delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)
372 						& SPIDELAY_C2TDELAY_MASK;
373 			delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)
374 						& SPIDELAY_T2CDELAY_MASK;
375 		}
376 
377 		if (spi->mode & SPI_READY) {
378 			spifmt |= SPIFMT_WAITENA_MASK;
379 			delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)
380 						& SPIDELAY_T2EDELAY_MASK;
381 			delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)
382 						& SPIDELAY_C2EDELAY_MASK;
383 		}
384 
385 		iowrite32(delay, dspi->base + SPIDELAY);
386 	}
387 
388 	iowrite32(spifmt, dspi->base + SPIFMT0);
389 
390 	return 0;
391 }
392 
393 static int davinci_spi_of_setup(struct spi_device *spi)
394 {
395 	struct davinci_spi_config *spicfg = spi->controller_data;
396 	struct device_node *np = spi->dev.of_node;
397 	u32 prop;
398 
399 	if (spicfg == NULL && np) {
400 		spicfg = kzalloc(sizeof(*spicfg), GFP_KERNEL);
401 		if (!spicfg)
402 			return -ENOMEM;
403 		*spicfg = davinci_spi_default_cfg;
404 		/* override with dt configured values */
405 		if (!of_property_read_u32(np, "ti,spi-wdelay", &prop))
406 			spicfg->wdelay = (u8)prop;
407 		spi->controller_data = spicfg;
408 	}
409 
410 	return 0;
411 }
412 
413 /**
414  * davinci_spi_setup - This functions will set default transfer method
415  * @spi: spi device on which data transfer to be done
416  *
417  * This functions sets the default transfer method.
418  */
419 static int davinci_spi_setup(struct spi_device *spi)
420 {
421 	int retval = 0;
422 	struct davinci_spi *dspi;
423 	struct davinci_spi_platform_data *pdata;
424 	struct spi_master *master = spi->master;
425 	struct device_node *np = spi->dev.of_node;
426 	bool internal_cs = true;
427 
428 	dspi = spi_master_get_devdata(spi->master);
429 	pdata = &dspi->pdata;
430 
431 	if (!(spi->mode & SPI_NO_CS)) {
432 		if (np && (master->cs_gpios != NULL) && (spi->cs_gpio >= 0)) {
433 			retval = gpio_direction_output(
434 				      spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
435 			internal_cs = false;
436 		} else if (pdata->chip_sel &&
437 			   spi->chip_select < pdata->num_chipselect &&
438 			   pdata->chip_sel[spi->chip_select] != SPI_INTERN_CS) {
439 			spi->cs_gpio = pdata->chip_sel[spi->chip_select];
440 			retval = gpio_direction_output(
441 				      spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
442 			internal_cs = false;
443 		}
444 
445 		if (retval) {
446 			dev_err(&spi->dev, "GPIO %d setup failed (%d)\n",
447 				spi->cs_gpio, retval);
448 			return retval;
449 		}
450 
451 		if (internal_cs)
452 			set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
453 	}
454 
455 	if (spi->mode & SPI_READY)
456 		set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
457 
458 	if (spi->mode & SPI_LOOP)
459 		set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
460 	else
461 		clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
462 
463 	return davinci_spi_of_setup(spi);
464 }
465 
466 static void davinci_spi_cleanup(struct spi_device *spi)
467 {
468 	struct davinci_spi_config *spicfg = spi->controller_data;
469 
470 	spi->controller_data = NULL;
471 	if (spi->dev.of_node)
472 		kfree(spicfg);
473 }
474 
475 static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
476 {
477 	struct device *sdev = dspi->bitbang.master->dev.parent;
478 
479 	if (int_status & SPIFLG_TIMEOUT_MASK) {
480 		dev_dbg(sdev, "SPI Time-out Error\n");
481 		return -ETIMEDOUT;
482 	}
483 	if (int_status & SPIFLG_DESYNC_MASK) {
484 		dev_dbg(sdev, "SPI Desynchronization Error\n");
485 		return -EIO;
486 	}
487 	if (int_status & SPIFLG_BITERR_MASK) {
488 		dev_dbg(sdev, "SPI Bit error\n");
489 		return -EIO;
490 	}
491 
492 	if (dspi->version == SPI_VERSION_2) {
493 		if (int_status & SPIFLG_DLEN_ERR_MASK) {
494 			dev_dbg(sdev, "SPI Data Length Error\n");
495 			return -EIO;
496 		}
497 		if (int_status & SPIFLG_PARERR_MASK) {
498 			dev_dbg(sdev, "SPI Parity Error\n");
499 			return -EIO;
500 		}
501 		if (int_status & SPIFLG_OVRRUN_MASK) {
502 			dev_dbg(sdev, "SPI Data Overrun error\n");
503 			return -EIO;
504 		}
505 		if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
506 			dev_dbg(sdev, "SPI Buffer Init Active\n");
507 			return -EBUSY;
508 		}
509 	}
510 
511 	return 0;
512 }
513 
514 /**
515  * davinci_spi_process_events - check for and handle any SPI controller events
516  * @dspi: the controller data
517  *
518  * This function will check the SPIFLG register and handle any events that are
519  * detected there
520  */
521 static int davinci_spi_process_events(struct davinci_spi *dspi)
522 {
523 	u32 buf, status, errors = 0, spidat1;
524 
525 	buf = ioread32(dspi->base + SPIBUF);
526 
527 	if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
528 		dspi->get_rx(buf & 0xFFFF, dspi);
529 		dspi->rcount--;
530 	}
531 
532 	status = ioread32(dspi->base + SPIFLG);
533 
534 	if (unlikely(status & SPIFLG_ERROR_MASK)) {
535 		errors = status & SPIFLG_ERROR_MASK;
536 		goto out;
537 	}
538 
539 	if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
540 		spidat1 = ioread32(dspi->base + SPIDAT1);
541 		dspi->wcount--;
542 		spidat1 &= ~0xFFFF;
543 		spidat1 |= 0xFFFF & dspi->get_tx(dspi);
544 		iowrite32(spidat1, dspi->base + SPIDAT1);
545 	}
546 
547 out:
548 	return errors;
549 }
550 
551 static void davinci_spi_dma_rx_callback(void *data)
552 {
553 	struct davinci_spi *dspi = (struct davinci_spi *)data;
554 
555 	dspi->rcount = 0;
556 
557 	if (!dspi->wcount && !dspi->rcount)
558 		complete(&dspi->done);
559 }
560 
561 static void davinci_spi_dma_tx_callback(void *data)
562 {
563 	struct davinci_spi *dspi = (struct davinci_spi *)data;
564 
565 	dspi->wcount = 0;
566 
567 	if (!dspi->wcount && !dspi->rcount)
568 		complete(&dspi->done);
569 }
570 
571 /**
572  * davinci_spi_bufs - functions which will handle transfer data
573  * @spi: spi device on which data transfer to be done
574  * @t: spi transfer in which transfer info is filled
575  *
576  * This function will put data to be transferred into data register
577  * of SPI controller and then wait until the completion will be marked
578  * by the IRQ Handler.
579  */
580 static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
581 {
582 	struct davinci_spi *dspi;
583 	int data_type, ret = -ENOMEM;
584 	u32 tx_data, spidat1;
585 	u32 errors = 0;
586 	struct davinci_spi_config *spicfg;
587 	struct davinci_spi_platform_data *pdata;
588 	unsigned uninitialized_var(rx_buf_count);
589 	void *dummy_buf = NULL;
590 	struct scatterlist sg_rx, sg_tx;
591 
592 	dspi = spi_master_get_devdata(spi->master);
593 	pdata = &dspi->pdata;
594 	spicfg = (struct davinci_spi_config *)spi->controller_data;
595 	if (!spicfg)
596 		spicfg = &davinci_spi_default_cfg;
597 
598 	/* convert len to words based on bits_per_word */
599 	data_type = dspi->bytes_per_word[spi->chip_select];
600 
601 	dspi->tx = t->tx_buf;
602 	dspi->rx = t->rx_buf;
603 	dspi->wcount = t->len / data_type;
604 	dspi->rcount = dspi->wcount;
605 
606 	spidat1 = ioread32(dspi->base + SPIDAT1);
607 
608 	clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
609 	set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
610 
611 	reinit_completion(&dspi->done);
612 
613 	if (spicfg->io_type == SPI_IO_TYPE_INTR)
614 		set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
615 
616 	if (spicfg->io_type != SPI_IO_TYPE_DMA) {
617 		/* start the transfer */
618 		dspi->wcount--;
619 		tx_data = dspi->get_tx(dspi);
620 		spidat1 &= 0xFFFF0000;
621 		spidat1 |= tx_data & 0xFFFF;
622 		iowrite32(spidat1, dspi->base + SPIDAT1);
623 	} else {
624 		struct dma_slave_config dma_rx_conf = {
625 			.direction = DMA_DEV_TO_MEM,
626 			.src_addr = (unsigned long)dspi->pbase + SPIBUF,
627 			.src_addr_width = data_type,
628 			.src_maxburst = 1,
629 		};
630 		struct dma_slave_config dma_tx_conf = {
631 			.direction = DMA_MEM_TO_DEV,
632 			.dst_addr = (unsigned long)dspi->pbase + SPIDAT1,
633 			.dst_addr_width = data_type,
634 			.dst_maxburst = 1,
635 		};
636 		struct dma_async_tx_descriptor *rxdesc;
637 		struct dma_async_tx_descriptor *txdesc;
638 		void *buf;
639 
640 		dummy_buf = kzalloc(t->len, GFP_KERNEL);
641 		if (!dummy_buf)
642 			goto err_alloc_dummy_buf;
643 
644 		dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf);
645 		dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf);
646 
647 		sg_init_table(&sg_rx, 1);
648 		if (!t->rx_buf)
649 			buf = dummy_buf;
650 		else
651 			buf = t->rx_buf;
652 		t->rx_dma = dma_map_single(&spi->dev, buf,
653 				t->len, DMA_FROM_DEVICE);
654 		if (!t->rx_dma) {
655 			ret = -EFAULT;
656 			goto err_rx_map;
657 		}
658 		sg_dma_address(&sg_rx) = t->rx_dma;
659 		sg_dma_len(&sg_rx) = t->len;
660 
661 		sg_init_table(&sg_tx, 1);
662 		if (!t->tx_buf)
663 			buf = dummy_buf;
664 		else
665 			buf = (void *)t->tx_buf;
666 		t->tx_dma = dma_map_single(&spi->dev, buf,
667 				t->len, DMA_TO_DEVICE);
668 		if (!t->tx_dma) {
669 			ret = -EFAULT;
670 			goto err_tx_map;
671 		}
672 		sg_dma_address(&sg_tx) = t->tx_dma;
673 		sg_dma_len(&sg_tx) = t->len;
674 
675 		rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx,
676 				&sg_rx, 1, DMA_DEV_TO_MEM,
677 				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
678 		if (!rxdesc)
679 			goto err_desc;
680 
681 		txdesc = dmaengine_prep_slave_sg(dspi->dma_tx,
682 				&sg_tx, 1, DMA_MEM_TO_DEV,
683 				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
684 		if (!txdesc)
685 			goto err_desc;
686 
687 		rxdesc->callback = davinci_spi_dma_rx_callback;
688 		rxdesc->callback_param = (void *)dspi;
689 		txdesc->callback = davinci_spi_dma_tx_callback;
690 		txdesc->callback_param = (void *)dspi;
691 
692 		if (pdata->cshold_bug)
693 			iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
694 
695 		dmaengine_submit(rxdesc);
696 		dmaengine_submit(txdesc);
697 
698 		dma_async_issue_pending(dspi->dma_rx);
699 		dma_async_issue_pending(dspi->dma_tx);
700 
701 		set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
702 	}
703 
704 	/* Wait for the transfer to complete */
705 	if (spicfg->io_type != SPI_IO_TYPE_POLL) {
706 		wait_for_completion_interruptible(&(dspi->done));
707 	} else {
708 		while (dspi->rcount > 0 || dspi->wcount > 0) {
709 			errors = davinci_spi_process_events(dspi);
710 			if (errors)
711 				break;
712 			cpu_relax();
713 		}
714 	}
715 
716 	clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
717 	if (spicfg->io_type == SPI_IO_TYPE_DMA) {
718 		clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
719 
720 		dma_unmap_single(&spi->dev, t->rx_dma,
721 				t->len, DMA_FROM_DEVICE);
722 		dma_unmap_single(&spi->dev, t->tx_dma,
723 				t->len, DMA_TO_DEVICE);
724 		kfree(dummy_buf);
725 	}
726 
727 	clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
728 	set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
729 
730 	/*
731 	 * Check for bit error, desync error,parity error,timeout error and
732 	 * receive overflow errors
733 	 */
734 	if (errors) {
735 		ret = davinci_spi_check_error(dspi, errors);
736 		WARN(!ret, "%s: error reported but no error found!\n",
737 							dev_name(&spi->dev));
738 		return ret;
739 	}
740 
741 	if (dspi->rcount != 0 || dspi->wcount != 0) {
742 		dev_err(&spi->dev, "SPI data transfer error\n");
743 		return -EIO;
744 	}
745 
746 	return t->len;
747 
748 err_desc:
749 	dma_unmap_single(&spi->dev, t->tx_dma, t->len, DMA_TO_DEVICE);
750 err_tx_map:
751 	dma_unmap_single(&spi->dev, t->rx_dma, t->len, DMA_FROM_DEVICE);
752 err_rx_map:
753 	kfree(dummy_buf);
754 err_alloc_dummy_buf:
755 	return ret;
756 }
757 
758 /**
759  * dummy_thread_fn - dummy thread function
760  * @irq: IRQ number for this SPI Master
761  * @context_data: structure for SPI Master controller davinci_spi
762  *
763  * This is to satisfy the request_threaded_irq() API so that the irq
764  * handler is called in interrupt context.
765  */
766 static irqreturn_t dummy_thread_fn(s32 irq, void *data)
767 {
768 	return IRQ_HANDLED;
769 }
770 
771 /**
772  * davinci_spi_irq - Interrupt handler for SPI Master Controller
773  * @irq: IRQ number for this SPI Master
774  * @context_data: structure for SPI Master controller davinci_spi
775  *
776  * ISR will determine that interrupt arrives either for READ or WRITE command.
777  * According to command it will do the appropriate action. It will check
778  * transfer length and if it is not zero then dispatch transfer command again.
779  * If transfer length is zero then it will indicate the COMPLETION so that
780  * davinci_spi_bufs function can go ahead.
781  */
782 static irqreturn_t davinci_spi_irq(s32 irq, void *data)
783 {
784 	struct davinci_spi *dspi = data;
785 	int status;
786 
787 	status = davinci_spi_process_events(dspi);
788 	if (unlikely(status != 0))
789 		clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
790 
791 	if ((!dspi->rcount && !dspi->wcount) || status)
792 		complete(&dspi->done);
793 
794 	return IRQ_HANDLED;
795 }
796 
797 static int davinci_spi_request_dma(struct davinci_spi *dspi)
798 {
799 	dma_cap_mask_t mask;
800 	struct device *sdev = dspi->bitbang.master->dev.parent;
801 	int r;
802 
803 	dma_cap_zero(mask);
804 	dma_cap_set(DMA_SLAVE, mask);
805 
806 	dspi->dma_rx = dma_request_channel(mask, edma_filter_fn,
807 					   &dspi->dma_rx_chnum);
808 	if (!dspi->dma_rx) {
809 		dev_err(sdev, "request RX DMA channel failed\n");
810 		r = -ENODEV;
811 		goto rx_dma_failed;
812 	}
813 
814 	dspi->dma_tx = dma_request_channel(mask, edma_filter_fn,
815 					   &dspi->dma_tx_chnum);
816 	if (!dspi->dma_tx) {
817 		dev_err(sdev, "request TX DMA channel failed\n");
818 		r = -ENODEV;
819 		goto tx_dma_failed;
820 	}
821 
822 	return 0;
823 
824 tx_dma_failed:
825 	dma_release_channel(dspi->dma_rx);
826 rx_dma_failed:
827 	return r;
828 }
829 
830 #if defined(CONFIG_OF)
831 
832 /* OF SPI data structure */
833 struct davinci_spi_of_data {
834 	u8	version;
835 	u8	prescaler_limit;
836 };
837 
838 static const struct davinci_spi_of_data dm6441_spi_data = {
839 	.version = SPI_VERSION_1,
840 	.prescaler_limit = 2,
841 };
842 
843 static const struct davinci_spi_of_data da830_spi_data = {
844 	.version = SPI_VERSION_2,
845 	.prescaler_limit = 2,
846 };
847 
848 static const struct davinci_spi_of_data keystone_spi_data = {
849 	.version = SPI_VERSION_1,
850 	.prescaler_limit = 0,
851 };
852 
853 static const struct of_device_id davinci_spi_of_match[] = {
854 	{
855 		.compatible = "ti,dm6441-spi",
856 		.data = &dm6441_spi_data,
857 	},
858 	{
859 		.compatible = "ti,da830-spi",
860 		.data = &da830_spi_data,
861 	},
862 	{
863 		.compatible = "ti,keystone-spi",
864 		.data = &keystone_spi_data,
865 	},
866 	{ },
867 };
868 MODULE_DEVICE_TABLE(of, davinci_spi_of_match);
869 
870 /**
871  * spi_davinci_get_pdata - Get platform data from DTS binding
872  * @pdev: ptr to platform data
873  * @dspi: ptr to driver data
874  *
875  * Parses and populates pdata in dspi from device tree bindings.
876  *
877  * NOTE: Not all platform data params are supported currently.
878  */
879 static int spi_davinci_get_pdata(struct platform_device *pdev,
880 			struct davinci_spi *dspi)
881 {
882 	struct device_node *node = pdev->dev.of_node;
883 	struct davinci_spi_of_data *spi_data;
884 	struct davinci_spi_platform_data *pdata;
885 	unsigned int num_cs, intr_line = 0;
886 	const struct of_device_id *match;
887 
888 	pdata = &dspi->pdata;
889 
890 	match = of_match_device(davinci_spi_of_match, &pdev->dev);
891 	if (!match)
892 		return -ENODEV;
893 
894 	spi_data = (struct davinci_spi_of_data *)match->data;
895 
896 	pdata->version = spi_data->version;
897 	pdata->prescaler_limit = spi_data->prescaler_limit;
898 	/*
899 	 * default num_cs is 1 and all chipsel are internal to the chip
900 	 * indicated by chip_sel being NULL or cs_gpios being NULL or
901 	 * set to -ENOENT. num-cs includes internal as well as gpios.
902 	 * indicated by chip_sel being NULL. GPIO based CS is not
903 	 * supported yet in DT bindings.
904 	 */
905 	num_cs = 1;
906 	of_property_read_u32(node, "num-cs", &num_cs);
907 	pdata->num_chipselect = num_cs;
908 	of_property_read_u32(node, "ti,davinci-spi-intr-line", &intr_line);
909 	pdata->intr_line = intr_line;
910 	return 0;
911 }
912 #else
913 static struct davinci_spi_platform_data
914 	*spi_davinci_get_pdata(struct platform_device *pdev,
915 		struct davinci_spi *dspi)
916 {
917 	return -ENODEV;
918 }
919 #endif
920 
921 /**
922  * davinci_spi_probe - probe function for SPI Master Controller
923  * @pdev: platform_device structure which contains plateform specific data
924  *
925  * According to Linux Device Model this function will be invoked by Linux
926  * with platform_device struct which contains the device specific info.
927  * This function will map the SPI controller's memory, register IRQ,
928  * Reset SPI controller and setting its registers to default value.
929  * It will invoke spi_bitbang_start to create work queue so that client driver
930  * can register transfer method to work queue.
931  */
932 static int davinci_spi_probe(struct platform_device *pdev)
933 {
934 	struct spi_master *master;
935 	struct davinci_spi *dspi;
936 	struct davinci_spi_platform_data *pdata;
937 	struct resource *r;
938 	resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
939 	resource_size_t	dma_tx_chan = SPI_NO_RESOURCE;
940 	int ret = 0;
941 	u32 spipc0;
942 
943 	master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
944 	if (master == NULL) {
945 		ret = -ENOMEM;
946 		goto err;
947 	}
948 
949 	platform_set_drvdata(pdev, master);
950 
951 	dspi = spi_master_get_devdata(master);
952 
953 	if (dev_get_platdata(&pdev->dev)) {
954 		pdata = dev_get_platdata(&pdev->dev);
955 		dspi->pdata = *pdata;
956 	} else {
957 		/* update dspi pdata with that from the DT */
958 		ret = spi_davinci_get_pdata(pdev, dspi);
959 		if (ret < 0)
960 			goto free_master;
961 	}
962 
963 	/* pdata in dspi is now updated and point pdata to that */
964 	pdata = &dspi->pdata;
965 
966 	dspi->bytes_per_word = devm_kzalloc(&pdev->dev,
967 					    sizeof(*dspi->bytes_per_word) *
968 					    pdata->num_chipselect, GFP_KERNEL);
969 	if (dspi->bytes_per_word == NULL) {
970 		ret = -ENOMEM;
971 		goto free_master;
972 	}
973 
974 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
975 	if (r == NULL) {
976 		ret = -ENOENT;
977 		goto free_master;
978 	}
979 
980 	dspi->pbase = r->start;
981 
982 	dspi->base = devm_ioremap_resource(&pdev->dev, r);
983 	if (IS_ERR(dspi->base)) {
984 		ret = PTR_ERR(dspi->base);
985 		goto free_master;
986 	}
987 
988 	ret = platform_get_irq(pdev, 0);
989 	if (ret == 0)
990 		ret = -EINVAL;
991 	if (ret < 0)
992 		goto free_master;
993 	dspi->irq = ret;
994 
995 	ret = devm_request_threaded_irq(&pdev->dev, dspi->irq, davinci_spi_irq,
996 				dummy_thread_fn, 0, dev_name(&pdev->dev), dspi);
997 	if (ret)
998 		goto free_master;
999 
1000 	dspi->bitbang.master = master;
1001 
1002 	dspi->clk = devm_clk_get(&pdev->dev, NULL);
1003 	if (IS_ERR(dspi->clk)) {
1004 		ret = -ENODEV;
1005 		goto free_master;
1006 	}
1007 	clk_prepare_enable(dspi->clk);
1008 
1009 	master->dev.of_node = pdev->dev.of_node;
1010 	master->bus_num = pdev->id;
1011 	master->num_chipselect = pdata->num_chipselect;
1012 	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16);
1013 	master->setup = davinci_spi_setup;
1014 	master->cleanup = davinci_spi_cleanup;
1015 
1016 	dspi->bitbang.chipselect = davinci_spi_chipselect;
1017 	dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;
1018 	dspi->prescaler_limit = pdata->prescaler_limit;
1019 	dspi->version = pdata->version;
1020 
1021 	dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
1022 	if (dspi->version == SPI_VERSION_2)
1023 		dspi->bitbang.flags |= SPI_READY;
1024 
1025 	if (pdev->dev.of_node) {
1026 		int i;
1027 
1028 		for (i = 0; i < pdata->num_chipselect; i++) {
1029 			int cs_gpio = of_get_named_gpio(pdev->dev.of_node,
1030 							"cs-gpios", i);
1031 
1032 			if (cs_gpio == -EPROBE_DEFER) {
1033 				ret = cs_gpio;
1034 				goto free_clk;
1035 			}
1036 
1037 			if (gpio_is_valid(cs_gpio)) {
1038 				ret = devm_gpio_request(&pdev->dev, cs_gpio,
1039 							dev_name(&pdev->dev));
1040 				if (ret)
1041 					goto free_clk;
1042 			}
1043 		}
1044 	}
1045 
1046 	r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1047 	if (r)
1048 		dma_rx_chan = r->start;
1049 	r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1050 	if (r)
1051 		dma_tx_chan = r->start;
1052 
1053 	dspi->bitbang.txrx_bufs = davinci_spi_bufs;
1054 	if (dma_rx_chan != SPI_NO_RESOURCE &&
1055 	    dma_tx_chan != SPI_NO_RESOURCE) {
1056 		dspi->dma_rx_chnum = dma_rx_chan;
1057 		dspi->dma_tx_chnum = dma_tx_chan;
1058 
1059 		ret = davinci_spi_request_dma(dspi);
1060 		if (ret)
1061 			goto free_clk;
1062 
1063 		dev_info(&pdev->dev, "DMA: supported\n");
1064 		dev_info(&pdev->dev, "DMA: RX channel: %pa, TX channel: %pa, event queue: %d\n",
1065 				&dma_rx_chan, &dma_tx_chan,
1066 				pdata->dma_event_q);
1067 	}
1068 
1069 	dspi->get_rx = davinci_spi_rx_buf_u8;
1070 	dspi->get_tx = davinci_spi_tx_buf_u8;
1071 
1072 	init_completion(&dspi->done);
1073 
1074 	/* Reset In/OUT SPI module */
1075 	iowrite32(0, dspi->base + SPIGCR0);
1076 	udelay(100);
1077 	iowrite32(1, dspi->base + SPIGCR0);
1078 
1079 	/* Set up SPIPC0.  CS and ENA init is done in davinci_spi_setup */
1080 	spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
1081 	iowrite32(spipc0, dspi->base + SPIPC0);
1082 
1083 	if (pdata->intr_line)
1084 		iowrite32(SPI_INTLVL_1, dspi->base + SPILVL);
1085 	else
1086 		iowrite32(SPI_INTLVL_0, dspi->base + SPILVL);
1087 
1088 	iowrite32(CS_DEFAULT, dspi->base + SPIDEF);
1089 
1090 	/* master mode default */
1091 	set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);
1092 	set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
1093 	set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
1094 
1095 	ret = spi_bitbang_start(&dspi->bitbang);
1096 	if (ret)
1097 		goto free_dma;
1098 
1099 	dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base);
1100 
1101 	return ret;
1102 
1103 free_dma:
1104 	dma_release_channel(dspi->dma_rx);
1105 	dma_release_channel(dspi->dma_tx);
1106 free_clk:
1107 	clk_disable_unprepare(dspi->clk);
1108 free_master:
1109 	spi_master_put(master);
1110 err:
1111 	return ret;
1112 }
1113 
1114 /**
1115  * davinci_spi_remove - remove function for SPI Master Controller
1116  * @pdev: platform_device structure which contains plateform specific data
1117  *
1118  * This function will do the reverse action of davinci_spi_probe function
1119  * It will free the IRQ and SPI controller's memory region.
1120  * It will also call spi_bitbang_stop to destroy the work queue which was
1121  * created by spi_bitbang_start.
1122  */
1123 static int davinci_spi_remove(struct platform_device *pdev)
1124 {
1125 	struct davinci_spi *dspi;
1126 	struct spi_master *master;
1127 
1128 	master = platform_get_drvdata(pdev);
1129 	dspi = spi_master_get_devdata(master);
1130 
1131 	spi_bitbang_stop(&dspi->bitbang);
1132 
1133 	clk_disable_unprepare(dspi->clk);
1134 	spi_master_put(master);
1135 
1136 	return 0;
1137 }
1138 
1139 static struct platform_driver davinci_spi_driver = {
1140 	.driver = {
1141 		.name = "spi_davinci",
1142 		.of_match_table = of_match_ptr(davinci_spi_of_match),
1143 	},
1144 	.probe = davinci_spi_probe,
1145 	.remove = davinci_spi_remove,
1146 };
1147 module_platform_driver(davinci_spi_driver);
1148 
1149 MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
1150 MODULE_LICENSE("GPL");
1151