1 /* 2 * Copyright (C) 2009 Texas Instruments. 3 * Copyright (C) 2010 EF Johnson Technologies 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/gpio.h> 23 #include <linux/module.h> 24 #include <linux/delay.h> 25 #include <linux/platform_device.h> 26 #include <linux/err.h> 27 #include <linux/clk.h> 28 #include <linux/dmaengine.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/edma.h> 31 #include <linux/of.h> 32 #include <linux/of_device.h> 33 #include <linux/of_gpio.h> 34 #include <linux/spi/spi.h> 35 #include <linux/spi/spi_bitbang.h> 36 #include <linux/slab.h> 37 38 #include <linux/platform_data/spi-davinci.h> 39 40 #define SPI_NO_RESOURCE ((resource_size_t)-1) 41 42 #define CS_DEFAULT 0xFF 43 44 #define SPIFMT_PHASE_MASK BIT(16) 45 #define SPIFMT_POLARITY_MASK BIT(17) 46 #define SPIFMT_DISTIMER_MASK BIT(18) 47 #define SPIFMT_SHIFTDIR_MASK BIT(20) 48 #define SPIFMT_WAITENA_MASK BIT(21) 49 #define SPIFMT_PARITYENA_MASK BIT(22) 50 #define SPIFMT_ODD_PARITY_MASK BIT(23) 51 #define SPIFMT_WDELAY_MASK 0x3f000000u 52 #define SPIFMT_WDELAY_SHIFT 24 53 #define SPIFMT_PRESCALE_SHIFT 8 54 55 /* SPIPC0 */ 56 #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ 57 #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ 58 #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ 59 #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ 60 61 #define SPIINT_MASKALL 0x0101035F 62 #define SPIINT_MASKINT 0x0000015F 63 #define SPI_INTLVL_1 0x000001FF 64 #define SPI_INTLVL_0 0x00000000 65 66 /* SPIDAT1 (upper 16 bit defines) */ 67 #define SPIDAT1_CSHOLD_MASK BIT(12) 68 69 /* SPIGCR1 */ 70 #define SPIGCR1_CLKMOD_MASK BIT(1) 71 #define SPIGCR1_MASTER_MASK BIT(0) 72 #define SPIGCR1_POWERDOWN_MASK BIT(8) 73 #define SPIGCR1_LOOPBACK_MASK BIT(16) 74 #define SPIGCR1_SPIENA_MASK BIT(24) 75 76 /* SPIBUF */ 77 #define SPIBUF_TXFULL_MASK BIT(29) 78 #define SPIBUF_RXEMPTY_MASK BIT(31) 79 80 /* SPIDELAY */ 81 #define SPIDELAY_C2TDELAY_SHIFT 24 82 #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT) 83 #define SPIDELAY_T2CDELAY_SHIFT 16 84 #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT) 85 #define SPIDELAY_T2EDELAY_SHIFT 8 86 #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT) 87 #define SPIDELAY_C2EDELAY_SHIFT 0 88 #define SPIDELAY_C2EDELAY_MASK 0xFF 89 90 /* Error Masks */ 91 #define SPIFLG_DLEN_ERR_MASK BIT(0) 92 #define SPIFLG_TIMEOUT_MASK BIT(1) 93 #define SPIFLG_PARERR_MASK BIT(2) 94 #define SPIFLG_DESYNC_MASK BIT(3) 95 #define SPIFLG_BITERR_MASK BIT(4) 96 #define SPIFLG_OVRRUN_MASK BIT(6) 97 #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) 98 #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ 99 | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ 100 | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ 101 | SPIFLG_OVRRUN_MASK) 102 103 #define SPIINT_DMA_REQ_EN BIT(16) 104 105 /* SPI Controller registers */ 106 #define SPIGCR0 0x00 107 #define SPIGCR1 0x04 108 #define SPIINT 0x08 109 #define SPILVL 0x0c 110 #define SPIFLG 0x10 111 #define SPIPC0 0x14 112 #define SPIDAT1 0x3c 113 #define SPIBUF 0x40 114 #define SPIDELAY 0x48 115 #define SPIDEF 0x4c 116 #define SPIFMT0 0x50 117 118 /* SPI Controller driver's private data. */ 119 struct davinci_spi { 120 struct spi_bitbang bitbang; 121 struct clk *clk; 122 123 u8 version; 124 resource_size_t pbase; 125 void __iomem *base; 126 u32 irq; 127 struct completion done; 128 129 const void *tx; 130 void *rx; 131 int rcount; 132 int wcount; 133 134 struct dma_chan *dma_rx; 135 struct dma_chan *dma_tx; 136 int dma_rx_chnum; 137 int dma_tx_chnum; 138 139 struct davinci_spi_platform_data pdata; 140 141 void (*get_rx)(u32 rx_data, struct davinci_spi *); 142 u32 (*get_tx)(struct davinci_spi *); 143 144 u8 *bytes_per_word; 145 }; 146 147 static struct davinci_spi_config davinci_spi_default_cfg; 148 149 static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi) 150 { 151 if (dspi->rx) { 152 u8 *rx = dspi->rx; 153 *rx++ = (u8)data; 154 dspi->rx = rx; 155 } 156 } 157 158 static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi) 159 { 160 if (dspi->rx) { 161 u16 *rx = dspi->rx; 162 *rx++ = (u16)data; 163 dspi->rx = rx; 164 } 165 } 166 167 static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi) 168 { 169 u32 data = 0; 170 if (dspi->tx) { 171 const u8 *tx = dspi->tx; 172 data = *tx++; 173 dspi->tx = tx; 174 } 175 return data; 176 } 177 178 static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi) 179 { 180 u32 data = 0; 181 if (dspi->tx) { 182 const u16 *tx = dspi->tx; 183 data = *tx++; 184 dspi->tx = tx; 185 } 186 return data; 187 } 188 189 static inline void set_io_bits(void __iomem *addr, u32 bits) 190 { 191 u32 v = ioread32(addr); 192 193 v |= bits; 194 iowrite32(v, addr); 195 } 196 197 static inline void clear_io_bits(void __iomem *addr, u32 bits) 198 { 199 u32 v = ioread32(addr); 200 201 v &= ~bits; 202 iowrite32(v, addr); 203 } 204 205 /* 206 * Interface to control the chip select signal 207 */ 208 static void davinci_spi_chipselect(struct spi_device *spi, int value) 209 { 210 struct davinci_spi *dspi; 211 struct davinci_spi_platform_data *pdata; 212 u8 chip_sel = spi->chip_select; 213 u16 spidat1 = CS_DEFAULT; 214 bool gpio_chipsel = false; 215 int gpio; 216 217 dspi = spi_master_get_devdata(spi->master); 218 pdata = &dspi->pdata; 219 220 if (spi->cs_gpio >= 0) { 221 /* SPI core parse and update master->cs_gpio */ 222 gpio_chipsel = true; 223 gpio = spi->cs_gpio; 224 } 225 226 /* 227 * Board specific chip select logic decides the polarity and cs 228 * line for the controller 229 */ 230 if (gpio_chipsel) { 231 if (value == BITBANG_CS_ACTIVE) 232 gpio_set_value(gpio, spi->mode & SPI_CS_HIGH); 233 else 234 gpio_set_value(gpio, !(spi->mode & SPI_CS_HIGH)); 235 } else { 236 if (value == BITBANG_CS_ACTIVE) { 237 spidat1 |= SPIDAT1_CSHOLD_MASK; 238 spidat1 &= ~(0x1 << chip_sel); 239 } 240 241 iowrite16(spidat1, dspi->base + SPIDAT1 + 2); 242 } 243 } 244 245 /** 246 * davinci_spi_get_prescale - Calculates the correct prescale value 247 * @maxspeed_hz: the maximum rate the SPI clock can run at 248 * 249 * This function calculates the prescale value that generates a clock rate 250 * less than or equal to the specified maximum. 251 * 252 * Returns: calculated prescale - 1 for easy programming into SPI registers 253 * or negative error number if valid prescalar cannot be updated. 254 */ 255 static inline int davinci_spi_get_prescale(struct davinci_spi *dspi, 256 u32 max_speed_hz) 257 { 258 int ret; 259 260 ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz); 261 262 if (ret < 3 || ret > 256) 263 return -EINVAL; 264 265 return ret - 1; 266 } 267 268 /** 269 * davinci_spi_setup_transfer - This functions will determine transfer method 270 * @spi: spi device on which data transfer to be done 271 * @t: spi transfer in which transfer info is filled 272 * 273 * This function determines data transfer method (8/16/32 bit transfer). 274 * It will also set the SPI Clock Control register according to 275 * SPI slave device freq. 276 */ 277 static int davinci_spi_setup_transfer(struct spi_device *spi, 278 struct spi_transfer *t) 279 { 280 281 struct davinci_spi *dspi; 282 struct davinci_spi_config *spicfg; 283 u8 bits_per_word = 0; 284 u32 hz = 0, spifmt = 0; 285 int prescale; 286 287 dspi = spi_master_get_devdata(spi->master); 288 spicfg = (struct davinci_spi_config *)spi->controller_data; 289 if (!spicfg) 290 spicfg = &davinci_spi_default_cfg; 291 292 if (t) { 293 bits_per_word = t->bits_per_word; 294 hz = t->speed_hz; 295 } 296 297 /* if bits_per_word is not set then set it default */ 298 if (!bits_per_word) 299 bits_per_word = spi->bits_per_word; 300 301 /* 302 * Assign function pointer to appropriate transfer method 303 * 8bit, 16bit or 32bit transfer 304 */ 305 if (bits_per_word <= 8) { 306 dspi->get_rx = davinci_spi_rx_buf_u8; 307 dspi->get_tx = davinci_spi_tx_buf_u8; 308 dspi->bytes_per_word[spi->chip_select] = 1; 309 } else { 310 dspi->get_rx = davinci_spi_rx_buf_u16; 311 dspi->get_tx = davinci_spi_tx_buf_u16; 312 dspi->bytes_per_word[spi->chip_select] = 2; 313 } 314 315 if (!hz) 316 hz = spi->max_speed_hz; 317 318 /* Set up SPIFMTn register, unique to this chipselect. */ 319 320 prescale = davinci_spi_get_prescale(dspi, hz); 321 if (prescale < 0) 322 return prescale; 323 324 spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f); 325 326 if (spi->mode & SPI_LSB_FIRST) 327 spifmt |= SPIFMT_SHIFTDIR_MASK; 328 329 if (spi->mode & SPI_CPOL) 330 spifmt |= SPIFMT_POLARITY_MASK; 331 332 if (!(spi->mode & SPI_CPHA)) 333 spifmt |= SPIFMT_PHASE_MASK; 334 335 /* 336 * Version 1 hardware supports two basic SPI modes: 337 * - Standard SPI mode uses 4 pins, with chipselect 338 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) 339 * (distinct from SPI_3WIRE, with just one data wire; 340 * or similar variants without MOSI or without MISO) 341 * 342 * Version 2 hardware supports an optional handshaking signal, 343 * so it can support two more modes: 344 * - 5 pin SPI variant is standard SPI plus SPI_READY 345 * - 4 pin with enable is (SPI_READY | SPI_NO_CS) 346 */ 347 348 if (dspi->version == SPI_VERSION_2) { 349 350 u32 delay = 0; 351 352 spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT) 353 & SPIFMT_WDELAY_MASK); 354 355 if (spicfg->odd_parity) 356 spifmt |= SPIFMT_ODD_PARITY_MASK; 357 358 if (spicfg->parity_enable) 359 spifmt |= SPIFMT_PARITYENA_MASK; 360 361 if (spicfg->timer_disable) { 362 spifmt |= SPIFMT_DISTIMER_MASK; 363 } else { 364 delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT) 365 & SPIDELAY_C2TDELAY_MASK; 366 delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT) 367 & SPIDELAY_T2CDELAY_MASK; 368 } 369 370 if (spi->mode & SPI_READY) { 371 spifmt |= SPIFMT_WAITENA_MASK; 372 delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT) 373 & SPIDELAY_T2EDELAY_MASK; 374 delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT) 375 & SPIDELAY_C2EDELAY_MASK; 376 } 377 378 iowrite32(delay, dspi->base + SPIDELAY); 379 } 380 381 iowrite32(spifmt, dspi->base + SPIFMT0); 382 383 return 0; 384 } 385 386 /** 387 * davinci_spi_setup - This functions will set default transfer method 388 * @spi: spi device on which data transfer to be done 389 * 390 * This functions sets the default transfer method. 391 */ 392 static int davinci_spi_setup(struct spi_device *spi) 393 { 394 int retval = 0; 395 struct davinci_spi *dspi; 396 struct davinci_spi_platform_data *pdata; 397 struct spi_master *master = spi->master; 398 struct device_node *np = spi->dev.of_node; 399 bool internal_cs = true; 400 unsigned long flags = GPIOF_DIR_OUT; 401 402 dspi = spi_master_get_devdata(spi->master); 403 pdata = &dspi->pdata; 404 405 flags |= (spi->mode & SPI_CS_HIGH) ? GPIOF_INIT_LOW : GPIOF_INIT_HIGH; 406 407 if (!(spi->mode & SPI_NO_CS)) { 408 if (np && (master->cs_gpios != NULL) && (spi->cs_gpio >= 0)) { 409 retval = gpio_request_one(spi->cs_gpio, 410 flags, dev_name(&spi->dev)); 411 internal_cs = false; 412 } else if (pdata->chip_sel && 413 spi->chip_select < pdata->num_chipselect && 414 pdata->chip_sel[spi->chip_select] != SPI_INTERN_CS) { 415 spi->cs_gpio = pdata->chip_sel[spi->chip_select]; 416 retval = gpio_request_one(spi->cs_gpio, 417 flags, dev_name(&spi->dev)); 418 internal_cs = false; 419 } 420 } 421 422 if (retval) { 423 dev_err(&spi->dev, "GPIO %d setup failed (%d)\n", 424 spi->cs_gpio, retval); 425 return retval; 426 } 427 428 if (internal_cs) 429 set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select); 430 431 if (spi->mode & SPI_READY) 432 set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK); 433 434 if (spi->mode & SPI_LOOP) 435 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); 436 else 437 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); 438 439 return retval; 440 } 441 442 static void davinci_spi_cleanup(struct spi_device *spi) 443 { 444 if (spi->cs_gpio >= 0) 445 gpio_free(spi->cs_gpio); 446 } 447 448 static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status) 449 { 450 struct device *sdev = dspi->bitbang.master->dev.parent; 451 452 if (int_status & SPIFLG_TIMEOUT_MASK) { 453 dev_dbg(sdev, "SPI Time-out Error\n"); 454 return -ETIMEDOUT; 455 } 456 if (int_status & SPIFLG_DESYNC_MASK) { 457 dev_dbg(sdev, "SPI Desynchronization Error\n"); 458 return -EIO; 459 } 460 if (int_status & SPIFLG_BITERR_MASK) { 461 dev_dbg(sdev, "SPI Bit error\n"); 462 return -EIO; 463 } 464 465 if (dspi->version == SPI_VERSION_2) { 466 if (int_status & SPIFLG_DLEN_ERR_MASK) { 467 dev_dbg(sdev, "SPI Data Length Error\n"); 468 return -EIO; 469 } 470 if (int_status & SPIFLG_PARERR_MASK) { 471 dev_dbg(sdev, "SPI Parity Error\n"); 472 return -EIO; 473 } 474 if (int_status & SPIFLG_OVRRUN_MASK) { 475 dev_dbg(sdev, "SPI Data Overrun error\n"); 476 return -EIO; 477 } 478 if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) { 479 dev_dbg(sdev, "SPI Buffer Init Active\n"); 480 return -EBUSY; 481 } 482 } 483 484 return 0; 485 } 486 487 /** 488 * davinci_spi_process_events - check for and handle any SPI controller events 489 * @dspi: the controller data 490 * 491 * This function will check the SPIFLG register and handle any events that are 492 * detected there 493 */ 494 static int davinci_spi_process_events(struct davinci_spi *dspi) 495 { 496 u32 buf, status, errors = 0, spidat1; 497 498 buf = ioread32(dspi->base + SPIBUF); 499 500 if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) { 501 dspi->get_rx(buf & 0xFFFF, dspi); 502 dspi->rcount--; 503 } 504 505 status = ioread32(dspi->base + SPIFLG); 506 507 if (unlikely(status & SPIFLG_ERROR_MASK)) { 508 errors = status & SPIFLG_ERROR_MASK; 509 goto out; 510 } 511 512 if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) { 513 spidat1 = ioread32(dspi->base + SPIDAT1); 514 dspi->wcount--; 515 spidat1 &= ~0xFFFF; 516 spidat1 |= 0xFFFF & dspi->get_tx(dspi); 517 iowrite32(spidat1, dspi->base + SPIDAT1); 518 } 519 520 out: 521 return errors; 522 } 523 524 static void davinci_spi_dma_rx_callback(void *data) 525 { 526 struct davinci_spi *dspi = (struct davinci_spi *)data; 527 528 dspi->rcount = 0; 529 530 if (!dspi->wcount && !dspi->rcount) 531 complete(&dspi->done); 532 } 533 534 static void davinci_spi_dma_tx_callback(void *data) 535 { 536 struct davinci_spi *dspi = (struct davinci_spi *)data; 537 538 dspi->wcount = 0; 539 540 if (!dspi->wcount && !dspi->rcount) 541 complete(&dspi->done); 542 } 543 544 /** 545 * davinci_spi_bufs - functions which will handle transfer data 546 * @spi: spi device on which data transfer to be done 547 * @t: spi transfer in which transfer info is filled 548 * 549 * This function will put data to be transferred into data register 550 * of SPI controller and then wait until the completion will be marked 551 * by the IRQ Handler. 552 */ 553 static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) 554 { 555 struct davinci_spi *dspi; 556 int data_type, ret = -ENOMEM; 557 u32 tx_data, spidat1; 558 u32 errors = 0; 559 struct davinci_spi_config *spicfg; 560 struct davinci_spi_platform_data *pdata; 561 unsigned uninitialized_var(rx_buf_count); 562 void *dummy_buf = NULL; 563 struct scatterlist sg_rx, sg_tx; 564 565 dspi = spi_master_get_devdata(spi->master); 566 pdata = &dspi->pdata; 567 spicfg = (struct davinci_spi_config *)spi->controller_data; 568 if (!spicfg) 569 spicfg = &davinci_spi_default_cfg; 570 571 /* convert len to words based on bits_per_word */ 572 data_type = dspi->bytes_per_word[spi->chip_select]; 573 574 dspi->tx = t->tx_buf; 575 dspi->rx = t->rx_buf; 576 dspi->wcount = t->len / data_type; 577 dspi->rcount = dspi->wcount; 578 579 spidat1 = ioread32(dspi->base + SPIDAT1); 580 581 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); 582 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); 583 584 reinit_completion(&dspi->done); 585 586 if (spicfg->io_type == SPI_IO_TYPE_INTR) 587 set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); 588 589 if (spicfg->io_type != SPI_IO_TYPE_DMA) { 590 /* start the transfer */ 591 dspi->wcount--; 592 tx_data = dspi->get_tx(dspi); 593 spidat1 &= 0xFFFF0000; 594 spidat1 |= tx_data & 0xFFFF; 595 iowrite32(spidat1, dspi->base + SPIDAT1); 596 } else { 597 struct dma_slave_config dma_rx_conf = { 598 .direction = DMA_DEV_TO_MEM, 599 .src_addr = (unsigned long)dspi->pbase + SPIBUF, 600 .src_addr_width = data_type, 601 .src_maxburst = 1, 602 }; 603 struct dma_slave_config dma_tx_conf = { 604 .direction = DMA_MEM_TO_DEV, 605 .dst_addr = (unsigned long)dspi->pbase + SPIDAT1, 606 .dst_addr_width = data_type, 607 .dst_maxburst = 1, 608 }; 609 struct dma_async_tx_descriptor *rxdesc; 610 struct dma_async_tx_descriptor *txdesc; 611 void *buf; 612 613 dummy_buf = kzalloc(t->len, GFP_KERNEL); 614 if (!dummy_buf) 615 goto err_alloc_dummy_buf; 616 617 dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf); 618 dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf); 619 620 sg_init_table(&sg_rx, 1); 621 if (!t->rx_buf) 622 buf = dummy_buf; 623 else 624 buf = t->rx_buf; 625 t->rx_dma = dma_map_single(&spi->dev, buf, 626 t->len, DMA_FROM_DEVICE); 627 if (!t->rx_dma) { 628 ret = -EFAULT; 629 goto err_rx_map; 630 } 631 sg_dma_address(&sg_rx) = t->rx_dma; 632 sg_dma_len(&sg_rx) = t->len; 633 634 sg_init_table(&sg_tx, 1); 635 if (!t->tx_buf) 636 buf = dummy_buf; 637 else 638 buf = (void *)t->tx_buf; 639 t->tx_dma = dma_map_single(&spi->dev, buf, 640 t->len, DMA_TO_DEVICE); 641 if (!t->tx_dma) { 642 ret = -EFAULT; 643 goto err_tx_map; 644 } 645 sg_dma_address(&sg_tx) = t->tx_dma; 646 sg_dma_len(&sg_tx) = t->len; 647 648 rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx, 649 &sg_rx, 1, DMA_DEV_TO_MEM, 650 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 651 if (!rxdesc) 652 goto err_desc; 653 654 txdesc = dmaengine_prep_slave_sg(dspi->dma_tx, 655 &sg_tx, 1, DMA_MEM_TO_DEV, 656 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 657 if (!txdesc) 658 goto err_desc; 659 660 rxdesc->callback = davinci_spi_dma_rx_callback; 661 rxdesc->callback_param = (void *)dspi; 662 txdesc->callback = davinci_spi_dma_tx_callback; 663 txdesc->callback_param = (void *)dspi; 664 665 if (pdata->cshold_bug) 666 iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2); 667 668 dmaengine_submit(rxdesc); 669 dmaengine_submit(txdesc); 670 671 dma_async_issue_pending(dspi->dma_rx); 672 dma_async_issue_pending(dspi->dma_tx); 673 674 set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); 675 } 676 677 /* Wait for the transfer to complete */ 678 if (spicfg->io_type != SPI_IO_TYPE_POLL) { 679 wait_for_completion_interruptible(&(dspi->done)); 680 } else { 681 while (dspi->rcount > 0 || dspi->wcount > 0) { 682 errors = davinci_spi_process_events(dspi); 683 if (errors) 684 break; 685 cpu_relax(); 686 } 687 } 688 689 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL); 690 if (spicfg->io_type == SPI_IO_TYPE_DMA) { 691 clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); 692 693 dma_unmap_single(&spi->dev, t->rx_dma, 694 t->len, DMA_FROM_DEVICE); 695 dma_unmap_single(&spi->dev, t->tx_dma, 696 t->len, DMA_TO_DEVICE); 697 kfree(dummy_buf); 698 } 699 700 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); 701 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); 702 703 /* 704 * Check for bit error, desync error,parity error,timeout error and 705 * receive overflow errors 706 */ 707 if (errors) { 708 ret = davinci_spi_check_error(dspi, errors); 709 WARN(!ret, "%s: error reported but no error found!\n", 710 dev_name(&spi->dev)); 711 return ret; 712 } 713 714 if (dspi->rcount != 0 || dspi->wcount != 0) { 715 dev_err(&spi->dev, "SPI data transfer error\n"); 716 return -EIO; 717 } 718 719 return t->len; 720 721 err_desc: 722 dma_unmap_single(&spi->dev, t->tx_dma, t->len, DMA_TO_DEVICE); 723 err_tx_map: 724 dma_unmap_single(&spi->dev, t->rx_dma, t->len, DMA_FROM_DEVICE); 725 err_rx_map: 726 kfree(dummy_buf); 727 err_alloc_dummy_buf: 728 return ret; 729 } 730 731 /** 732 * dummy_thread_fn - dummy thread function 733 * @irq: IRQ number for this SPI Master 734 * @context_data: structure for SPI Master controller davinci_spi 735 * 736 * This is to satisfy the request_threaded_irq() API so that the irq 737 * handler is called in interrupt context. 738 */ 739 static irqreturn_t dummy_thread_fn(s32 irq, void *data) 740 { 741 return IRQ_HANDLED; 742 } 743 744 /** 745 * davinci_spi_irq - Interrupt handler for SPI Master Controller 746 * @irq: IRQ number for this SPI Master 747 * @context_data: structure for SPI Master controller davinci_spi 748 * 749 * ISR will determine that interrupt arrives either for READ or WRITE command. 750 * According to command it will do the appropriate action. It will check 751 * transfer length and if it is not zero then dispatch transfer command again. 752 * If transfer length is zero then it will indicate the COMPLETION so that 753 * davinci_spi_bufs function can go ahead. 754 */ 755 static irqreturn_t davinci_spi_irq(s32 irq, void *data) 756 { 757 struct davinci_spi *dspi = data; 758 int status; 759 760 status = davinci_spi_process_events(dspi); 761 if (unlikely(status != 0)) 762 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); 763 764 if ((!dspi->rcount && !dspi->wcount) || status) 765 complete(&dspi->done); 766 767 return IRQ_HANDLED; 768 } 769 770 static int davinci_spi_request_dma(struct davinci_spi *dspi) 771 { 772 dma_cap_mask_t mask; 773 struct device *sdev = dspi->bitbang.master->dev.parent; 774 int r; 775 776 dma_cap_zero(mask); 777 dma_cap_set(DMA_SLAVE, mask); 778 779 dspi->dma_rx = dma_request_channel(mask, edma_filter_fn, 780 &dspi->dma_rx_chnum); 781 if (!dspi->dma_rx) { 782 dev_err(sdev, "request RX DMA channel failed\n"); 783 r = -ENODEV; 784 goto rx_dma_failed; 785 } 786 787 dspi->dma_tx = dma_request_channel(mask, edma_filter_fn, 788 &dspi->dma_tx_chnum); 789 if (!dspi->dma_tx) { 790 dev_err(sdev, "request TX DMA channel failed\n"); 791 r = -ENODEV; 792 goto tx_dma_failed; 793 } 794 795 return 0; 796 797 tx_dma_failed: 798 dma_release_channel(dspi->dma_rx); 799 rx_dma_failed: 800 return r; 801 } 802 803 #if defined(CONFIG_OF) 804 static const struct of_device_id davinci_spi_of_match[] = { 805 { 806 .compatible = "ti,dm6441-spi", 807 }, 808 { 809 .compatible = "ti,da830-spi", 810 .data = (void *)SPI_VERSION_2, 811 }, 812 { }, 813 }; 814 MODULE_DEVICE_TABLE(of, davinci_spi_of_match); 815 816 /** 817 * spi_davinci_get_pdata - Get platform data from DTS binding 818 * @pdev: ptr to platform data 819 * @dspi: ptr to driver data 820 * 821 * Parses and populates pdata in dspi from device tree bindings. 822 * 823 * NOTE: Not all platform data params are supported currently. 824 */ 825 static int spi_davinci_get_pdata(struct platform_device *pdev, 826 struct davinci_spi *dspi) 827 { 828 struct device_node *node = pdev->dev.of_node; 829 struct davinci_spi_platform_data *pdata; 830 unsigned int num_cs, intr_line = 0; 831 const struct of_device_id *match; 832 833 pdata = &dspi->pdata; 834 835 pdata->version = SPI_VERSION_1; 836 match = of_match_device(davinci_spi_of_match, &pdev->dev); 837 if (!match) 838 return -ENODEV; 839 840 /* match data has the SPI version number for SPI_VERSION_2 */ 841 if (match->data == (void *)SPI_VERSION_2) 842 pdata->version = SPI_VERSION_2; 843 844 /* 845 * default num_cs is 1 and all chipsel are internal to the chip 846 * indicated by chip_sel being NULL or cs_gpios being NULL or 847 * set to -ENOENT. num-cs includes internal as well as gpios. 848 * indicated by chip_sel being NULL. GPIO based CS is not 849 * supported yet in DT bindings. 850 */ 851 num_cs = 1; 852 of_property_read_u32(node, "num-cs", &num_cs); 853 pdata->num_chipselect = num_cs; 854 of_property_read_u32(node, "ti,davinci-spi-intr-line", &intr_line); 855 pdata->intr_line = intr_line; 856 return 0; 857 } 858 #else 859 static struct davinci_spi_platform_data 860 *spi_davinci_get_pdata(struct platform_device *pdev, 861 struct davinci_spi *dspi) 862 { 863 return -ENODEV; 864 } 865 #endif 866 867 /** 868 * davinci_spi_probe - probe function for SPI Master Controller 869 * @pdev: platform_device structure which contains plateform specific data 870 * 871 * According to Linux Device Model this function will be invoked by Linux 872 * with platform_device struct which contains the device specific info. 873 * This function will map the SPI controller's memory, register IRQ, 874 * Reset SPI controller and setting its registers to default value. 875 * It will invoke spi_bitbang_start to create work queue so that client driver 876 * can register transfer method to work queue. 877 */ 878 static int davinci_spi_probe(struct platform_device *pdev) 879 { 880 struct spi_master *master; 881 struct davinci_spi *dspi; 882 struct davinci_spi_platform_data *pdata; 883 struct resource *r; 884 resource_size_t dma_rx_chan = SPI_NO_RESOURCE; 885 resource_size_t dma_tx_chan = SPI_NO_RESOURCE; 886 int ret = 0; 887 u32 spipc0; 888 889 master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi)); 890 if (master == NULL) { 891 ret = -ENOMEM; 892 goto err; 893 } 894 895 platform_set_drvdata(pdev, master); 896 897 dspi = spi_master_get_devdata(master); 898 899 if (dev_get_platdata(&pdev->dev)) { 900 pdata = dev_get_platdata(&pdev->dev); 901 dspi->pdata = *pdata; 902 } else { 903 /* update dspi pdata with that from the DT */ 904 ret = spi_davinci_get_pdata(pdev, dspi); 905 if (ret < 0) 906 goto free_master; 907 } 908 909 /* pdata in dspi is now updated and point pdata to that */ 910 pdata = &dspi->pdata; 911 912 dspi->bytes_per_word = devm_kzalloc(&pdev->dev, 913 sizeof(*dspi->bytes_per_word) * 914 pdata->num_chipselect, GFP_KERNEL); 915 if (dspi->bytes_per_word == NULL) { 916 ret = -ENOMEM; 917 goto free_master; 918 } 919 920 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 921 if (r == NULL) { 922 ret = -ENOENT; 923 goto free_master; 924 } 925 926 dspi->pbase = r->start; 927 928 dspi->base = devm_ioremap_resource(&pdev->dev, r); 929 if (IS_ERR(dspi->base)) { 930 ret = PTR_ERR(dspi->base); 931 goto free_master; 932 } 933 934 dspi->irq = platform_get_irq(pdev, 0); 935 if (dspi->irq <= 0) { 936 ret = -EINVAL; 937 goto free_master; 938 } 939 940 ret = devm_request_threaded_irq(&pdev->dev, dspi->irq, davinci_spi_irq, 941 dummy_thread_fn, 0, dev_name(&pdev->dev), dspi); 942 if (ret) 943 goto free_master; 944 945 dspi->bitbang.master = master; 946 947 dspi->clk = devm_clk_get(&pdev->dev, NULL); 948 if (IS_ERR(dspi->clk)) { 949 ret = -ENODEV; 950 goto free_master; 951 } 952 clk_prepare_enable(dspi->clk); 953 954 master->dev.of_node = pdev->dev.of_node; 955 master->bus_num = pdev->id; 956 master->num_chipselect = pdata->num_chipselect; 957 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16); 958 master->setup = davinci_spi_setup; 959 master->cleanup = davinci_spi_cleanup; 960 961 dspi->bitbang.chipselect = davinci_spi_chipselect; 962 dspi->bitbang.setup_transfer = davinci_spi_setup_transfer; 963 964 dspi->version = pdata->version; 965 966 dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP; 967 if (dspi->version == SPI_VERSION_2) 968 dspi->bitbang.flags |= SPI_READY; 969 970 r = platform_get_resource(pdev, IORESOURCE_DMA, 0); 971 if (r) 972 dma_rx_chan = r->start; 973 r = platform_get_resource(pdev, IORESOURCE_DMA, 1); 974 if (r) 975 dma_tx_chan = r->start; 976 977 dspi->bitbang.txrx_bufs = davinci_spi_bufs; 978 if (dma_rx_chan != SPI_NO_RESOURCE && 979 dma_tx_chan != SPI_NO_RESOURCE) { 980 dspi->dma_rx_chnum = dma_rx_chan; 981 dspi->dma_tx_chnum = dma_tx_chan; 982 983 ret = davinci_spi_request_dma(dspi); 984 if (ret) 985 goto free_clk; 986 987 dev_info(&pdev->dev, "DMA: supported\n"); 988 dev_info(&pdev->dev, "DMA: RX channel: %pa, TX channel: %pa, " 989 "event queue: %d\n", &dma_rx_chan, &dma_tx_chan, 990 pdata->dma_event_q); 991 } 992 993 dspi->get_rx = davinci_spi_rx_buf_u8; 994 dspi->get_tx = davinci_spi_tx_buf_u8; 995 996 init_completion(&dspi->done); 997 998 /* Reset In/OUT SPI module */ 999 iowrite32(0, dspi->base + SPIGCR0); 1000 udelay(100); 1001 iowrite32(1, dspi->base + SPIGCR0); 1002 1003 /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ 1004 spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; 1005 iowrite32(spipc0, dspi->base + SPIPC0); 1006 1007 if (pdata->intr_line) 1008 iowrite32(SPI_INTLVL_1, dspi->base + SPILVL); 1009 else 1010 iowrite32(SPI_INTLVL_0, dspi->base + SPILVL); 1011 1012 iowrite32(CS_DEFAULT, dspi->base + SPIDEF); 1013 1014 /* master mode default */ 1015 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); 1016 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK); 1017 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); 1018 1019 ret = spi_bitbang_start(&dspi->bitbang); 1020 if (ret) 1021 goto free_dma; 1022 1023 dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base); 1024 1025 return ret; 1026 1027 free_dma: 1028 dma_release_channel(dspi->dma_rx); 1029 dma_release_channel(dspi->dma_tx); 1030 free_clk: 1031 clk_disable_unprepare(dspi->clk); 1032 free_master: 1033 spi_master_put(master); 1034 err: 1035 return ret; 1036 } 1037 1038 /** 1039 * davinci_spi_remove - remove function for SPI Master Controller 1040 * @pdev: platform_device structure which contains plateform specific data 1041 * 1042 * This function will do the reverse action of davinci_spi_probe function 1043 * It will free the IRQ and SPI controller's memory region. 1044 * It will also call spi_bitbang_stop to destroy the work queue which was 1045 * created by spi_bitbang_start. 1046 */ 1047 static int davinci_spi_remove(struct platform_device *pdev) 1048 { 1049 struct davinci_spi *dspi; 1050 struct spi_master *master; 1051 1052 master = platform_get_drvdata(pdev); 1053 dspi = spi_master_get_devdata(master); 1054 1055 spi_bitbang_stop(&dspi->bitbang); 1056 1057 clk_disable_unprepare(dspi->clk); 1058 spi_master_put(master); 1059 1060 return 0; 1061 } 1062 1063 static struct platform_driver davinci_spi_driver = { 1064 .driver = { 1065 .name = "spi_davinci", 1066 .owner = THIS_MODULE, 1067 .of_match_table = of_match_ptr(davinci_spi_of_match), 1068 }, 1069 .probe = davinci_spi_probe, 1070 .remove = davinci_spi_remove, 1071 }; 1072 module_platform_driver(davinci_spi_driver); 1073 1074 MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver"); 1075 MODULE_LICENSE("GPL"); 1076