1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Cadence SPI controller driver (master mode only) 4 * 5 * Copyright (C) 2008 - 2014 Xilinx, Inc. 6 * 7 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c) 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/of_irq.h> 17 #include <linux/of_address.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/spi/spi.h> 21 22 /* Name of this driver */ 23 #define CDNS_SPI_NAME "cdns-spi" 24 25 /* Register offset definitions */ 26 #define CDNS_SPI_CR 0x00 /* Configuration Register, RW */ 27 #define CDNS_SPI_ISR 0x04 /* Interrupt Status Register, RO */ 28 #define CDNS_SPI_IER 0x08 /* Interrupt Enable Register, WO */ 29 #define CDNS_SPI_IDR 0x0c /* Interrupt Disable Register, WO */ 30 #define CDNS_SPI_IMR 0x10 /* Interrupt Enabled Mask Register, RO */ 31 #define CDNS_SPI_ER 0x14 /* Enable/Disable Register, RW */ 32 #define CDNS_SPI_DR 0x18 /* Delay Register, RW */ 33 #define CDNS_SPI_TXD 0x1C /* Data Transmit Register, WO */ 34 #define CDNS_SPI_RXD 0x20 /* Data Receive Register, RO */ 35 #define CDNS_SPI_SICR 0x24 /* Slave Idle Count Register, RW */ 36 #define CDNS_SPI_THLD 0x28 /* Transmit FIFO Watermark Register,RW */ 37 38 #define SPI_AUTOSUSPEND_TIMEOUT 3000 39 /* 40 * SPI Configuration Register bit Masks 41 * 42 * This register contains various control bits that affect the operation 43 * of the SPI controller 44 */ 45 #define CDNS_SPI_CR_MANSTRT 0x00010000 /* Manual TX Start */ 46 #define CDNS_SPI_CR_CPHA 0x00000004 /* Clock Phase Control */ 47 #define CDNS_SPI_CR_CPOL 0x00000002 /* Clock Polarity Control */ 48 #define CDNS_SPI_CR_SSCTRL 0x00003C00 /* Slave Select Mask */ 49 #define CDNS_SPI_CR_PERI_SEL 0x00000200 /* Peripheral Select Decode */ 50 #define CDNS_SPI_CR_BAUD_DIV 0x00000038 /* Baud Rate Divisor Mask */ 51 #define CDNS_SPI_CR_MSTREN 0x00000001 /* Master Enable Mask */ 52 #define CDNS_SPI_CR_MANSTRTEN 0x00008000 /* Manual TX Enable Mask */ 53 #define CDNS_SPI_CR_SSFORCE 0x00004000 /* Manual SS Enable Mask */ 54 #define CDNS_SPI_CR_BAUD_DIV_4 0x00000008 /* Default Baud Div Mask */ 55 #define CDNS_SPI_CR_DEFAULT (CDNS_SPI_CR_MSTREN | \ 56 CDNS_SPI_CR_SSCTRL | \ 57 CDNS_SPI_CR_SSFORCE | \ 58 CDNS_SPI_CR_BAUD_DIV_4) 59 60 /* 61 * SPI Configuration Register - Baud rate and slave select 62 * 63 * These are the values used in the calculation of baud rate divisor and 64 * setting the slave select. 65 */ 66 67 #define CDNS_SPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */ 68 #define CDNS_SPI_BAUD_DIV_MIN 1 /* Baud rate divisor minimum */ 69 #define CDNS_SPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */ 70 #define CDNS_SPI_SS_SHIFT 10 /* Slave Select field shift in CR */ 71 #define CDNS_SPI_SS0 0x1 /* Slave Select zero */ 72 73 /* 74 * SPI Interrupt Registers bit Masks 75 * 76 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same 77 * bit definitions. 78 */ 79 #define CDNS_SPI_IXR_TXOW 0x00000004 /* SPI TX FIFO Overwater */ 80 #define CDNS_SPI_IXR_MODF 0x00000002 /* SPI Mode Fault */ 81 #define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */ 82 #define CDNS_SPI_IXR_DEFAULT (CDNS_SPI_IXR_TXOW | \ 83 CDNS_SPI_IXR_MODF) 84 #define CDNS_SPI_IXR_TXFULL 0x00000008 /* SPI TX Full */ 85 #define CDNS_SPI_IXR_ALL 0x0000007F /* SPI all interrupts */ 86 87 /* 88 * SPI Enable Register bit Masks 89 * 90 * This register is used to enable or disable the SPI controller 91 */ 92 #define CDNS_SPI_ER_ENABLE 0x00000001 /* SPI Enable Bit Mask */ 93 #define CDNS_SPI_ER_DISABLE 0x0 /* SPI Disable Bit Mask */ 94 95 /* SPI FIFO depth in bytes */ 96 #define CDNS_SPI_FIFO_DEPTH 128 97 98 /* Default number of chip select lines */ 99 #define CDNS_SPI_DEFAULT_NUM_CS 4 100 101 /** 102 * struct cdns_spi - This definition defines spi driver instance 103 * @regs: Virtual address of the SPI controller registers 104 * @ref_clk: Pointer to the peripheral clock 105 * @pclk: Pointer to the APB clock 106 * @speed_hz: Current SPI bus clock speed in Hz 107 * @txbuf: Pointer to the TX buffer 108 * @rxbuf: Pointer to the RX buffer 109 * @tx_bytes: Number of bytes left to transfer 110 * @rx_bytes: Number of bytes requested 111 * @dev_busy: Device busy flag 112 * @is_decoded_cs: Flag for decoder property set or not 113 */ 114 struct cdns_spi { 115 void __iomem *regs; 116 struct clk *ref_clk; 117 struct clk *pclk; 118 unsigned int clk_rate; 119 u32 speed_hz; 120 const u8 *txbuf; 121 u8 *rxbuf; 122 int tx_bytes; 123 int rx_bytes; 124 u8 dev_busy; 125 u32 is_decoded_cs; 126 }; 127 128 /* Macros for the SPI controller read/write */ 129 static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset) 130 { 131 return readl_relaxed(xspi->regs + offset); 132 } 133 134 static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val) 135 { 136 writel_relaxed(val, xspi->regs + offset); 137 } 138 139 /** 140 * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller 141 * @xspi: Pointer to the cdns_spi structure 142 * 143 * On reset the SPI controller is configured to be in master mode, baud rate 144 * divisor is set to 4, threshold value for TX FIFO not full interrupt is set 145 * to 1 and size of the word to be transferred as 8 bit. 146 * This function initializes the SPI controller to disable and clear all the 147 * interrupts, enable manual slave select and manual start, deselect all the 148 * chip select lines, and enable the SPI controller. 149 */ 150 static void cdns_spi_init_hw(struct cdns_spi *xspi) 151 { 152 u32 ctrl_reg = CDNS_SPI_CR_DEFAULT; 153 154 if (xspi->is_decoded_cs) 155 ctrl_reg |= CDNS_SPI_CR_PERI_SEL; 156 157 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE); 158 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_ALL); 159 160 /* Clear the RX FIFO */ 161 while (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_RXNEMTY) 162 cdns_spi_read(xspi, CDNS_SPI_RXD); 163 164 cdns_spi_write(xspi, CDNS_SPI_ISR, CDNS_SPI_IXR_ALL); 165 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg); 166 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE); 167 } 168 169 /** 170 * cdns_spi_chipselect - Select or deselect the chip select line 171 * @spi: Pointer to the spi_device structure 172 * @is_high: Select(0) or deselect (1) the chip select line 173 */ 174 static void cdns_spi_chipselect(struct spi_device *spi, bool is_high) 175 { 176 struct cdns_spi *xspi = spi_master_get_devdata(spi->master); 177 u32 ctrl_reg; 178 179 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR); 180 181 if (is_high) { 182 /* Deselect the slave */ 183 ctrl_reg |= CDNS_SPI_CR_SSCTRL; 184 } else { 185 /* Select the slave */ 186 ctrl_reg &= ~CDNS_SPI_CR_SSCTRL; 187 if (!(xspi->is_decoded_cs)) 188 ctrl_reg |= ((~(CDNS_SPI_SS0 << spi->chip_select)) << 189 CDNS_SPI_SS_SHIFT) & 190 CDNS_SPI_CR_SSCTRL; 191 else 192 ctrl_reg |= (spi->chip_select << CDNS_SPI_SS_SHIFT) & 193 CDNS_SPI_CR_SSCTRL; 194 } 195 196 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg); 197 } 198 199 /** 200 * cdns_spi_config_clock_mode - Sets clock polarity and phase 201 * @spi: Pointer to the spi_device structure 202 * 203 * Sets the requested clock polarity and phase. 204 */ 205 static void cdns_spi_config_clock_mode(struct spi_device *spi) 206 { 207 struct cdns_spi *xspi = spi_master_get_devdata(spi->master); 208 u32 ctrl_reg, new_ctrl_reg; 209 210 new_ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR); 211 ctrl_reg = new_ctrl_reg; 212 213 /* Set the SPI clock phase and clock polarity */ 214 new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA | CDNS_SPI_CR_CPOL); 215 if (spi->mode & SPI_CPHA) 216 new_ctrl_reg |= CDNS_SPI_CR_CPHA; 217 if (spi->mode & SPI_CPOL) 218 new_ctrl_reg |= CDNS_SPI_CR_CPOL; 219 220 if (new_ctrl_reg != ctrl_reg) { 221 /* 222 * Just writing the CR register does not seem to apply the clock 223 * setting changes. This is problematic when changing the clock 224 * polarity as it will cause the SPI slave to see spurious clock 225 * transitions. To workaround the issue toggle the ER register. 226 */ 227 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE); 228 cdns_spi_write(xspi, CDNS_SPI_CR, new_ctrl_reg); 229 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE); 230 } 231 } 232 233 /** 234 * cdns_spi_config_clock_freq - Sets clock frequency 235 * @spi: Pointer to the spi_device structure 236 * @transfer: Pointer to the spi_transfer structure which provides 237 * information about next transfer setup parameters 238 * 239 * Sets the requested clock frequency. 240 * Note: If the requested frequency is not an exact match with what can be 241 * obtained using the prescalar value the driver sets the clock frequency which 242 * is lower than the requested frequency (maximum lower) for the transfer. If 243 * the requested frequency is higher or lower than that is supported by the SPI 244 * controller the driver will set the highest or lowest frequency supported by 245 * controller. 246 */ 247 static void cdns_spi_config_clock_freq(struct spi_device *spi, 248 struct spi_transfer *transfer) 249 { 250 struct cdns_spi *xspi = spi_master_get_devdata(spi->master); 251 u32 ctrl_reg, baud_rate_val; 252 unsigned long frequency; 253 254 frequency = xspi->clk_rate; 255 256 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR); 257 258 /* Set the clock frequency */ 259 if (xspi->speed_hz != transfer->speed_hz) { 260 /* first valid value is 1 */ 261 baud_rate_val = CDNS_SPI_BAUD_DIV_MIN; 262 while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) && 263 (frequency / (2 << baud_rate_val)) > transfer->speed_hz) 264 baud_rate_val++; 265 266 ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV; 267 ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT; 268 269 xspi->speed_hz = frequency / (2 << baud_rate_val); 270 } 271 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg); 272 } 273 274 /** 275 * cdns_spi_setup_transfer - Configure SPI controller for specified transfer 276 * @spi: Pointer to the spi_device structure 277 * @transfer: Pointer to the spi_transfer structure which provides 278 * information about next transfer setup parameters 279 * 280 * Sets the operational mode of SPI controller for the next SPI transfer and 281 * sets the requested clock frequency. 282 * 283 * Return: Always 0 284 */ 285 static int cdns_spi_setup_transfer(struct spi_device *spi, 286 struct spi_transfer *transfer) 287 { 288 struct cdns_spi *xspi = spi_master_get_devdata(spi->master); 289 290 cdns_spi_config_clock_freq(spi, transfer); 291 292 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n", 293 __func__, spi->mode, spi->bits_per_word, 294 xspi->speed_hz); 295 296 return 0; 297 } 298 299 /** 300 * cdns_spi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible 301 * @xspi: Pointer to the cdns_spi structure 302 */ 303 static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi) 304 { 305 unsigned long trans_cnt = 0; 306 307 while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) && 308 (xspi->tx_bytes > 0)) { 309 310 /* When xspi in busy condition, bytes may send failed, 311 * then spi control did't work thoroughly, add one byte delay 312 */ 313 if (cdns_spi_read(xspi, CDNS_SPI_ISR) & 314 CDNS_SPI_IXR_TXFULL) 315 udelay(10); 316 317 if (xspi->txbuf) 318 cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++); 319 else 320 cdns_spi_write(xspi, CDNS_SPI_TXD, 0); 321 322 xspi->tx_bytes--; 323 trans_cnt++; 324 } 325 } 326 327 /** 328 * cdns_spi_irq - Interrupt service routine of the SPI controller 329 * @irq: IRQ number 330 * @dev_id: Pointer to the xspi structure 331 * 332 * This function handles TX empty and Mode Fault interrupts only. 333 * On TX empty interrupt this function reads the received data from RX FIFO and 334 * fills the TX FIFO if there is any data remaining to be transferred. 335 * On Mode Fault interrupt this function indicates that transfer is completed, 336 * the SPI subsystem will identify the error as the remaining bytes to be 337 * transferred is non-zero. 338 * 339 * Return: IRQ_HANDLED when handled; IRQ_NONE otherwise. 340 */ 341 static irqreturn_t cdns_spi_irq(int irq, void *dev_id) 342 { 343 struct spi_master *master = dev_id; 344 struct cdns_spi *xspi = spi_master_get_devdata(master); 345 irqreturn_t status; 346 u32 intr_status; 347 348 status = IRQ_NONE; 349 intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR); 350 cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status); 351 352 if (intr_status & CDNS_SPI_IXR_MODF) { 353 /* Indicate that transfer is completed, the SPI subsystem will 354 * identify the error as the remaining bytes to be 355 * transferred is non-zero 356 */ 357 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_DEFAULT); 358 spi_finalize_current_transfer(master); 359 status = IRQ_HANDLED; 360 } else if (intr_status & CDNS_SPI_IXR_TXOW) { 361 unsigned long trans_cnt; 362 363 trans_cnt = xspi->rx_bytes - xspi->tx_bytes; 364 365 /* Read out the data from the RX FIFO */ 366 while (trans_cnt) { 367 u8 data; 368 369 data = cdns_spi_read(xspi, CDNS_SPI_RXD); 370 if (xspi->rxbuf) 371 *xspi->rxbuf++ = data; 372 373 xspi->rx_bytes--; 374 trans_cnt--; 375 } 376 377 if (xspi->tx_bytes) { 378 /* There is more data to send */ 379 cdns_spi_fill_tx_fifo(xspi); 380 } else { 381 /* Transfer is completed */ 382 cdns_spi_write(xspi, CDNS_SPI_IDR, 383 CDNS_SPI_IXR_DEFAULT); 384 spi_finalize_current_transfer(master); 385 } 386 status = IRQ_HANDLED; 387 } 388 389 return status; 390 } 391 392 static int cdns_prepare_message(struct spi_master *master, 393 struct spi_message *msg) 394 { 395 cdns_spi_config_clock_mode(msg->spi); 396 return 0; 397 } 398 399 /** 400 * cdns_transfer_one - Initiates the SPI transfer 401 * @master: Pointer to spi_master structure 402 * @spi: Pointer to the spi_device structure 403 * @transfer: Pointer to the spi_transfer structure which provides 404 * information about next transfer parameters 405 * 406 * This function fills the TX FIFO, starts the SPI transfer and 407 * returns a positive transfer count so that core will wait for completion. 408 * 409 * Return: Number of bytes transferred in the last transfer 410 */ 411 static int cdns_transfer_one(struct spi_master *master, 412 struct spi_device *spi, 413 struct spi_transfer *transfer) 414 { 415 struct cdns_spi *xspi = spi_master_get_devdata(master); 416 417 xspi->txbuf = transfer->tx_buf; 418 xspi->rxbuf = transfer->rx_buf; 419 xspi->tx_bytes = transfer->len; 420 xspi->rx_bytes = transfer->len; 421 422 cdns_spi_setup_transfer(spi, transfer); 423 cdns_spi_fill_tx_fifo(xspi); 424 spi_transfer_delay_exec(transfer); 425 426 cdns_spi_write(xspi, CDNS_SPI_IER, CDNS_SPI_IXR_DEFAULT); 427 return transfer->len; 428 } 429 430 /** 431 * cdns_prepare_transfer_hardware - Prepares hardware for transfer. 432 * @master: Pointer to the spi_master structure which provides 433 * information about the controller. 434 * 435 * This function enables SPI master controller. 436 * 437 * Return: 0 always 438 */ 439 static int cdns_prepare_transfer_hardware(struct spi_master *master) 440 { 441 struct cdns_spi *xspi = spi_master_get_devdata(master); 442 443 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE); 444 445 return 0; 446 } 447 448 /** 449 * cdns_unprepare_transfer_hardware - Relaxes hardware after transfer 450 * @master: Pointer to the spi_master structure which provides 451 * information about the controller. 452 * 453 * This function disables the SPI master controller. 454 * 455 * Return: 0 always 456 */ 457 static int cdns_unprepare_transfer_hardware(struct spi_master *master) 458 { 459 struct cdns_spi *xspi = spi_master_get_devdata(master); 460 461 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE); 462 463 return 0; 464 } 465 466 /** 467 * cdns_spi_probe - Probe method for the SPI driver 468 * @pdev: Pointer to the platform_device structure 469 * 470 * This function initializes the driver data structures and the hardware. 471 * 472 * Return: 0 on success and error value on error 473 */ 474 static int cdns_spi_probe(struct platform_device *pdev) 475 { 476 int ret = 0, irq; 477 struct spi_master *master; 478 struct cdns_spi *xspi; 479 u32 num_cs; 480 481 master = spi_alloc_master(&pdev->dev, sizeof(*xspi)); 482 if (!master) 483 return -ENOMEM; 484 485 xspi = spi_master_get_devdata(master); 486 master->dev.of_node = pdev->dev.of_node; 487 platform_set_drvdata(pdev, master); 488 489 xspi->regs = devm_platform_ioremap_resource(pdev, 0); 490 if (IS_ERR(xspi->regs)) { 491 ret = PTR_ERR(xspi->regs); 492 goto remove_master; 493 } 494 495 xspi->pclk = devm_clk_get(&pdev->dev, "pclk"); 496 if (IS_ERR(xspi->pclk)) { 497 dev_err(&pdev->dev, "pclk clock not found.\n"); 498 ret = PTR_ERR(xspi->pclk); 499 goto remove_master; 500 } 501 502 xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk"); 503 if (IS_ERR(xspi->ref_clk)) { 504 dev_err(&pdev->dev, "ref_clk clock not found.\n"); 505 ret = PTR_ERR(xspi->ref_clk); 506 goto remove_master; 507 } 508 509 ret = clk_prepare_enable(xspi->pclk); 510 if (ret) { 511 dev_err(&pdev->dev, "Unable to enable APB clock.\n"); 512 goto remove_master; 513 } 514 515 ret = clk_prepare_enable(xspi->ref_clk); 516 if (ret) { 517 dev_err(&pdev->dev, "Unable to enable device clock.\n"); 518 goto clk_dis_apb; 519 } 520 521 pm_runtime_use_autosuspend(&pdev->dev); 522 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); 523 pm_runtime_get_noresume(&pdev->dev); 524 pm_runtime_set_active(&pdev->dev); 525 pm_runtime_enable(&pdev->dev); 526 527 ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs); 528 if (ret < 0) 529 master->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS; 530 else 531 master->num_chipselect = num_cs; 532 533 ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs", 534 &xspi->is_decoded_cs); 535 if (ret < 0) 536 xspi->is_decoded_cs = 0; 537 538 /* SPI controller initializations */ 539 cdns_spi_init_hw(xspi); 540 541 irq = platform_get_irq(pdev, 0); 542 if (irq <= 0) { 543 ret = -ENXIO; 544 goto clk_dis_all; 545 } 546 547 ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq, 548 0, pdev->name, master); 549 if (ret != 0) { 550 ret = -ENXIO; 551 dev_err(&pdev->dev, "request_irq failed\n"); 552 goto clk_dis_all; 553 } 554 555 master->use_gpio_descriptors = true; 556 master->prepare_transfer_hardware = cdns_prepare_transfer_hardware; 557 master->prepare_message = cdns_prepare_message; 558 master->transfer_one = cdns_transfer_one; 559 master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware; 560 master->set_cs = cdns_spi_chipselect; 561 master->auto_runtime_pm = true; 562 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 563 564 xspi->clk_rate = clk_get_rate(xspi->ref_clk); 565 /* Set to default valid value */ 566 master->max_speed_hz = xspi->clk_rate / 4; 567 xspi->speed_hz = master->max_speed_hz; 568 569 master->bits_per_word_mask = SPI_BPW_MASK(8); 570 571 pm_runtime_mark_last_busy(&pdev->dev); 572 pm_runtime_put_autosuspend(&pdev->dev); 573 574 ret = spi_register_master(master); 575 if (ret) { 576 dev_err(&pdev->dev, "spi_register_master failed\n"); 577 goto clk_dis_all; 578 } 579 580 return ret; 581 582 clk_dis_all: 583 pm_runtime_set_suspended(&pdev->dev); 584 pm_runtime_disable(&pdev->dev); 585 clk_disable_unprepare(xspi->ref_clk); 586 clk_dis_apb: 587 clk_disable_unprepare(xspi->pclk); 588 remove_master: 589 spi_master_put(master); 590 return ret; 591 } 592 593 /** 594 * cdns_spi_remove - Remove method for the SPI driver 595 * @pdev: Pointer to the platform_device structure 596 * 597 * This function is called if a device is physically removed from the system or 598 * if the driver module is being unloaded. It frees all resources allocated to 599 * the device. 600 * 601 * Return: 0 on success and error value on error 602 */ 603 static int cdns_spi_remove(struct platform_device *pdev) 604 { 605 struct spi_master *master = platform_get_drvdata(pdev); 606 struct cdns_spi *xspi = spi_master_get_devdata(master); 607 608 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE); 609 610 clk_disable_unprepare(xspi->ref_clk); 611 clk_disable_unprepare(xspi->pclk); 612 pm_runtime_set_suspended(&pdev->dev); 613 pm_runtime_disable(&pdev->dev); 614 615 spi_unregister_master(master); 616 617 return 0; 618 } 619 620 /** 621 * cdns_spi_suspend - Suspend method for the SPI driver 622 * @dev: Address of the platform_device structure 623 * 624 * This function disables the SPI controller and 625 * changes the driver state to "suspend" 626 * 627 * Return: 0 on success and error value on error 628 */ 629 static int __maybe_unused cdns_spi_suspend(struct device *dev) 630 { 631 struct spi_master *master = dev_get_drvdata(dev); 632 633 return spi_master_suspend(master); 634 } 635 636 /** 637 * cdns_spi_resume - Resume method for the SPI driver 638 * @dev: Address of the platform_device structure 639 * 640 * This function changes the driver state to "ready" 641 * 642 * Return: 0 on success and error value on error 643 */ 644 static int __maybe_unused cdns_spi_resume(struct device *dev) 645 { 646 struct spi_master *master = dev_get_drvdata(dev); 647 struct cdns_spi *xspi = spi_master_get_devdata(master); 648 649 cdns_spi_init_hw(xspi); 650 return spi_master_resume(master); 651 } 652 653 /** 654 * cdns_spi_runtime_resume - Runtime resume method for the SPI driver 655 * @dev: Address of the platform_device structure 656 * 657 * This function enables the clocks 658 * 659 * Return: 0 on success and error value on error 660 */ 661 static int __maybe_unused cdns_spi_runtime_resume(struct device *dev) 662 { 663 struct spi_master *master = dev_get_drvdata(dev); 664 struct cdns_spi *xspi = spi_master_get_devdata(master); 665 int ret; 666 667 ret = clk_prepare_enable(xspi->pclk); 668 if (ret) { 669 dev_err(dev, "Cannot enable APB clock.\n"); 670 return ret; 671 } 672 673 ret = clk_prepare_enable(xspi->ref_clk); 674 if (ret) { 675 dev_err(dev, "Cannot enable device clock.\n"); 676 clk_disable_unprepare(xspi->pclk); 677 return ret; 678 } 679 return 0; 680 } 681 682 /** 683 * cdns_spi_runtime_suspend - Runtime suspend method for the SPI driver 684 * @dev: Address of the platform_device structure 685 * 686 * This function disables the clocks 687 * 688 * Return: Always 0 689 */ 690 static int __maybe_unused cdns_spi_runtime_suspend(struct device *dev) 691 { 692 struct spi_master *master = dev_get_drvdata(dev); 693 struct cdns_spi *xspi = spi_master_get_devdata(master); 694 695 clk_disable_unprepare(xspi->ref_clk); 696 clk_disable_unprepare(xspi->pclk); 697 698 return 0; 699 } 700 701 static const struct dev_pm_ops cdns_spi_dev_pm_ops = { 702 SET_RUNTIME_PM_OPS(cdns_spi_runtime_suspend, 703 cdns_spi_runtime_resume, NULL) 704 SET_SYSTEM_SLEEP_PM_OPS(cdns_spi_suspend, cdns_spi_resume) 705 }; 706 707 static const struct of_device_id cdns_spi_of_match[] = { 708 { .compatible = "xlnx,zynq-spi-r1p6" }, 709 { .compatible = "cdns,spi-r1p6" }, 710 { /* end of table */ } 711 }; 712 MODULE_DEVICE_TABLE(of, cdns_spi_of_match); 713 714 /* cdns_spi_driver - This structure defines the SPI subsystem platform driver */ 715 static struct platform_driver cdns_spi_driver = { 716 .probe = cdns_spi_probe, 717 .remove = cdns_spi_remove, 718 .driver = { 719 .name = CDNS_SPI_NAME, 720 .of_match_table = cdns_spi_of_match, 721 .pm = &cdns_spi_dev_pm_ops, 722 }, 723 }; 724 725 module_platform_driver(cdns_spi_driver); 726 727 MODULE_AUTHOR("Xilinx, Inc."); 728 MODULE_DESCRIPTION("Cadence SPI driver"); 729 MODULE_LICENSE("GPL"); 730