xref: /openbmc/linux/drivers/spi/spi-cadence.c (revision 62e59c4e)
1 /*
2  * Cadence SPI controller driver (master mode only)
3  *
4  * Copyright (C) 2008 - 2014 Xilinx, Inc.
5  *
6  * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
7  *
8  * This program is free software; you can redistribute it and/or modify it under
9  * the terms of the GNU General Public License version 2 as published by the
10  * Free Software Foundation; either version 2 of the License, or (at your
11  * option) any later version.
12  */
13 
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_address.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/spi/spi.h>
25 
26 /* Name of this driver */
27 #define CDNS_SPI_NAME		"cdns-spi"
28 
29 /* Register offset definitions */
30 #define CDNS_SPI_CR	0x00 /* Configuration  Register, RW */
31 #define CDNS_SPI_ISR	0x04 /* Interrupt Status Register, RO */
32 #define CDNS_SPI_IER	0x08 /* Interrupt Enable Register, WO */
33 #define CDNS_SPI_IDR	0x0c /* Interrupt Disable Register, WO */
34 #define CDNS_SPI_IMR	0x10 /* Interrupt Enabled Mask Register, RO */
35 #define CDNS_SPI_ER	0x14 /* Enable/Disable Register, RW */
36 #define CDNS_SPI_DR	0x18 /* Delay Register, RW */
37 #define CDNS_SPI_TXD	0x1C /* Data Transmit Register, WO */
38 #define CDNS_SPI_RXD	0x20 /* Data Receive Register, RO */
39 #define CDNS_SPI_SICR	0x24 /* Slave Idle Count Register, RW */
40 #define CDNS_SPI_THLD	0x28 /* Transmit FIFO Watermark Register,RW */
41 
42 #define SPI_AUTOSUSPEND_TIMEOUT		3000
43 /*
44  * SPI Configuration Register bit Masks
45  *
46  * This register contains various control bits that affect the operation
47  * of the SPI controller
48  */
49 #define CDNS_SPI_CR_MANSTRT	0x00010000 /* Manual TX Start */
50 #define CDNS_SPI_CR_CPHA		0x00000004 /* Clock Phase Control */
51 #define CDNS_SPI_CR_CPOL		0x00000002 /* Clock Polarity Control */
52 #define CDNS_SPI_CR_SSCTRL		0x00003C00 /* Slave Select Mask */
53 #define CDNS_SPI_CR_PERI_SEL	0x00000200 /* Peripheral Select Decode */
54 #define CDNS_SPI_CR_BAUD_DIV	0x00000038 /* Baud Rate Divisor Mask */
55 #define CDNS_SPI_CR_MSTREN		0x00000001 /* Master Enable Mask */
56 #define CDNS_SPI_CR_MANSTRTEN	0x00008000 /* Manual TX Enable Mask */
57 #define CDNS_SPI_CR_SSFORCE	0x00004000 /* Manual SS Enable Mask */
58 #define CDNS_SPI_CR_BAUD_DIV_4	0x00000008 /* Default Baud Div Mask */
59 #define CDNS_SPI_CR_DEFAULT	(CDNS_SPI_CR_MSTREN | \
60 					CDNS_SPI_CR_SSCTRL | \
61 					CDNS_SPI_CR_SSFORCE | \
62 					CDNS_SPI_CR_BAUD_DIV_4)
63 
64 /*
65  * SPI Configuration Register - Baud rate and slave select
66  *
67  * These are the values used in the calculation of baud rate divisor and
68  * setting the slave select.
69  */
70 
71 #define CDNS_SPI_BAUD_DIV_MAX		7 /* Baud rate divisor maximum */
72 #define CDNS_SPI_BAUD_DIV_MIN		1 /* Baud rate divisor minimum */
73 #define CDNS_SPI_BAUD_DIV_SHIFT		3 /* Baud rate divisor shift in CR */
74 #define CDNS_SPI_SS_SHIFT		10 /* Slave Select field shift in CR */
75 #define CDNS_SPI_SS0			0x1 /* Slave Select zero */
76 
77 /*
78  * SPI Interrupt Registers bit Masks
79  *
80  * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
81  * bit definitions.
82  */
83 #define CDNS_SPI_IXR_TXOW	0x00000004 /* SPI TX FIFO Overwater */
84 #define CDNS_SPI_IXR_MODF	0x00000002 /* SPI Mode Fault */
85 #define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */
86 #define CDNS_SPI_IXR_DEFAULT	(CDNS_SPI_IXR_TXOW | \
87 					CDNS_SPI_IXR_MODF)
88 #define CDNS_SPI_IXR_TXFULL	0x00000008 /* SPI TX Full */
89 #define CDNS_SPI_IXR_ALL	0x0000007F /* SPI all interrupts */
90 
91 /*
92  * SPI Enable Register bit Masks
93  *
94  * This register is used to enable or disable the SPI controller
95  */
96 #define CDNS_SPI_ER_ENABLE	0x00000001 /* SPI Enable Bit Mask */
97 #define CDNS_SPI_ER_DISABLE	0x0 /* SPI Disable Bit Mask */
98 
99 /* SPI FIFO depth in bytes */
100 #define CDNS_SPI_FIFO_DEPTH	128
101 
102 /* Default number of chip select lines */
103 #define CDNS_SPI_DEFAULT_NUM_CS		4
104 
105 /**
106  * struct cdns_spi - This definition defines spi driver instance
107  * @regs:		Virtual address of the SPI controller registers
108  * @ref_clk:		Pointer to the peripheral clock
109  * @pclk:		Pointer to the APB clock
110  * @speed_hz:		Current SPI bus clock speed in Hz
111  * @txbuf:		Pointer	to the TX buffer
112  * @rxbuf:		Pointer to the RX buffer
113  * @tx_bytes:		Number of bytes left to transfer
114  * @rx_bytes:		Number of bytes requested
115  * @dev_busy:		Device busy flag
116  * @is_decoded_cs:	Flag for decoder property set or not
117  */
118 struct cdns_spi {
119 	void __iomem *regs;
120 	struct clk *ref_clk;
121 	struct clk *pclk;
122 	u32 speed_hz;
123 	const u8 *txbuf;
124 	u8 *rxbuf;
125 	int tx_bytes;
126 	int rx_bytes;
127 	u8 dev_busy;
128 	u32 is_decoded_cs;
129 };
130 
131 /* Macros for the SPI controller read/write */
132 static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset)
133 {
134 	return readl_relaxed(xspi->regs + offset);
135 }
136 
137 static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
138 {
139 	writel_relaxed(val, xspi->regs + offset);
140 }
141 
142 /**
143  * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller
144  * @xspi:	Pointer to the cdns_spi structure
145  *
146  * On reset the SPI controller is configured to be in master mode, baud rate
147  * divisor is set to 4, threshold value for TX FIFO not full interrupt is set
148  * to 1 and size of the word to be transferred as 8 bit.
149  * This function initializes the SPI controller to disable and clear all the
150  * interrupts, enable manual slave select and manual start, deselect all the
151  * chip select lines, and enable the SPI controller.
152  */
153 static void cdns_spi_init_hw(struct cdns_spi *xspi)
154 {
155 	u32 ctrl_reg = CDNS_SPI_CR_DEFAULT;
156 
157 	if (xspi->is_decoded_cs)
158 		ctrl_reg |= CDNS_SPI_CR_PERI_SEL;
159 
160 	cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
161 	cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_ALL);
162 
163 	/* Clear the RX FIFO */
164 	while (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_RXNEMTY)
165 		cdns_spi_read(xspi, CDNS_SPI_RXD);
166 
167 	cdns_spi_write(xspi, CDNS_SPI_ISR, CDNS_SPI_IXR_ALL);
168 	cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
169 	cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
170 }
171 
172 /**
173  * cdns_spi_chipselect - Select or deselect the chip select line
174  * @spi:	Pointer to the spi_device structure
175  * @enable:	Select (1) or deselect (0) the chip select line
176  */
177 static void cdns_spi_chipselect(struct spi_device *spi, bool enable)
178 {
179 	struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
180 	u32 ctrl_reg;
181 
182 	ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
183 
184 	if (!enable) {
185 		/* Deselect the slave */
186 		ctrl_reg |= CDNS_SPI_CR_SSCTRL;
187 	} else {
188 		/* Select the slave */
189 		ctrl_reg &= ~CDNS_SPI_CR_SSCTRL;
190 		if (!(xspi->is_decoded_cs))
191 			ctrl_reg |= ((~(CDNS_SPI_SS0 << spi->chip_select)) <<
192 				     CDNS_SPI_SS_SHIFT) &
193 				     CDNS_SPI_CR_SSCTRL;
194 		else
195 			ctrl_reg |= (spi->chip_select << CDNS_SPI_SS_SHIFT) &
196 				     CDNS_SPI_CR_SSCTRL;
197 	}
198 
199 	cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
200 }
201 
202 /**
203  * cdns_spi_config_clock_mode - Sets clock polarity and phase
204  * @spi:	Pointer to the spi_device structure
205  *
206  * Sets the requested clock polarity and phase.
207  */
208 static void cdns_spi_config_clock_mode(struct spi_device *spi)
209 {
210 	struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
211 	u32 ctrl_reg, new_ctrl_reg;
212 
213 	new_ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
214 	ctrl_reg = new_ctrl_reg;
215 
216 	/* Set the SPI clock phase and clock polarity */
217 	new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA | CDNS_SPI_CR_CPOL);
218 	if (spi->mode & SPI_CPHA)
219 		new_ctrl_reg |= CDNS_SPI_CR_CPHA;
220 	if (spi->mode & SPI_CPOL)
221 		new_ctrl_reg |= CDNS_SPI_CR_CPOL;
222 
223 	if (new_ctrl_reg != ctrl_reg) {
224 		/*
225 		 * Just writing the CR register does not seem to apply the clock
226 		 * setting changes. This is problematic when changing the clock
227 		 * polarity as it will cause the SPI slave to see spurious clock
228 		 * transitions. To workaround the issue toggle the ER register.
229 		 */
230 		cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
231 		cdns_spi_write(xspi, CDNS_SPI_CR, new_ctrl_reg);
232 		cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
233 	}
234 }
235 
236 /**
237  * cdns_spi_config_clock_freq - Sets clock frequency
238  * @spi:	Pointer to the spi_device structure
239  * @transfer:	Pointer to the spi_transfer structure which provides
240  *		information about next transfer setup parameters
241  *
242  * Sets the requested clock frequency.
243  * Note: If the requested frequency is not an exact match with what can be
244  * obtained using the prescalar value the driver sets the clock frequency which
245  * is lower than the requested frequency (maximum lower) for the transfer. If
246  * the requested frequency is higher or lower than that is supported by the SPI
247  * controller the driver will set the highest or lowest frequency supported by
248  * controller.
249  */
250 static void cdns_spi_config_clock_freq(struct spi_device *spi,
251 				       struct spi_transfer *transfer)
252 {
253 	struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
254 	u32 ctrl_reg, baud_rate_val;
255 	unsigned long frequency;
256 
257 	frequency = clk_get_rate(xspi->ref_clk);
258 
259 	ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
260 
261 	/* Set the clock frequency */
262 	if (xspi->speed_hz != transfer->speed_hz) {
263 		/* first valid value is 1 */
264 		baud_rate_val = CDNS_SPI_BAUD_DIV_MIN;
265 		while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) &&
266 		       (frequency / (2 << baud_rate_val)) > transfer->speed_hz)
267 			baud_rate_val++;
268 
269 		ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV;
270 		ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT;
271 
272 		xspi->speed_hz = frequency / (2 << baud_rate_val);
273 	}
274 	cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
275 }
276 
277 /**
278  * cdns_spi_setup_transfer - Configure SPI controller for specified transfer
279  * @spi:	Pointer to the spi_device structure
280  * @transfer:	Pointer to the spi_transfer structure which provides
281  *		information about next transfer setup parameters
282  *
283  * Sets the operational mode of SPI controller for the next SPI transfer and
284  * sets the requested clock frequency.
285  *
286  * Return:	Always 0
287  */
288 static int cdns_spi_setup_transfer(struct spi_device *spi,
289 				   struct spi_transfer *transfer)
290 {
291 	struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
292 
293 	cdns_spi_config_clock_freq(spi, transfer);
294 
295 	dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n",
296 		__func__, spi->mode, spi->bits_per_word,
297 		xspi->speed_hz);
298 
299 	return 0;
300 }
301 
302 /**
303  * cdns_spi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
304  * @xspi:	Pointer to the cdns_spi structure
305  */
306 static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi)
307 {
308 	unsigned long trans_cnt = 0;
309 
310 	while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) &&
311 	       (xspi->tx_bytes > 0)) {
312 
313 		/* When xspi in busy condition, bytes may send failed,
314 		 * then spi control did't work thoroughly, add one byte delay
315 		 */
316 		if (cdns_spi_read(xspi, CDNS_SPI_ISR) &
317 		    CDNS_SPI_IXR_TXFULL)
318 			udelay(10);
319 
320 		if (xspi->txbuf)
321 			cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
322 		else
323 			cdns_spi_write(xspi, CDNS_SPI_TXD, 0);
324 
325 		xspi->tx_bytes--;
326 		trans_cnt++;
327 	}
328 }
329 
330 /**
331  * cdns_spi_irq - Interrupt service routine of the SPI controller
332  * @irq:	IRQ number
333  * @dev_id:	Pointer to the xspi structure
334  *
335  * This function handles TX empty and Mode Fault interrupts only.
336  * On TX empty interrupt this function reads the received data from RX FIFO and
337  * fills the TX FIFO if there is any data remaining to be transferred.
338  * On Mode Fault interrupt this function indicates that transfer is completed,
339  * the SPI subsystem will identify the error as the remaining bytes to be
340  * transferred is non-zero.
341  *
342  * Return:	IRQ_HANDLED when handled; IRQ_NONE otherwise.
343  */
344 static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
345 {
346 	struct spi_master *master = dev_id;
347 	struct cdns_spi *xspi = spi_master_get_devdata(master);
348 	u32 intr_status, status;
349 
350 	status = IRQ_NONE;
351 	intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
352 	cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
353 
354 	if (intr_status & CDNS_SPI_IXR_MODF) {
355 		/* Indicate that transfer is completed, the SPI subsystem will
356 		 * identify the error as the remaining bytes to be
357 		 * transferred is non-zero
358 		 */
359 		cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_DEFAULT);
360 		spi_finalize_current_transfer(master);
361 		status = IRQ_HANDLED;
362 	} else if (intr_status & CDNS_SPI_IXR_TXOW) {
363 		unsigned long trans_cnt;
364 
365 		trans_cnt = xspi->rx_bytes - xspi->tx_bytes;
366 
367 		/* Read out the data from the RX FIFO */
368 		while (trans_cnt) {
369 			u8 data;
370 
371 			data = cdns_spi_read(xspi, CDNS_SPI_RXD);
372 			if (xspi->rxbuf)
373 				*xspi->rxbuf++ = data;
374 
375 			xspi->rx_bytes--;
376 			trans_cnt--;
377 		}
378 
379 		if (xspi->tx_bytes) {
380 			/* There is more data to send */
381 			cdns_spi_fill_tx_fifo(xspi);
382 		} else {
383 			/* Transfer is completed */
384 			cdns_spi_write(xspi, CDNS_SPI_IDR,
385 				       CDNS_SPI_IXR_DEFAULT);
386 			spi_finalize_current_transfer(master);
387 		}
388 		status = IRQ_HANDLED;
389 	}
390 
391 	return status;
392 }
393 
394 static int cdns_prepare_message(struct spi_master *master,
395 				struct spi_message *msg)
396 {
397 	cdns_spi_config_clock_mode(msg->spi);
398 	return 0;
399 }
400 
401 /**
402  * cdns_transfer_one - Initiates the SPI transfer
403  * @master:	Pointer to spi_master structure
404  * @spi:	Pointer to the spi_device structure
405  * @transfer:	Pointer to the spi_transfer structure which provides
406  *		information about next transfer parameters
407  *
408  * This function fills the TX FIFO, starts the SPI transfer and
409  * returns a positive transfer count so that core will wait for completion.
410  *
411  * Return:	Number of bytes transferred in the last transfer
412  */
413 static int cdns_transfer_one(struct spi_master *master,
414 			     struct spi_device *spi,
415 			     struct spi_transfer *transfer)
416 {
417 	struct cdns_spi *xspi = spi_master_get_devdata(master);
418 
419 	xspi->txbuf = transfer->tx_buf;
420 	xspi->rxbuf = transfer->rx_buf;
421 	xspi->tx_bytes = transfer->len;
422 	xspi->rx_bytes = transfer->len;
423 
424 	cdns_spi_setup_transfer(spi, transfer);
425 
426 	cdns_spi_fill_tx_fifo(xspi);
427 
428 	cdns_spi_write(xspi, CDNS_SPI_IER, CDNS_SPI_IXR_DEFAULT);
429 	return transfer->len;
430 }
431 
432 /**
433  * cdns_prepare_transfer_hardware - Prepares hardware for transfer.
434  * @master:	Pointer to the spi_master structure which provides
435  *		information about the controller.
436  *
437  * This function enables SPI master controller.
438  *
439  * Return:	0 always
440  */
441 static int cdns_prepare_transfer_hardware(struct spi_master *master)
442 {
443 	struct cdns_spi *xspi = spi_master_get_devdata(master);
444 
445 	cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
446 
447 	return 0;
448 }
449 
450 /**
451  * cdns_unprepare_transfer_hardware - Relaxes hardware after transfer
452  * @master:	Pointer to the spi_master structure which provides
453  *		information about the controller.
454  *
455  * This function disables the SPI master controller.
456  *
457  * Return:	0 always
458  */
459 static int cdns_unprepare_transfer_hardware(struct spi_master *master)
460 {
461 	struct cdns_spi *xspi = spi_master_get_devdata(master);
462 
463 	cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
464 
465 	return 0;
466 }
467 
468 /**
469  * cdns_spi_probe - Probe method for the SPI driver
470  * @pdev:	Pointer to the platform_device structure
471  *
472  * This function initializes the driver data structures and the hardware.
473  *
474  * Return:	0 on success and error value on error
475  */
476 static int cdns_spi_probe(struct platform_device *pdev)
477 {
478 	int ret = 0, irq;
479 	struct spi_master *master;
480 	struct cdns_spi *xspi;
481 	struct resource *res;
482 	u32 num_cs;
483 
484 	master = spi_alloc_master(&pdev->dev, sizeof(*xspi));
485 	if (!master)
486 		return -ENOMEM;
487 
488 	xspi = spi_master_get_devdata(master);
489 	master->dev.of_node = pdev->dev.of_node;
490 	platform_set_drvdata(pdev, master);
491 
492 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
493 	xspi->regs = devm_ioremap_resource(&pdev->dev, res);
494 	if (IS_ERR(xspi->regs)) {
495 		ret = PTR_ERR(xspi->regs);
496 		goto remove_master;
497 	}
498 
499 	xspi->pclk = devm_clk_get(&pdev->dev, "pclk");
500 	if (IS_ERR(xspi->pclk)) {
501 		dev_err(&pdev->dev, "pclk clock not found.\n");
502 		ret = PTR_ERR(xspi->pclk);
503 		goto remove_master;
504 	}
505 
506 	xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
507 	if (IS_ERR(xspi->ref_clk)) {
508 		dev_err(&pdev->dev, "ref_clk clock not found.\n");
509 		ret = PTR_ERR(xspi->ref_clk);
510 		goto remove_master;
511 	}
512 
513 	ret = clk_prepare_enable(xspi->pclk);
514 	if (ret) {
515 		dev_err(&pdev->dev, "Unable to enable APB clock.\n");
516 		goto remove_master;
517 	}
518 
519 	ret = clk_prepare_enable(xspi->ref_clk);
520 	if (ret) {
521 		dev_err(&pdev->dev, "Unable to enable device clock.\n");
522 		goto clk_dis_apb;
523 	}
524 
525 	ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
526 	if (ret < 0)
527 		master->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
528 	else
529 		master->num_chipselect = num_cs;
530 
531 	ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
532 				   &xspi->is_decoded_cs);
533 	if (ret < 0)
534 		xspi->is_decoded_cs = 0;
535 
536 	/* SPI controller initializations */
537 	cdns_spi_init_hw(xspi);
538 
539 	pm_runtime_set_active(&pdev->dev);
540 	pm_runtime_enable(&pdev->dev);
541 	pm_runtime_use_autosuspend(&pdev->dev);
542 	pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
543 
544 	irq = platform_get_irq(pdev, 0);
545 	if (irq <= 0) {
546 		ret = -ENXIO;
547 		dev_err(&pdev->dev, "irq number is invalid\n");
548 		goto clk_dis_all;
549 	}
550 
551 	ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq,
552 			       0, pdev->name, master);
553 	if (ret != 0) {
554 		ret = -ENXIO;
555 		dev_err(&pdev->dev, "request_irq failed\n");
556 		goto clk_dis_all;
557 	}
558 
559 	master->use_gpio_descriptors = true;
560 	master->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
561 	master->prepare_message = cdns_prepare_message;
562 	master->transfer_one = cdns_transfer_one;
563 	master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
564 	master->set_cs = cdns_spi_chipselect;
565 	master->auto_runtime_pm = true;
566 	master->mode_bits = SPI_CPOL | SPI_CPHA;
567 
568 	/* Set to default valid value */
569 	master->max_speed_hz = clk_get_rate(xspi->ref_clk) / 4;
570 	xspi->speed_hz = master->max_speed_hz;
571 
572 	master->bits_per_word_mask = SPI_BPW_MASK(8);
573 
574 	ret = spi_register_master(master);
575 	if (ret) {
576 		dev_err(&pdev->dev, "spi_register_master failed\n");
577 		goto clk_dis_all;
578 	}
579 
580 	return ret;
581 
582 clk_dis_all:
583 	pm_runtime_set_suspended(&pdev->dev);
584 	pm_runtime_disable(&pdev->dev);
585 	clk_disable_unprepare(xspi->ref_clk);
586 clk_dis_apb:
587 	clk_disable_unprepare(xspi->pclk);
588 remove_master:
589 	spi_master_put(master);
590 	return ret;
591 }
592 
593 /**
594  * cdns_spi_remove - Remove method for the SPI driver
595  * @pdev:	Pointer to the platform_device structure
596  *
597  * This function is called if a device is physically removed from the system or
598  * if the driver module is being unloaded. It frees all resources allocated to
599  * the device.
600  *
601  * Return:	0 on success and error value on error
602  */
603 static int cdns_spi_remove(struct platform_device *pdev)
604 {
605 	struct spi_master *master = platform_get_drvdata(pdev);
606 	struct cdns_spi *xspi = spi_master_get_devdata(master);
607 
608 	cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
609 
610 	clk_disable_unprepare(xspi->ref_clk);
611 	clk_disable_unprepare(xspi->pclk);
612 	pm_runtime_set_suspended(&pdev->dev);
613 	pm_runtime_disable(&pdev->dev);
614 
615 	spi_unregister_master(master);
616 
617 	return 0;
618 }
619 
620 /**
621  * cdns_spi_suspend - Suspend method for the SPI driver
622  * @dev:	Address of the platform_device structure
623  *
624  * This function disables the SPI controller and
625  * changes the driver state to "suspend"
626  *
627  * Return:	0 on success and error value on error
628  */
629 static int __maybe_unused cdns_spi_suspend(struct device *dev)
630 {
631 	struct spi_master *master = dev_get_drvdata(dev);
632 
633 	return spi_master_suspend(master);
634 }
635 
636 /**
637  * cdns_spi_resume - Resume method for the SPI driver
638  * @dev:	Address of the platform_device structure
639  *
640  * This function changes the driver state to "ready"
641  *
642  * Return:	0 on success and error value on error
643  */
644 static int __maybe_unused cdns_spi_resume(struct device *dev)
645 {
646 	struct spi_master *master = dev_get_drvdata(dev);
647 	struct cdns_spi *xspi = spi_master_get_devdata(master);
648 
649 	cdns_spi_init_hw(xspi);
650 	return spi_master_resume(master);
651 }
652 
653 /**
654  * cdns_spi_runtime_resume - Runtime resume method for the SPI driver
655  * @dev:	Address of the platform_device structure
656  *
657  * This function enables the clocks
658  *
659  * Return:	0 on success and error value on error
660  */
661 static int __maybe_unused cnds_runtime_resume(struct device *dev)
662 {
663 	struct spi_master *master = dev_get_drvdata(dev);
664 	struct cdns_spi *xspi = spi_master_get_devdata(master);
665 	int ret;
666 
667 	ret = clk_prepare_enable(xspi->pclk);
668 	if (ret) {
669 		dev_err(dev, "Cannot enable APB clock.\n");
670 		return ret;
671 	}
672 
673 	ret = clk_prepare_enable(xspi->ref_clk);
674 	if (ret) {
675 		dev_err(dev, "Cannot enable device clock.\n");
676 		clk_disable_unprepare(xspi->pclk);
677 		return ret;
678 	}
679 	return 0;
680 }
681 
682 /**
683  * cdns_spi_runtime_suspend - Runtime suspend method for the SPI driver
684  * @dev:	Address of the platform_device structure
685  *
686  * This function disables the clocks
687  *
688  * Return:	Always 0
689  */
690 static int __maybe_unused cnds_runtime_suspend(struct device *dev)
691 {
692 	struct spi_master *master = dev_get_drvdata(dev);
693 	struct cdns_spi *xspi = spi_master_get_devdata(master);
694 
695 	clk_disable_unprepare(xspi->ref_clk);
696 	clk_disable_unprepare(xspi->pclk);
697 
698 	return 0;
699 }
700 
701 static const struct dev_pm_ops cdns_spi_dev_pm_ops = {
702 	SET_RUNTIME_PM_OPS(cnds_runtime_suspend,
703 			   cnds_runtime_resume, NULL)
704 	SET_SYSTEM_SLEEP_PM_OPS(cdns_spi_suspend, cdns_spi_resume)
705 };
706 
707 static const struct of_device_id cdns_spi_of_match[] = {
708 	{ .compatible = "xlnx,zynq-spi-r1p6" },
709 	{ .compatible = "cdns,spi-r1p6" },
710 	{ /* end of table */ }
711 };
712 MODULE_DEVICE_TABLE(of, cdns_spi_of_match);
713 
714 /* cdns_spi_driver - This structure defines the SPI subsystem platform driver */
715 static struct platform_driver cdns_spi_driver = {
716 	.probe	= cdns_spi_probe,
717 	.remove	= cdns_spi_remove,
718 	.driver = {
719 		.name = CDNS_SPI_NAME,
720 		.of_match_table = cdns_spi_of_match,
721 		.pm = &cdns_spi_dev_pm_ops,
722 	},
723 };
724 
725 module_platform_driver(cdns_spi_driver);
726 
727 MODULE_AUTHOR("Xilinx, Inc.");
728 MODULE_DESCRIPTION("Cadence SPI driver");
729 MODULE_LICENSE("GPL");
730