xref: /openbmc/linux/drivers/spi/spi-cadence.c (revision 3ddc8b84)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Cadence SPI controller driver (host and target mode)
4  *
5  * Copyright (C) 2008 - 2014 Xilinx, Inc.
6  *
7  * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
8  */
9 
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/of_irq.h>
18 #include <linux/of_address.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/spi/spi.h>
22 
23 /* Name of this driver */
24 #define CDNS_SPI_NAME		"cdns-spi"
25 
26 /* Register offset definitions */
27 #define CDNS_SPI_CR	0x00 /* Configuration  Register, RW */
28 #define CDNS_SPI_ISR	0x04 /* Interrupt Status Register, RO */
29 #define CDNS_SPI_IER	0x08 /* Interrupt Enable Register, WO */
30 #define CDNS_SPI_IDR	0x0c /* Interrupt Disable Register, WO */
31 #define CDNS_SPI_IMR	0x10 /* Interrupt Enabled Mask Register, RO */
32 #define CDNS_SPI_ER	0x14 /* Enable/Disable Register, RW */
33 #define CDNS_SPI_DR	0x18 /* Delay Register, RW */
34 #define CDNS_SPI_TXD	0x1C /* Data Transmit Register, WO */
35 #define CDNS_SPI_RXD	0x20 /* Data Receive Register, RO */
36 #define CDNS_SPI_SICR	0x24 /* Slave Idle Count Register, RW */
37 #define CDNS_SPI_THLD	0x28 /* Transmit FIFO Watermark Register,RW */
38 
39 #define SPI_AUTOSUSPEND_TIMEOUT		3000
40 /*
41  * SPI Configuration Register bit Masks
42  *
43  * This register contains various control bits that affect the operation
44  * of the SPI controller
45  */
46 #define CDNS_SPI_CR_MANSTRT	0x00010000 /* Manual TX Start */
47 #define CDNS_SPI_CR_CPHA		0x00000004 /* Clock Phase Control */
48 #define CDNS_SPI_CR_CPOL		0x00000002 /* Clock Polarity Control */
49 #define CDNS_SPI_CR_SSCTRL		0x00003C00 /* Slave Select Mask */
50 #define CDNS_SPI_CR_PERI_SEL	0x00000200 /* Peripheral Select Decode */
51 #define CDNS_SPI_CR_BAUD_DIV	0x00000038 /* Baud Rate Divisor Mask */
52 #define CDNS_SPI_CR_MSTREN		0x00000001 /* Master Enable Mask */
53 #define CDNS_SPI_CR_MANSTRTEN	0x00008000 /* Manual TX Enable Mask */
54 #define CDNS_SPI_CR_SSFORCE	0x00004000 /* Manual SS Enable Mask */
55 #define CDNS_SPI_CR_BAUD_DIV_4	0x00000008 /* Default Baud Div Mask */
56 #define CDNS_SPI_CR_DEFAULT	(CDNS_SPI_CR_MSTREN | \
57 					CDNS_SPI_CR_SSCTRL | \
58 					CDNS_SPI_CR_SSFORCE | \
59 					CDNS_SPI_CR_BAUD_DIV_4)
60 
61 /*
62  * SPI Configuration Register - Baud rate and target select
63  *
64  * These are the values used in the calculation of baud rate divisor and
65  * setting the target select.
66  */
67 
68 #define CDNS_SPI_BAUD_DIV_MAX		7 /* Baud rate divisor maximum */
69 #define CDNS_SPI_BAUD_DIV_MIN		1 /* Baud rate divisor minimum */
70 #define CDNS_SPI_BAUD_DIV_SHIFT		3 /* Baud rate divisor shift in CR */
71 #define CDNS_SPI_SS_SHIFT		10 /* Slave Select field shift in CR */
72 #define CDNS_SPI_SS0			0x1 /* Slave Select zero */
73 #define CDNS_SPI_NOSS			0xF /* No Slave select */
74 
75 /*
76  * SPI Interrupt Registers bit Masks
77  *
78  * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
79  * bit definitions.
80  */
81 #define CDNS_SPI_IXR_TXOW	0x00000004 /* SPI TX FIFO Overwater */
82 #define CDNS_SPI_IXR_MODF	0x00000002 /* SPI Mode Fault */
83 #define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */
84 #define CDNS_SPI_IXR_DEFAULT	(CDNS_SPI_IXR_TXOW | \
85 					CDNS_SPI_IXR_MODF)
86 #define CDNS_SPI_IXR_TXFULL	0x00000008 /* SPI TX Full */
87 #define CDNS_SPI_IXR_ALL	0x0000007F /* SPI all interrupts */
88 
89 /*
90  * SPI Enable Register bit Masks
91  *
92  * This register is used to enable or disable the SPI controller
93  */
94 #define CDNS_SPI_ER_ENABLE	0x00000001 /* SPI Enable Bit Mask */
95 #define CDNS_SPI_ER_DISABLE	0x0 /* SPI Disable Bit Mask */
96 
97 /* Default number of chip select lines */
98 #define CDNS_SPI_DEFAULT_NUM_CS		4
99 
100 /**
101  * struct cdns_spi - This definition defines spi driver instance
102  * @regs:		Virtual address of the SPI controller registers
103  * @ref_clk:		Pointer to the peripheral clock
104  * @pclk:		Pointer to the APB clock
105  * @clk_rate:		Reference clock frequency, taken from @ref_clk
106  * @speed_hz:		Current SPI bus clock speed in Hz
107  * @txbuf:		Pointer	to the TX buffer
108  * @rxbuf:		Pointer to the RX buffer
109  * @tx_bytes:		Number of bytes left to transfer
110  * @rx_bytes:		Number of bytes requested
111  * @dev_busy:		Device busy flag
112  * @is_decoded_cs:	Flag for decoder property set or not
113  * @tx_fifo_depth:	Depth of the TX FIFO
114  */
115 struct cdns_spi {
116 	void __iomem *regs;
117 	struct clk *ref_clk;
118 	struct clk *pclk;
119 	unsigned int clk_rate;
120 	u32 speed_hz;
121 	const u8 *txbuf;
122 	u8 *rxbuf;
123 	int tx_bytes;
124 	int rx_bytes;
125 	u8 dev_busy;
126 	u32 is_decoded_cs;
127 	unsigned int tx_fifo_depth;
128 };
129 
130 /* Macros for the SPI controller read/write */
131 static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset)
132 {
133 	return readl_relaxed(xspi->regs + offset);
134 }
135 
136 static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
137 {
138 	writel_relaxed(val, xspi->regs + offset);
139 }
140 
141 /**
142  * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller
143  * @xspi:	Pointer to the cdns_spi structure
144  * @is_target:	Flag to indicate target or host mode
145  * * On reset the SPI controller is configured to target or host mode.
146  * In host mode baud rate divisor is set to 4, threshold value for TX FIFO
147  * not full interrupt is set to 1 and size of the word to be transferred as 8 bit.
148  *
149  * This function initializes the SPI controller to disable and clear all the
150  * interrupts, enable manual target select and manual start, deselect all the
151  * chip select lines, and enable the SPI controller.
152  */
153 static void cdns_spi_init_hw(struct cdns_spi *xspi, bool is_target)
154 {
155 	u32 ctrl_reg = 0;
156 
157 	if (!is_target)
158 		ctrl_reg |= CDNS_SPI_CR_DEFAULT;
159 
160 	if (xspi->is_decoded_cs)
161 		ctrl_reg |= CDNS_SPI_CR_PERI_SEL;
162 
163 	cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
164 	cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_ALL);
165 
166 	/* Clear the RX FIFO */
167 	while (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_RXNEMTY)
168 		cdns_spi_read(xspi, CDNS_SPI_RXD);
169 
170 	cdns_spi_write(xspi, CDNS_SPI_ISR, CDNS_SPI_IXR_ALL);
171 	cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
172 	cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
173 }
174 
175 /**
176  * cdns_spi_chipselect - Select or deselect the chip select line
177  * @spi:	Pointer to the spi_device structure
178  * @is_high:	Select(0) or deselect (1) the chip select line
179  */
180 static void cdns_spi_chipselect(struct spi_device *spi, bool is_high)
181 {
182 	struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
183 	u32 ctrl_reg;
184 
185 	ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
186 
187 	if (is_high) {
188 		/* Deselect the target */
189 		ctrl_reg |= CDNS_SPI_CR_SSCTRL;
190 	} else {
191 		/* Select the target */
192 		ctrl_reg &= ~CDNS_SPI_CR_SSCTRL;
193 		if (!(xspi->is_decoded_cs))
194 			ctrl_reg |= ((~(CDNS_SPI_SS0 << spi_get_chipselect(spi, 0))) <<
195 				     CDNS_SPI_SS_SHIFT) &
196 				     CDNS_SPI_CR_SSCTRL;
197 		else
198 			ctrl_reg |= (spi_get_chipselect(spi, 0) << CDNS_SPI_SS_SHIFT) &
199 				     CDNS_SPI_CR_SSCTRL;
200 	}
201 
202 	cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
203 }
204 
205 /**
206  * cdns_spi_config_clock_mode - Sets clock polarity and phase
207  * @spi:	Pointer to the spi_device structure
208  *
209  * Sets the requested clock polarity and phase.
210  */
211 static void cdns_spi_config_clock_mode(struct spi_device *spi)
212 {
213 	struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
214 	u32 ctrl_reg, new_ctrl_reg;
215 
216 	new_ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
217 	ctrl_reg = new_ctrl_reg;
218 
219 	/* Set the SPI clock phase and clock polarity */
220 	new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA | CDNS_SPI_CR_CPOL);
221 	if (spi->mode & SPI_CPHA)
222 		new_ctrl_reg |= CDNS_SPI_CR_CPHA;
223 	if (spi->mode & SPI_CPOL)
224 		new_ctrl_reg |= CDNS_SPI_CR_CPOL;
225 
226 	if (new_ctrl_reg != ctrl_reg) {
227 		/*
228 		 * Just writing the CR register does not seem to apply the clock
229 		 * setting changes. This is problematic when changing the clock
230 		 * polarity as it will cause the SPI target to see spurious clock
231 		 * transitions. To workaround the issue toggle the ER register.
232 		 */
233 		cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
234 		cdns_spi_write(xspi, CDNS_SPI_CR, new_ctrl_reg);
235 		cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
236 	}
237 }
238 
239 /**
240  * cdns_spi_config_clock_freq - Sets clock frequency
241  * @spi:	Pointer to the spi_device structure
242  * @transfer:	Pointer to the spi_transfer structure which provides
243  *		information about next transfer setup parameters
244  *
245  * Sets the requested clock frequency.
246  * Note: If the requested frequency is not an exact match with what can be
247  * obtained using the prescalar value the driver sets the clock frequency which
248  * is lower than the requested frequency (maximum lower) for the transfer. If
249  * the requested frequency is higher or lower than that is supported by the SPI
250  * controller the driver will set the highest or lowest frequency supported by
251  * controller.
252  */
253 static void cdns_spi_config_clock_freq(struct spi_device *spi,
254 				       struct spi_transfer *transfer)
255 {
256 	struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
257 	u32 ctrl_reg, baud_rate_val;
258 	unsigned long frequency;
259 
260 	frequency = xspi->clk_rate;
261 
262 	ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
263 
264 	/* Set the clock frequency */
265 	if (xspi->speed_hz != transfer->speed_hz) {
266 		/* first valid value is 1 */
267 		baud_rate_val = CDNS_SPI_BAUD_DIV_MIN;
268 		while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) &&
269 		       (frequency / (2 << baud_rate_val)) > transfer->speed_hz)
270 			baud_rate_val++;
271 
272 		ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV;
273 		ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT;
274 
275 		xspi->speed_hz = frequency / (2 << baud_rate_val);
276 	}
277 	cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
278 }
279 
280 /**
281  * cdns_spi_setup_transfer - Configure SPI controller for specified transfer
282  * @spi:	Pointer to the spi_device structure
283  * @transfer:	Pointer to the spi_transfer structure which provides
284  *		information about next transfer setup parameters
285  *
286  * Sets the operational mode of SPI controller for the next SPI transfer and
287  * sets the requested clock frequency.
288  *
289  * Return:	Always 0
290  */
291 static int cdns_spi_setup_transfer(struct spi_device *spi,
292 				   struct spi_transfer *transfer)
293 {
294 	struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
295 
296 	cdns_spi_config_clock_freq(spi, transfer);
297 
298 	dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n",
299 		__func__, spi->mode, spi->bits_per_word,
300 		xspi->speed_hz);
301 
302 	return 0;
303 }
304 
305 /**
306  * cdns_spi_process_fifo - Fills the TX FIFO, and drain the RX FIFO
307  * @xspi:	Pointer to the cdns_spi structure
308  * @ntx:	Number of bytes to pack into the TX FIFO
309  * @nrx:	Number of bytes to drain from the RX FIFO
310  */
311 static void cdns_spi_process_fifo(struct cdns_spi *xspi, int ntx, int nrx)
312 {
313 	ntx = clamp(ntx, 0, xspi->tx_bytes);
314 	nrx = clamp(nrx, 0, xspi->rx_bytes);
315 
316 	xspi->tx_bytes -= ntx;
317 	xspi->rx_bytes -= nrx;
318 
319 	while (ntx || nrx) {
320 		if (ntx) {
321 			if (xspi->txbuf)
322 				cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
323 			else
324 				cdns_spi_write(xspi, CDNS_SPI_TXD, 0);
325 
326 			ntx--;
327 		}
328 
329 		if (nrx) {
330 			u8 data = cdns_spi_read(xspi, CDNS_SPI_RXD);
331 
332 			if (xspi->rxbuf)
333 				*xspi->rxbuf++ = data;
334 
335 			nrx--;
336 		}
337 	}
338 }
339 
340 /**
341  * cdns_spi_irq - Interrupt service routine of the SPI controller
342  * @irq:	IRQ number
343  * @dev_id:	Pointer to the xspi structure
344  *
345  * This function handles TX empty and Mode Fault interrupts only.
346  * On TX empty interrupt this function reads the received data from RX FIFO and
347  * fills the TX FIFO if there is any data remaining to be transferred.
348  * On Mode Fault interrupt this function indicates that transfer is completed,
349  * the SPI subsystem will identify the error as the remaining bytes to be
350  * transferred is non-zero.
351  *
352  * Return:	IRQ_HANDLED when handled; IRQ_NONE otherwise.
353  */
354 static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
355 {
356 	struct spi_controller *ctlr = dev_id;
357 	struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
358 	irqreturn_t status;
359 	u32 intr_status;
360 
361 	status = IRQ_NONE;
362 	intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
363 	cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
364 
365 	if (intr_status & CDNS_SPI_IXR_MODF) {
366 		/* Indicate that transfer is completed, the SPI subsystem will
367 		 * identify the error as the remaining bytes to be
368 		 * transferred is non-zero
369 		 */
370 		cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_DEFAULT);
371 		spi_finalize_current_transfer(ctlr);
372 		status = IRQ_HANDLED;
373 	} else if (intr_status & CDNS_SPI_IXR_TXOW) {
374 		int threshold = cdns_spi_read(xspi, CDNS_SPI_THLD);
375 		int trans_cnt = xspi->rx_bytes - xspi->tx_bytes;
376 
377 		if (threshold > 1)
378 			trans_cnt -= threshold;
379 
380 		/* Set threshold to one if number of pending are
381 		 * less than half fifo
382 		 */
383 		if (xspi->tx_bytes < xspi->tx_fifo_depth >> 1)
384 			cdns_spi_write(xspi, CDNS_SPI_THLD, 1);
385 
386 		if (xspi->tx_bytes) {
387 			cdns_spi_process_fifo(xspi, trans_cnt, trans_cnt);
388 		} else {
389 			/* Fixed delay due to controller limitation with
390 			 * RX_NEMPTY incorrect status
391 			 * Xilinx AR:65885 contains more details
392 			 */
393 			udelay(10);
394 			cdns_spi_process_fifo(xspi, 0, trans_cnt);
395 			cdns_spi_write(xspi, CDNS_SPI_IDR,
396 				       CDNS_SPI_IXR_DEFAULT);
397 			spi_finalize_current_transfer(ctlr);
398 		}
399 		status = IRQ_HANDLED;
400 	}
401 
402 	return status;
403 }
404 
405 static int cdns_prepare_message(struct spi_controller *ctlr,
406 				struct spi_message *msg)
407 {
408 	if (!spi_controller_is_target(ctlr))
409 		cdns_spi_config_clock_mode(msg->spi);
410 	return 0;
411 }
412 
413 /**
414  * cdns_transfer_one - Initiates the SPI transfer
415  * @ctlr:	Pointer to spi_controller structure
416  * @spi:	Pointer to the spi_device structure
417  * @transfer:	Pointer to the spi_transfer structure which provides
418  *		information about next transfer parameters
419  *
420  * This function in host mode fills the TX FIFO, starts the SPI transfer and
421  * returns a positive transfer count so that core will wait for completion.
422  * This function in target mode fills the TX FIFO and wait for transfer trigger.
423  *
424  * Return:	Number of bytes transferred in the last transfer
425  */
426 static int cdns_transfer_one(struct spi_controller *ctlr,
427 			     struct spi_device *spi,
428 			     struct spi_transfer *transfer)
429 {
430 	struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
431 
432 	xspi->txbuf = transfer->tx_buf;
433 	xspi->rxbuf = transfer->rx_buf;
434 	xspi->tx_bytes = transfer->len;
435 	xspi->rx_bytes = transfer->len;
436 
437 	if (!spi_controller_is_target(ctlr)) {
438 		cdns_spi_setup_transfer(spi, transfer);
439 	} else {
440 		/* Set TX empty threshold to half of FIFO depth
441 		 * only if TX bytes are more than FIFO depth.
442 		 */
443 		if (xspi->tx_bytes > xspi->tx_fifo_depth)
444 			cdns_spi_write(xspi, CDNS_SPI_THLD, xspi->tx_fifo_depth >> 1);
445 	}
446 
447 	/* When xspi in busy condition, bytes may send failed,
448 	 * then spi control didn't work thoroughly, add one byte delay
449 	 */
450 	if (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_TXFULL)
451 		udelay(10);
452 
453 	cdns_spi_process_fifo(xspi, xspi->tx_fifo_depth, 0);
454 
455 	cdns_spi_write(xspi, CDNS_SPI_IER, CDNS_SPI_IXR_DEFAULT);
456 	return transfer->len;
457 }
458 
459 /**
460  * cdns_prepare_transfer_hardware - Prepares hardware for transfer.
461  * @ctlr:	Pointer to the spi_controller structure which provides
462  *		information about the controller.
463  *
464  * This function enables SPI host controller.
465  *
466  * Return:	0 always
467  */
468 static int cdns_prepare_transfer_hardware(struct spi_controller *ctlr)
469 {
470 	struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
471 
472 	cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
473 
474 	return 0;
475 }
476 
477 /**
478  * cdns_unprepare_transfer_hardware - Relaxes hardware after transfer
479  * @ctlr:	Pointer to the spi_controller structure which provides
480  *		information about the controller.
481  *
482  * This function disables the SPI host controller when no target selected.
483  * This function flush out if any pending data in FIFO.
484  *
485  * Return:	0 always
486  */
487 static int cdns_unprepare_transfer_hardware(struct spi_controller *ctlr)
488 {
489 	struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
490 	u32 ctrl_reg;
491 	unsigned int cnt = xspi->tx_fifo_depth;
492 
493 	if (spi_controller_is_target(ctlr)) {
494 		while (cnt--)
495 			cdns_spi_read(xspi, CDNS_SPI_RXD);
496 	}
497 
498 	/* Disable the SPI if target is deselected */
499 	ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
500 	ctrl_reg = (ctrl_reg & CDNS_SPI_CR_SSCTRL) >>  CDNS_SPI_SS_SHIFT;
501 	if (ctrl_reg == CDNS_SPI_NOSS || spi_controller_is_target(ctlr))
502 		cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
503 
504 	/* Reset to default */
505 	cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1);
506 	return 0;
507 }
508 
509 /**
510  * cdns_spi_detect_fifo_depth - Detect the FIFO depth of the hardware
511  * @xspi:	Pointer to the cdns_spi structure
512  *
513  * The depth of the TX FIFO is a synthesis configuration parameter of the SPI
514  * IP. The FIFO threshold register is sized so that its maximum value can be the
515  * FIFO size - 1. This is used to detect the size of the FIFO.
516  */
517 static void cdns_spi_detect_fifo_depth(struct cdns_spi *xspi)
518 {
519 	/* The MSBs will get truncated giving us the size of the FIFO */
520 	cdns_spi_write(xspi, CDNS_SPI_THLD, 0xffff);
521 	xspi->tx_fifo_depth = cdns_spi_read(xspi, CDNS_SPI_THLD) + 1;
522 
523 	/* Reset to default */
524 	cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1);
525 }
526 
527 /**
528  * cdns_target_abort - Abort target transfer
529  * @ctlr:	Pointer to the spi_controller structure
530  *
531  * This function abort target transfer if there any transfer timeout.
532  *
533  * Return:      0 always
534  */
535 static int cdns_target_abort(struct spi_controller *ctlr)
536 {
537 	struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
538 	u32 intr_status;
539 
540 	intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
541 	cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
542 	cdns_spi_write(xspi, CDNS_SPI_IDR, (CDNS_SPI_IXR_MODF | CDNS_SPI_IXR_RXNEMTY));
543 	spi_finalize_current_transfer(ctlr);
544 
545 	return 0;
546 }
547 
548 /**
549  * cdns_spi_probe - Probe method for the SPI driver
550  * @pdev:	Pointer to the platform_device structure
551  *
552  * This function initializes the driver data structures and the hardware.
553  *
554  * Return:	0 on success and error value on error
555  */
556 static int cdns_spi_probe(struct platform_device *pdev)
557 {
558 	int ret = 0, irq;
559 	struct spi_controller *ctlr;
560 	struct cdns_spi *xspi;
561 	u32 num_cs;
562 	bool target;
563 
564 	target = of_property_read_bool(pdev->dev.of_node, "spi-slave");
565 	if (target)
566 		ctlr = spi_alloc_target(&pdev->dev, sizeof(*xspi));
567 	else
568 		ctlr = spi_alloc_host(&pdev->dev, sizeof(*xspi));
569 
570 	if (!ctlr)
571 		return -ENOMEM;
572 
573 	xspi = spi_controller_get_devdata(ctlr);
574 	ctlr->dev.of_node = pdev->dev.of_node;
575 	platform_set_drvdata(pdev, ctlr);
576 
577 	xspi->regs = devm_platform_ioremap_resource(pdev, 0);
578 	if (IS_ERR(xspi->regs)) {
579 		ret = PTR_ERR(xspi->regs);
580 		goto remove_ctlr;
581 	}
582 
583 	xspi->pclk = devm_clk_get(&pdev->dev, "pclk");
584 	if (IS_ERR(xspi->pclk)) {
585 		dev_err(&pdev->dev, "pclk clock not found.\n");
586 		ret = PTR_ERR(xspi->pclk);
587 		goto remove_ctlr;
588 	}
589 
590 	ret = clk_prepare_enable(xspi->pclk);
591 	if (ret) {
592 		dev_err(&pdev->dev, "Unable to enable APB clock.\n");
593 		goto remove_ctlr;
594 	}
595 
596 	if (!spi_controller_is_target(ctlr)) {
597 		xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
598 		if (IS_ERR(xspi->ref_clk)) {
599 			dev_err(&pdev->dev, "ref_clk clock not found.\n");
600 			ret = PTR_ERR(xspi->ref_clk);
601 			goto clk_dis_apb;
602 		}
603 
604 		ret = clk_prepare_enable(xspi->ref_clk);
605 		if (ret) {
606 			dev_err(&pdev->dev, "Unable to enable device clock.\n");
607 			goto clk_dis_apb;
608 		}
609 
610 		pm_runtime_use_autosuspend(&pdev->dev);
611 		pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
612 		pm_runtime_get_noresume(&pdev->dev);
613 		pm_runtime_set_active(&pdev->dev);
614 		pm_runtime_enable(&pdev->dev);
615 
616 		ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
617 		if (ret < 0)
618 			ctlr->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
619 		else
620 			ctlr->num_chipselect = num_cs;
621 
622 		ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
623 					   &xspi->is_decoded_cs);
624 		if (ret < 0)
625 			xspi->is_decoded_cs = 0;
626 	}
627 
628 	cdns_spi_detect_fifo_depth(xspi);
629 
630 	/* SPI controller initializations */
631 	cdns_spi_init_hw(xspi, spi_controller_is_target(ctlr));
632 
633 	irq = platform_get_irq(pdev, 0);
634 	if (irq < 0) {
635 		ret = irq;
636 		goto clk_dis_all;
637 	}
638 
639 	ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq,
640 			       0, pdev->name, ctlr);
641 	if (ret != 0) {
642 		ret = -ENXIO;
643 		dev_err(&pdev->dev, "request_irq failed\n");
644 		goto clk_dis_all;
645 	}
646 
647 	ctlr->use_gpio_descriptors = true;
648 	ctlr->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
649 	ctlr->prepare_message = cdns_prepare_message;
650 	ctlr->transfer_one = cdns_transfer_one;
651 	ctlr->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
652 	ctlr->mode_bits = SPI_CPOL | SPI_CPHA;
653 	ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
654 
655 	if (!spi_controller_is_target(ctlr)) {
656 		ctlr->mode_bits |=  SPI_CS_HIGH;
657 		ctlr->set_cs = cdns_spi_chipselect;
658 		ctlr->auto_runtime_pm = true;
659 		xspi->clk_rate = clk_get_rate(xspi->ref_clk);
660 		/* Set to default valid value */
661 		ctlr->max_speed_hz = xspi->clk_rate / 4;
662 		xspi->speed_hz = ctlr->max_speed_hz;
663 		pm_runtime_mark_last_busy(&pdev->dev);
664 		pm_runtime_put_autosuspend(&pdev->dev);
665 	} else {
666 		ctlr->mode_bits |= SPI_NO_CS;
667 		ctlr->target_abort = cdns_target_abort;
668 	}
669 	ret = spi_register_controller(ctlr);
670 	if (ret) {
671 		dev_err(&pdev->dev, "spi_register_controller failed\n");
672 		goto clk_dis_all;
673 	}
674 
675 	return ret;
676 
677 clk_dis_all:
678 	if (!spi_controller_is_target(ctlr)) {
679 		pm_runtime_set_suspended(&pdev->dev);
680 		pm_runtime_disable(&pdev->dev);
681 		clk_disable_unprepare(xspi->ref_clk);
682 	}
683 clk_dis_apb:
684 	clk_disable_unprepare(xspi->pclk);
685 remove_ctlr:
686 	spi_controller_put(ctlr);
687 	return ret;
688 }
689 
690 /**
691  * cdns_spi_remove - Remove method for the SPI driver
692  * @pdev:	Pointer to the platform_device structure
693  *
694  * This function is called if a device is physically removed from the system or
695  * if the driver module is being unloaded. It frees all resources allocated to
696  * the device.
697  */
698 static void cdns_spi_remove(struct platform_device *pdev)
699 {
700 	struct spi_controller *ctlr = platform_get_drvdata(pdev);
701 	struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
702 
703 	cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
704 
705 	clk_disable_unprepare(xspi->ref_clk);
706 	clk_disable_unprepare(xspi->pclk);
707 	pm_runtime_set_suspended(&pdev->dev);
708 	pm_runtime_disable(&pdev->dev);
709 
710 	spi_unregister_controller(ctlr);
711 }
712 
713 /**
714  * cdns_spi_suspend - Suspend method for the SPI driver
715  * @dev:	Address of the platform_device structure
716  *
717  * This function disables the SPI controller and
718  * changes the driver state to "suspend"
719  *
720  * Return:	0 on success and error value on error
721  */
722 static int __maybe_unused cdns_spi_suspend(struct device *dev)
723 {
724 	struct spi_controller *ctlr = dev_get_drvdata(dev);
725 
726 	return spi_controller_suspend(ctlr);
727 }
728 
729 /**
730  * cdns_spi_resume - Resume method for the SPI driver
731  * @dev:	Address of the platform_device structure
732  *
733  * This function changes the driver state to "ready"
734  *
735  * Return:	0 on success and error value on error
736  */
737 static int __maybe_unused cdns_spi_resume(struct device *dev)
738 {
739 	struct spi_controller *ctlr = dev_get_drvdata(dev);
740 	struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
741 
742 	cdns_spi_init_hw(xspi, spi_controller_is_target(ctlr));
743 	return spi_controller_resume(ctlr);
744 }
745 
746 /**
747  * cdns_spi_runtime_resume - Runtime resume method for the SPI driver
748  * @dev:	Address of the platform_device structure
749  *
750  * This function enables the clocks
751  *
752  * Return:	0 on success and error value on error
753  */
754 static int __maybe_unused cdns_spi_runtime_resume(struct device *dev)
755 {
756 	struct spi_controller *ctlr = dev_get_drvdata(dev);
757 	struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
758 	int ret;
759 
760 	ret = clk_prepare_enable(xspi->pclk);
761 	if (ret) {
762 		dev_err(dev, "Cannot enable APB clock.\n");
763 		return ret;
764 	}
765 
766 	ret = clk_prepare_enable(xspi->ref_clk);
767 	if (ret) {
768 		dev_err(dev, "Cannot enable device clock.\n");
769 		clk_disable_unprepare(xspi->pclk);
770 		return ret;
771 	}
772 	return 0;
773 }
774 
775 /**
776  * cdns_spi_runtime_suspend - Runtime suspend method for the SPI driver
777  * @dev:	Address of the platform_device structure
778  *
779  * This function disables the clocks
780  *
781  * Return:	Always 0
782  */
783 static int __maybe_unused cdns_spi_runtime_suspend(struct device *dev)
784 {
785 	struct spi_controller *ctlr = dev_get_drvdata(dev);
786 	struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
787 
788 	clk_disable_unprepare(xspi->ref_clk);
789 	clk_disable_unprepare(xspi->pclk);
790 
791 	return 0;
792 }
793 
794 static const struct dev_pm_ops cdns_spi_dev_pm_ops = {
795 	SET_RUNTIME_PM_OPS(cdns_spi_runtime_suspend,
796 			   cdns_spi_runtime_resume, NULL)
797 	SET_SYSTEM_SLEEP_PM_OPS(cdns_spi_suspend, cdns_spi_resume)
798 };
799 
800 static const struct of_device_id cdns_spi_of_match[] = {
801 	{ .compatible = "xlnx,zynq-spi-r1p6" },
802 	{ .compatible = "cdns,spi-r1p6" },
803 	{ /* end of table */ }
804 };
805 MODULE_DEVICE_TABLE(of, cdns_spi_of_match);
806 
807 /* cdns_spi_driver - This structure defines the SPI subsystem platform driver */
808 static struct platform_driver cdns_spi_driver = {
809 	.probe	= cdns_spi_probe,
810 	.remove_new = cdns_spi_remove,
811 	.driver = {
812 		.name = CDNS_SPI_NAME,
813 		.of_match_table = cdns_spi_of_match,
814 		.pm = &cdns_spi_dev_pm_ops,
815 	},
816 };
817 
818 module_platform_driver(cdns_spi_driver);
819 
820 MODULE_AUTHOR("Xilinx, Inc.");
821 MODULE_DESCRIPTION("Cadence SPI driver");
822 MODULE_LICENSE("GPL");
823