1 /* 2 * Cadence SPI controller driver (master mode only) 3 * 4 * Copyright (C) 2008 - 2014 Xilinx, Inc. 5 * 6 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c) 7 * 8 * This program is free software; you can redistribute it and/or modify it under 9 * the terms of the GNU General Public License version 2 as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/module.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_address.h> 21 #include <linux/platform_device.h> 22 #include <linux/spi/spi.h> 23 24 /* Name of this driver */ 25 #define CDNS_SPI_NAME "cdns-spi" 26 27 /* Register offset definitions */ 28 #define CDNS_SPI_CR_OFFSET 0x00 /* Configuration Register, RW */ 29 #define CDNS_SPI_ISR_OFFSET 0x04 /* Interrupt Status Register, RO */ 30 #define CDNS_SPI_IER_OFFSET 0x08 /* Interrupt Enable Register, WO */ 31 #define CDNS_SPI_IDR_OFFSET 0x0c /* Interrupt Disable Register, WO */ 32 #define CDNS_SPI_IMR_OFFSET 0x10 /* Interrupt Enabled Mask Register, RO */ 33 #define CDNS_SPI_ER_OFFSET 0x14 /* Enable/Disable Register, RW */ 34 #define CDNS_SPI_DR_OFFSET 0x18 /* Delay Register, RW */ 35 #define CDNS_SPI_TXD_OFFSET 0x1C /* Data Transmit Register, WO */ 36 #define CDNS_SPI_RXD_OFFSET 0x20 /* Data Receive Register, RO */ 37 #define CDNS_SPI_SICR_OFFSET 0x24 /* Slave Idle Count Register, RW */ 38 #define CDNS_SPI_THLD_OFFSET 0x28 /* Transmit FIFO Watermark Register,RW */ 39 40 /* 41 * SPI Configuration Register bit Masks 42 * 43 * This register contains various control bits that affect the operation 44 * of the SPI controller 45 */ 46 #define CDNS_SPI_CR_MANSTRT_MASK 0x00010000 /* Manual TX Start */ 47 #define CDNS_SPI_CR_CPHA_MASK 0x00000004 /* Clock Phase Control */ 48 #define CDNS_SPI_CR_CPOL_MASK 0x00000002 /* Clock Polarity Control */ 49 #define CDNS_SPI_CR_SSCTRL_MASK 0x00003C00 /* Slave Select Mask */ 50 #define CDNS_SPI_CR_BAUD_DIV_MASK 0x00000038 /* Baud Rate Divisor Mask */ 51 #define CDNS_SPI_CR_MSTREN_MASK 0x00000001 /* Master Enable Mask */ 52 #define CDNS_SPI_CR_MANSTRTEN_MASK 0x00008000 /* Manual TX Enable Mask */ 53 #define CDNS_SPI_CR_SSFORCE_MASK 0x00004000 /* Manual SS Enable Mask */ 54 #define CDNS_SPI_CR_BAUD_DIV_4_MASK 0x00000008 /* Default Baud Div Mask */ 55 #define CDNS_SPI_CR_DEFAULT_MASK (CDNS_SPI_CR_MSTREN_MASK | \ 56 CDNS_SPI_CR_SSCTRL_MASK | \ 57 CDNS_SPI_CR_SSFORCE_MASK | \ 58 CDNS_SPI_CR_BAUD_DIV_4_MASK) 59 60 /* 61 * SPI Configuration Register - Baud rate and slave select 62 * 63 * These are the values used in the calculation of baud rate divisor and 64 * setting the slave select. 65 */ 66 67 #define CDNS_SPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */ 68 #define CDNS_SPI_BAUD_DIV_MIN 1 /* Baud rate divisor minimum */ 69 #define CDNS_SPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */ 70 #define CDNS_SPI_SS_SHIFT 10 /* Slave Select field shift in CR */ 71 #define CDNS_SPI_SS0 0x1 /* Slave Select zero */ 72 73 /* 74 * SPI Interrupt Registers bit Masks 75 * 76 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same 77 * bit definitions. 78 */ 79 #define CDNS_SPI_IXR_TXOW_MASK 0x00000004 /* SPI TX FIFO Overwater */ 80 #define CDNS_SPI_IXR_MODF_MASK 0x00000002 /* SPI Mode Fault */ 81 #define CDNS_SPI_IXR_RXNEMTY_MASK 0x00000010 /* SPI RX FIFO Not Empty */ 82 #define CDNS_SPI_IXR_DEFAULT_MASK (CDNS_SPI_IXR_TXOW_MASK | \ 83 CDNS_SPI_IXR_MODF_MASK) 84 #define CDNS_SPI_IXR_TXFULL_MASK 0x00000008 /* SPI TX Full */ 85 #define CDNS_SPI_IXR_ALL_MASK 0x0000007F /* SPI all interrupts */ 86 87 /* 88 * SPI Enable Register bit Masks 89 * 90 * This register is used to enable or disable the SPI controller 91 */ 92 #define CDNS_SPI_ER_ENABLE_MASK 0x00000001 /* SPI Enable Bit Mask */ 93 #define CDNS_SPI_ER_DISABLE_MASK 0x0 /* SPI Disable Bit Mask */ 94 95 /* SPI FIFO depth in bytes */ 96 #define CDNS_SPI_FIFO_DEPTH 128 97 98 /* Default number of chip select lines */ 99 #define CDNS_SPI_DEFAULT_NUM_CS 4 100 101 /** 102 * struct cdns_spi - This definition defines spi driver instance 103 * @regs: Virtual address of the SPI controller registers 104 * @ref_clk: Pointer to the peripheral clock 105 * @pclk: Pointer to the APB clock 106 * @speed_hz: Current SPI bus clock speed in Hz 107 * @txbuf: Pointer to the TX buffer 108 * @rxbuf: Pointer to the RX buffer 109 * @tx_bytes: Number of bytes left to transfer 110 * @rx_bytes: Number of bytes requested 111 * @dev_busy: Device busy flag 112 * @is_decoded_cs: Flag for decoder property set or not 113 */ 114 struct cdns_spi { 115 void __iomem *regs; 116 struct clk *ref_clk; 117 struct clk *pclk; 118 u32 speed_hz; 119 const u8 *txbuf; 120 u8 *rxbuf; 121 int tx_bytes; 122 int rx_bytes; 123 u8 dev_busy; 124 u32 is_decoded_cs; 125 }; 126 127 /* Macros for the SPI controller read/write */ 128 static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset) 129 { 130 return readl_relaxed(xspi->regs + offset); 131 } 132 133 static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val) 134 { 135 writel_relaxed(val, xspi->regs + offset); 136 } 137 138 /** 139 * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller 140 * @xspi: Pointer to the cdns_spi structure 141 * 142 * On reset the SPI controller is configured to be in master mode, baud rate 143 * divisor is set to 4, threshold value for TX FIFO not full interrupt is set 144 * to 1 and size of the word to be transferred as 8 bit. 145 * This function initializes the SPI controller to disable and clear all the 146 * interrupts, enable manual slave select and manual start, deselect all the 147 * chip select lines, and enable the SPI controller. 148 */ 149 static void cdns_spi_init_hw(struct cdns_spi *xspi) 150 { 151 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET, 152 CDNS_SPI_ER_DISABLE_MASK); 153 cdns_spi_write(xspi, CDNS_SPI_IDR_OFFSET, 154 CDNS_SPI_IXR_ALL_MASK); 155 156 /* Clear the RX FIFO */ 157 while (cdns_spi_read(xspi, CDNS_SPI_ISR_OFFSET) & 158 CDNS_SPI_IXR_RXNEMTY_MASK) 159 cdns_spi_read(xspi, CDNS_SPI_RXD_OFFSET); 160 161 cdns_spi_write(xspi, CDNS_SPI_ISR_OFFSET, 162 CDNS_SPI_IXR_ALL_MASK); 163 cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, 164 CDNS_SPI_CR_DEFAULT_MASK); 165 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET, 166 CDNS_SPI_ER_ENABLE_MASK); 167 } 168 169 /** 170 * cdns_spi_chipselect - Select or deselect the chip select line 171 * @spi: Pointer to the spi_device structure 172 * @is_on: Select(0) or deselect (1) the chip select line 173 */ 174 static void cdns_spi_chipselect(struct spi_device *spi, bool is_high) 175 { 176 struct cdns_spi *xspi = spi_master_get_devdata(spi->master); 177 u32 ctrl_reg; 178 179 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR_OFFSET); 180 181 if (is_high) { 182 /* Deselect the slave */ 183 ctrl_reg |= CDNS_SPI_CR_SSCTRL_MASK; 184 } else { 185 /* Select the slave */ 186 ctrl_reg &= ~CDNS_SPI_CR_SSCTRL_MASK; 187 if (!(xspi->is_decoded_cs)) 188 ctrl_reg |= ((~(CDNS_SPI_SS0 << spi->chip_select)) << 189 CDNS_SPI_SS_SHIFT) & 190 CDNS_SPI_CR_SSCTRL_MASK; 191 else 192 ctrl_reg |= (spi->chip_select << CDNS_SPI_SS_SHIFT) & 193 CDNS_SPI_CR_SSCTRL_MASK; 194 } 195 196 cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, ctrl_reg); 197 } 198 199 /** 200 * cdns_spi_config_clock_mode - Sets clock polarity and phase 201 * @spi: Pointer to the spi_device structure 202 * 203 * Sets the requested clock polarity and phase. 204 */ 205 static void cdns_spi_config_clock_mode(struct spi_device *spi) 206 { 207 struct cdns_spi *xspi = spi_master_get_devdata(spi->master); 208 u32 ctrl_reg, new_ctrl_reg; 209 210 new_ctrl_reg = ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR_OFFSET); 211 212 /* Set the SPI clock phase and clock polarity */ 213 new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA_MASK | CDNS_SPI_CR_CPOL_MASK); 214 if (spi->mode & SPI_CPHA) 215 new_ctrl_reg |= CDNS_SPI_CR_CPHA_MASK; 216 if (spi->mode & SPI_CPOL) 217 new_ctrl_reg |= CDNS_SPI_CR_CPOL_MASK; 218 219 if (new_ctrl_reg != ctrl_reg) { 220 /* 221 * Just writing the CR register does not seem to apply the clock 222 * setting changes. This is problematic when changing the clock 223 * polarity as it will cause the SPI slave to see spurious clock 224 * transitions. To workaround the issue toggle the ER register. 225 */ 226 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET, 227 CDNS_SPI_ER_DISABLE_MASK); 228 cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, new_ctrl_reg); 229 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET, 230 CDNS_SPI_ER_ENABLE_MASK); 231 } 232 } 233 234 /** 235 * cdns_spi_config_clock_freq - Sets clock frequency 236 * @spi: Pointer to the spi_device structure 237 * @transfer: Pointer to the spi_transfer structure which provides 238 * information about next transfer setup parameters 239 * 240 * Sets the requested clock frequency. 241 * Note: If the requested frequency is not an exact match with what can be 242 * obtained using the prescalar value the driver sets the clock frequency which 243 * is lower than the requested frequency (maximum lower) for the transfer. If 244 * the requested frequency is higher or lower than that is supported by the SPI 245 * controller the driver will set the highest or lowest frequency supported by 246 * controller. 247 */ 248 static void cdns_spi_config_clock_freq(struct spi_device *spi, 249 struct spi_transfer *transfer) 250 { 251 struct cdns_spi *xspi = spi_master_get_devdata(spi->master); 252 u32 ctrl_reg, baud_rate_val; 253 unsigned long frequency; 254 255 frequency = clk_get_rate(xspi->ref_clk); 256 257 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR_OFFSET); 258 259 /* Set the clock frequency */ 260 if (xspi->speed_hz != transfer->speed_hz) { 261 /* first valid value is 1 */ 262 baud_rate_val = CDNS_SPI_BAUD_DIV_MIN; 263 while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) && 264 (frequency / (2 << baud_rate_val)) > transfer->speed_hz) 265 baud_rate_val++; 266 267 ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV_MASK; 268 ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT; 269 270 xspi->speed_hz = frequency / (2 << baud_rate_val); 271 } 272 cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, ctrl_reg); 273 } 274 275 /** 276 * cdns_spi_setup_transfer - Configure SPI controller for specified transfer 277 * @spi: Pointer to the spi_device structure 278 * @transfer: Pointer to the spi_transfer structure which provides 279 * information about next transfer setup parameters 280 * 281 * Sets the operational mode of SPI controller for the next SPI transfer and 282 * sets the requested clock frequency. 283 * 284 * Return: Always 0 285 */ 286 static int cdns_spi_setup_transfer(struct spi_device *spi, 287 struct spi_transfer *transfer) 288 { 289 struct cdns_spi *xspi = spi_master_get_devdata(spi->master); 290 291 cdns_spi_config_clock_freq(spi, transfer); 292 293 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n", 294 __func__, spi->mode, spi->bits_per_word, 295 xspi->speed_hz); 296 297 return 0; 298 } 299 300 /** 301 * cdns_spi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible 302 * @xspi: Pointer to the cdns_spi structure 303 */ 304 static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi) 305 { 306 unsigned long trans_cnt = 0; 307 308 while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) && 309 (xspi->tx_bytes > 0)) { 310 if (xspi->txbuf) 311 cdns_spi_write(xspi, CDNS_SPI_TXD_OFFSET, 312 *xspi->txbuf++); 313 else 314 cdns_spi_write(xspi, CDNS_SPI_TXD_OFFSET, 0); 315 316 xspi->tx_bytes--; 317 trans_cnt++; 318 } 319 } 320 321 /** 322 * cdns_spi_irq - Interrupt service routine of the SPI controller 323 * @irq: IRQ number 324 * @dev_id: Pointer to the xspi structure 325 * 326 * This function handles TX empty and Mode Fault interrupts only. 327 * On TX empty interrupt this function reads the received data from RX FIFO and 328 * fills the TX FIFO if there is any data remaining to be transferred. 329 * On Mode Fault interrupt this function indicates that transfer is completed, 330 * the SPI subsystem will identify the error as the remaining bytes to be 331 * transferred is non-zero. 332 * 333 * Return: IRQ_HANDLED when handled; IRQ_NONE otherwise. 334 */ 335 static irqreturn_t cdns_spi_irq(int irq, void *dev_id) 336 { 337 struct spi_master *master = dev_id; 338 struct cdns_spi *xspi = spi_master_get_devdata(master); 339 u32 intr_status, status; 340 341 status = IRQ_NONE; 342 intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR_OFFSET); 343 cdns_spi_write(xspi, CDNS_SPI_ISR_OFFSET, intr_status); 344 345 if (intr_status & CDNS_SPI_IXR_MODF_MASK) { 346 /* Indicate that transfer is completed, the SPI subsystem will 347 * identify the error as the remaining bytes to be 348 * transferred is non-zero 349 */ 350 cdns_spi_write(xspi, CDNS_SPI_IDR_OFFSET, 351 CDNS_SPI_IXR_DEFAULT_MASK); 352 spi_finalize_current_transfer(master); 353 status = IRQ_HANDLED; 354 } else if (intr_status & CDNS_SPI_IXR_TXOW_MASK) { 355 unsigned long trans_cnt; 356 357 trans_cnt = xspi->rx_bytes - xspi->tx_bytes; 358 359 /* Read out the data from the RX FIFO */ 360 while (trans_cnt) { 361 u8 data; 362 363 data = cdns_spi_read(xspi, CDNS_SPI_RXD_OFFSET); 364 if (xspi->rxbuf) 365 *xspi->rxbuf++ = data; 366 367 xspi->rx_bytes--; 368 trans_cnt--; 369 } 370 371 if (xspi->tx_bytes) { 372 /* There is more data to send */ 373 cdns_spi_fill_tx_fifo(xspi); 374 } else { 375 /* Transfer is completed */ 376 cdns_spi_write(xspi, CDNS_SPI_IDR_OFFSET, 377 CDNS_SPI_IXR_DEFAULT_MASK); 378 spi_finalize_current_transfer(master); 379 } 380 status = IRQ_HANDLED; 381 } 382 383 return status; 384 } 385 static int cdns_prepare_message(struct spi_master *master, 386 struct spi_message *msg) 387 { 388 cdns_spi_config_clock_mode(msg->spi); 389 return 0; 390 } 391 392 /** 393 * cdns_transfer_one - Initiates the SPI transfer 394 * @master: Pointer to spi_master structure 395 * @spi: Pointer to the spi_device structure 396 * @transfer: Pointer to the spi_transfer structure which provides 397 * information about next transfer parameters 398 * 399 * This function fills the TX FIFO, starts the SPI transfer and 400 * returns a positive transfer count so that core will wait for completion. 401 * 402 * Return: Number of bytes transferred in the last transfer 403 */ 404 static int cdns_transfer_one(struct spi_master *master, 405 struct spi_device *spi, 406 struct spi_transfer *transfer) 407 { 408 struct cdns_spi *xspi = spi_master_get_devdata(master); 409 410 xspi->txbuf = transfer->tx_buf; 411 xspi->rxbuf = transfer->rx_buf; 412 xspi->tx_bytes = transfer->len; 413 xspi->rx_bytes = transfer->len; 414 415 cdns_spi_setup_transfer(spi, transfer); 416 417 cdns_spi_fill_tx_fifo(xspi); 418 419 cdns_spi_write(xspi, CDNS_SPI_IER_OFFSET, 420 CDNS_SPI_IXR_DEFAULT_MASK); 421 return transfer->len; 422 } 423 424 /** 425 * cdns_prepare_transfer_hardware - Prepares hardware for transfer. 426 * @master: Pointer to the spi_master structure which provides 427 * information about the controller. 428 * 429 * This function enables SPI master controller. 430 * 431 * Return: 0 always 432 */ 433 static int cdns_prepare_transfer_hardware(struct spi_master *master) 434 { 435 struct cdns_spi *xspi = spi_master_get_devdata(master); 436 437 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET, 438 CDNS_SPI_ER_ENABLE_MASK); 439 440 return 0; 441 } 442 443 /** 444 * cdns_unprepare_transfer_hardware - Relaxes hardware after transfer 445 * @master: Pointer to the spi_master structure which provides 446 * information about the controller. 447 * 448 * This function disables the SPI master controller. 449 * 450 * Return: 0 always 451 */ 452 static int cdns_unprepare_transfer_hardware(struct spi_master *master) 453 { 454 struct cdns_spi *xspi = spi_master_get_devdata(master); 455 456 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET, 457 CDNS_SPI_ER_DISABLE_MASK); 458 459 return 0; 460 } 461 462 /** 463 * cdns_spi_probe - Probe method for the SPI driver 464 * @pdev: Pointer to the platform_device structure 465 * 466 * This function initializes the driver data structures and the hardware. 467 * 468 * Return: 0 on success and error value on error 469 */ 470 static int cdns_spi_probe(struct platform_device *pdev) 471 { 472 int ret = 0, irq; 473 struct spi_master *master; 474 struct cdns_spi *xspi; 475 struct resource *res; 476 u32 num_cs; 477 478 master = spi_alloc_master(&pdev->dev, sizeof(*xspi)); 479 if (master == NULL) 480 return -ENOMEM; 481 482 xspi = spi_master_get_devdata(master); 483 master->dev.of_node = pdev->dev.of_node; 484 platform_set_drvdata(pdev, master); 485 486 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 487 xspi->regs = devm_ioremap_resource(&pdev->dev, res); 488 if (IS_ERR(xspi->regs)) { 489 ret = PTR_ERR(xspi->regs); 490 goto remove_master; 491 } 492 493 xspi->pclk = devm_clk_get(&pdev->dev, "pclk"); 494 if (IS_ERR(xspi->pclk)) { 495 dev_err(&pdev->dev, "pclk clock not found.\n"); 496 ret = PTR_ERR(xspi->pclk); 497 goto remove_master; 498 } 499 500 xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk"); 501 if (IS_ERR(xspi->ref_clk)) { 502 dev_err(&pdev->dev, "ref_clk clock not found.\n"); 503 ret = PTR_ERR(xspi->ref_clk); 504 goto remove_master; 505 } 506 507 ret = clk_prepare_enable(xspi->pclk); 508 if (ret) { 509 dev_err(&pdev->dev, "Unable to enable APB clock.\n"); 510 goto remove_master; 511 } 512 513 ret = clk_prepare_enable(xspi->ref_clk); 514 if (ret) { 515 dev_err(&pdev->dev, "Unable to enable device clock.\n"); 516 goto clk_dis_apb; 517 } 518 519 /* SPI controller initializations */ 520 cdns_spi_init_hw(xspi); 521 522 irq = platform_get_irq(pdev, 0); 523 if (irq <= 0) { 524 ret = -ENXIO; 525 dev_err(&pdev->dev, "irq number is invalid\n"); 526 goto remove_master; 527 } 528 529 ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq, 530 0, pdev->name, master); 531 if (ret != 0) { 532 ret = -ENXIO; 533 dev_err(&pdev->dev, "request_irq failed\n"); 534 goto remove_master; 535 } 536 537 ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs); 538 539 if (ret < 0) 540 master->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS; 541 else 542 master->num_chipselect = num_cs; 543 544 ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs", 545 &xspi->is_decoded_cs); 546 547 if (ret < 0) 548 xspi->is_decoded_cs = 0; 549 550 master->prepare_transfer_hardware = cdns_prepare_transfer_hardware; 551 master->prepare_message = cdns_prepare_message; 552 master->transfer_one = cdns_transfer_one; 553 master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware; 554 master->set_cs = cdns_spi_chipselect; 555 master->mode_bits = SPI_CPOL | SPI_CPHA; 556 557 /* Set to default valid value */ 558 master->max_speed_hz = clk_get_rate(xspi->ref_clk) / 4; 559 xspi->speed_hz = master->max_speed_hz; 560 561 master->bits_per_word_mask = SPI_BPW_MASK(8); 562 563 ret = spi_register_master(master); 564 if (ret) { 565 dev_err(&pdev->dev, "spi_register_master failed\n"); 566 goto clk_dis_all; 567 } 568 569 return ret; 570 571 clk_dis_all: 572 clk_disable_unprepare(xspi->ref_clk); 573 clk_dis_apb: 574 clk_disable_unprepare(xspi->pclk); 575 remove_master: 576 spi_master_put(master); 577 return ret; 578 } 579 580 /** 581 * cdns_spi_remove - Remove method for the SPI driver 582 * @pdev: Pointer to the platform_device structure 583 * 584 * This function is called if a device is physically removed from the system or 585 * if the driver module is being unloaded. It frees all resources allocated to 586 * the device. 587 * 588 * Return: 0 on success and error value on error 589 */ 590 static int cdns_spi_remove(struct platform_device *pdev) 591 { 592 struct spi_master *master = platform_get_drvdata(pdev); 593 struct cdns_spi *xspi = spi_master_get_devdata(master); 594 595 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET, 596 CDNS_SPI_ER_DISABLE_MASK); 597 598 clk_disable_unprepare(xspi->ref_clk); 599 clk_disable_unprepare(xspi->pclk); 600 601 spi_unregister_master(master); 602 603 return 0; 604 } 605 606 /** 607 * cdns_spi_suspend - Suspend method for the SPI driver 608 * @dev: Address of the platform_device structure 609 * 610 * This function disables the SPI controller and 611 * changes the driver state to "suspend" 612 * 613 * Return: Always 0 614 */ 615 static int __maybe_unused cdns_spi_suspend(struct device *dev) 616 { 617 struct platform_device *pdev = container_of(dev, 618 struct platform_device, dev); 619 struct spi_master *master = platform_get_drvdata(pdev); 620 struct cdns_spi *xspi = spi_master_get_devdata(master); 621 622 spi_master_suspend(master); 623 624 clk_disable_unprepare(xspi->ref_clk); 625 626 clk_disable_unprepare(xspi->pclk); 627 628 return 0; 629 } 630 631 /** 632 * cdns_spi_resume - Resume method for the SPI driver 633 * @dev: Address of the platform_device structure 634 * 635 * This function changes the driver state to "ready" 636 * 637 * Return: 0 on success and error value on error 638 */ 639 static int __maybe_unused cdns_spi_resume(struct device *dev) 640 { 641 struct platform_device *pdev = container_of(dev, 642 struct platform_device, dev); 643 struct spi_master *master = platform_get_drvdata(pdev); 644 struct cdns_spi *xspi = spi_master_get_devdata(master); 645 int ret = 0; 646 647 ret = clk_prepare_enable(xspi->pclk); 648 if (ret) { 649 dev_err(dev, "Cannot enable APB clock.\n"); 650 return ret; 651 } 652 653 ret = clk_prepare_enable(xspi->ref_clk); 654 if (ret) { 655 dev_err(dev, "Cannot enable device clock.\n"); 656 clk_disable(xspi->pclk); 657 return ret; 658 } 659 spi_master_resume(master); 660 661 return 0; 662 } 663 664 static SIMPLE_DEV_PM_OPS(cdns_spi_dev_pm_ops, cdns_spi_suspend, 665 cdns_spi_resume); 666 667 static const struct of_device_id cdns_spi_of_match[] = { 668 { .compatible = "xlnx,zynq-spi-r1p6" }, 669 { .compatible = "cdns,spi-r1p6" }, 670 { /* end of table */ } 671 }; 672 MODULE_DEVICE_TABLE(of, cdns_spi_of_match); 673 674 /* cdns_spi_driver - This structure defines the SPI subsystem platform driver */ 675 static struct platform_driver cdns_spi_driver = { 676 .probe = cdns_spi_probe, 677 .remove = cdns_spi_remove, 678 .driver = { 679 .name = CDNS_SPI_NAME, 680 .owner = THIS_MODULE, 681 .of_match_table = cdns_spi_of_match, 682 .pm = &cdns_spi_dev_pm_ops, 683 }, 684 }; 685 686 module_platform_driver(cdns_spi_driver); 687 688 MODULE_AUTHOR("Xilinx, Inc."); 689 MODULE_DESCRIPTION("Cadence SPI driver"); 690 MODULE_LICENSE("GPL"); 691