1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Driver for Cadence QSPI Controller 4 // 5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved. 6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved. 7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 8 9 #include <linux/clk.h> 10 #include <linux/completion.h> 11 #include <linux/delay.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/dmaengine.h> 14 #include <linux/err.h> 15 #include <linux/errno.h> 16 #include <linux/firmware/xlnx-zynqmp.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/jiffies.h> 21 #include <linux/kernel.h> 22 #include <linux/log2.h> 23 #include <linux/module.h> 24 #include <linux/of_device.h> 25 #include <linux/of.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/reset.h> 29 #include <linux/sched.h> 30 #include <linux/spi/spi.h> 31 #include <linux/spi/spi-mem.h> 32 #include <linux/timer.h> 33 34 #define CQSPI_NAME "cadence-qspi" 35 #define CQSPI_MAX_CHIPSELECT 16 36 37 /* Quirks */ 38 #define CQSPI_NEEDS_WR_DELAY BIT(0) 39 #define CQSPI_DISABLE_DAC_MODE BIT(1) 40 #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) 41 #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) 42 #define CQSPI_SLOW_SRAM BIT(4) 43 #define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) 44 45 /* Capabilities */ 46 #define CQSPI_SUPPORTS_OCTAL BIT(0) 47 48 #define CQSPI_OP_WIDTH(part) ((part).nbytes ? ilog2((part).buswidth) : 0) 49 50 struct cqspi_st; 51 52 struct cqspi_flash_pdata { 53 struct cqspi_st *cqspi; 54 u32 clk_rate; 55 u32 read_delay; 56 u32 tshsl_ns; 57 u32 tsd2d_ns; 58 u32 tchsh_ns; 59 u32 tslch_ns; 60 u8 cs; 61 }; 62 63 struct cqspi_st { 64 struct platform_device *pdev; 65 struct spi_master *master; 66 struct clk *clk; 67 unsigned int sclk; 68 69 void __iomem *iobase; 70 void __iomem *ahb_base; 71 resource_size_t ahb_size; 72 struct completion transfer_complete; 73 74 struct dma_chan *rx_chan; 75 struct completion rx_dma_complete; 76 dma_addr_t mmap_phys_base; 77 78 int current_cs; 79 unsigned long master_ref_clk_hz; 80 bool is_decoded_cs; 81 u32 fifo_depth; 82 u32 fifo_width; 83 u32 num_chipselect; 84 bool rclk_en; 85 u32 trigger_address; 86 u32 wr_delay; 87 bool use_direct_mode; 88 bool use_direct_mode_wr; 89 struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; 90 bool use_dma_read; 91 u32 pd_dev_id; 92 bool wr_completion; 93 bool slow_sram; 94 bool apb_ahb_hazard; 95 }; 96 97 struct cqspi_driver_platdata { 98 u32 hwcaps_mask; 99 u8 quirks; 100 int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata, 101 u_char *rxbuf, loff_t from_addr, size_t n_rx); 102 u32 (*get_dma_status)(struct cqspi_st *cqspi); 103 }; 104 105 /* Operation timeout value */ 106 #define CQSPI_TIMEOUT_MS 500 107 #define CQSPI_READ_TIMEOUT_MS 10 108 109 #define CQSPI_DUMMY_CLKS_PER_BYTE 8 110 #define CQSPI_DUMMY_BYTES_MAX 4 111 #define CQSPI_DUMMY_CLKS_MAX 31 112 113 #define CQSPI_STIG_DATA_LEN_MAX 8 114 115 /* Register map */ 116 #define CQSPI_REG_CONFIG 0x00 117 #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0) 118 #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7) 119 #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9) 120 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 121 #define CQSPI_REG_CONFIG_DMA_MASK BIT(15) 122 #define CQSPI_REG_CONFIG_BAUD_LSB 19 123 #define CQSPI_REG_CONFIG_DTR_PROTO BIT(24) 124 #define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30) 125 #define CQSPI_REG_CONFIG_IDLE_LSB 31 126 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF 127 #define CQSPI_REG_CONFIG_BAUD_MASK 0xF 128 129 #define CQSPI_REG_RD_INSTR 0x04 130 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 131 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 132 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 133 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 134 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 135 #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 136 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 137 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 138 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 139 #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F 140 141 #define CQSPI_REG_WR_INSTR 0x08 142 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 143 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12 144 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16 145 146 #define CQSPI_REG_DELAY 0x0C 147 #define CQSPI_REG_DELAY_TSLCH_LSB 0 148 #define CQSPI_REG_DELAY_TCHSH_LSB 8 149 #define CQSPI_REG_DELAY_TSD2D_LSB 16 150 #define CQSPI_REG_DELAY_TSHSL_LSB 24 151 #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF 152 #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF 153 #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF 154 #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF 155 156 #define CQSPI_REG_READCAPTURE 0x10 157 #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0 158 #define CQSPI_REG_READCAPTURE_DELAY_LSB 1 159 #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF 160 161 #define CQSPI_REG_SIZE 0x14 162 #define CQSPI_REG_SIZE_ADDRESS_LSB 0 163 #define CQSPI_REG_SIZE_PAGE_LSB 4 164 #define CQSPI_REG_SIZE_BLOCK_LSB 16 165 #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF 166 #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF 167 #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F 168 169 #define CQSPI_REG_SRAMPARTITION 0x18 170 #define CQSPI_REG_INDIRECTTRIGGER 0x1C 171 172 #define CQSPI_REG_DMA 0x20 173 #define CQSPI_REG_DMA_SINGLE_LSB 0 174 #define CQSPI_REG_DMA_BURST_LSB 8 175 #define CQSPI_REG_DMA_SINGLE_MASK 0xFF 176 #define CQSPI_REG_DMA_BURST_MASK 0xFF 177 178 #define CQSPI_REG_REMAP 0x24 179 #define CQSPI_REG_MODE_BIT 0x28 180 181 #define CQSPI_REG_SDRAMLEVEL 0x2C 182 #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 183 #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 184 #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF 185 #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF 186 187 #define CQSPI_REG_WR_COMPLETION_CTRL 0x38 188 #define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14) 189 190 #define CQSPI_REG_IRQSTATUS 0x40 191 #define CQSPI_REG_IRQMASK 0x44 192 193 #define CQSPI_REG_INDIRECTRD 0x60 194 #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0) 195 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1) 196 #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5) 197 198 #define CQSPI_REG_INDIRECTRDWATERMARK 0x64 199 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 200 #define CQSPI_REG_INDIRECTRDBYTES 0x6C 201 202 #define CQSPI_REG_CMDCTRL 0x90 203 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0) 204 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1) 205 #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 206 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 207 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 208 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 209 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 210 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 211 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 212 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 213 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 214 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 215 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 216 #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F 217 218 #define CQSPI_REG_INDIRECTWR 0x70 219 #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0) 220 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1) 221 #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5) 222 223 #define CQSPI_REG_INDIRECTWRWATERMARK 0x74 224 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 225 #define CQSPI_REG_INDIRECTWRBYTES 0x7C 226 227 #define CQSPI_REG_INDTRIG_ADDRRANGE 0x80 228 229 #define CQSPI_REG_CMDADDRESS 0x94 230 #define CQSPI_REG_CMDREADDATALOWER 0xA0 231 #define CQSPI_REG_CMDREADDATAUPPER 0xA4 232 #define CQSPI_REG_CMDWRITEDATALOWER 0xA8 233 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC 234 235 #define CQSPI_REG_POLLING_STATUS 0xB0 236 #define CQSPI_REG_POLLING_STATUS_DUMMY_LSB 16 237 238 #define CQSPI_REG_OP_EXT_LOWER 0xE0 239 #define CQSPI_REG_OP_EXT_READ_LSB 24 240 #define CQSPI_REG_OP_EXT_WRITE_LSB 16 241 #define CQSPI_REG_OP_EXT_STIG_LSB 0 242 243 #define CQSPI_REG_VERSAL_DMA_SRC_ADDR 0x1000 244 245 #define CQSPI_REG_VERSAL_DMA_DST_ADDR 0x1800 246 #define CQSPI_REG_VERSAL_DMA_DST_SIZE 0x1804 247 248 #define CQSPI_REG_VERSAL_DMA_DST_CTRL 0x180C 249 250 #define CQSPI_REG_VERSAL_DMA_DST_I_STS 0x1814 251 #define CQSPI_REG_VERSAL_DMA_DST_I_EN 0x1818 252 #define CQSPI_REG_VERSAL_DMA_DST_I_DIS 0x181C 253 #define CQSPI_REG_VERSAL_DMA_DST_DONE_MASK BIT(1) 254 255 #define CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB 0x1828 256 257 #define CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL 0xF43FFA00 258 #define CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL 0x6 259 260 /* Interrupt status bits */ 261 #define CQSPI_REG_IRQ_MODE_ERR BIT(0) 262 #define CQSPI_REG_IRQ_UNDERFLOW BIT(1) 263 #define CQSPI_REG_IRQ_IND_COMP BIT(2) 264 #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3) 265 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4) 266 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5) 267 #define CQSPI_REG_IRQ_WATERMARK BIT(6) 268 #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12) 269 270 #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \ 271 CQSPI_REG_IRQ_IND_SRAM_FULL | \ 272 CQSPI_REG_IRQ_IND_COMP) 273 274 #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \ 275 CQSPI_REG_IRQ_WATERMARK | \ 276 CQSPI_REG_IRQ_UNDERFLOW) 277 278 #define CQSPI_IRQ_STATUS_MASK 0x1FFFF 279 #define CQSPI_DMA_UNALIGN 0x3 280 281 #define CQSPI_REG_VERSAL_DMA_VAL 0x602 282 283 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr) 284 { 285 u32 val; 286 287 return readl_relaxed_poll_timeout(reg, val, 288 (((clr ? ~val : val) & mask) == mask), 289 10, CQSPI_TIMEOUT_MS * 1000); 290 } 291 292 static bool cqspi_is_idle(struct cqspi_st *cqspi) 293 { 294 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 295 296 return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB); 297 } 298 299 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi) 300 { 301 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL); 302 303 reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB; 304 return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK; 305 } 306 307 static u32 cqspi_get_versal_dma_status(struct cqspi_st *cqspi) 308 { 309 u32 dma_status; 310 311 dma_status = readl(cqspi->iobase + 312 CQSPI_REG_VERSAL_DMA_DST_I_STS); 313 writel(dma_status, cqspi->iobase + 314 CQSPI_REG_VERSAL_DMA_DST_I_STS); 315 316 return dma_status & CQSPI_REG_VERSAL_DMA_DST_DONE_MASK; 317 } 318 319 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev) 320 { 321 struct cqspi_st *cqspi = dev; 322 unsigned int irq_status; 323 struct device *device = &cqspi->pdev->dev; 324 const struct cqspi_driver_platdata *ddata; 325 326 ddata = of_device_get_match_data(device); 327 328 /* Read interrupt status */ 329 irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS); 330 331 /* Clear interrupt */ 332 writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS); 333 334 if (cqspi->use_dma_read && ddata && ddata->get_dma_status) { 335 if (ddata->get_dma_status(cqspi)) { 336 complete(&cqspi->transfer_complete); 337 return IRQ_HANDLED; 338 } 339 } 340 341 else if (!cqspi->slow_sram) 342 irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR; 343 else 344 irq_status &= CQSPI_REG_IRQ_WATERMARK | CQSPI_IRQ_MASK_WR; 345 346 if (irq_status) 347 complete(&cqspi->transfer_complete); 348 349 return IRQ_HANDLED; 350 } 351 352 static unsigned int cqspi_calc_rdreg(const struct spi_mem_op *op) 353 { 354 u32 rdreg = 0; 355 356 rdreg |= CQSPI_OP_WIDTH(op->cmd) << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; 357 rdreg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; 358 rdreg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; 359 360 return rdreg; 361 } 362 363 static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op) 364 { 365 unsigned int dummy_clk; 366 367 if (!op->dummy.nbytes) 368 return 0; 369 370 dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth); 371 if (op->cmd.dtr) 372 dummy_clk /= 2; 373 374 return dummy_clk; 375 } 376 377 static int cqspi_wait_idle(struct cqspi_st *cqspi) 378 { 379 const unsigned int poll_idle_retry = 3; 380 unsigned int count = 0; 381 unsigned long timeout; 382 383 timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS); 384 while (1) { 385 /* 386 * Read few times in succession to ensure the controller 387 * is indeed idle, that is, the bit does not transition 388 * low again. 389 */ 390 if (cqspi_is_idle(cqspi)) 391 count++; 392 else 393 count = 0; 394 395 if (count >= poll_idle_retry) 396 return 0; 397 398 if (time_after(jiffies, timeout)) { 399 /* Timeout, in busy mode. */ 400 dev_err(&cqspi->pdev->dev, 401 "QSPI is still busy after %dms timeout.\n", 402 CQSPI_TIMEOUT_MS); 403 return -ETIMEDOUT; 404 } 405 406 cpu_relax(); 407 } 408 } 409 410 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg) 411 { 412 void __iomem *reg_base = cqspi->iobase; 413 int ret; 414 415 /* Write the CMDCTRL without start execution. */ 416 writel(reg, reg_base + CQSPI_REG_CMDCTRL); 417 /* Start execute */ 418 reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK; 419 writel(reg, reg_base + CQSPI_REG_CMDCTRL); 420 421 /* Polling for completion. */ 422 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL, 423 CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1); 424 if (ret) { 425 dev_err(&cqspi->pdev->dev, 426 "Flash command execution timed out.\n"); 427 return ret; 428 } 429 430 /* Polling QSPI idle status. */ 431 return cqspi_wait_idle(cqspi); 432 } 433 434 static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata, 435 const struct spi_mem_op *op, 436 unsigned int shift) 437 { 438 struct cqspi_st *cqspi = f_pdata->cqspi; 439 void __iomem *reg_base = cqspi->iobase; 440 unsigned int reg; 441 u8 ext; 442 443 if (op->cmd.nbytes != 2) 444 return -EINVAL; 445 446 /* Opcode extension is the LSB. */ 447 ext = op->cmd.opcode & 0xff; 448 449 reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER); 450 reg &= ~(0xff << shift); 451 reg |= ext << shift; 452 writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER); 453 454 return 0; 455 } 456 457 static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata, 458 const struct spi_mem_op *op, unsigned int shift) 459 { 460 struct cqspi_st *cqspi = f_pdata->cqspi; 461 void __iomem *reg_base = cqspi->iobase; 462 unsigned int reg; 463 int ret; 464 465 reg = readl(reg_base + CQSPI_REG_CONFIG); 466 467 /* 468 * We enable dual byte opcode here. The callers have to set up the 469 * extension opcode based on which type of operation it is. 470 */ 471 if (op->cmd.dtr) { 472 reg |= CQSPI_REG_CONFIG_DTR_PROTO; 473 reg |= CQSPI_REG_CONFIG_DUAL_OPCODE; 474 475 /* Set up command opcode extension. */ 476 ret = cqspi_setup_opcode_ext(f_pdata, op, shift); 477 if (ret) 478 return ret; 479 } else { 480 reg &= ~CQSPI_REG_CONFIG_DTR_PROTO; 481 reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE; 482 } 483 484 writel(reg, reg_base + CQSPI_REG_CONFIG); 485 486 return cqspi_wait_idle(cqspi); 487 } 488 489 static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, 490 const struct spi_mem_op *op) 491 { 492 struct cqspi_st *cqspi = f_pdata->cqspi; 493 void __iomem *reg_base = cqspi->iobase; 494 u8 *rxbuf = op->data.buf.in; 495 u8 opcode; 496 size_t n_rx = op->data.nbytes; 497 unsigned int rdreg; 498 unsigned int reg; 499 unsigned int dummy_clk; 500 size_t read_len; 501 int status; 502 503 status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB); 504 if (status) 505 return status; 506 507 if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) { 508 dev_err(&cqspi->pdev->dev, 509 "Invalid input argument, len %zu rxbuf 0x%p\n", 510 n_rx, rxbuf); 511 return -EINVAL; 512 } 513 514 if (op->cmd.dtr) 515 opcode = op->cmd.opcode >> 8; 516 else 517 opcode = op->cmd.opcode; 518 519 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 520 521 rdreg = cqspi_calc_rdreg(op); 522 writel(rdreg, reg_base + CQSPI_REG_RD_INSTR); 523 524 dummy_clk = cqspi_calc_dummy(op); 525 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 526 return -EOPNOTSUPP; 527 528 if (dummy_clk) 529 reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK) 530 << CQSPI_REG_CMDCTRL_DUMMY_LSB; 531 532 reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); 533 534 /* 0 means 1 byte. */ 535 reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) 536 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); 537 538 /* setup ADDR BIT field */ 539 if (op->addr.nbytes) { 540 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 541 reg |= ((op->addr.nbytes - 1) & 542 CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) 543 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; 544 545 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); 546 } 547 548 status = cqspi_exec_flash_cmd(cqspi, reg); 549 if (status) 550 return status; 551 552 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER); 553 554 /* Put the read value into rx_buf */ 555 read_len = (n_rx > 4) ? 4 : n_rx; 556 memcpy(rxbuf, ®, read_len); 557 rxbuf += read_len; 558 559 if (n_rx > 4) { 560 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER); 561 562 read_len = n_rx - read_len; 563 memcpy(rxbuf, ®, read_len); 564 } 565 566 /* Reset CMD_CTRL Reg once command read completes */ 567 writel(0, reg_base + CQSPI_REG_CMDCTRL); 568 569 return 0; 570 } 571 572 static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata, 573 const struct spi_mem_op *op) 574 { 575 struct cqspi_st *cqspi = f_pdata->cqspi; 576 void __iomem *reg_base = cqspi->iobase; 577 u8 opcode; 578 const u8 *txbuf = op->data.buf.out; 579 size_t n_tx = op->data.nbytes; 580 unsigned int reg; 581 unsigned int data; 582 size_t write_len; 583 int ret; 584 585 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB); 586 if (ret) 587 return ret; 588 589 if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) { 590 dev_err(&cqspi->pdev->dev, 591 "Invalid input argument, cmdlen %zu txbuf 0x%p\n", 592 n_tx, txbuf); 593 return -EINVAL; 594 } 595 596 reg = cqspi_calc_rdreg(op); 597 writel(reg, reg_base + CQSPI_REG_RD_INSTR); 598 599 if (op->cmd.dtr) 600 opcode = op->cmd.opcode >> 8; 601 else 602 opcode = op->cmd.opcode; 603 604 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 605 606 if (op->addr.nbytes) { 607 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 608 reg |= ((op->addr.nbytes - 1) & 609 CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) 610 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; 611 612 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); 613 } 614 615 if (n_tx) { 616 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB); 617 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) 618 << CQSPI_REG_CMDCTRL_WR_BYTES_LSB; 619 data = 0; 620 write_len = (n_tx > 4) ? 4 : n_tx; 621 memcpy(&data, txbuf, write_len); 622 txbuf += write_len; 623 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER); 624 625 if (n_tx > 4) { 626 data = 0; 627 write_len = n_tx - 4; 628 memcpy(&data, txbuf, write_len); 629 writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER); 630 } 631 } 632 633 ret = cqspi_exec_flash_cmd(cqspi, reg); 634 635 /* Reset CMD_CTRL Reg once command write completes */ 636 writel(0, reg_base + CQSPI_REG_CMDCTRL); 637 638 return ret; 639 } 640 641 static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata, 642 const struct spi_mem_op *op) 643 { 644 struct cqspi_st *cqspi = f_pdata->cqspi; 645 void __iomem *reg_base = cqspi->iobase; 646 unsigned int dummy_clk = 0; 647 unsigned int reg; 648 int ret; 649 u8 opcode; 650 651 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB); 652 if (ret) 653 return ret; 654 655 if (op->cmd.dtr) 656 opcode = op->cmd.opcode >> 8; 657 else 658 opcode = op->cmd.opcode; 659 660 reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB; 661 reg |= cqspi_calc_rdreg(op); 662 663 /* Setup dummy clock cycles */ 664 dummy_clk = cqspi_calc_dummy(op); 665 666 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 667 return -EOPNOTSUPP; 668 669 if (dummy_clk) 670 reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK) 671 << CQSPI_REG_RD_INSTR_DUMMY_LSB; 672 673 writel(reg, reg_base + CQSPI_REG_RD_INSTR); 674 675 /* Set address width */ 676 reg = readl(reg_base + CQSPI_REG_SIZE); 677 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 678 reg |= (op->addr.nbytes - 1); 679 writel(reg, reg_base + CQSPI_REG_SIZE); 680 return 0; 681 } 682 683 static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, 684 u8 *rxbuf, loff_t from_addr, 685 const size_t n_rx) 686 { 687 struct cqspi_st *cqspi = f_pdata->cqspi; 688 struct device *dev = &cqspi->pdev->dev; 689 void __iomem *reg_base = cqspi->iobase; 690 void __iomem *ahb_base = cqspi->ahb_base; 691 unsigned int remaining = n_rx; 692 unsigned int mod_bytes = n_rx % 4; 693 unsigned int bytes_to_read = 0; 694 u8 *rxbuf_end = rxbuf + n_rx; 695 int ret = 0; 696 697 writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 698 writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES); 699 700 /* Clear all interrupts. */ 701 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 702 703 /* 704 * On SoCFPGA platform reading the SRAM is slow due to 705 * hardware limitation and causing read interrupt storm to CPU, 706 * so enabling only watermark interrupt to disable all read 707 * interrupts later as we want to run "bytes to read" loop with 708 * all the read interrupts disabled for max performance. 709 */ 710 711 if (!cqspi->slow_sram) 712 writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK); 713 else 714 writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK); 715 716 reinit_completion(&cqspi->transfer_complete); 717 writel(CQSPI_REG_INDIRECTRD_START_MASK, 718 reg_base + CQSPI_REG_INDIRECTRD); 719 720 while (remaining > 0) { 721 if (!wait_for_completion_timeout(&cqspi->transfer_complete, 722 msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) 723 ret = -ETIMEDOUT; 724 725 /* 726 * Disable all read interrupts until 727 * we are out of "bytes to read" 728 */ 729 if (cqspi->slow_sram) 730 writel(0x0, reg_base + CQSPI_REG_IRQMASK); 731 732 bytes_to_read = cqspi_get_rd_sram_level(cqspi); 733 734 if (ret && bytes_to_read == 0) { 735 dev_err(dev, "Indirect read timeout, no bytes\n"); 736 goto failrd; 737 } 738 739 while (bytes_to_read != 0) { 740 unsigned int word_remain = round_down(remaining, 4); 741 742 bytes_to_read *= cqspi->fifo_width; 743 bytes_to_read = bytes_to_read > remaining ? 744 remaining : bytes_to_read; 745 bytes_to_read = round_down(bytes_to_read, 4); 746 /* Read 4 byte word chunks then single bytes */ 747 if (bytes_to_read) { 748 ioread32_rep(ahb_base, rxbuf, 749 (bytes_to_read / 4)); 750 } else if (!word_remain && mod_bytes) { 751 unsigned int temp = ioread32(ahb_base); 752 753 bytes_to_read = mod_bytes; 754 memcpy(rxbuf, &temp, min((unsigned int) 755 (rxbuf_end - rxbuf), 756 bytes_to_read)); 757 } 758 rxbuf += bytes_to_read; 759 remaining -= bytes_to_read; 760 bytes_to_read = cqspi_get_rd_sram_level(cqspi); 761 } 762 763 if (remaining > 0) { 764 reinit_completion(&cqspi->transfer_complete); 765 if (cqspi->slow_sram) 766 writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK); 767 } 768 } 769 770 /* Check indirect done status */ 771 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD, 772 CQSPI_REG_INDIRECTRD_DONE_MASK, 0); 773 if (ret) { 774 dev_err(dev, "Indirect read completion error (%i)\n", ret); 775 goto failrd; 776 } 777 778 /* Disable interrupt */ 779 writel(0, reg_base + CQSPI_REG_IRQMASK); 780 781 /* Clear indirect completion status */ 782 writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD); 783 784 return 0; 785 786 failrd: 787 /* Disable interrupt */ 788 writel(0, reg_base + CQSPI_REG_IRQMASK); 789 790 /* Cancel the indirect read */ 791 writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK, 792 reg_base + CQSPI_REG_INDIRECTRD); 793 return ret; 794 } 795 796 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable) 797 { 798 void __iomem *reg_base = cqspi->iobase; 799 unsigned int reg; 800 801 reg = readl(reg_base + CQSPI_REG_CONFIG); 802 803 if (enable) 804 reg |= CQSPI_REG_CONFIG_ENABLE_MASK; 805 else 806 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; 807 808 writel(reg, reg_base + CQSPI_REG_CONFIG); 809 } 810 811 static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata, 812 u_char *rxbuf, loff_t from_addr, 813 size_t n_rx) 814 { 815 struct cqspi_st *cqspi = f_pdata->cqspi; 816 struct device *dev = &cqspi->pdev->dev; 817 void __iomem *reg_base = cqspi->iobase; 818 u32 reg, bytes_to_dma; 819 loff_t addr = from_addr; 820 void *buf = rxbuf; 821 dma_addr_t dma_addr; 822 u8 bytes_rem; 823 int ret = 0; 824 825 bytes_rem = n_rx % 4; 826 bytes_to_dma = (n_rx - bytes_rem); 827 828 if (!bytes_to_dma) 829 goto nondmard; 830 831 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA); 832 if (ret) 833 return ret; 834 835 cqspi_controller_enable(cqspi, 0); 836 837 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 838 reg |= CQSPI_REG_CONFIG_DMA_MASK; 839 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 840 841 cqspi_controller_enable(cqspi, 1); 842 843 dma_addr = dma_map_single(dev, rxbuf, bytes_to_dma, DMA_FROM_DEVICE); 844 if (dma_mapping_error(dev, dma_addr)) { 845 dev_err(dev, "dma mapping failed\n"); 846 return -ENOMEM; 847 } 848 849 writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 850 writel(bytes_to_dma, reg_base + CQSPI_REG_INDIRECTRDBYTES); 851 writel(CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL, 852 reg_base + CQSPI_REG_INDTRIG_ADDRRANGE); 853 854 /* Clear all interrupts. */ 855 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 856 857 /* Enable DMA done interrupt */ 858 writel(CQSPI_REG_VERSAL_DMA_DST_DONE_MASK, 859 reg_base + CQSPI_REG_VERSAL_DMA_DST_I_EN); 860 861 /* Default DMA periph configuration */ 862 writel(CQSPI_REG_VERSAL_DMA_VAL, reg_base + CQSPI_REG_DMA); 863 864 /* Configure DMA Dst address */ 865 writel(lower_32_bits(dma_addr), 866 reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR); 867 writel(upper_32_bits(dma_addr), 868 reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB); 869 870 /* Configure DMA Src address */ 871 writel(cqspi->trigger_address, reg_base + 872 CQSPI_REG_VERSAL_DMA_SRC_ADDR); 873 874 /* Set DMA destination size */ 875 writel(bytes_to_dma, reg_base + CQSPI_REG_VERSAL_DMA_DST_SIZE); 876 877 /* Set DMA destination control */ 878 writel(CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL, 879 reg_base + CQSPI_REG_VERSAL_DMA_DST_CTRL); 880 881 writel(CQSPI_REG_INDIRECTRD_START_MASK, 882 reg_base + CQSPI_REG_INDIRECTRD); 883 884 reinit_completion(&cqspi->transfer_complete); 885 886 if (!wait_for_completion_timeout(&cqspi->transfer_complete, 887 msecs_to_jiffies(max_t(size_t, bytes_to_dma, 500)))) { 888 ret = -ETIMEDOUT; 889 goto failrd; 890 } 891 892 /* Disable DMA interrupt */ 893 writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS); 894 895 /* Clear indirect completion status */ 896 writel(CQSPI_REG_INDIRECTRD_DONE_MASK, 897 cqspi->iobase + CQSPI_REG_INDIRECTRD); 898 dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE); 899 900 cqspi_controller_enable(cqspi, 0); 901 902 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 903 reg &= ~CQSPI_REG_CONFIG_DMA_MASK; 904 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 905 906 cqspi_controller_enable(cqspi, 1); 907 908 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, 909 PM_OSPI_MUX_SEL_LINEAR); 910 if (ret) 911 return ret; 912 913 nondmard: 914 if (bytes_rem) { 915 addr += bytes_to_dma; 916 buf += bytes_to_dma; 917 ret = cqspi_indirect_read_execute(f_pdata, buf, addr, 918 bytes_rem); 919 if (ret) 920 return ret; 921 } 922 923 return 0; 924 925 failrd: 926 /* Disable DMA interrupt */ 927 writel(0x0, reg_base + CQSPI_REG_VERSAL_DMA_DST_I_DIS); 928 929 /* Cancel the indirect read */ 930 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 931 reg_base + CQSPI_REG_INDIRECTRD); 932 933 dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE); 934 935 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 936 reg &= ~CQSPI_REG_CONFIG_DMA_MASK; 937 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 938 939 zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR); 940 941 return ret; 942 } 943 944 static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata, 945 const struct spi_mem_op *op) 946 { 947 unsigned int reg; 948 int ret; 949 struct cqspi_st *cqspi = f_pdata->cqspi; 950 void __iomem *reg_base = cqspi->iobase; 951 u8 opcode; 952 953 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB); 954 if (ret) 955 return ret; 956 957 if (op->cmd.dtr) 958 opcode = op->cmd.opcode >> 8; 959 else 960 opcode = op->cmd.opcode; 961 962 /* Set opcode. */ 963 reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; 964 reg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; 965 reg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; 966 writel(reg, reg_base + CQSPI_REG_WR_INSTR); 967 reg = cqspi_calc_rdreg(op); 968 writel(reg, reg_base + CQSPI_REG_RD_INSTR); 969 970 /* 971 * SPI NAND flashes require the address of the status register to be 972 * passed in the Read SR command. Also, some SPI NOR flashes like the 973 * cypress Semper flash expect a 4-byte dummy address in the Read SR 974 * command in DTR mode. 975 * 976 * But this controller does not support address phase in the Read SR 977 * command when doing auto-HW polling. So, disable write completion 978 * polling on the controller's side. spinand and spi-nor will take 979 * care of polling the status register. 980 */ 981 if (cqspi->wr_completion) { 982 reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL); 983 reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL; 984 writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL); 985 /* 986 * DAC mode require auto polling as flash needs to be polled 987 * for write completion in case of bubble in SPI transaction 988 * due to slow CPU/DMA master. 989 */ 990 cqspi->use_direct_mode_wr = false; 991 } 992 993 reg = readl(reg_base + CQSPI_REG_SIZE); 994 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 995 reg |= (op->addr.nbytes - 1); 996 writel(reg, reg_base + CQSPI_REG_SIZE); 997 return 0; 998 } 999 1000 static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, 1001 loff_t to_addr, const u8 *txbuf, 1002 const size_t n_tx) 1003 { 1004 struct cqspi_st *cqspi = f_pdata->cqspi; 1005 struct device *dev = &cqspi->pdev->dev; 1006 void __iomem *reg_base = cqspi->iobase; 1007 unsigned int remaining = n_tx; 1008 unsigned int write_bytes; 1009 int ret; 1010 1011 writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR); 1012 writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES); 1013 1014 /* Clear all interrupts. */ 1015 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 1016 1017 writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK); 1018 1019 reinit_completion(&cqspi->transfer_complete); 1020 writel(CQSPI_REG_INDIRECTWR_START_MASK, 1021 reg_base + CQSPI_REG_INDIRECTWR); 1022 /* 1023 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access 1024 * Controller programming sequence, couple of cycles of 1025 * QSPI_REF_CLK delay is required for the above bit to 1026 * be internally synchronized by the QSPI module. Provide 5 1027 * cycles of delay. 1028 */ 1029 if (cqspi->wr_delay) 1030 ndelay(cqspi->wr_delay); 1031 1032 /* 1033 * If a hazard exists between the APB and AHB interfaces, perform a 1034 * dummy readback from the controller to ensure synchronization. 1035 */ 1036 if (cqspi->apb_ahb_hazard) 1037 readl(reg_base + CQSPI_REG_INDIRECTWR); 1038 1039 while (remaining > 0) { 1040 size_t write_words, mod_bytes; 1041 1042 write_bytes = remaining; 1043 write_words = write_bytes / 4; 1044 mod_bytes = write_bytes % 4; 1045 /* Write 4 bytes at a time then single bytes. */ 1046 if (write_words) { 1047 iowrite32_rep(cqspi->ahb_base, txbuf, write_words); 1048 txbuf += (write_words * 4); 1049 } 1050 if (mod_bytes) { 1051 unsigned int temp = 0xFFFFFFFF; 1052 1053 memcpy(&temp, txbuf, mod_bytes); 1054 iowrite32(temp, cqspi->ahb_base); 1055 txbuf += mod_bytes; 1056 } 1057 1058 if (!wait_for_completion_timeout(&cqspi->transfer_complete, 1059 msecs_to_jiffies(CQSPI_TIMEOUT_MS))) { 1060 dev_err(dev, "Indirect write timeout\n"); 1061 ret = -ETIMEDOUT; 1062 goto failwr; 1063 } 1064 1065 remaining -= write_bytes; 1066 1067 if (remaining > 0) 1068 reinit_completion(&cqspi->transfer_complete); 1069 } 1070 1071 /* Check indirect done status */ 1072 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR, 1073 CQSPI_REG_INDIRECTWR_DONE_MASK, 0); 1074 if (ret) { 1075 dev_err(dev, "Indirect write completion error (%i)\n", ret); 1076 goto failwr; 1077 } 1078 1079 /* Disable interrupt. */ 1080 writel(0, reg_base + CQSPI_REG_IRQMASK); 1081 1082 /* Clear indirect completion status */ 1083 writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR); 1084 1085 cqspi_wait_idle(cqspi); 1086 1087 return 0; 1088 1089 failwr: 1090 /* Disable interrupt. */ 1091 writel(0, reg_base + CQSPI_REG_IRQMASK); 1092 1093 /* Cancel the indirect write */ 1094 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 1095 reg_base + CQSPI_REG_INDIRECTWR); 1096 return ret; 1097 } 1098 1099 static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata) 1100 { 1101 struct cqspi_st *cqspi = f_pdata->cqspi; 1102 void __iomem *reg_base = cqspi->iobase; 1103 unsigned int chip_select = f_pdata->cs; 1104 unsigned int reg; 1105 1106 reg = readl(reg_base + CQSPI_REG_CONFIG); 1107 if (cqspi->is_decoded_cs) { 1108 reg |= CQSPI_REG_CONFIG_DECODE_MASK; 1109 } else { 1110 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; 1111 1112 /* Convert CS if without decoder. 1113 * CS0 to 4b'1110 1114 * CS1 to 4b'1101 1115 * CS2 to 4b'1011 1116 * CS3 to 4b'0111 1117 */ 1118 chip_select = 0xF & ~(1 << chip_select); 1119 } 1120 1121 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK 1122 << CQSPI_REG_CONFIG_CHIPSELECT_LSB); 1123 reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK) 1124 << CQSPI_REG_CONFIG_CHIPSELECT_LSB; 1125 writel(reg, reg_base + CQSPI_REG_CONFIG); 1126 } 1127 1128 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz, 1129 const unsigned int ns_val) 1130 { 1131 unsigned int ticks; 1132 1133 ticks = ref_clk_hz / 1000; /* kHz */ 1134 ticks = DIV_ROUND_UP(ticks * ns_val, 1000000); 1135 1136 return ticks; 1137 } 1138 1139 static void cqspi_delay(struct cqspi_flash_pdata *f_pdata) 1140 { 1141 struct cqspi_st *cqspi = f_pdata->cqspi; 1142 void __iomem *iobase = cqspi->iobase; 1143 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 1144 unsigned int tshsl, tchsh, tslch, tsd2d; 1145 unsigned int reg; 1146 unsigned int tsclk; 1147 1148 /* calculate the number of ref ticks for one sclk tick */ 1149 tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk); 1150 1151 tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns); 1152 /* this particular value must be at least one sclk */ 1153 if (tshsl < tsclk) 1154 tshsl = tsclk; 1155 1156 tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns); 1157 tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns); 1158 tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns); 1159 1160 reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK) 1161 << CQSPI_REG_DELAY_TSHSL_LSB; 1162 reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK) 1163 << CQSPI_REG_DELAY_TCHSH_LSB; 1164 reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK) 1165 << CQSPI_REG_DELAY_TSLCH_LSB; 1166 reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK) 1167 << CQSPI_REG_DELAY_TSD2D_LSB; 1168 writel(reg, iobase + CQSPI_REG_DELAY); 1169 } 1170 1171 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi) 1172 { 1173 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 1174 void __iomem *reg_base = cqspi->iobase; 1175 u32 reg, div; 1176 1177 /* Recalculate the baudrate divisor based on QSPI specification. */ 1178 div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1; 1179 1180 /* Maximum baud divisor */ 1181 if (div > CQSPI_REG_CONFIG_BAUD_MASK) { 1182 div = CQSPI_REG_CONFIG_BAUD_MASK; 1183 dev_warn(&cqspi->pdev->dev, 1184 "Unable to adjust clock <= %d hz. Reduced to %d hz\n", 1185 cqspi->sclk, ref_clk_hz/((div+1)*2)); 1186 } 1187 1188 reg = readl(reg_base + CQSPI_REG_CONFIG); 1189 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); 1190 reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB; 1191 writel(reg, reg_base + CQSPI_REG_CONFIG); 1192 } 1193 1194 static void cqspi_readdata_capture(struct cqspi_st *cqspi, 1195 const bool bypass, 1196 const unsigned int delay) 1197 { 1198 void __iomem *reg_base = cqspi->iobase; 1199 unsigned int reg; 1200 1201 reg = readl(reg_base + CQSPI_REG_READCAPTURE); 1202 1203 if (bypass) 1204 reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 1205 else 1206 reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 1207 1208 reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK 1209 << CQSPI_REG_READCAPTURE_DELAY_LSB); 1210 1211 reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK) 1212 << CQSPI_REG_READCAPTURE_DELAY_LSB; 1213 1214 writel(reg, reg_base + CQSPI_REG_READCAPTURE); 1215 } 1216 1217 static void cqspi_configure(struct cqspi_flash_pdata *f_pdata, 1218 unsigned long sclk) 1219 { 1220 struct cqspi_st *cqspi = f_pdata->cqspi; 1221 int switch_cs = (cqspi->current_cs != f_pdata->cs); 1222 int switch_ck = (cqspi->sclk != sclk); 1223 1224 if (switch_cs || switch_ck) 1225 cqspi_controller_enable(cqspi, 0); 1226 1227 /* Switch chip select. */ 1228 if (switch_cs) { 1229 cqspi->current_cs = f_pdata->cs; 1230 cqspi_chipselect(f_pdata); 1231 } 1232 1233 /* Setup baudrate divisor and delays */ 1234 if (switch_ck) { 1235 cqspi->sclk = sclk; 1236 cqspi_config_baudrate_div(cqspi); 1237 cqspi_delay(f_pdata); 1238 cqspi_readdata_capture(cqspi, !cqspi->rclk_en, 1239 f_pdata->read_delay); 1240 } 1241 1242 if (switch_cs || switch_ck) 1243 cqspi_controller_enable(cqspi, 1); 1244 } 1245 1246 static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata, 1247 const struct spi_mem_op *op) 1248 { 1249 struct cqspi_st *cqspi = f_pdata->cqspi; 1250 loff_t to = op->addr.val; 1251 size_t len = op->data.nbytes; 1252 const u_char *buf = op->data.buf.out; 1253 int ret; 1254 1255 ret = cqspi_write_setup(f_pdata, op); 1256 if (ret) 1257 return ret; 1258 1259 /* 1260 * Some flashes like the Cypress Semper flash expect a dummy 4-byte 1261 * address (all 0s) with the read status register command in DTR mode. 1262 * But this controller does not support sending dummy address bytes to 1263 * the flash when it is polling the write completion register in DTR 1264 * mode. So, we can not use direct mode when in DTR mode for writing 1265 * data. 1266 */ 1267 if (!op->cmd.dtr && cqspi->use_direct_mode && 1268 cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) { 1269 memcpy_toio(cqspi->ahb_base + to, buf, len); 1270 return cqspi_wait_idle(cqspi); 1271 } 1272 1273 return cqspi_indirect_write_execute(f_pdata, to, buf, len); 1274 } 1275 1276 static void cqspi_rx_dma_callback(void *param) 1277 { 1278 struct cqspi_st *cqspi = param; 1279 1280 complete(&cqspi->rx_dma_complete); 1281 } 1282 1283 static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata, 1284 u_char *buf, loff_t from, size_t len) 1285 { 1286 struct cqspi_st *cqspi = f_pdata->cqspi; 1287 struct device *dev = &cqspi->pdev->dev; 1288 enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; 1289 dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from; 1290 int ret = 0; 1291 struct dma_async_tx_descriptor *tx; 1292 dma_cookie_t cookie; 1293 dma_addr_t dma_dst; 1294 struct device *ddev; 1295 1296 if (!cqspi->rx_chan || !virt_addr_valid(buf)) { 1297 memcpy_fromio(buf, cqspi->ahb_base + from, len); 1298 return 0; 1299 } 1300 1301 ddev = cqspi->rx_chan->device->dev; 1302 dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE); 1303 if (dma_mapping_error(ddev, dma_dst)) { 1304 dev_err(dev, "dma mapping failed\n"); 1305 return -ENOMEM; 1306 } 1307 tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src, 1308 len, flags); 1309 if (!tx) { 1310 dev_err(dev, "device_prep_dma_memcpy error\n"); 1311 ret = -EIO; 1312 goto err_unmap; 1313 } 1314 1315 tx->callback = cqspi_rx_dma_callback; 1316 tx->callback_param = cqspi; 1317 cookie = tx->tx_submit(tx); 1318 reinit_completion(&cqspi->rx_dma_complete); 1319 1320 ret = dma_submit_error(cookie); 1321 if (ret) { 1322 dev_err(dev, "dma_submit_error %d\n", cookie); 1323 ret = -EIO; 1324 goto err_unmap; 1325 } 1326 1327 dma_async_issue_pending(cqspi->rx_chan); 1328 if (!wait_for_completion_timeout(&cqspi->rx_dma_complete, 1329 msecs_to_jiffies(max_t(size_t, len, 500)))) { 1330 dmaengine_terminate_sync(cqspi->rx_chan); 1331 dev_err(dev, "DMA wait_for_completion_timeout\n"); 1332 ret = -ETIMEDOUT; 1333 goto err_unmap; 1334 } 1335 1336 err_unmap: 1337 dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE); 1338 1339 return ret; 1340 } 1341 1342 static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata, 1343 const struct spi_mem_op *op) 1344 { 1345 struct cqspi_st *cqspi = f_pdata->cqspi; 1346 struct device *dev = &cqspi->pdev->dev; 1347 const struct cqspi_driver_platdata *ddata; 1348 loff_t from = op->addr.val; 1349 size_t len = op->data.nbytes; 1350 u_char *buf = op->data.buf.in; 1351 u64 dma_align = (u64)(uintptr_t)buf; 1352 int ret; 1353 1354 ddata = of_device_get_match_data(dev); 1355 1356 ret = cqspi_read_setup(f_pdata, op); 1357 if (ret) 1358 return ret; 1359 1360 if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) 1361 return cqspi_direct_read_execute(f_pdata, buf, from, len); 1362 1363 if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma && 1364 virt_addr_valid(buf) && ((dma_align & CQSPI_DMA_UNALIGN) == 0)) 1365 return ddata->indirect_read_dma(f_pdata, buf, from, len); 1366 1367 return cqspi_indirect_read_execute(f_pdata, buf, from, len); 1368 } 1369 1370 static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op) 1371 { 1372 struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); 1373 struct cqspi_flash_pdata *f_pdata; 1374 1375 f_pdata = &cqspi->f_pdata[spi_get_chipselect(mem->spi, 0)]; 1376 cqspi_configure(f_pdata, mem->spi->max_speed_hz); 1377 1378 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { 1379 /* 1380 * Performing reads in DAC mode forces to read minimum 4 bytes 1381 * which is unsupported on some flash devices during register 1382 * reads, prefer STIG mode for such small reads. 1383 */ 1384 if (!op->addr.nbytes || 1385 op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX) 1386 return cqspi_command_read(f_pdata, op); 1387 1388 return cqspi_read(f_pdata, op); 1389 } 1390 1391 if (!op->addr.nbytes || !op->data.buf.out) 1392 return cqspi_command_write(f_pdata, op); 1393 1394 return cqspi_write(f_pdata, op); 1395 } 1396 1397 static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) 1398 { 1399 int ret; 1400 1401 ret = cqspi_mem_process(mem, op); 1402 if (ret) 1403 dev_err(&mem->spi->dev, "operation failed with %d\n", ret); 1404 1405 return ret; 1406 } 1407 1408 static bool cqspi_supports_mem_op(struct spi_mem *mem, 1409 const struct spi_mem_op *op) 1410 { 1411 bool all_true, all_false; 1412 1413 /* 1414 * op->dummy.dtr is required for converting nbytes into ncycles. 1415 * Also, don't check the dtr field of the op phase having zero nbytes. 1416 */ 1417 all_true = op->cmd.dtr && 1418 (!op->addr.nbytes || op->addr.dtr) && 1419 (!op->dummy.nbytes || op->dummy.dtr) && 1420 (!op->data.nbytes || op->data.dtr); 1421 1422 all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && 1423 !op->data.dtr; 1424 1425 if (all_true) { 1426 /* Right now we only support 8-8-8 DTR mode. */ 1427 if (op->cmd.nbytes && op->cmd.buswidth != 8) 1428 return false; 1429 if (op->addr.nbytes && op->addr.buswidth != 8) 1430 return false; 1431 if (op->data.nbytes && op->data.buswidth != 8) 1432 return false; 1433 } else if (!all_false) { 1434 /* Mixed DTR modes are not supported. */ 1435 return false; 1436 } 1437 1438 return spi_mem_default_supports_op(mem, op); 1439 } 1440 1441 static int cqspi_of_get_flash_pdata(struct platform_device *pdev, 1442 struct cqspi_flash_pdata *f_pdata, 1443 struct device_node *np) 1444 { 1445 if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) { 1446 dev_err(&pdev->dev, "couldn't determine read-delay\n"); 1447 return -ENXIO; 1448 } 1449 1450 if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) { 1451 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n"); 1452 return -ENXIO; 1453 } 1454 1455 if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) { 1456 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n"); 1457 return -ENXIO; 1458 } 1459 1460 if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) { 1461 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n"); 1462 return -ENXIO; 1463 } 1464 1465 if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) { 1466 dev_err(&pdev->dev, "couldn't determine tslch-ns\n"); 1467 return -ENXIO; 1468 } 1469 1470 if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) { 1471 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n"); 1472 return -ENXIO; 1473 } 1474 1475 return 0; 1476 } 1477 1478 static int cqspi_of_get_pdata(struct cqspi_st *cqspi) 1479 { 1480 struct device *dev = &cqspi->pdev->dev; 1481 struct device_node *np = dev->of_node; 1482 u32 id[2]; 1483 1484 cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); 1485 1486 if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { 1487 dev_err(dev, "couldn't determine fifo-depth\n"); 1488 return -ENXIO; 1489 } 1490 1491 if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) { 1492 dev_err(dev, "couldn't determine fifo-width\n"); 1493 return -ENXIO; 1494 } 1495 1496 if (of_property_read_u32(np, "cdns,trigger-address", 1497 &cqspi->trigger_address)) { 1498 dev_err(dev, "couldn't determine trigger-address\n"); 1499 return -ENXIO; 1500 } 1501 1502 if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) 1503 cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT; 1504 1505 cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); 1506 1507 if (!of_property_read_u32_array(np, "power-domains", id, 1508 ARRAY_SIZE(id))) 1509 cqspi->pd_dev_id = id[1]; 1510 1511 return 0; 1512 } 1513 1514 static void cqspi_controller_init(struct cqspi_st *cqspi) 1515 { 1516 u32 reg; 1517 1518 cqspi_controller_enable(cqspi, 0); 1519 1520 /* Configure the remap address register, no remap */ 1521 writel(0, cqspi->iobase + CQSPI_REG_REMAP); 1522 1523 /* Disable all interrupts. */ 1524 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); 1525 1526 /* Configure the SRAM split to 1:1 . */ 1527 writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); 1528 1529 /* Load indirect trigger address. */ 1530 writel(cqspi->trigger_address, 1531 cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); 1532 1533 /* Program read watermark -- 1/2 of the FIFO. */ 1534 writel(cqspi->fifo_depth * cqspi->fifo_width / 2, 1535 cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); 1536 /* Program write watermark -- 1/8 of the FIFO. */ 1537 writel(cqspi->fifo_depth * cqspi->fifo_width / 8, 1538 cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); 1539 1540 /* Disable direct access controller */ 1541 if (!cqspi->use_direct_mode) { 1542 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 1543 reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL; 1544 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 1545 } 1546 1547 /* Enable DMA interface */ 1548 if (cqspi->use_dma_read) { 1549 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 1550 reg |= CQSPI_REG_CONFIG_DMA_MASK; 1551 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 1552 } 1553 1554 cqspi_controller_enable(cqspi, 1); 1555 } 1556 1557 static int cqspi_request_mmap_dma(struct cqspi_st *cqspi) 1558 { 1559 dma_cap_mask_t mask; 1560 1561 dma_cap_zero(mask); 1562 dma_cap_set(DMA_MEMCPY, mask); 1563 1564 cqspi->rx_chan = dma_request_chan_by_mask(&mask); 1565 if (IS_ERR(cqspi->rx_chan)) { 1566 int ret = PTR_ERR(cqspi->rx_chan); 1567 1568 cqspi->rx_chan = NULL; 1569 return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n"); 1570 } 1571 init_completion(&cqspi->rx_dma_complete); 1572 1573 return 0; 1574 } 1575 1576 static const char *cqspi_get_name(struct spi_mem *mem) 1577 { 1578 struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); 1579 struct device *dev = &cqspi->pdev->dev; 1580 1581 return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), 1582 spi_get_chipselect(mem->spi, 0)); 1583 } 1584 1585 static const struct spi_controller_mem_ops cqspi_mem_ops = { 1586 .exec_op = cqspi_exec_mem_op, 1587 .get_name = cqspi_get_name, 1588 .supports_op = cqspi_supports_mem_op, 1589 }; 1590 1591 static const struct spi_controller_mem_caps cqspi_mem_caps = { 1592 .dtr = true, 1593 }; 1594 1595 static int cqspi_setup_flash(struct cqspi_st *cqspi) 1596 { 1597 struct platform_device *pdev = cqspi->pdev; 1598 struct device *dev = &pdev->dev; 1599 struct device_node *np = dev->of_node; 1600 struct cqspi_flash_pdata *f_pdata; 1601 unsigned int cs; 1602 int ret; 1603 1604 /* Get flash device data */ 1605 for_each_available_child_of_node(dev->of_node, np) { 1606 ret = of_property_read_u32(np, "reg", &cs); 1607 if (ret) { 1608 dev_err(dev, "Couldn't determine chip select.\n"); 1609 of_node_put(np); 1610 return ret; 1611 } 1612 1613 if (cs >= CQSPI_MAX_CHIPSELECT) { 1614 dev_err(dev, "Chip select %d out of range.\n", cs); 1615 of_node_put(np); 1616 return -EINVAL; 1617 } 1618 1619 f_pdata = &cqspi->f_pdata[cs]; 1620 f_pdata->cqspi = cqspi; 1621 f_pdata->cs = cs; 1622 1623 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np); 1624 if (ret) { 1625 of_node_put(np); 1626 return ret; 1627 } 1628 } 1629 1630 return 0; 1631 } 1632 1633 static int cqspi_probe(struct platform_device *pdev) 1634 { 1635 const struct cqspi_driver_platdata *ddata; 1636 struct reset_control *rstc, *rstc_ocp, *rstc_ref; 1637 struct device *dev = &pdev->dev; 1638 struct spi_master *master; 1639 struct resource *res_ahb; 1640 struct cqspi_st *cqspi; 1641 int ret; 1642 int irq; 1643 1644 master = devm_spi_alloc_master(&pdev->dev, sizeof(*cqspi)); 1645 if (!master) { 1646 dev_err(&pdev->dev, "spi_alloc_master failed\n"); 1647 return -ENOMEM; 1648 } 1649 master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; 1650 master->mem_ops = &cqspi_mem_ops; 1651 master->mem_caps = &cqspi_mem_caps; 1652 master->dev.of_node = pdev->dev.of_node; 1653 1654 cqspi = spi_master_get_devdata(master); 1655 1656 cqspi->pdev = pdev; 1657 cqspi->master = master; 1658 platform_set_drvdata(pdev, cqspi); 1659 1660 /* Obtain configuration from OF. */ 1661 ret = cqspi_of_get_pdata(cqspi); 1662 if (ret) { 1663 dev_err(dev, "Cannot get mandatory OF data.\n"); 1664 return -ENODEV; 1665 } 1666 1667 /* Obtain QSPI clock. */ 1668 cqspi->clk = devm_clk_get(dev, NULL); 1669 if (IS_ERR(cqspi->clk)) { 1670 dev_err(dev, "Cannot claim QSPI clock.\n"); 1671 ret = PTR_ERR(cqspi->clk); 1672 return ret; 1673 } 1674 1675 /* Obtain and remap controller address. */ 1676 cqspi->iobase = devm_platform_ioremap_resource(pdev, 0); 1677 if (IS_ERR(cqspi->iobase)) { 1678 dev_err(dev, "Cannot remap controller address.\n"); 1679 ret = PTR_ERR(cqspi->iobase); 1680 return ret; 1681 } 1682 1683 /* Obtain and remap AHB address. */ 1684 cqspi->ahb_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res_ahb); 1685 if (IS_ERR(cqspi->ahb_base)) { 1686 dev_err(dev, "Cannot remap AHB address.\n"); 1687 ret = PTR_ERR(cqspi->ahb_base); 1688 return ret; 1689 } 1690 cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start; 1691 cqspi->ahb_size = resource_size(res_ahb); 1692 1693 init_completion(&cqspi->transfer_complete); 1694 1695 /* Obtain IRQ line. */ 1696 irq = platform_get_irq(pdev, 0); 1697 if (irq < 0) 1698 return -ENXIO; 1699 1700 pm_runtime_enable(dev); 1701 ret = pm_runtime_resume_and_get(dev); 1702 if (ret < 0) 1703 goto probe_pm_failed; 1704 1705 ret = clk_prepare_enable(cqspi->clk); 1706 if (ret) { 1707 dev_err(dev, "Cannot enable QSPI clock.\n"); 1708 goto probe_clk_failed; 1709 } 1710 1711 /* Obtain QSPI reset control */ 1712 rstc = devm_reset_control_get_optional_exclusive(dev, "qspi"); 1713 if (IS_ERR(rstc)) { 1714 ret = PTR_ERR(rstc); 1715 dev_err(dev, "Cannot get QSPI reset.\n"); 1716 goto probe_reset_failed; 1717 } 1718 1719 rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); 1720 if (IS_ERR(rstc_ocp)) { 1721 ret = PTR_ERR(rstc_ocp); 1722 dev_err(dev, "Cannot get QSPI OCP reset.\n"); 1723 goto probe_reset_failed; 1724 } 1725 1726 if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) { 1727 rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref"); 1728 if (IS_ERR(rstc_ref)) { 1729 ret = PTR_ERR(rstc_ref); 1730 dev_err(dev, "Cannot get QSPI REF reset.\n"); 1731 goto probe_reset_failed; 1732 } 1733 reset_control_assert(rstc_ref); 1734 reset_control_deassert(rstc_ref); 1735 } 1736 1737 reset_control_assert(rstc); 1738 reset_control_deassert(rstc); 1739 1740 reset_control_assert(rstc_ocp); 1741 reset_control_deassert(rstc_ocp); 1742 1743 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); 1744 master->max_speed_hz = cqspi->master_ref_clk_hz; 1745 1746 /* write completion is supported by default */ 1747 cqspi->wr_completion = true; 1748 1749 ddata = of_device_get_match_data(dev); 1750 if (ddata) { 1751 if (ddata->quirks & CQSPI_NEEDS_WR_DELAY) 1752 cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, 1753 cqspi->master_ref_clk_hz); 1754 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL) 1755 master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; 1756 if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) { 1757 cqspi->use_direct_mode = true; 1758 cqspi->use_direct_mode_wr = true; 1759 } 1760 if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA) 1761 cqspi->use_dma_read = true; 1762 if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION) 1763 cqspi->wr_completion = false; 1764 if (ddata->quirks & CQSPI_SLOW_SRAM) 1765 cqspi->slow_sram = true; 1766 if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) 1767 cqspi->apb_ahb_hazard = true; 1768 1769 if (of_device_is_compatible(pdev->dev.of_node, 1770 "xlnx,versal-ospi-1.0")) { 1771 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); 1772 if (ret) 1773 goto probe_reset_failed; 1774 } 1775 } 1776 1777 ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0, 1778 pdev->name, cqspi); 1779 if (ret) { 1780 dev_err(dev, "Cannot request IRQ.\n"); 1781 goto probe_reset_failed; 1782 } 1783 1784 cqspi_wait_idle(cqspi); 1785 cqspi_controller_init(cqspi); 1786 cqspi->current_cs = -1; 1787 cqspi->sclk = 0; 1788 1789 master->num_chipselect = cqspi->num_chipselect; 1790 1791 ret = cqspi_setup_flash(cqspi); 1792 if (ret) { 1793 dev_err(dev, "failed to setup flash parameters %d\n", ret); 1794 goto probe_setup_failed; 1795 } 1796 1797 if (cqspi->use_direct_mode) { 1798 ret = cqspi_request_mmap_dma(cqspi); 1799 if (ret == -EPROBE_DEFER) 1800 goto probe_setup_failed; 1801 } 1802 1803 ret = spi_register_master(master); 1804 if (ret) { 1805 dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret); 1806 goto probe_setup_failed; 1807 } 1808 1809 return 0; 1810 probe_setup_failed: 1811 cqspi_controller_enable(cqspi, 0); 1812 probe_reset_failed: 1813 clk_disable_unprepare(cqspi->clk); 1814 probe_clk_failed: 1815 pm_runtime_put_sync(dev); 1816 probe_pm_failed: 1817 pm_runtime_disable(dev); 1818 return ret; 1819 } 1820 1821 static void cqspi_remove(struct platform_device *pdev) 1822 { 1823 struct cqspi_st *cqspi = platform_get_drvdata(pdev); 1824 1825 spi_unregister_master(cqspi->master); 1826 cqspi_controller_enable(cqspi, 0); 1827 1828 if (cqspi->rx_chan) 1829 dma_release_channel(cqspi->rx_chan); 1830 1831 clk_disable_unprepare(cqspi->clk); 1832 1833 pm_runtime_put_sync(&pdev->dev); 1834 pm_runtime_disable(&pdev->dev); 1835 } 1836 1837 static int cqspi_suspend(struct device *dev) 1838 { 1839 struct cqspi_st *cqspi = dev_get_drvdata(dev); 1840 struct spi_master *master = dev_get_drvdata(dev); 1841 int ret; 1842 1843 ret = spi_master_suspend(master); 1844 cqspi_controller_enable(cqspi, 0); 1845 1846 clk_disable_unprepare(cqspi->clk); 1847 1848 return ret; 1849 } 1850 1851 static int cqspi_resume(struct device *dev) 1852 { 1853 struct cqspi_st *cqspi = dev_get_drvdata(dev); 1854 struct spi_master *master = dev_get_drvdata(dev); 1855 1856 clk_prepare_enable(cqspi->clk); 1857 cqspi_wait_idle(cqspi); 1858 cqspi_controller_init(cqspi); 1859 1860 cqspi->current_cs = -1; 1861 cqspi->sclk = 0; 1862 1863 return spi_master_resume(master); 1864 } 1865 1866 static DEFINE_SIMPLE_DEV_PM_OPS(cqspi_dev_pm_ops, cqspi_suspend, cqspi_resume); 1867 1868 static const struct cqspi_driver_platdata cdns_qspi = { 1869 .quirks = CQSPI_DISABLE_DAC_MODE, 1870 }; 1871 1872 static const struct cqspi_driver_platdata k2g_qspi = { 1873 .quirks = CQSPI_NEEDS_WR_DELAY, 1874 }; 1875 1876 static const struct cqspi_driver_platdata am654_ospi = { 1877 .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 1878 .quirks = CQSPI_NEEDS_WR_DELAY, 1879 }; 1880 1881 static const struct cqspi_driver_platdata intel_lgm_qspi = { 1882 .quirks = CQSPI_DISABLE_DAC_MODE, 1883 }; 1884 1885 static const struct cqspi_driver_platdata socfpga_qspi = { 1886 .quirks = CQSPI_DISABLE_DAC_MODE 1887 | CQSPI_NO_SUPPORT_WR_COMPLETION 1888 | CQSPI_SLOW_SRAM, 1889 }; 1890 1891 static const struct cqspi_driver_platdata versal_ospi = { 1892 .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 1893 .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA, 1894 .indirect_read_dma = cqspi_versal_indirect_read_dma, 1895 .get_dma_status = cqspi_get_versal_dma_status, 1896 }; 1897 1898 static const struct cqspi_driver_platdata jh7110_qspi = { 1899 .quirks = CQSPI_DISABLE_DAC_MODE, 1900 }; 1901 1902 static const struct cqspi_driver_platdata pensando_cdns_qspi = { 1903 .quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE, 1904 }; 1905 1906 static const struct of_device_id cqspi_dt_ids[] = { 1907 { 1908 .compatible = "cdns,qspi-nor", 1909 .data = &cdns_qspi, 1910 }, 1911 { 1912 .compatible = "ti,k2g-qspi", 1913 .data = &k2g_qspi, 1914 }, 1915 { 1916 .compatible = "ti,am654-ospi", 1917 .data = &am654_ospi, 1918 }, 1919 { 1920 .compatible = "intel,lgm-qspi", 1921 .data = &intel_lgm_qspi, 1922 }, 1923 { 1924 .compatible = "xlnx,versal-ospi-1.0", 1925 .data = &versal_ospi, 1926 }, 1927 { 1928 .compatible = "intel,socfpga-qspi", 1929 .data = &socfpga_qspi, 1930 }, 1931 { 1932 .compatible = "starfive,jh7110-qspi", 1933 .data = &jh7110_qspi, 1934 }, 1935 { 1936 .compatible = "amd,pensando-elba-qspi", 1937 .data = &pensando_cdns_qspi, 1938 }, 1939 { /* end of table */ } 1940 }; 1941 1942 MODULE_DEVICE_TABLE(of, cqspi_dt_ids); 1943 1944 static struct platform_driver cqspi_platform_driver = { 1945 .probe = cqspi_probe, 1946 .remove_new = cqspi_remove, 1947 .driver = { 1948 .name = CQSPI_NAME, 1949 .pm = &cqspi_dev_pm_ops, 1950 .of_match_table = cqspi_dt_ids, 1951 }, 1952 }; 1953 1954 module_platform_driver(cqspi_platform_driver); 1955 1956 MODULE_DESCRIPTION("Cadence QSPI Controller Driver"); 1957 MODULE_LICENSE("GPL v2"); 1958 MODULE_ALIAS("platform:" CQSPI_NAME); 1959 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>"); 1960 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>"); 1961 MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>"); 1962 MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>"); 1963 MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>"); 1964