1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // Driver for Cadence QSPI Controller
4 //
5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
8 
9 #include <linux/clk.h>
10 #include <linux/completion.h>
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/dmaengine.h>
14 #include <linux/err.h>
15 #include <linux/errno.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/iopoll.h>
19 #include <linux/jiffies.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/of_device.h>
23 #include <linux/of.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/reset.h>
27 #include <linux/sched.h>
28 #include <linux/spi/spi.h>
29 #include <linux/spi/spi-mem.h>
30 #include <linux/timer.h>
31 
32 #define CQSPI_NAME			"cadence-qspi"
33 #define CQSPI_MAX_CHIPSELECT		16
34 
35 /* Quirks */
36 #define CQSPI_NEEDS_WR_DELAY		BIT(0)
37 #define CQSPI_DISABLE_DAC_MODE		BIT(1)
38 
39 /* Capabilities */
40 #define CQSPI_SUPPORTS_OCTAL		BIT(0)
41 
42 struct cqspi_st;
43 
44 struct cqspi_flash_pdata {
45 	struct cqspi_st	*cqspi;
46 	u32		clk_rate;
47 	u32		read_delay;
48 	u32		tshsl_ns;
49 	u32		tsd2d_ns;
50 	u32		tchsh_ns;
51 	u32		tslch_ns;
52 	u8		inst_width;
53 	u8		addr_width;
54 	u8		data_width;
55 	u8		cs;
56 };
57 
58 struct cqspi_st {
59 	struct platform_device	*pdev;
60 
61 	struct clk		*clk;
62 	unsigned int		sclk;
63 
64 	void __iomem		*iobase;
65 	void __iomem		*ahb_base;
66 	resource_size_t		ahb_size;
67 	struct completion	transfer_complete;
68 
69 	struct dma_chan		*rx_chan;
70 	struct completion	rx_dma_complete;
71 	dma_addr_t		mmap_phys_base;
72 
73 	int			current_cs;
74 	unsigned long		master_ref_clk_hz;
75 	bool			is_decoded_cs;
76 	u32			fifo_depth;
77 	u32			fifo_width;
78 	bool			rclk_en;
79 	u32			trigger_address;
80 	u32			wr_delay;
81 	bool			use_direct_mode;
82 	struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
83 };
84 
85 struct cqspi_driver_platdata {
86 	u32 hwcaps_mask;
87 	u8 quirks;
88 };
89 
90 /* Operation timeout value */
91 #define CQSPI_TIMEOUT_MS			500
92 #define CQSPI_READ_TIMEOUT_MS			10
93 
94 /* Instruction type */
95 #define CQSPI_INST_TYPE_SINGLE			0
96 #define CQSPI_INST_TYPE_DUAL			1
97 #define CQSPI_INST_TYPE_QUAD			2
98 #define CQSPI_INST_TYPE_OCTAL			3
99 
100 #define CQSPI_DUMMY_CLKS_PER_BYTE		8
101 #define CQSPI_DUMMY_BYTES_MAX			4
102 #define CQSPI_DUMMY_CLKS_MAX			31
103 
104 #define CQSPI_STIG_DATA_LEN_MAX			8
105 
106 /* Register map */
107 #define CQSPI_REG_CONFIG			0x00
108 #define CQSPI_REG_CONFIG_ENABLE_MASK		BIT(0)
109 #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL	BIT(7)
110 #define CQSPI_REG_CONFIG_DECODE_MASK		BIT(9)
111 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB		10
112 #define CQSPI_REG_CONFIG_DMA_MASK		BIT(15)
113 #define CQSPI_REG_CONFIG_BAUD_LSB		19
114 #define CQSPI_REG_CONFIG_IDLE_LSB		31
115 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK	0xF
116 #define CQSPI_REG_CONFIG_BAUD_MASK		0xF
117 
118 #define CQSPI_REG_RD_INSTR			0x04
119 #define CQSPI_REG_RD_INSTR_OPCODE_LSB		0
120 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB	8
121 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB	12
122 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB	16
123 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB		20
124 #define CQSPI_REG_RD_INSTR_DUMMY_LSB		24
125 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK	0x3
126 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK	0x3
127 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK	0x3
128 #define CQSPI_REG_RD_INSTR_DUMMY_MASK		0x1F
129 
130 #define CQSPI_REG_WR_INSTR			0x08
131 #define CQSPI_REG_WR_INSTR_OPCODE_LSB		0
132 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB	12
133 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB	16
134 
135 #define CQSPI_REG_DELAY				0x0C
136 #define CQSPI_REG_DELAY_TSLCH_LSB		0
137 #define CQSPI_REG_DELAY_TCHSH_LSB		8
138 #define CQSPI_REG_DELAY_TSD2D_LSB		16
139 #define CQSPI_REG_DELAY_TSHSL_LSB		24
140 #define CQSPI_REG_DELAY_TSLCH_MASK		0xFF
141 #define CQSPI_REG_DELAY_TCHSH_MASK		0xFF
142 #define CQSPI_REG_DELAY_TSD2D_MASK		0xFF
143 #define CQSPI_REG_DELAY_TSHSL_MASK		0xFF
144 
145 #define CQSPI_REG_READCAPTURE			0x10
146 #define CQSPI_REG_READCAPTURE_BYPASS_LSB	0
147 #define CQSPI_REG_READCAPTURE_DELAY_LSB		1
148 #define CQSPI_REG_READCAPTURE_DELAY_MASK	0xF
149 
150 #define CQSPI_REG_SIZE				0x14
151 #define CQSPI_REG_SIZE_ADDRESS_LSB		0
152 #define CQSPI_REG_SIZE_PAGE_LSB			4
153 #define CQSPI_REG_SIZE_BLOCK_LSB		16
154 #define CQSPI_REG_SIZE_ADDRESS_MASK		0xF
155 #define CQSPI_REG_SIZE_PAGE_MASK		0xFFF
156 #define CQSPI_REG_SIZE_BLOCK_MASK		0x3F
157 
158 #define CQSPI_REG_SRAMPARTITION			0x18
159 #define CQSPI_REG_INDIRECTTRIGGER		0x1C
160 
161 #define CQSPI_REG_DMA				0x20
162 #define CQSPI_REG_DMA_SINGLE_LSB		0
163 #define CQSPI_REG_DMA_BURST_LSB			8
164 #define CQSPI_REG_DMA_SINGLE_MASK		0xFF
165 #define CQSPI_REG_DMA_BURST_MASK		0xFF
166 
167 #define CQSPI_REG_REMAP				0x24
168 #define CQSPI_REG_MODE_BIT			0x28
169 
170 #define CQSPI_REG_SDRAMLEVEL			0x2C
171 #define CQSPI_REG_SDRAMLEVEL_RD_LSB		0
172 #define CQSPI_REG_SDRAMLEVEL_WR_LSB		16
173 #define CQSPI_REG_SDRAMLEVEL_RD_MASK		0xFFFF
174 #define CQSPI_REG_SDRAMLEVEL_WR_MASK		0xFFFF
175 
176 #define CQSPI_REG_IRQSTATUS			0x40
177 #define CQSPI_REG_IRQMASK			0x44
178 
179 #define CQSPI_REG_INDIRECTRD			0x60
180 #define CQSPI_REG_INDIRECTRD_START_MASK		BIT(0)
181 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK	BIT(1)
182 #define CQSPI_REG_INDIRECTRD_DONE_MASK		BIT(5)
183 
184 #define CQSPI_REG_INDIRECTRDWATERMARK		0x64
185 #define CQSPI_REG_INDIRECTRDSTARTADDR		0x68
186 #define CQSPI_REG_INDIRECTRDBYTES		0x6C
187 
188 #define CQSPI_REG_CMDCTRL			0x90
189 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK		BIT(0)
190 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK	BIT(1)
191 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB		12
192 #define CQSPI_REG_CMDCTRL_WR_EN_LSB		15
193 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB		16
194 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB		19
195 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB		20
196 #define CQSPI_REG_CMDCTRL_RD_EN_LSB		23
197 #define CQSPI_REG_CMDCTRL_OPCODE_LSB		24
198 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK		0x7
199 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK	0x3
200 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK		0x7
201 
202 #define CQSPI_REG_INDIRECTWR			0x70
203 #define CQSPI_REG_INDIRECTWR_START_MASK		BIT(0)
204 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK	BIT(1)
205 #define CQSPI_REG_INDIRECTWR_DONE_MASK		BIT(5)
206 
207 #define CQSPI_REG_INDIRECTWRWATERMARK		0x74
208 #define CQSPI_REG_INDIRECTWRSTARTADDR		0x78
209 #define CQSPI_REG_INDIRECTWRBYTES		0x7C
210 
211 #define CQSPI_REG_CMDADDRESS			0x94
212 #define CQSPI_REG_CMDREADDATALOWER		0xA0
213 #define CQSPI_REG_CMDREADDATAUPPER		0xA4
214 #define CQSPI_REG_CMDWRITEDATALOWER		0xA8
215 #define CQSPI_REG_CMDWRITEDATAUPPER		0xAC
216 
217 /* Interrupt status bits */
218 #define CQSPI_REG_IRQ_MODE_ERR			BIT(0)
219 #define CQSPI_REG_IRQ_UNDERFLOW			BIT(1)
220 #define CQSPI_REG_IRQ_IND_COMP			BIT(2)
221 #define CQSPI_REG_IRQ_IND_RD_REJECT		BIT(3)
222 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR		BIT(4)
223 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR		BIT(5)
224 #define CQSPI_REG_IRQ_WATERMARK			BIT(6)
225 #define CQSPI_REG_IRQ_IND_SRAM_FULL		BIT(12)
226 
227 #define CQSPI_IRQ_MASK_RD		(CQSPI_REG_IRQ_WATERMARK	| \
228 					 CQSPI_REG_IRQ_IND_SRAM_FULL	| \
229 					 CQSPI_REG_IRQ_IND_COMP)
230 
231 #define CQSPI_IRQ_MASK_WR		(CQSPI_REG_IRQ_IND_COMP		| \
232 					 CQSPI_REG_IRQ_WATERMARK	| \
233 					 CQSPI_REG_IRQ_UNDERFLOW)
234 
235 #define CQSPI_IRQ_STATUS_MASK		0x1FFFF
236 
237 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr)
238 {
239 	u32 val;
240 
241 	return readl_relaxed_poll_timeout(reg, val,
242 					  (((clr ? ~val : val) & mask) == mask),
243 					  10, CQSPI_TIMEOUT_MS * 1000);
244 }
245 
246 static bool cqspi_is_idle(struct cqspi_st *cqspi)
247 {
248 	u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
249 
250 	return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB);
251 }
252 
253 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
254 {
255 	u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
256 
257 	reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
258 	return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
259 }
260 
261 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
262 {
263 	struct cqspi_st *cqspi = dev;
264 	unsigned int irq_status;
265 
266 	/* Read interrupt status */
267 	irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
268 
269 	/* Clear interrupt */
270 	writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
271 
272 	irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
273 
274 	if (irq_status)
275 		complete(&cqspi->transfer_complete);
276 
277 	return IRQ_HANDLED;
278 }
279 
280 static unsigned int cqspi_calc_rdreg(struct cqspi_flash_pdata *f_pdata)
281 {
282 	u32 rdreg = 0;
283 
284 	rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
285 	rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
286 	rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
287 
288 	return rdreg;
289 }
290 
291 static int cqspi_wait_idle(struct cqspi_st *cqspi)
292 {
293 	const unsigned int poll_idle_retry = 3;
294 	unsigned int count = 0;
295 	unsigned long timeout;
296 
297 	timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
298 	while (1) {
299 		/*
300 		 * Read few times in succession to ensure the controller
301 		 * is indeed idle, that is, the bit does not transition
302 		 * low again.
303 		 */
304 		if (cqspi_is_idle(cqspi))
305 			count++;
306 		else
307 			count = 0;
308 
309 		if (count >= poll_idle_retry)
310 			return 0;
311 
312 		if (time_after(jiffies, timeout)) {
313 			/* Timeout, in busy mode. */
314 			dev_err(&cqspi->pdev->dev,
315 				"QSPI is still busy after %dms timeout.\n",
316 				CQSPI_TIMEOUT_MS);
317 			return -ETIMEDOUT;
318 		}
319 
320 		cpu_relax();
321 	}
322 }
323 
324 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
325 {
326 	void __iomem *reg_base = cqspi->iobase;
327 	int ret;
328 
329 	/* Write the CMDCTRL without start execution. */
330 	writel(reg, reg_base + CQSPI_REG_CMDCTRL);
331 	/* Start execute */
332 	reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
333 	writel(reg, reg_base + CQSPI_REG_CMDCTRL);
334 
335 	/* Polling for completion. */
336 	ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
337 				 CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
338 	if (ret) {
339 		dev_err(&cqspi->pdev->dev,
340 			"Flash command execution timed out.\n");
341 		return ret;
342 	}
343 
344 	/* Polling QSPI idle status. */
345 	return cqspi_wait_idle(cqspi);
346 }
347 
348 static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata,
349 			      const struct spi_mem_op *op)
350 {
351 	struct cqspi_st *cqspi = f_pdata->cqspi;
352 	void __iomem *reg_base = cqspi->iobase;
353 	u8 *rxbuf = op->data.buf.in;
354 	u8 opcode = op->cmd.opcode;
355 	size_t n_rx = op->data.nbytes;
356 	unsigned int rdreg;
357 	unsigned int reg;
358 	size_t read_len;
359 	int status;
360 
361 	if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
362 		dev_err(&cqspi->pdev->dev,
363 			"Invalid input argument, len %zu rxbuf 0x%p\n",
364 			n_rx, rxbuf);
365 		return -EINVAL;
366 	}
367 
368 	reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
369 
370 	rdreg = cqspi_calc_rdreg(f_pdata);
371 	writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
372 
373 	reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
374 
375 	/* 0 means 1 byte. */
376 	reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
377 		<< CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
378 	status = cqspi_exec_flash_cmd(cqspi, reg);
379 	if (status)
380 		return status;
381 
382 	reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
383 
384 	/* Put the read value into rx_buf */
385 	read_len = (n_rx > 4) ? 4 : n_rx;
386 	memcpy(rxbuf, &reg, read_len);
387 	rxbuf += read_len;
388 
389 	if (n_rx > 4) {
390 		reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
391 
392 		read_len = n_rx - read_len;
393 		memcpy(rxbuf, &reg, read_len);
394 	}
395 
396 	return 0;
397 }
398 
399 static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata,
400 			       const struct spi_mem_op *op)
401 {
402 	struct cqspi_st *cqspi = f_pdata->cqspi;
403 	void __iomem *reg_base = cqspi->iobase;
404 	const u8 opcode = op->cmd.opcode;
405 	const u8 *txbuf = op->data.buf.out;
406 	size_t n_tx = op->data.nbytes;
407 	unsigned int reg;
408 	unsigned int data;
409 	size_t write_len;
410 
411 	if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) {
412 		dev_err(&cqspi->pdev->dev,
413 			"Invalid input argument, cmdlen %zu txbuf 0x%p\n",
414 			n_tx, txbuf);
415 		return -EINVAL;
416 	}
417 
418 	reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
419 
420 	if (op->addr.nbytes) {
421 		reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
422 		reg |= ((op->addr.nbytes - 1) &
423 			CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
424 			<< CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
425 
426 		writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);
427 	}
428 
429 	if (n_tx) {
430 		reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
431 		reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
432 			<< CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
433 		data = 0;
434 		write_len = (n_tx > 4) ? 4 : n_tx;
435 		memcpy(&data, txbuf, write_len);
436 		txbuf += write_len;
437 		writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
438 
439 		if (n_tx > 4) {
440 			data = 0;
441 			write_len = n_tx - 4;
442 			memcpy(&data, txbuf, write_len);
443 			writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);
444 		}
445 	}
446 
447 	return cqspi_exec_flash_cmd(cqspi, reg);
448 }
449 
450 static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata,
451 			    const struct spi_mem_op *op)
452 {
453 	struct cqspi_st *cqspi = f_pdata->cqspi;
454 	void __iomem *reg_base = cqspi->iobase;
455 	unsigned int dummy_clk = 0;
456 	unsigned int reg;
457 
458 	reg = op->cmd.opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
459 	reg |= cqspi_calc_rdreg(f_pdata);
460 
461 	/* Setup dummy clock cycles */
462 	dummy_clk = op->dummy.nbytes * 8;
463 	if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
464 		dummy_clk = CQSPI_DUMMY_CLKS_MAX;
465 
466 	if (dummy_clk)
467 		reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
468 		       << CQSPI_REG_RD_INSTR_DUMMY_LSB;
469 
470 	writel(reg, reg_base + CQSPI_REG_RD_INSTR);
471 
472 	/* Set address width */
473 	reg = readl(reg_base + CQSPI_REG_SIZE);
474 	reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
475 	reg |= (op->addr.nbytes - 1);
476 	writel(reg, reg_base + CQSPI_REG_SIZE);
477 	return 0;
478 }
479 
480 static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
481 				       u8 *rxbuf, loff_t from_addr,
482 				       const size_t n_rx)
483 {
484 	struct cqspi_st *cqspi = f_pdata->cqspi;
485 	struct device *dev = &cqspi->pdev->dev;
486 	void __iomem *reg_base = cqspi->iobase;
487 	void __iomem *ahb_base = cqspi->ahb_base;
488 	unsigned int remaining = n_rx;
489 	unsigned int mod_bytes = n_rx % 4;
490 	unsigned int bytes_to_read = 0;
491 	u8 *rxbuf_end = rxbuf + n_rx;
492 	int ret = 0;
493 
494 	writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
495 	writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
496 
497 	/* Clear all interrupts. */
498 	writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
499 
500 	writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
501 
502 	reinit_completion(&cqspi->transfer_complete);
503 	writel(CQSPI_REG_INDIRECTRD_START_MASK,
504 	       reg_base + CQSPI_REG_INDIRECTRD);
505 
506 	while (remaining > 0) {
507 		if (!wait_for_completion_timeout(&cqspi->transfer_complete,
508 						 msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS)))
509 			ret = -ETIMEDOUT;
510 
511 		bytes_to_read = cqspi_get_rd_sram_level(cqspi);
512 
513 		if (ret && bytes_to_read == 0) {
514 			dev_err(dev, "Indirect read timeout, no bytes\n");
515 			goto failrd;
516 		}
517 
518 		while (bytes_to_read != 0) {
519 			unsigned int word_remain = round_down(remaining, 4);
520 
521 			bytes_to_read *= cqspi->fifo_width;
522 			bytes_to_read = bytes_to_read > remaining ?
523 					remaining : bytes_to_read;
524 			bytes_to_read = round_down(bytes_to_read, 4);
525 			/* Read 4 byte word chunks then single bytes */
526 			if (bytes_to_read) {
527 				ioread32_rep(ahb_base, rxbuf,
528 					     (bytes_to_read / 4));
529 			} else if (!word_remain && mod_bytes) {
530 				unsigned int temp = ioread32(ahb_base);
531 
532 				bytes_to_read = mod_bytes;
533 				memcpy(rxbuf, &temp, min((unsigned int)
534 							 (rxbuf_end - rxbuf),
535 							 bytes_to_read));
536 			}
537 			rxbuf += bytes_to_read;
538 			remaining -= bytes_to_read;
539 			bytes_to_read = cqspi_get_rd_sram_level(cqspi);
540 		}
541 
542 		if (remaining > 0)
543 			reinit_completion(&cqspi->transfer_complete);
544 	}
545 
546 	/* Check indirect done status */
547 	ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
548 				 CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
549 	if (ret) {
550 		dev_err(dev, "Indirect read completion error (%i)\n", ret);
551 		goto failrd;
552 	}
553 
554 	/* Disable interrupt */
555 	writel(0, reg_base + CQSPI_REG_IRQMASK);
556 
557 	/* Clear indirect completion status */
558 	writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
559 
560 	return 0;
561 
562 failrd:
563 	/* Disable interrupt */
564 	writel(0, reg_base + CQSPI_REG_IRQMASK);
565 
566 	/* Cancel the indirect read */
567 	writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
568 	       reg_base + CQSPI_REG_INDIRECTRD);
569 	return ret;
570 }
571 
572 static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata,
573 			     const struct spi_mem_op *op)
574 {
575 	unsigned int reg;
576 	struct cqspi_st *cqspi = f_pdata->cqspi;
577 	void __iomem *reg_base = cqspi->iobase;
578 
579 	/* Set opcode. */
580 	reg = op->cmd.opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
581 	writel(reg, reg_base + CQSPI_REG_WR_INSTR);
582 	reg = cqspi_calc_rdreg(f_pdata);
583 	writel(reg, reg_base + CQSPI_REG_RD_INSTR);
584 
585 	reg = readl(reg_base + CQSPI_REG_SIZE);
586 	reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
587 	reg |= (op->addr.nbytes - 1);
588 	writel(reg, reg_base + CQSPI_REG_SIZE);
589 	return 0;
590 }
591 
592 static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata,
593 					loff_t to_addr, const u8 *txbuf,
594 					const size_t n_tx)
595 {
596 	struct cqspi_st *cqspi = f_pdata->cqspi;
597 	struct device *dev = &cqspi->pdev->dev;
598 	void __iomem *reg_base = cqspi->iobase;
599 	unsigned int remaining = n_tx;
600 	unsigned int write_bytes;
601 	int ret;
602 
603 	writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
604 	writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
605 
606 	/* Clear all interrupts. */
607 	writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
608 
609 	writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
610 
611 	reinit_completion(&cqspi->transfer_complete);
612 	writel(CQSPI_REG_INDIRECTWR_START_MASK,
613 	       reg_base + CQSPI_REG_INDIRECTWR);
614 	/*
615 	 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
616 	 * Controller programming sequence, couple of cycles of
617 	 * QSPI_REF_CLK delay is required for the above bit to
618 	 * be internally synchronized by the QSPI module. Provide 5
619 	 * cycles of delay.
620 	 */
621 	if (cqspi->wr_delay)
622 		ndelay(cqspi->wr_delay);
623 
624 	while (remaining > 0) {
625 		size_t write_words, mod_bytes;
626 
627 		write_bytes = remaining;
628 		write_words = write_bytes / 4;
629 		mod_bytes = write_bytes % 4;
630 		/* Write 4 bytes at a time then single bytes. */
631 		if (write_words) {
632 			iowrite32_rep(cqspi->ahb_base, txbuf, write_words);
633 			txbuf += (write_words * 4);
634 		}
635 		if (mod_bytes) {
636 			unsigned int temp = 0xFFFFFFFF;
637 
638 			memcpy(&temp, txbuf, mod_bytes);
639 			iowrite32(temp, cqspi->ahb_base);
640 			txbuf += mod_bytes;
641 		}
642 
643 		if (!wait_for_completion_timeout(&cqspi->transfer_complete,
644 						 msecs_to_jiffies(CQSPI_TIMEOUT_MS))) {
645 			dev_err(dev, "Indirect write timeout\n");
646 			ret = -ETIMEDOUT;
647 			goto failwr;
648 		}
649 
650 		remaining -= write_bytes;
651 
652 		if (remaining > 0)
653 			reinit_completion(&cqspi->transfer_complete);
654 	}
655 
656 	/* Check indirect done status */
657 	ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
658 				 CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
659 	if (ret) {
660 		dev_err(dev, "Indirect write completion error (%i)\n", ret);
661 		goto failwr;
662 	}
663 
664 	/* Disable interrupt. */
665 	writel(0, reg_base + CQSPI_REG_IRQMASK);
666 
667 	/* Clear indirect completion status */
668 	writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
669 
670 	cqspi_wait_idle(cqspi);
671 
672 	return 0;
673 
674 failwr:
675 	/* Disable interrupt. */
676 	writel(0, reg_base + CQSPI_REG_IRQMASK);
677 
678 	/* Cancel the indirect write */
679 	writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
680 	       reg_base + CQSPI_REG_INDIRECTWR);
681 	return ret;
682 }
683 
684 static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata)
685 {
686 	struct cqspi_st *cqspi = f_pdata->cqspi;
687 	void __iomem *reg_base = cqspi->iobase;
688 	unsigned int chip_select = f_pdata->cs;
689 	unsigned int reg;
690 
691 	reg = readl(reg_base + CQSPI_REG_CONFIG);
692 	if (cqspi->is_decoded_cs) {
693 		reg |= CQSPI_REG_CONFIG_DECODE_MASK;
694 	} else {
695 		reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
696 
697 		/* Convert CS if without decoder.
698 		 * CS0 to 4b'1110
699 		 * CS1 to 4b'1101
700 		 * CS2 to 4b'1011
701 		 * CS3 to 4b'0111
702 		 */
703 		chip_select = 0xF & ~(1 << chip_select);
704 	}
705 
706 	reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
707 		 << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
708 	reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
709 	    << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
710 	writel(reg, reg_base + CQSPI_REG_CONFIG);
711 }
712 
713 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
714 					   const unsigned int ns_val)
715 {
716 	unsigned int ticks;
717 
718 	ticks = ref_clk_hz / 1000;	/* kHz */
719 	ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
720 
721 	return ticks;
722 }
723 
724 static void cqspi_delay(struct cqspi_flash_pdata *f_pdata)
725 {
726 	struct cqspi_st *cqspi = f_pdata->cqspi;
727 	void __iomem *iobase = cqspi->iobase;
728 	const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
729 	unsigned int tshsl, tchsh, tslch, tsd2d;
730 	unsigned int reg;
731 	unsigned int tsclk;
732 
733 	/* calculate the number of ref ticks for one sclk tick */
734 	tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
735 
736 	tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
737 	/* this particular value must be at least one sclk */
738 	if (tshsl < tsclk)
739 		tshsl = tsclk;
740 
741 	tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
742 	tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
743 	tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
744 
745 	reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
746 	       << CQSPI_REG_DELAY_TSHSL_LSB;
747 	reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
748 		<< CQSPI_REG_DELAY_TCHSH_LSB;
749 	reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
750 		<< CQSPI_REG_DELAY_TSLCH_LSB;
751 	reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
752 		<< CQSPI_REG_DELAY_TSD2D_LSB;
753 	writel(reg, iobase + CQSPI_REG_DELAY);
754 }
755 
756 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
757 {
758 	const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
759 	void __iomem *reg_base = cqspi->iobase;
760 	u32 reg, div;
761 
762 	/* Recalculate the baudrate divisor based on QSPI specification. */
763 	div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
764 
765 	reg = readl(reg_base + CQSPI_REG_CONFIG);
766 	reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
767 	reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
768 	writel(reg, reg_base + CQSPI_REG_CONFIG);
769 }
770 
771 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
772 				   const bool bypass,
773 				   const unsigned int delay)
774 {
775 	void __iomem *reg_base = cqspi->iobase;
776 	unsigned int reg;
777 
778 	reg = readl(reg_base + CQSPI_REG_READCAPTURE);
779 
780 	if (bypass)
781 		reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
782 	else
783 		reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
784 
785 	reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
786 		 << CQSPI_REG_READCAPTURE_DELAY_LSB);
787 
788 	reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
789 		<< CQSPI_REG_READCAPTURE_DELAY_LSB;
790 
791 	writel(reg, reg_base + CQSPI_REG_READCAPTURE);
792 }
793 
794 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
795 {
796 	void __iomem *reg_base = cqspi->iobase;
797 	unsigned int reg;
798 
799 	reg = readl(reg_base + CQSPI_REG_CONFIG);
800 
801 	if (enable)
802 		reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
803 	else
804 		reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
805 
806 	writel(reg, reg_base + CQSPI_REG_CONFIG);
807 }
808 
809 static void cqspi_configure(struct cqspi_flash_pdata *f_pdata,
810 			    unsigned long sclk)
811 {
812 	struct cqspi_st *cqspi = f_pdata->cqspi;
813 	int switch_cs = (cqspi->current_cs != f_pdata->cs);
814 	int switch_ck = (cqspi->sclk != sclk);
815 
816 	if (switch_cs || switch_ck)
817 		cqspi_controller_enable(cqspi, 0);
818 
819 	/* Switch chip select. */
820 	if (switch_cs) {
821 		cqspi->current_cs = f_pdata->cs;
822 		cqspi_chipselect(f_pdata);
823 	}
824 
825 	/* Setup baudrate divisor and delays */
826 	if (switch_ck) {
827 		cqspi->sclk = sclk;
828 		cqspi_config_baudrate_div(cqspi);
829 		cqspi_delay(f_pdata);
830 		cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
831 				       f_pdata->read_delay);
832 	}
833 
834 	if (switch_cs || switch_ck)
835 		cqspi_controller_enable(cqspi, 1);
836 }
837 
838 static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata,
839 			      const struct spi_mem_op *op)
840 {
841 	f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE;
842 	f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE;
843 	f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
844 
845 	if (op->data.dir == SPI_MEM_DATA_IN) {
846 		switch (op->data.buswidth) {
847 		case 1:
848 			f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
849 			break;
850 		case 2:
851 			f_pdata->data_width = CQSPI_INST_TYPE_DUAL;
852 			break;
853 		case 4:
854 			f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
855 			break;
856 		case 8:
857 			f_pdata->data_width = CQSPI_INST_TYPE_OCTAL;
858 			break;
859 		default:
860 			return -EINVAL;
861 		}
862 	}
863 
864 	return 0;
865 }
866 
867 static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata,
868 			   const struct spi_mem_op *op)
869 {
870 	struct cqspi_st *cqspi = f_pdata->cqspi;
871 	loff_t to = op->addr.val;
872 	size_t len = op->data.nbytes;
873 	const u_char *buf = op->data.buf.out;
874 	int ret;
875 
876 	ret = cqspi_set_protocol(f_pdata, op);
877 	if (ret)
878 		return ret;
879 
880 	ret = cqspi_write_setup(f_pdata, op);
881 	if (ret)
882 		return ret;
883 
884 	if (cqspi->use_direct_mode && ((to + len) <= cqspi->ahb_size)) {
885 		memcpy_toio(cqspi->ahb_base + to, buf, len);
886 		return cqspi_wait_idle(cqspi);
887 	}
888 
889 	return cqspi_indirect_write_execute(f_pdata, to, buf, len);
890 }
891 
892 static void cqspi_rx_dma_callback(void *param)
893 {
894 	struct cqspi_st *cqspi = param;
895 
896 	complete(&cqspi->rx_dma_complete);
897 }
898 
899 static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata,
900 				     u_char *buf, loff_t from, size_t len)
901 {
902 	struct cqspi_st *cqspi = f_pdata->cqspi;
903 	struct device *dev = &cqspi->pdev->dev;
904 	enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
905 	dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from;
906 	int ret = 0;
907 	struct dma_async_tx_descriptor *tx;
908 	dma_cookie_t cookie;
909 	dma_addr_t dma_dst;
910 	struct device *ddev;
911 
912 	if (!cqspi->rx_chan || !virt_addr_valid(buf)) {
913 		memcpy_fromio(buf, cqspi->ahb_base + from, len);
914 		return 0;
915 	}
916 
917 	ddev = cqspi->rx_chan->device->dev;
918 	dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE);
919 	if (dma_mapping_error(ddev, dma_dst)) {
920 		dev_err(dev, "dma mapping failed\n");
921 		return -ENOMEM;
922 	}
923 	tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src,
924 				       len, flags);
925 	if (!tx) {
926 		dev_err(dev, "device_prep_dma_memcpy error\n");
927 		ret = -EIO;
928 		goto err_unmap;
929 	}
930 
931 	tx->callback = cqspi_rx_dma_callback;
932 	tx->callback_param = cqspi;
933 	cookie = tx->tx_submit(tx);
934 	reinit_completion(&cqspi->rx_dma_complete);
935 
936 	ret = dma_submit_error(cookie);
937 	if (ret) {
938 		dev_err(dev, "dma_submit_error %d\n", cookie);
939 		ret = -EIO;
940 		goto err_unmap;
941 	}
942 
943 	dma_async_issue_pending(cqspi->rx_chan);
944 	if (!wait_for_completion_timeout(&cqspi->rx_dma_complete,
945 					 msecs_to_jiffies(len))) {
946 		dmaengine_terminate_sync(cqspi->rx_chan);
947 		dev_err(dev, "DMA wait_for_completion_timeout\n");
948 		ret = -ETIMEDOUT;
949 		goto err_unmap;
950 	}
951 
952 err_unmap:
953 	dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE);
954 
955 	return ret;
956 }
957 
958 static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata,
959 			  const struct spi_mem_op *op)
960 {
961 	struct cqspi_st *cqspi = f_pdata->cqspi;
962 	loff_t from = op->addr.val;
963 	size_t len = op->data.nbytes;
964 	u_char *buf = op->data.buf.in;
965 	int ret;
966 
967 	ret = cqspi_set_protocol(f_pdata, op);
968 	if (ret)
969 		return ret;
970 
971 	ret = cqspi_read_setup(f_pdata, op);
972 	if (ret)
973 		return ret;
974 
975 	if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size))
976 		return cqspi_direct_read_execute(f_pdata, buf, from, len);
977 
978 	return cqspi_indirect_read_execute(f_pdata, buf, from, len);
979 }
980 
981 static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op)
982 {
983 	struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master);
984 	struct cqspi_flash_pdata *f_pdata;
985 
986 	f_pdata = &cqspi->f_pdata[mem->spi->chip_select];
987 	cqspi_configure(f_pdata, mem->spi->max_speed_hz);
988 
989 	if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
990 		if (!op->addr.nbytes)
991 			return cqspi_command_read(f_pdata, op);
992 
993 		return cqspi_read(f_pdata, op);
994 	}
995 
996 	if (!op->addr.nbytes || !op->data.buf.out)
997 		return cqspi_command_write(f_pdata, op);
998 
999 	return cqspi_write(f_pdata, op);
1000 }
1001 
1002 static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
1003 {
1004 	int ret;
1005 
1006 	ret = cqspi_mem_process(mem, op);
1007 	if (ret)
1008 		dev_err(&mem->spi->dev, "operation failed with %d\n", ret);
1009 
1010 	return ret;
1011 }
1012 
1013 static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
1014 				    struct cqspi_flash_pdata *f_pdata,
1015 				    struct device_node *np)
1016 {
1017 	if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
1018 		dev_err(&pdev->dev, "couldn't determine read-delay\n");
1019 		return -ENXIO;
1020 	}
1021 
1022 	if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
1023 		dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
1024 		return -ENXIO;
1025 	}
1026 
1027 	if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
1028 		dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
1029 		return -ENXIO;
1030 	}
1031 
1032 	if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
1033 		dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
1034 		return -ENXIO;
1035 	}
1036 
1037 	if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
1038 		dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
1039 		return -ENXIO;
1040 	}
1041 
1042 	if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
1043 		dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
1044 		return -ENXIO;
1045 	}
1046 
1047 	return 0;
1048 }
1049 
1050 static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
1051 {
1052 	struct device *dev = &cqspi->pdev->dev;
1053 	struct device_node *np = dev->of_node;
1054 
1055 	cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1056 
1057 	if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1058 		dev_err(dev, "couldn't determine fifo-depth\n");
1059 		return -ENXIO;
1060 	}
1061 
1062 	if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1063 		dev_err(dev, "couldn't determine fifo-width\n");
1064 		return -ENXIO;
1065 	}
1066 
1067 	if (of_property_read_u32(np, "cdns,trigger-address",
1068 				 &cqspi->trigger_address)) {
1069 		dev_err(dev, "couldn't determine trigger-address\n");
1070 		return -ENXIO;
1071 	}
1072 
1073 	cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
1074 
1075 	return 0;
1076 }
1077 
1078 static void cqspi_controller_init(struct cqspi_st *cqspi)
1079 {
1080 	u32 reg;
1081 
1082 	cqspi_controller_enable(cqspi, 0);
1083 
1084 	/* Configure the remap address register, no remap */
1085 	writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1086 
1087 	/* Disable all interrupts. */
1088 	writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1089 
1090 	/* Configure the SRAM split to 1:1 . */
1091 	writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1092 
1093 	/* Load indirect trigger address. */
1094 	writel(cqspi->trigger_address,
1095 	       cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1096 
1097 	/* Program read watermark -- 1/2 of the FIFO. */
1098 	writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1099 	       cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1100 	/* Program write watermark -- 1/8 of the FIFO. */
1101 	writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1102 	       cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1103 
1104 	/* Enable Direct Access Controller */
1105 	reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1106 	reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
1107 	writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1108 
1109 	cqspi_controller_enable(cqspi, 1);
1110 }
1111 
1112 static int cqspi_request_mmap_dma(struct cqspi_st *cqspi)
1113 {
1114 	dma_cap_mask_t mask;
1115 
1116 	dma_cap_zero(mask);
1117 	dma_cap_set(DMA_MEMCPY, mask);
1118 
1119 	cqspi->rx_chan = dma_request_chan_by_mask(&mask);
1120 	if (IS_ERR(cqspi->rx_chan)) {
1121 		int ret = PTR_ERR(cqspi->rx_chan);
1122 		cqspi->rx_chan = NULL;
1123 		return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n");
1124 	}
1125 	init_completion(&cqspi->rx_dma_complete);
1126 
1127 	return 0;
1128 }
1129 
1130 static const char *cqspi_get_name(struct spi_mem *mem)
1131 {
1132 	struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master);
1133 	struct device *dev = &cqspi->pdev->dev;
1134 
1135 	return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select);
1136 }
1137 
1138 static const struct spi_controller_mem_ops cqspi_mem_ops = {
1139 	.exec_op = cqspi_exec_mem_op,
1140 	.get_name = cqspi_get_name,
1141 };
1142 
1143 static int cqspi_setup_flash(struct cqspi_st *cqspi)
1144 {
1145 	struct platform_device *pdev = cqspi->pdev;
1146 	struct device *dev = &pdev->dev;
1147 	struct device_node *np = dev->of_node;
1148 	struct cqspi_flash_pdata *f_pdata;
1149 	unsigned int cs;
1150 	int ret;
1151 
1152 	/* Get flash device data */
1153 	for_each_available_child_of_node(dev->of_node, np) {
1154 		ret = of_property_read_u32(np, "reg", &cs);
1155 		if (ret) {
1156 			dev_err(dev, "Couldn't determine chip select.\n");
1157 			return ret;
1158 		}
1159 
1160 		if (cs >= CQSPI_MAX_CHIPSELECT) {
1161 			dev_err(dev, "Chip select %d out of range.\n", cs);
1162 			return -EINVAL;
1163 		}
1164 
1165 		f_pdata = &cqspi->f_pdata[cs];
1166 		f_pdata->cqspi = cqspi;
1167 		f_pdata->cs = cs;
1168 
1169 		ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
1170 		if (ret)
1171 			return ret;
1172 	}
1173 
1174 	return 0;
1175 }
1176 
1177 static int cqspi_probe(struct platform_device *pdev)
1178 {
1179 	const struct cqspi_driver_platdata *ddata;
1180 	struct reset_control *rstc, *rstc_ocp;
1181 	struct device *dev = &pdev->dev;
1182 	struct spi_master *master;
1183 	struct resource *res_ahb;
1184 	struct cqspi_st *cqspi;
1185 	struct resource *res;
1186 	int ret;
1187 	int irq;
1188 
1189 	master = spi_alloc_master(&pdev->dev, sizeof(*cqspi));
1190 	if (!master) {
1191 		dev_err(&pdev->dev, "spi_alloc_master failed\n");
1192 		return -ENOMEM;
1193 	}
1194 	master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL;
1195 	master->mem_ops = &cqspi_mem_ops;
1196 	master->dev.of_node = pdev->dev.of_node;
1197 
1198 	cqspi = spi_master_get_devdata(master);
1199 
1200 	cqspi->pdev = pdev;
1201 
1202 	/* Obtain configuration from OF. */
1203 	ret = cqspi_of_get_pdata(cqspi);
1204 	if (ret) {
1205 		dev_err(dev, "Cannot get mandatory OF data.\n");
1206 		ret = -ENODEV;
1207 		goto probe_master_put;
1208 	}
1209 
1210 	/* Obtain QSPI clock. */
1211 	cqspi->clk = devm_clk_get(dev, NULL);
1212 	if (IS_ERR(cqspi->clk)) {
1213 		dev_err(dev, "Cannot claim QSPI clock.\n");
1214 		ret = PTR_ERR(cqspi->clk);
1215 		goto probe_master_put;
1216 	}
1217 
1218 	/* Obtain and remap controller address. */
1219 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1220 	cqspi->iobase = devm_ioremap_resource(dev, res);
1221 	if (IS_ERR(cqspi->iobase)) {
1222 		dev_err(dev, "Cannot remap controller address.\n");
1223 		ret = PTR_ERR(cqspi->iobase);
1224 		goto probe_master_put;
1225 	}
1226 
1227 	/* Obtain and remap AHB address. */
1228 	res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1229 	cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb);
1230 	if (IS_ERR(cqspi->ahb_base)) {
1231 		dev_err(dev, "Cannot remap AHB address.\n");
1232 		ret = PTR_ERR(cqspi->ahb_base);
1233 		goto probe_master_put;
1234 	}
1235 	cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
1236 	cqspi->ahb_size = resource_size(res_ahb);
1237 
1238 	init_completion(&cqspi->transfer_complete);
1239 
1240 	/* Obtain IRQ line. */
1241 	irq = platform_get_irq(pdev, 0);
1242 	if (irq < 0) {
1243 		ret = -ENXIO;
1244 		goto probe_master_put;
1245 	}
1246 
1247 	pm_runtime_enable(dev);
1248 	ret = pm_runtime_get_sync(dev);
1249 	if (ret < 0) {
1250 		pm_runtime_put_noidle(dev);
1251 		goto probe_master_put;
1252 	}
1253 
1254 	ret = clk_prepare_enable(cqspi->clk);
1255 	if (ret) {
1256 		dev_err(dev, "Cannot enable QSPI clock.\n");
1257 		goto probe_clk_failed;
1258 	}
1259 
1260 	/* Obtain QSPI reset control */
1261 	rstc = devm_reset_control_get_optional_exclusive(dev, "qspi");
1262 	if (IS_ERR(rstc)) {
1263 		dev_err(dev, "Cannot get QSPI reset.\n");
1264 		goto probe_reset_failed;
1265 	}
1266 
1267 	rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp");
1268 	if (IS_ERR(rstc_ocp)) {
1269 		dev_err(dev, "Cannot get QSPI OCP reset.\n");
1270 		goto probe_reset_failed;
1271 	}
1272 
1273 	reset_control_assert(rstc);
1274 	reset_control_deassert(rstc);
1275 
1276 	reset_control_assert(rstc_ocp);
1277 	reset_control_deassert(rstc_ocp);
1278 
1279 	cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1280 	ddata  = of_device_get_match_data(dev);
1281 	if (ddata) {
1282 		if (ddata->quirks & CQSPI_NEEDS_WR_DELAY)
1283 			cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
1284 						cqspi->master_ref_clk_hz);
1285 		if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL)
1286 			master->mode_bits |= SPI_RX_OCTAL;
1287 		if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE))
1288 			cqspi->use_direct_mode = true;
1289 	}
1290 
1291 	ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
1292 			       pdev->name, cqspi);
1293 	if (ret) {
1294 		dev_err(dev, "Cannot request IRQ.\n");
1295 		goto probe_reset_failed;
1296 	}
1297 
1298 	cqspi_wait_idle(cqspi);
1299 	cqspi_controller_init(cqspi);
1300 	cqspi->current_cs = -1;
1301 	cqspi->sclk = 0;
1302 
1303 	ret = cqspi_setup_flash(cqspi);
1304 	if (ret) {
1305 		dev_err(dev, "failed to setup flash parameters %d\n", ret);
1306 		goto probe_setup_failed;
1307 	}
1308 
1309 	if (cqspi->use_direct_mode) {
1310 		ret = cqspi_request_mmap_dma(cqspi);
1311 		if (ret == -EPROBE_DEFER)
1312 			goto probe_setup_failed;
1313 	}
1314 
1315 	ret = devm_spi_register_master(dev, master);
1316 	if (ret) {
1317 		dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret);
1318 		goto probe_setup_failed;
1319 	}
1320 
1321 	return 0;
1322 probe_setup_failed:
1323 	cqspi_controller_enable(cqspi, 0);
1324 probe_reset_failed:
1325 	clk_disable_unprepare(cqspi->clk);
1326 probe_clk_failed:
1327 	pm_runtime_put_sync(dev);
1328 	pm_runtime_disable(dev);
1329 probe_master_put:
1330 	spi_master_put(master);
1331 	return ret;
1332 }
1333 
1334 static int cqspi_remove(struct platform_device *pdev)
1335 {
1336 	struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1337 
1338 	cqspi_controller_enable(cqspi, 0);
1339 
1340 	if (cqspi->rx_chan)
1341 		dma_release_channel(cqspi->rx_chan);
1342 
1343 	clk_disable_unprepare(cqspi->clk);
1344 
1345 	pm_runtime_put_sync(&pdev->dev);
1346 	pm_runtime_disable(&pdev->dev);
1347 
1348 	return 0;
1349 }
1350 
1351 #ifdef CONFIG_PM_SLEEP
1352 static int cqspi_suspend(struct device *dev)
1353 {
1354 	struct cqspi_st *cqspi = dev_get_drvdata(dev);
1355 
1356 	cqspi_controller_enable(cqspi, 0);
1357 	return 0;
1358 }
1359 
1360 static int cqspi_resume(struct device *dev)
1361 {
1362 	struct cqspi_st *cqspi = dev_get_drvdata(dev);
1363 
1364 	cqspi_controller_enable(cqspi, 1);
1365 	return 0;
1366 }
1367 
1368 static const struct dev_pm_ops cqspi__dev_pm_ops = {
1369 	.suspend = cqspi_suspend,
1370 	.resume = cqspi_resume,
1371 };
1372 
1373 #define CQSPI_DEV_PM_OPS	(&cqspi__dev_pm_ops)
1374 #else
1375 #define CQSPI_DEV_PM_OPS	NULL
1376 #endif
1377 
1378 static const struct cqspi_driver_platdata cdns_qspi = {
1379 	.quirks = CQSPI_DISABLE_DAC_MODE,
1380 };
1381 
1382 static const struct cqspi_driver_platdata k2g_qspi = {
1383 	.quirks = CQSPI_NEEDS_WR_DELAY,
1384 };
1385 
1386 static const struct cqspi_driver_platdata am654_ospi = {
1387 	.hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
1388 	.quirks = CQSPI_NEEDS_WR_DELAY,
1389 };
1390 
1391 static const struct of_device_id cqspi_dt_ids[] = {
1392 	{
1393 		.compatible = "cdns,qspi-nor",
1394 		.data = &cdns_qspi,
1395 	},
1396 	{
1397 		.compatible = "ti,k2g-qspi",
1398 		.data = &k2g_qspi,
1399 	},
1400 	{
1401 		.compatible = "ti,am654-ospi",
1402 		.data = &am654_ospi,
1403 	},
1404 	{ /* end of table */ }
1405 };
1406 
1407 MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
1408 
1409 static struct platform_driver cqspi_platform_driver = {
1410 	.probe = cqspi_probe,
1411 	.remove = cqspi_remove,
1412 	.driver = {
1413 		.name = CQSPI_NAME,
1414 		.pm = CQSPI_DEV_PM_OPS,
1415 		.of_match_table = cqspi_dt_ids,
1416 	},
1417 };
1418 
1419 module_platform_driver(cqspi_platform_driver);
1420 
1421 MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
1422 MODULE_LICENSE("GPL v2");
1423 MODULE_ALIAS("platform:" CQSPI_NAME);
1424 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
1425 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");
1426 MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>");
1427 MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>");
1428