1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Driver for Cadence QSPI Controller 4 // 5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved. 6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved. 7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 8 9 #include <linux/clk.h> 10 #include <linux/completion.h> 11 #include <linux/delay.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/dmaengine.h> 14 #include <linux/err.h> 15 #include <linux/errno.h> 16 #include <linux/firmware/xlnx-zynqmp.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/jiffies.h> 21 #include <linux/kernel.h> 22 #include <linux/log2.h> 23 #include <linux/module.h> 24 #include <linux/of_device.h> 25 #include <linux/of.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/reset.h> 29 #include <linux/sched.h> 30 #include <linux/spi/spi.h> 31 #include <linux/spi/spi-mem.h> 32 #include <linux/timer.h> 33 34 #define CQSPI_NAME "cadence-qspi" 35 #define CQSPI_MAX_CHIPSELECT 16 36 37 /* Quirks */ 38 #define CQSPI_NEEDS_WR_DELAY BIT(0) 39 #define CQSPI_DISABLE_DAC_MODE BIT(1) 40 #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) 41 #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) 42 #define CQSPI_SLOW_SRAM BIT(4) 43 44 /* Capabilities */ 45 #define CQSPI_SUPPORTS_OCTAL BIT(0) 46 47 #define CQSPI_OP_WIDTH(part) ((part).nbytes ? ilog2((part).buswidth) : 0) 48 49 struct cqspi_st; 50 51 struct cqspi_flash_pdata { 52 struct cqspi_st *cqspi; 53 u32 clk_rate; 54 u32 read_delay; 55 u32 tshsl_ns; 56 u32 tsd2d_ns; 57 u32 tchsh_ns; 58 u32 tslch_ns; 59 u8 cs; 60 }; 61 62 struct cqspi_st { 63 struct platform_device *pdev; 64 struct spi_master *master; 65 struct clk *clk; 66 unsigned int sclk; 67 68 void __iomem *iobase; 69 void __iomem *ahb_base; 70 resource_size_t ahb_size; 71 struct completion transfer_complete; 72 73 struct dma_chan *rx_chan; 74 struct completion rx_dma_complete; 75 dma_addr_t mmap_phys_base; 76 77 int current_cs; 78 unsigned long master_ref_clk_hz; 79 bool is_decoded_cs; 80 u32 fifo_depth; 81 u32 fifo_width; 82 u32 num_chipselect; 83 bool rclk_en; 84 u32 trigger_address; 85 u32 wr_delay; 86 bool use_direct_mode; 87 bool use_direct_mode_wr; 88 struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; 89 bool use_dma_read; 90 u32 pd_dev_id; 91 bool wr_completion; 92 bool slow_sram; 93 }; 94 95 struct cqspi_driver_platdata { 96 u32 hwcaps_mask; 97 u8 quirks; 98 int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata, 99 u_char *rxbuf, loff_t from_addr, size_t n_rx); 100 u32 (*get_dma_status)(struct cqspi_st *cqspi); 101 }; 102 103 /* Operation timeout value */ 104 #define CQSPI_TIMEOUT_MS 500 105 #define CQSPI_READ_TIMEOUT_MS 10 106 107 #define CQSPI_DUMMY_CLKS_PER_BYTE 8 108 #define CQSPI_DUMMY_BYTES_MAX 4 109 #define CQSPI_DUMMY_CLKS_MAX 31 110 111 #define CQSPI_STIG_DATA_LEN_MAX 8 112 113 /* Register map */ 114 #define CQSPI_REG_CONFIG 0x00 115 #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0) 116 #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7) 117 #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9) 118 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 119 #define CQSPI_REG_CONFIG_DMA_MASK BIT(15) 120 #define CQSPI_REG_CONFIG_BAUD_LSB 19 121 #define CQSPI_REG_CONFIG_DTR_PROTO BIT(24) 122 #define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30) 123 #define CQSPI_REG_CONFIG_IDLE_LSB 31 124 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF 125 #define CQSPI_REG_CONFIG_BAUD_MASK 0xF 126 127 #define CQSPI_REG_RD_INSTR 0x04 128 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 129 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 130 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 131 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 132 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 133 #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 134 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 135 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 136 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 137 #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F 138 139 #define CQSPI_REG_WR_INSTR 0x08 140 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 141 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12 142 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16 143 144 #define CQSPI_REG_DELAY 0x0C 145 #define CQSPI_REG_DELAY_TSLCH_LSB 0 146 #define CQSPI_REG_DELAY_TCHSH_LSB 8 147 #define CQSPI_REG_DELAY_TSD2D_LSB 16 148 #define CQSPI_REG_DELAY_TSHSL_LSB 24 149 #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF 150 #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF 151 #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF 152 #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF 153 154 #define CQSPI_REG_READCAPTURE 0x10 155 #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0 156 #define CQSPI_REG_READCAPTURE_DELAY_LSB 1 157 #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF 158 159 #define CQSPI_REG_SIZE 0x14 160 #define CQSPI_REG_SIZE_ADDRESS_LSB 0 161 #define CQSPI_REG_SIZE_PAGE_LSB 4 162 #define CQSPI_REG_SIZE_BLOCK_LSB 16 163 #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF 164 #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF 165 #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F 166 167 #define CQSPI_REG_SRAMPARTITION 0x18 168 #define CQSPI_REG_INDIRECTTRIGGER 0x1C 169 170 #define CQSPI_REG_DMA 0x20 171 #define CQSPI_REG_DMA_SINGLE_LSB 0 172 #define CQSPI_REG_DMA_BURST_LSB 8 173 #define CQSPI_REG_DMA_SINGLE_MASK 0xFF 174 #define CQSPI_REG_DMA_BURST_MASK 0xFF 175 176 #define CQSPI_REG_REMAP 0x24 177 #define CQSPI_REG_MODE_BIT 0x28 178 179 #define CQSPI_REG_SDRAMLEVEL 0x2C 180 #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 181 #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 182 #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF 183 #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF 184 185 #define CQSPI_REG_WR_COMPLETION_CTRL 0x38 186 #define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14) 187 188 #define CQSPI_REG_IRQSTATUS 0x40 189 #define CQSPI_REG_IRQMASK 0x44 190 191 #define CQSPI_REG_INDIRECTRD 0x60 192 #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0) 193 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1) 194 #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5) 195 196 #define CQSPI_REG_INDIRECTRDWATERMARK 0x64 197 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 198 #define CQSPI_REG_INDIRECTRDBYTES 0x6C 199 200 #define CQSPI_REG_CMDCTRL 0x90 201 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0) 202 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1) 203 #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 204 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 205 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 206 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 207 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 208 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 209 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 210 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 211 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 212 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 213 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 214 #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F 215 216 #define CQSPI_REG_INDIRECTWR 0x70 217 #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0) 218 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1) 219 #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5) 220 221 #define CQSPI_REG_INDIRECTWRWATERMARK 0x74 222 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 223 #define CQSPI_REG_INDIRECTWRBYTES 0x7C 224 225 #define CQSPI_REG_INDTRIG_ADDRRANGE 0x80 226 227 #define CQSPI_REG_CMDADDRESS 0x94 228 #define CQSPI_REG_CMDREADDATALOWER 0xA0 229 #define CQSPI_REG_CMDREADDATAUPPER 0xA4 230 #define CQSPI_REG_CMDWRITEDATALOWER 0xA8 231 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC 232 233 #define CQSPI_REG_POLLING_STATUS 0xB0 234 #define CQSPI_REG_POLLING_STATUS_DUMMY_LSB 16 235 236 #define CQSPI_REG_OP_EXT_LOWER 0xE0 237 #define CQSPI_REG_OP_EXT_READ_LSB 24 238 #define CQSPI_REG_OP_EXT_WRITE_LSB 16 239 #define CQSPI_REG_OP_EXT_STIG_LSB 0 240 241 #define CQSPI_REG_VERSAL_DMA_SRC_ADDR 0x1000 242 243 #define CQSPI_REG_VERSAL_DMA_DST_ADDR 0x1800 244 #define CQSPI_REG_VERSAL_DMA_DST_SIZE 0x1804 245 246 #define CQSPI_REG_VERSAL_DMA_DST_CTRL 0x180C 247 248 #define CQSPI_REG_VERSAL_DMA_DST_I_STS 0x1814 249 #define CQSPI_REG_VERSAL_DMA_DST_I_EN 0x1818 250 #define CQSPI_REG_VERSAL_DMA_DST_I_DIS 0x181C 251 #define CQSPI_REG_VERSAL_DMA_DST_DONE_MASK BIT(1) 252 253 #define CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB 0x1828 254 255 #define CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL 0xF43FFA00 256 #define CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL 0x6 257 258 /* Interrupt status bits */ 259 #define CQSPI_REG_IRQ_MODE_ERR BIT(0) 260 #define CQSPI_REG_IRQ_UNDERFLOW BIT(1) 261 #define CQSPI_REG_IRQ_IND_COMP BIT(2) 262 #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3) 263 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4) 264 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5) 265 #define CQSPI_REG_IRQ_WATERMARK BIT(6) 266 #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12) 267 268 #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \ 269 CQSPI_REG_IRQ_IND_SRAM_FULL | \ 270 CQSPI_REG_IRQ_IND_COMP) 271 272 #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \ 273 CQSPI_REG_IRQ_WATERMARK | \ 274 CQSPI_REG_IRQ_UNDERFLOW) 275 276 #define CQSPI_IRQ_STATUS_MASK 0x1FFFF 277 #define CQSPI_DMA_UNALIGN 0x3 278 279 #define CQSPI_REG_VERSAL_DMA_VAL 0x602 280 281 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr) 282 { 283 u32 val; 284 285 return readl_relaxed_poll_timeout(reg, val, 286 (((clr ? ~val : val) & mask) == mask), 287 10, CQSPI_TIMEOUT_MS * 1000); 288 } 289 290 static bool cqspi_is_idle(struct cqspi_st *cqspi) 291 { 292 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 293 294 return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB); 295 } 296 297 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi) 298 { 299 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL); 300 301 reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB; 302 return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK; 303 } 304 305 static u32 cqspi_get_versal_dma_status(struct cqspi_st *cqspi) 306 { 307 u32 dma_status; 308 309 dma_status = readl(cqspi->iobase + 310 CQSPI_REG_VERSAL_DMA_DST_I_STS); 311 writel(dma_status, cqspi->iobase + 312 CQSPI_REG_VERSAL_DMA_DST_I_STS); 313 314 return dma_status & CQSPI_REG_VERSAL_DMA_DST_DONE_MASK; 315 } 316 317 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev) 318 { 319 struct cqspi_st *cqspi = dev; 320 unsigned int irq_status; 321 struct device *device = &cqspi->pdev->dev; 322 const struct cqspi_driver_platdata *ddata; 323 324 ddata = of_device_get_match_data(device); 325 326 /* Read interrupt status */ 327 irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS); 328 329 /* Clear interrupt */ 330 writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS); 331 332 if (cqspi->use_dma_read && ddata && ddata->get_dma_status) { 333 if (ddata->get_dma_status(cqspi)) { 334 complete(&cqspi->transfer_complete); 335 return IRQ_HANDLED; 336 } 337 } 338 339 else if (!cqspi->slow_sram) 340 irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR; 341 else 342 irq_status &= CQSPI_REG_IRQ_WATERMARK | CQSPI_IRQ_MASK_WR; 343 344 if (irq_status) 345 complete(&cqspi->transfer_complete); 346 347 return IRQ_HANDLED; 348 } 349 350 static unsigned int cqspi_calc_rdreg(const struct spi_mem_op *op) 351 { 352 u32 rdreg = 0; 353 354 rdreg |= CQSPI_OP_WIDTH(op->cmd) << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; 355 rdreg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; 356 rdreg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; 357 358 return rdreg; 359 } 360 361 static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op) 362 { 363 unsigned int dummy_clk; 364 365 if (!op->dummy.nbytes) 366 return 0; 367 368 dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth); 369 if (op->cmd.dtr) 370 dummy_clk /= 2; 371 372 return dummy_clk; 373 } 374 375 static int cqspi_wait_idle(struct cqspi_st *cqspi) 376 { 377 const unsigned int poll_idle_retry = 3; 378 unsigned int count = 0; 379 unsigned long timeout; 380 381 timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS); 382 while (1) { 383 /* 384 * Read few times in succession to ensure the controller 385 * is indeed idle, that is, the bit does not transition 386 * low again. 387 */ 388 if (cqspi_is_idle(cqspi)) 389 count++; 390 else 391 count = 0; 392 393 if (count >= poll_idle_retry) 394 return 0; 395 396 if (time_after(jiffies, timeout)) { 397 /* Timeout, in busy mode. */ 398 dev_err(&cqspi->pdev->dev, 399 "QSPI is still busy after %dms timeout.\n", 400 CQSPI_TIMEOUT_MS); 401 return -ETIMEDOUT; 402 } 403 404 cpu_relax(); 405 } 406 } 407 408 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg) 409 { 410 void __iomem *reg_base = cqspi->iobase; 411 int ret; 412 413 /* Write the CMDCTRL without start execution. */ 414 writel(reg, reg_base + CQSPI_REG_CMDCTRL); 415 /* Start execute */ 416 reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK; 417 writel(reg, reg_base + CQSPI_REG_CMDCTRL); 418 419 /* Polling for completion. */ 420 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL, 421 CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1); 422 if (ret) { 423 dev_err(&cqspi->pdev->dev, 424 "Flash command execution timed out.\n"); 425 return ret; 426 } 427 428 /* Polling QSPI idle status. */ 429 return cqspi_wait_idle(cqspi); 430 } 431 432 static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata, 433 const struct spi_mem_op *op, 434 unsigned int shift) 435 { 436 struct cqspi_st *cqspi = f_pdata->cqspi; 437 void __iomem *reg_base = cqspi->iobase; 438 unsigned int reg; 439 u8 ext; 440 441 if (op->cmd.nbytes != 2) 442 return -EINVAL; 443 444 /* Opcode extension is the LSB. */ 445 ext = op->cmd.opcode & 0xff; 446 447 reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER); 448 reg &= ~(0xff << shift); 449 reg |= ext << shift; 450 writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER); 451 452 return 0; 453 } 454 455 static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata, 456 const struct spi_mem_op *op, unsigned int shift) 457 { 458 struct cqspi_st *cqspi = f_pdata->cqspi; 459 void __iomem *reg_base = cqspi->iobase; 460 unsigned int reg; 461 int ret; 462 463 reg = readl(reg_base + CQSPI_REG_CONFIG); 464 465 /* 466 * We enable dual byte opcode here. The callers have to set up the 467 * extension opcode based on which type of operation it is. 468 */ 469 if (op->cmd.dtr) { 470 reg |= CQSPI_REG_CONFIG_DTR_PROTO; 471 reg |= CQSPI_REG_CONFIG_DUAL_OPCODE; 472 473 /* Set up command opcode extension. */ 474 ret = cqspi_setup_opcode_ext(f_pdata, op, shift); 475 if (ret) 476 return ret; 477 } else { 478 reg &= ~CQSPI_REG_CONFIG_DTR_PROTO; 479 reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE; 480 } 481 482 writel(reg, reg_base + CQSPI_REG_CONFIG); 483 484 return cqspi_wait_idle(cqspi); 485 } 486 487 static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, 488 const struct spi_mem_op *op) 489 { 490 struct cqspi_st *cqspi = f_pdata->cqspi; 491 void __iomem *reg_base = cqspi->iobase; 492 u8 *rxbuf = op->data.buf.in; 493 u8 opcode; 494 size_t n_rx = op->data.nbytes; 495 unsigned int rdreg; 496 unsigned int reg; 497 unsigned int dummy_clk; 498 size_t read_len; 499 int status; 500 501 status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB); 502 if (status) 503 return status; 504 505 if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) { 506 dev_err(&cqspi->pdev->dev, 507 "Invalid input argument, len %zu rxbuf 0x%p\n", 508 n_rx, rxbuf); 509 return -EINVAL; 510 } 511 512 if (op->cmd.dtr) 513 opcode = op->cmd.opcode >> 8; 514 else 515 opcode = op->cmd.opcode; 516 517 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 518 519 rdreg = cqspi_calc_rdreg(op); 520 writel(rdreg, reg_base + CQSPI_REG_RD_INSTR); 521 522 dummy_clk = cqspi_calc_dummy(op); 523 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 524 return -EOPNOTSUPP; 525 526 if (dummy_clk) 527 reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK) 528 << CQSPI_REG_CMDCTRL_DUMMY_LSB; 529 530 reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); 531 532 /* 0 means 1 byte. */ 533 reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) 534 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); 535 536 /* setup ADDR BIT field */ 537 if (op->addr.nbytes) { 538 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 539 reg |= ((op->addr.nbytes - 1) & 540 CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) 541 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; 542 543 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); 544 } 545 546 status = cqspi_exec_flash_cmd(cqspi, reg); 547 if (status) 548 return status; 549 550 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER); 551 552 /* Put the read value into rx_buf */ 553 read_len = (n_rx > 4) ? 4 : n_rx; 554 memcpy(rxbuf, ®, read_len); 555 rxbuf += read_len; 556 557 if (n_rx > 4) { 558 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER); 559 560 read_len = n_rx - read_len; 561 memcpy(rxbuf, ®, read_len); 562 } 563 564 /* Reset CMD_CTRL Reg once command read completes */ 565 writel(0, reg_base + CQSPI_REG_CMDCTRL); 566 567 return 0; 568 } 569 570 static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata, 571 const struct spi_mem_op *op) 572 { 573 struct cqspi_st *cqspi = f_pdata->cqspi; 574 void __iomem *reg_base = cqspi->iobase; 575 u8 opcode; 576 const u8 *txbuf = op->data.buf.out; 577 size_t n_tx = op->data.nbytes; 578 unsigned int reg; 579 unsigned int data; 580 size_t write_len; 581 int ret; 582 583 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB); 584 if (ret) 585 return ret; 586 587 if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) { 588 dev_err(&cqspi->pdev->dev, 589 "Invalid input argument, cmdlen %zu txbuf 0x%p\n", 590 n_tx, txbuf); 591 return -EINVAL; 592 } 593 594 reg = cqspi_calc_rdreg(op); 595 writel(reg, reg_base + CQSPI_REG_RD_INSTR); 596 597 if (op->cmd.dtr) 598 opcode = op->cmd.opcode >> 8; 599 else 600 opcode = op->cmd.opcode; 601 602 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 603 604 if (op->addr.nbytes) { 605 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 606 reg |= ((op->addr.nbytes - 1) & 607 CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) 608 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; 609 610 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); 611 } 612 613 if (n_tx) { 614 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB); 615 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) 616 << CQSPI_REG_CMDCTRL_WR_BYTES_LSB; 617 data = 0; 618 write_len = (n_tx > 4) ? 4 : n_tx; 619 memcpy(&data, txbuf, write_len); 620 txbuf += write_len; 621 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER); 622 623 if (n_tx > 4) { 624 data = 0; 625 write_len = n_tx - 4; 626 memcpy(&data, txbuf, write_len); 627 writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER); 628 } 629 } 630 631 ret = cqspi_exec_flash_cmd(cqspi, reg); 632 633 /* Reset CMD_CTRL Reg once command write completes */ 634 writel(0, reg_base + CQSPI_REG_CMDCTRL); 635 636 return ret; 637 } 638 639 static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata, 640 const struct spi_mem_op *op) 641 { 642 struct cqspi_st *cqspi = f_pdata->cqspi; 643 void __iomem *reg_base = cqspi->iobase; 644 unsigned int dummy_clk = 0; 645 unsigned int reg; 646 int ret; 647 u8 opcode; 648 649 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB); 650 if (ret) 651 return ret; 652 653 if (op->cmd.dtr) 654 opcode = op->cmd.opcode >> 8; 655 else 656 opcode = op->cmd.opcode; 657 658 reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB; 659 reg |= cqspi_calc_rdreg(op); 660 661 /* Setup dummy clock cycles */ 662 dummy_clk = cqspi_calc_dummy(op); 663 664 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 665 return -EOPNOTSUPP; 666 667 if (dummy_clk) 668 reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK) 669 << CQSPI_REG_RD_INSTR_DUMMY_LSB; 670 671 writel(reg, reg_base + CQSPI_REG_RD_INSTR); 672 673 /* Set address width */ 674 reg = readl(reg_base + CQSPI_REG_SIZE); 675 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 676 reg |= (op->addr.nbytes - 1); 677 writel(reg, reg_base + CQSPI_REG_SIZE); 678 return 0; 679 } 680 681 static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, 682 u8 *rxbuf, loff_t from_addr, 683 const size_t n_rx) 684 { 685 struct cqspi_st *cqspi = f_pdata->cqspi; 686 struct device *dev = &cqspi->pdev->dev; 687 void __iomem *reg_base = cqspi->iobase; 688 void __iomem *ahb_base = cqspi->ahb_base; 689 unsigned int remaining = n_rx; 690 unsigned int mod_bytes = n_rx % 4; 691 unsigned int bytes_to_read = 0; 692 u8 *rxbuf_end = rxbuf + n_rx; 693 int ret = 0; 694 695 writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 696 writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES); 697 698 /* Clear all interrupts. */ 699 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 700 701 /* 702 * On SoCFPGA platform reading the SRAM is slow due to 703 * hardware limitation and causing read interrupt storm to CPU, 704 * so enabling only watermark interrupt to disable all read 705 * interrupts later as we want to run "bytes to read" loop with 706 * all the read interrupts disabled for max performance. 707 */ 708 709 if (!cqspi->slow_sram) 710 writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK); 711 else 712 writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK); 713 714 reinit_completion(&cqspi->transfer_complete); 715 writel(CQSPI_REG_INDIRECTRD_START_MASK, 716 reg_base + CQSPI_REG_INDIRECTRD); 717 718 while (remaining > 0) { 719 if (!wait_for_completion_timeout(&cqspi->transfer_complete, 720 msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) 721 ret = -ETIMEDOUT; 722 723 /* 724 * Disable all read interrupts until 725 * we are out of "bytes to read" 726 */ 727 if (cqspi->slow_sram) 728 writel(0x0, reg_base + CQSPI_REG_IRQMASK); 729 730 bytes_to_read = cqspi_get_rd_sram_level(cqspi); 731 732 if (ret && bytes_to_read == 0) { 733 dev_err(dev, "Indirect read timeout, no bytes\n"); 734 goto failrd; 735 } 736 737 while (bytes_to_read != 0) { 738 unsigned int word_remain = round_down(remaining, 4); 739 740 bytes_to_read *= cqspi->fifo_width; 741 bytes_to_read = bytes_to_read > remaining ? 742 remaining : bytes_to_read; 743 bytes_to_read = round_down(bytes_to_read, 4); 744 /* Read 4 byte word chunks then single bytes */ 745 if (bytes_to_read) { 746 ioread32_rep(ahb_base, rxbuf, 747 (bytes_to_read / 4)); 748 } else if (!word_remain && mod_bytes) { 749 unsigned int temp = ioread32(ahb_base); 750 751 bytes_to_read = mod_bytes; 752 memcpy(rxbuf, &temp, min((unsigned int) 753 (rxbuf_end - rxbuf), 754 bytes_to_read)); 755 } 756 rxbuf += bytes_to_read; 757 remaining -= bytes_to_read; 758 bytes_to_read = cqspi_get_rd_sram_level(cqspi); 759 } 760 761 if (remaining > 0) { 762 reinit_completion(&cqspi->transfer_complete); 763 if (cqspi->slow_sram) 764 writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK); 765 } 766 } 767 768 /* Check indirect done status */ 769 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD, 770 CQSPI_REG_INDIRECTRD_DONE_MASK, 0); 771 if (ret) { 772 dev_err(dev, "Indirect read completion error (%i)\n", ret); 773 goto failrd; 774 } 775 776 /* Disable interrupt */ 777 writel(0, reg_base + CQSPI_REG_IRQMASK); 778 779 /* Clear indirect completion status */ 780 writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD); 781 782 return 0; 783 784 failrd: 785 /* Disable interrupt */ 786 writel(0, reg_base + CQSPI_REG_IRQMASK); 787 788 /* Cancel the indirect read */ 789 writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK, 790 reg_base + CQSPI_REG_INDIRECTRD); 791 return ret; 792 } 793 794 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable) 795 { 796 void __iomem *reg_base = cqspi->iobase; 797 unsigned int reg; 798 799 reg = readl(reg_base + CQSPI_REG_CONFIG); 800 801 if (enable) 802 reg |= CQSPI_REG_CONFIG_ENABLE_MASK; 803 else 804 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; 805 806 writel(reg, reg_base + CQSPI_REG_CONFIG); 807 } 808 809 static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata, 810 u_char *rxbuf, loff_t from_addr, 811 size_t n_rx) 812 { 813 struct cqspi_st *cqspi = f_pdata->cqspi; 814 struct device *dev = &cqspi->pdev->dev; 815 void __iomem *reg_base = cqspi->iobase; 816 u32 reg, bytes_to_dma; 817 loff_t addr = from_addr; 818 void *buf = rxbuf; 819 dma_addr_t dma_addr; 820 u8 bytes_rem; 821 int ret = 0; 822 823 bytes_rem = n_rx % 4; 824 bytes_to_dma = (n_rx - bytes_rem); 825 826 if (!bytes_to_dma) 827 goto nondmard; 828 829 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA); 830 if (ret) 831 return ret; 832 833 cqspi_controller_enable(cqspi, 0); 834 835 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 836 reg |= CQSPI_REG_CONFIG_DMA_MASK; 837 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 838 839 cqspi_controller_enable(cqspi, 1); 840 841 dma_addr = dma_map_single(dev, rxbuf, bytes_to_dma, DMA_FROM_DEVICE); 842 if (dma_mapping_error(dev, dma_addr)) { 843 dev_err(dev, "dma mapping failed\n"); 844 return -ENOMEM; 845 } 846 847 writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 848 writel(bytes_to_dma, reg_base + CQSPI_REG_INDIRECTRDBYTES); 849 writel(CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL, 850 reg_base + CQSPI_REG_INDTRIG_ADDRRANGE); 851 852 /* Clear all interrupts. */ 853 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 854 855 /* Enable DMA done interrupt */ 856 writel(CQSPI_REG_VERSAL_DMA_DST_DONE_MASK, 857 reg_base + CQSPI_REG_VERSAL_DMA_DST_I_EN); 858 859 /* Default DMA periph configuration */ 860 writel(CQSPI_REG_VERSAL_DMA_VAL, reg_base + CQSPI_REG_DMA); 861 862 /* Configure DMA Dst address */ 863 writel(lower_32_bits(dma_addr), 864 reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR); 865 writel(upper_32_bits(dma_addr), 866 reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB); 867 868 /* Configure DMA Src address */ 869 writel(cqspi->trigger_address, reg_base + 870 CQSPI_REG_VERSAL_DMA_SRC_ADDR); 871 872 /* Set DMA destination size */ 873 writel(bytes_to_dma, reg_base + CQSPI_REG_VERSAL_DMA_DST_SIZE); 874 875 /* Set DMA destination control */ 876 writel(CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL, 877 reg_base + CQSPI_REG_VERSAL_DMA_DST_CTRL); 878 879 writel(CQSPI_REG_INDIRECTRD_START_MASK, 880 reg_base + CQSPI_REG_INDIRECTRD); 881 882 reinit_completion(&cqspi->transfer_complete); 883 884 if (!wait_for_completion_timeout(&cqspi->transfer_complete, 885 msecs_to_jiffies(max_t(size_t, bytes_to_dma, 500)))) { 886 ret = -ETIMEDOUT; 887 goto failrd; 888 } 889 890 /* Disable DMA interrupt */ 891 writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS); 892 893 /* Clear indirect completion status */ 894 writel(CQSPI_REG_INDIRECTRD_DONE_MASK, 895 cqspi->iobase + CQSPI_REG_INDIRECTRD); 896 dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE); 897 898 cqspi_controller_enable(cqspi, 0); 899 900 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 901 reg &= ~CQSPI_REG_CONFIG_DMA_MASK; 902 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 903 904 cqspi_controller_enable(cqspi, 1); 905 906 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, 907 PM_OSPI_MUX_SEL_LINEAR); 908 if (ret) 909 return ret; 910 911 nondmard: 912 if (bytes_rem) { 913 addr += bytes_to_dma; 914 buf += bytes_to_dma; 915 ret = cqspi_indirect_read_execute(f_pdata, buf, addr, 916 bytes_rem); 917 if (ret) 918 return ret; 919 } 920 921 return 0; 922 923 failrd: 924 /* Disable DMA interrupt */ 925 writel(0x0, reg_base + CQSPI_REG_VERSAL_DMA_DST_I_DIS); 926 927 /* Cancel the indirect read */ 928 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 929 reg_base + CQSPI_REG_INDIRECTRD); 930 931 dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE); 932 933 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 934 reg &= ~CQSPI_REG_CONFIG_DMA_MASK; 935 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 936 937 zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR); 938 939 return ret; 940 } 941 942 static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata, 943 const struct spi_mem_op *op) 944 { 945 unsigned int reg; 946 int ret; 947 struct cqspi_st *cqspi = f_pdata->cqspi; 948 void __iomem *reg_base = cqspi->iobase; 949 u8 opcode; 950 951 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB); 952 if (ret) 953 return ret; 954 955 if (op->cmd.dtr) 956 opcode = op->cmd.opcode >> 8; 957 else 958 opcode = op->cmd.opcode; 959 960 /* Set opcode. */ 961 reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; 962 reg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; 963 reg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; 964 writel(reg, reg_base + CQSPI_REG_WR_INSTR); 965 reg = cqspi_calc_rdreg(op); 966 writel(reg, reg_base + CQSPI_REG_RD_INSTR); 967 968 /* 969 * SPI NAND flashes require the address of the status register to be 970 * passed in the Read SR command. Also, some SPI NOR flashes like the 971 * cypress Semper flash expect a 4-byte dummy address in the Read SR 972 * command in DTR mode. 973 * 974 * But this controller does not support address phase in the Read SR 975 * command when doing auto-HW polling. So, disable write completion 976 * polling on the controller's side. spinand and spi-nor will take 977 * care of polling the status register. 978 */ 979 if (cqspi->wr_completion) { 980 reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL); 981 reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL; 982 writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL); 983 /* 984 * DAC mode require auto polling as flash needs to be polled 985 * for write completion in case of bubble in SPI transaction 986 * due to slow CPU/DMA master. 987 */ 988 cqspi->use_direct_mode_wr = false; 989 } 990 991 reg = readl(reg_base + CQSPI_REG_SIZE); 992 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 993 reg |= (op->addr.nbytes - 1); 994 writel(reg, reg_base + CQSPI_REG_SIZE); 995 return 0; 996 } 997 998 static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, 999 loff_t to_addr, const u8 *txbuf, 1000 const size_t n_tx) 1001 { 1002 struct cqspi_st *cqspi = f_pdata->cqspi; 1003 struct device *dev = &cqspi->pdev->dev; 1004 void __iomem *reg_base = cqspi->iobase; 1005 unsigned int remaining = n_tx; 1006 unsigned int write_bytes; 1007 int ret; 1008 1009 writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR); 1010 writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES); 1011 1012 /* Clear all interrupts. */ 1013 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 1014 1015 writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK); 1016 1017 reinit_completion(&cqspi->transfer_complete); 1018 writel(CQSPI_REG_INDIRECTWR_START_MASK, 1019 reg_base + CQSPI_REG_INDIRECTWR); 1020 /* 1021 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access 1022 * Controller programming sequence, couple of cycles of 1023 * QSPI_REF_CLK delay is required for the above bit to 1024 * be internally synchronized by the QSPI module. Provide 5 1025 * cycles of delay. 1026 */ 1027 if (cqspi->wr_delay) 1028 ndelay(cqspi->wr_delay); 1029 1030 while (remaining > 0) { 1031 size_t write_words, mod_bytes; 1032 1033 write_bytes = remaining; 1034 write_words = write_bytes / 4; 1035 mod_bytes = write_bytes % 4; 1036 /* Write 4 bytes at a time then single bytes. */ 1037 if (write_words) { 1038 iowrite32_rep(cqspi->ahb_base, txbuf, write_words); 1039 txbuf += (write_words * 4); 1040 } 1041 if (mod_bytes) { 1042 unsigned int temp = 0xFFFFFFFF; 1043 1044 memcpy(&temp, txbuf, mod_bytes); 1045 iowrite32(temp, cqspi->ahb_base); 1046 txbuf += mod_bytes; 1047 } 1048 1049 if (!wait_for_completion_timeout(&cqspi->transfer_complete, 1050 msecs_to_jiffies(CQSPI_TIMEOUT_MS))) { 1051 dev_err(dev, "Indirect write timeout\n"); 1052 ret = -ETIMEDOUT; 1053 goto failwr; 1054 } 1055 1056 remaining -= write_bytes; 1057 1058 if (remaining > 0) 1059 reinit_completion(&cqspi->transfer_complete); 1060 } 1061 1062 /* Check indirect done status */ 1063 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR, 1064 CQSPI_REG_INDIRECTWR_DONE_MASK, 0); 1065 if (ret) { 1066 dev_err(dev, "Indirect write completion error (%i)\n", ret); 1067 goto failwr; 1068 } 1069 1070 /* Disable interrupt. */ 1071 writel(0, reg_base + CQSPI_REG_IRQMASK); 1072 1073 /* Clear indirect completion status */ 1074 writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR); 1075 1076 cqspi_wait_idle(cqspi); 1077 1078 return 0; 1079 1080 failwr: 1081 /* Disable interrupt. */ 1082 writel(0, reg_base + CQSPI_REG_IRQMASK); 1083 1084 /* Cancel the indirect write */ 1085 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 1086 reg_base + CQSPI_REG_INDIRECTWR); 1087 return ret; 1088 } 1089 1090 static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata) 1091 { 1092 struct cqspi_st *cqspi = f_pdata->cqspi; 1093 void __iomem *reg_base = cqspi->iobase; 1094 unsigned int chip_select = f_pdata->cs; 1095 unsigned int reg; 1096 1097 reg = readl(reg_base + CQSPI_REG_CONFIG); 1098 if (cqspi->is_decoded_cs) { 1099 reg |= CQSPI_REG_CONFIG_DECODE_MASK; 1100 } else { 1101 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; 1102 1103 /* Convert CS if without decoder. 1104 * CS0 to 4b'1110 1105 * CS1 to 4b'1101 1106 * CS2 to 4b'1011 1107 * CS3 to 4b'0111 1108 */ 1109 chip_select = 0xF & ~(1 << chip_select); 1110 } 1111 1112 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK 1113 << CQSPI_REG_CONFIG_CHIPSELECT_LSB); 1114 reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK) 1115 << CQSPI_REG_CONFIG_CHIPSELECT_LSB; 1116 writel(reg, reg_base + CQSPI_REG_CONFIG); 1117 } 1118 1119 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz, 1120 const unsigned int ns_val) 1121 { 1122 unsigned int ticks; 1123 1124 ticks = ref_clk_hz / 1000; /* kHz */ 1125 ticks = DIV_ROUND_UP(ticks * ns_val, 1000000); 1126 1127 return ticks; 1128 } 1129 1130 static void cqspi_delay(struct cqspi_flash_pdata *f_pdata) 1131 { 1132 struct cqspi_st *cqspi = f_pdata->cqspi; 1133 void __iomem *iobase = cqspi->iobase; 1134 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 1135 unsigned int tshsl, tchsh, tslch, tsd2d; 1136 unsigned int reg; 1137 unsigned int tsclk; 1138 1139 /* calculate the number of ref ticks for one sclk tick */ 1140 tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk); 1141 1142 tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns); 1143 /* this particular value must be at least one sclk */ 1144 if (tshsl < tsclk) 1145 tshsl = tsclk; 1146 1147 tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns); 1148 tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns); 1149 tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns); 1150 1151 reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK) 1152 << CQSPI_REG_DELAY_TSHSL_LSB; 1153 reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK) 1154 << CQSPI_REG_DELAY_TCHSH_LSB; 1155 reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK) 1156 << CQSPI_REG_DELAY_TSLCH_LSB; 1157 reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK) 1158 << CQSPI_REG_DELAY_TSD2D_LSB; 1159 writel(reg, iobase + CQSPI_REG_DELAY); 1160 } 1161 1162 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi) 1163 { 1164 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 1165 void __iomem *reg_base = cqspi->iobase; 1166 u32 reg, div; 1167 1168 /* Recalculate the baudrate divisor based on QSPI specification. */ 1169 div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1; 1170 1171 /* Maximum baud divisor */ 1172 if (div > CQSPI_REG_CONFIG_BAUD_MASK) { 1173 div = CQSPI_REG_CONFIG_BAUD_MASK; 1174 dev_warn(&cqspi->pdev->dev, 1175 "Unable to adjust clock <= %d hz. Reduced to %d hz\n", 1176 cqspi->sclk, ref_clk_hz/((div+1)*2)); 1177 } 1178 1179 reg = readl(reg_base + CQSPI_REG_CONFIG); 1180 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); 1181 reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB; 1182 writel(reg, reg_base + CQSPI_REG_CONFIG); 1183 } 1184 1185 static void cqspi_readdata_capture(struct cqspi_st *cqspi, 1186 const bool bypass, 1187 const unsigned int delay) 1188 { 1189 void __iomem *reg_base = cqspi->iobase; 1190 unsigned int reg; 1191 1192 reg = readl(reg_base + CQSPI_REG_READCAPTURE); 1193 1194 if (bypass) 1195 reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 1196 else 1197 reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 1198 1199 reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK 1200 << CQSPI_REG_READCAPTURE_DELAY_LSB); 1201 1202 reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK) 1203 << CQSPI_REG_READCAPTURE_DELAY_LSB; 1204 1205 writel(reg, reg_base + CQSPI_REG_READCAPTURE); 1206 } 1207 1208 static void cqspi_configure(struct cqspi_flash_pdata *f_pdata, 1209 unsigned long sclk) 1210 { 1211 struct cqspi_st *cqspi = f_pdata->cqspi; 1212 int switch_cs = (cqspi->current_cs != f_pdata->cs); 1213 int switch_ck = (cqspi->sclk != sclk); 1214 1215 if (switch_cs || switch_ck) 1216 cqspi_controller_enable(cqspi, 0); 1217 1218 /* Switch chip select. */ 1219 if (switch_cs) { 1220 cqspi->current_cs = f_pdata->cs; 1221 cqspi_chipselect(f_pdata); 1222 } 1223 1224 /* Setup baudrate divisor and delays */ 1225 if (switch_ck) { 1226 cqspi->sclk = sclk; 1227 cqspi_config_baudrate_div(cqspi); 1228 cqspi_delay(f_pdata); 1229 cqspi_readdata_capture(cqspi, !cqspi->rclk_en, 1230 f_pdata->read_delay); 1231 } 1232 1233 if (switch_cs || switch_ck) 1234 cqspi_controller_enable(cqspi, 1); 1235 } 1236 1237 static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata, 1238 const struct spi_mem_op *op) 1239 { 1240 struct cqspi_st *cqspi = f_pdata->cqspi; 1241 loff_t to = op->addr.val; 1242 size_t len = op->data.nbytes; 1243 const u_char *buf = op->data.buf.out; 1244 int ret; 1245 1246 ret = cqspi_write_setup(f_pdata, op); 1247 if (ret) 1248 return ret; 1249 1250 /* 1251 * Some flashes like the Cypress Semper flash expect a dummy 4-byte 1252 * address (all 0s) with the read status register command in DTR mode. 1253 * But this controller does not support sending dummy address bytes to 1254 * the flash when it is polling the write completion register in DTR 1255 * mode. So, we can not use direct mode when in DTR mode for writing 1256 * data. 1257 */ 1258 if (!op->cmd.dtr && cqspi->use_direct_mode && 1259 cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) { 1260 memcpy_toio(cqspi->ahb_base + to, buf, len); 1261 return cqspi_wait_idle(cqspi); 1262 } 1263 1264 return cqspi_indirect_write_execute(f_pdata, to, buf, len); 1265 } 1266 1267 static void cqspi_rx_dma_callback(void *param) 1268 { 1269 struct cqspi_st *cqspi = param; 1270 1271 complete(&cqspi->rx_dma_complete); 1272 } 1273 1274 static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata, 1275 u_char *buf, loff_t from, size_t len) 1276 { 1277 struct cqspi_st *cqspi = f_pdata->cqspi; 1278 struct device *dev = &cqspi->pdev->dev; 1279 enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; 1280 dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from; 1281 int ret = 0; 1282 struct dma_async_tx_descriptor *tx; 1283 dma_cookie_t cookie; 1284 dma_addr_t dma_dst; 1285 struct device *ddev; 1286 1287 if (!cqspi->rx_chan || !virt_addr_valid(buf)) { 1288 memcpy_fromio(buf, cqspi->ahb_base + from, len); 1289 return 0; 1290 } 1291 1292 ddev = cqspi->rx_chan->device->dev; 1293 dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE); 1294 if (dma_mapping_error(ddev, dma_dst)) { 1295 dev_err(dev, "dma mapping failed\n"); 1296 return -ENOMEM; 1297 } 1298 tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src, 1299 len, flags); 1300 if (!tx) { 1301 dev_err(dev, "device_prep_dma_memcpy error\n"); 1302 ret = -EIO; 1303 goto err_unmap; 1304 } 1305 1306 tx->callback = cqspi_rx_dma_callback; 1307 tx->callback_param = cqspi; 1308 cookie = tx->tx_submit(tx); 1309 reinit_completion(&cqspi->rx_dma_complete); 1310 1311 ret = dma_submit_error(cookie); 1312 if (ret) { 1313 dev_err(dev, "dma_submit_error %d\n", cookie); 1314 ret = -EIO; 1315 goto err_unmap; 1316 } 1317 1318 dma_async_issue_pending(cqspi->rx_chan); 1319 if (!wait_for_completion_timeout(&cqspi->rx_dma_complete, 1320 msecs_to_jiffies(max_t(size_t, len, 500)))) { 1321 dmaengine_terminate_sync(cqspi->rx_chan); 1322 dev_err(dev, "DMA wait_for_completion_timeout\n"); 1323 ret = -ETIMEDOUT; 1324 goto err_unmap; 1325 } 1326 1327 err_unmap: 1328 dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE); 1329 1330 return ret; 1331 } 1332 1333 static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata, 1334 const struct spi_mem_op *op) 1335 { 1336 struct cqspi_st *cqspi = f_pdata->cqspi; 1337 struct device *dev = &cqspi->pdev->dev; 1338 const struct cqspi_driver_platdata *ddata; 1339 loff_t from = op->addr.val; 1340 size_t len = op->data.nbytes; 1341 u_char *buf = op->data.buf.in; 1342 u64 dma_align = (u64)(uintptr_t)buf; 1343 int ret; 1344 1345 ddata = of_device_get_match_data(dev); 1346 1347 ret = cqspi_read_setup(f_pdata, op); 1348 if (ret) 1349 return ret; 1350 1351 if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) 1352 return cqspi_direct_read_execute(f_pdata, buf, from, len); 1353 1354 if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma && 1355 virt_addr_valid(buf) && ((dma_align & CQSPI_DMA_UNALIGN) == 0)) 1356 return ddata->indirect_read_dma(f_pdata, buf, from, len); 1357 1358 return cqspi_indirect_read_execute(f_pdata, buf, from, len); 1359 } 1360 1361 static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op) 1362 { 1363 struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); 1364 struct cqspi_flash_pdata *f_pdata; 1365 1366 f_pdata = &cqspi->f_pdata[spi_get_chipselect(mem->spi, 0)]; 1367 cqspi_configure(f_pdata, mem->spi->max_speed_hz); 1368 1369 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { 1370 /* 1371 * Performing reads in DAC mode forces to read minimum 4 bytes 1372 * which is unsupported on some flash devices during register 1373 * reads, prefer STIG mode for such small reads. 1374 */ 1375 if (!op->addr.nbytes || 1376 op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX) 1377 return cqspi_command_read(f_pdata, op); 1378 1379 return cqspi_read(f_pdata, op); 1380 } 1381 1382 if (!op->addr.nbytes || !op->data.buf.out) 1383 return cqspi_command_write(f_pdata, op); 1384 1385 return cqspi_write(f_pdata, op); 1386 } 1387 1388 static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) 1389 { 1390 int ret; 1391 1392 ret = cqspi_mem_process(mem, op); 1393 if (ret) 1394 dev_err(&mem->spi->dev, "operation failed with %d\n", ret); 1395 1396 return ret; 1397 } 1398 1399 static bool cqspi_supports_mem_op(struct spi_mem *mem, 1400 const struct spi_mem_op *op) 1401 { 1402 bool all_true, all_false; 1403 1404 /* 1405 * op->dummy.dtr is required for converting nbytes into ncycles. 1406 * Also, don't check the dtr field of the op phase having zero nbytes. 1407 */ 1408 all_true = op->cmd.dtr && 1409 (!op->addr.nbytes || op->addr.dtr) && 1410 (!op->dummy.nbytes || op->dummy.dtr) && 1411 (!op->data.nbytes || op->data.dtr); 1412 1413 all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && 1414 !op->data.dtr; 1415 1416 if (all_true) { 1417 /* Right now we only support 8-8-8 DTR mode. */ 1418 if (op->cmd.nbytes && op->cmd.buswidth != 8) 1419 return false; 1420 if (op->addr.nbytes && op->addr.buswidth != 8) 1421 return false; 1422 if (op->data.nbytes && op->data.buswidth != 8) 1423 return false; 1424 } else if (!all_false) { 1425 /* Mixed DTR modes are not supported. */ 1426 return false; 1427 } 1428 1429 return spi_mem_default_supports_op(mem, op); 1430 } 1431 1432 static int cqspi_of_get_flash_pdata(struct platform_device *pdev, 1433 struct cqspi_flash_pdata *f_pdata, 1434 struct device_node *np) 1435 { 1436 if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) { 1437 dev_err(&pdev->dev, "couldn't determine read-delay\n"); 1438 return -ENXIO; 1439 } 1440 1441 if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) { 1442 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n"); 1443 return -ENXIO; 1444 } 1445 1446 if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) { 1447 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n"); 1448 return -ENXIO; 1449 } 1450 1451 if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) { 1452 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n"); 1453 return -ENXIO; 1454 } 1455 1456 if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) { 1457 dev_err(&pdev->dev, "couldn't determine tslch-ns\n"); 1458 return -ENXIO; 1459 } 1460 1461 if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) { 1462 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n"); 1463 return -ENXIO; 1464 } 1465 1466 return 0; 1467 } 1468 1469 static int cqspi_of_get_pdata(struct cqspi_st *cqspi) 1470 { 1471 struct device *dev = &cqspi->pdev->dev; 1472 struct device_node *np = dev->of_node; 1473 u32 id[2]; 1474 1475 cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); 1476 1477 if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { 1478 dev_err(dev, "couldn't determine fifo-depth\n"); 1479 return -ENXIO; 1480 } 1481 1482 if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) { 1483 dev_err(dev, "couldn't determine fifo-width\n"); 1484 return -ENXIO; 1485 } 1486 1487 if (of_property_read_u32(np, "cdns,trigger-address", 1488 &cqspi->trigger_address)) { 1489 dev_err(dev, "couldn't determine trigger-address\n"); 1490 return -ENXIO; 1491 } 1492 1493 if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) 1494 cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT; 1495 1496 cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); 1497 1498 if (!of_property_read_u32_array(np, "power-domains", id, 1499 ARRAY_SIZE(id))) 1500 cqspi->pd_dev_id = id[1]; 1501 1502 return 0; 1503 } 1504 1505 static void cqspi_controller_init(struct cqspi_st *cqspi) 1506 { 1507 u32 reg; 1508 1509 cqspi_controller_enable(cqspi, 0); 1510 1511 /* Configure the remap address register, no remap */ 1512 writel(0, cqspi->iobase + CQSPI_REG_REMAP); 1513 1514 /* Disable all interrupts. */ 1515 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); 1516 1517 /* Configure the SRAM split to 1:1 . */ 1518 writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); 1519 1520 /* Load indirect trigger address. */ 1521 writel(cqspi->trigger_address, 1522 cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); 1523 1524 /* Program read watermark -- 1/2 of the FIFO. */ 1525 writel(cqspi->fifo_depth * cqspi->fifo_width / 2, 1526 cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); 1527 /* Program write watermark -- 1/8 of the FIFO. */ 1528 writel(cqspi->fifo_depth * cqspi->fifo_width / 8, 1529 cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); 1530 1531 /* Disable direct access controller */ 1532 if (!cqspi->use_direct_mode) { 1533 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 1534 reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL; 1535 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 1536 } 1537 1538 /* Enable DMA interface */ 1539 if (cqspi->use_dma_read) { 1540 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 1541 reg |= CQSPI_REG_CONFIG_DMA_MASK; 1542 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 1543 } 1544 1545 cqspi_controller_enable(cqspi, 1); 1546 } 1547 1548 static int cqspi_request_mmap_dma(struct cqspi_st *cqspi) 1549 { 1550 dma_cap_mask_t mask; 1551 1552 dma_cap_zero(mask); 1553 dma_cap_set(DMA_MEMCPY, mask); 1554 1555 cqspi->rx_chan = dma_request_chan_by_mask(&mask); 1556 if (IS_ERR(cqspi->rx_chan)) { 1557 int ret = PTR_ERR(cqspi->rx_chan); 1558 1559 cqspi->rx_chan = NULL; 1560 return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n"); 1561 } 1562 init_completion(&cqspi->rx_dma_complete); 1563 1564 return 0; 1565 } 1566 1567 static const char *cqspi_get_name(struct spi_mem *mem) 1568 { 1569 struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); 1570 struct device *dev = &cqspi->pdev->dev; 1571 1572 return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), 1573 spi_get_chipselect(mem->spi, 0)); 1574 } 1575 1576 static const struct spi_controller_mem_ops cqspi_mem_ops = { 1577 .exec_op = cqspi_exec_mem_op, 1578 .get_name = cqspi_get_name, 1579 .supports_op = cqspi_supports_mem_op, 1580 }; 1581 1582 static const struct spi_controller_mem_caps cqspi_mem_caps = { 1583 .dtr = true, 1584 }; 1585 1586 static int cqspi_setup_flash(struct cqspi_st *cqspi) 1587 { 1588 struct platform_device *pdev = cqspi->pdev; 1589 struct device *dev = &pdev->dev; 1590 struct device_node *np = dev->of_node; 1591 struct cqspi_flash_pdata *f_pdata; 1592 unsigned int cs; 1593 int ret; 1594 1595 /* Get flash device data */ 1596 for_each_available_child_of_node(dev->of_node, np) { 1597 ret = of_property_read_u32(np, "reg", &cs); 1598 if (ret) { 1599 dev_err(dev, "Couldn't determine chip select.\n"); 1600 of_node_put(np); 1601 return ret; 1602 } 1603 1604 if (cs >= CQSPI_MAX_CHIPSELECT) { 1605 dev_err(dev, "Chip select %d out of range.\n", cs); 1606 of_node_put(np); 1607 return -EINVAL; 1608 } 1609 1610 f_pdata = &cqspi->f_pdata[cs]; 1611 f_pdata->cqspi = cqspi; 1612 f_pdata->cs = cs; 1613 1614 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np); 1615 if (ret) { 1616 of_node_put(np); 1617 return ret; 1618 } 1619 } 1620 1621 return 0; 1622 } 1623 1624 static int cqspi_probe(struct platform_device *pdev) 1625 { 1626 const struct cqspi_driver_platdata *ddata; 1627 struct reset_control *rstc, *rstc_ocp, *rstc_ref; 1628 struct device *dev = &pdev->dev; 1629 struct spi_master *master; 1630 struct resource *res_ahb; 1631 struct cqspi_st *cqspi; 1632 int ret; 1633 int irq; 1634 1635 master = devm_spi_alloc_master(&pdev->dev, sizeof(*cqspi)); 1636 if (!master) { 1637 dev_err(&pdev->dev, "spi_alloc_master failed\n"); 1638 return -ENOMEM; 1639 } 1640 master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; 1641 master->mem_ops = &cqspi_mem_ops; 1642 master->mem_caps = &cqspi_mem_caps; 1643 master->dev.of_node = pdev->dev.of_node; 1644 1645 cqspi = spi_master_get_devdata(master); 1646 1647 cqspi->pdev = pdev; 1648 cqspi->master = master; 1649 platform_set_drvdata(pdev, cqspi); 1650 1651 /* Obtain configuration from OF. */ 1652 ret = cqspi_of_get_pdata(cqspi); 1653 if (ret) { 1654 dev_err(dev, "Cannot get mandatory OF data.\n"); 1655 return -ENODEV; 1656 } 1657 1658 /* Obtain QSPI clock. */ 1659 cqspi->clk = devm_clk_get(dev, NULL); 1660 if (IS_ERR(cqspi->clk)) { 1661 dev_err(dev, "Cannot claim QSPI clock.\n"); 1662 ret = PTR_ERR(cqspi->clk); 1663 return ret; 1664 } 1665 1666 /* Obtain and remap controller address. */ 1667 cqspi->iobase = devm_platform_ioremap_resource(pdev, 0); 1668 if (IS_ERR(cqspi->iobase)) { 1669 dev_err(dev, "Cannot remap controller address.\n"); 1670 ret = PTR_ERR(cqspi->iobase); 1671 return ret; 1672 } 1673 1674 /* Obtain and remap AHB address. */ 1675 cqspi->ahb_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res_ahb); 1676 if (IS_ERR(cqspi->ahb_base)) { 1677 dev_err(dev, "Cannot remap AHB address.\n"); 1678 ret = PTR_ERR(cqspi->ahb_base); 1679 return ret; 1680 } 1681 cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start; 1682 cqspi->ahb_size = resource_size(res_ahb); 1683 1684 init_completion(&cqspi->transfer_complete); 1685 1686 /* Obtain IRQ line. */ 1687 irq = platform_get_irq(pdev, 0); 1688 if (irq < 0) 1689 return -ENXIO; 1690 1691 pm_runtime_enable(dev); 1692 ret = pm_runtime_resume_and_get(dev); 1693 if (ret < 0) 1694 goto probe_pm_failed; 1695 1696 ret = clk_prepare_enable(cqspi->clk); 1697 if (ret) { 1698 dev_err(dev, "Cannot enable QSPI clock.\n"); 1699 goto probe_clk_failed; 1700 } 1701 1702 /* Obtain QSPI reset control */ 1703 rstc = devm_reset_control_get_optional_exclusive(dev, "qspi"); 1704 if (IS_ERR(rstc)) { 1705 ret = PTR_ERR(rstc); 1706 dev_err(dev, "Cannot get QSPI reset.\n"); 1707 goto probe_reset_failed; 1708 } 1709 1710 rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); 1711 if (IS_ERR(rstc_ocp)) { 1712 ret = PTR_ERR(rstc_ocp); 1713 dev_err(dev, "Cannot get QSPI OCP reset.\n"); 1714 goto probe_reset_failed; 1715 } 1716 1717 if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) { 1718 rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref"); 1719 if (IS_ERR(rstc_ref)) { 1720 ret = PTR_ERR(rstc_ref); 1721 dev_err(dev, "Cannot get QSPI REF reset.\n"); 1722 goto probe_reset_failed; 1723 } 1724 reset_control_assert(rstc_ref); 1725 reset_control_deassert(rstc_ref); 1726 } 1727 1728 reset_control_assert(rstc); 1729 reset_control_deassert(rstc); 1730 1731 reset_control_assert(rstc_ocp); 1732 reset_control_deassert(rstc_ocp); 1733 1734 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); 1735 master->max_speed_hz = cqspi->master_ref_clk_hz; 1736 1737 /* write completion is supported by default */ 1738 cqspi->wr_completion = true; 1739 1740 ddata = of_device_get_match_data(dev); 1741 if (ddata) { 1742 if (ddata->quirks & CQSPI_NEEDS_WR_DELAY) 1743 cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, 1744 cqspi->master_ref_clk_hz); 1745 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL) 1746 master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; 1747 if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) { 1748 cqspi->use_direct_mode = true; 1749 cqspi->use_direct_mode_wr = true; 1750 } 1751 if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA) 1752 cqspi->use_dma_read = true; 1753 if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION) 1754 cqspi->wr_completion = false; 1755 if (ddata->quirks & CQSPI_SLOW_SRAM) 1756 cqspi->slow_sram = true; 1757 1758 if (of_device_is_compatible(pdev->dev.of_node, 1759 "xlnx,versal-ospi-1.0")) 1760 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); 1761 } 1762 1763 ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0, 1764 pdev->name, cqspi); 1765 if (ret) { 1766 dev_err(dev, "Cannot request IRQ.\n"); 1767 goto probe_reset_failed; 1768 } 1769 1770 cqspi_wait_idle(cqspi); 1771 cqspi_controller_init(cqspi); 1772 cqspi->current_cs = -1; 1773 cqspi->sclk = 0; 1774 1775 master->num_chipselect = cqspi->num_chipselect; 1776 1777 ret = cqspi_setup_flash(cqspi); 1778 if (ret) { 1779 dev_err(dev, "failed to setup flash parameters %d\n", ret); 1780 goto probe_setup_failed; 1781 } 1782 1783 if (cqspi->use_direct_mode) { 1784 ret = cqspi_request_mmap_dma(cqspi); 1785 if (ret == -EPROBE_DEFER) 1786 goto probe_setup_failed; 1787 } 1788 1789 ret = spi_register_master(master); 1790 if (ret) { 1791 dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret); 1792 goto probe_setup_failed; 1793 } 1794 1795 return 0; 1796 probe_setup_failed: 1797 cqspi_controller_enable(cqspi, 0); 1798 probe_reset_failed: 1799 clk_disable_unprepare(cqspi->clk); 1800 probe_clk_failed: 1801 pm_runtime_put_sync(dev); 1802 probe_pm_failed: 1803 pm_runtime_disable(dev); 1804 return ret; 1805 } 1806 1807 static void cqspi_remove(struct platform_device *pdev) 1808 { 1809 struct cqspi_st *cqspi = platform_get_drvdata(pdev); 1810 1811 spi_unregister_master(cqspi->master); 1812 cqspi_controller_enable(cqspi, 0); 1813 1814 if (cqspi->rx_chan) 1815 dma_release_channel(cqspi->rx_chan); 1816 1817 clk_disable_unprepare(cqspi->clk); 1818 1819 pm_runtime_put_sync(&pdev->dev); 1820 pm_runtime_disable(&pdev->dev); 1821 } 1822 1823 static int cqspi_suspend(struct device *dev) 1824 { 1825 struct cqspi_st *cqspi = dev_get_drvdata(dev); 1826 struct spi_master *master = dev_get_drvdata(dev); 1827 int ret; 1828 1829 ret = spi_master_suspend(master); 1830 cqspi_controller_enable(cqspi, 0); 1831 1832 clk_disable_unprepare(cqspi->clk); 1833 1834 return ret; 1835 } 1836 1837 static int cqspi_resume(struct device *dev) 1838 { 1839 struct cqspi_st *cqspi = dev_get_drvdata(dev); 1840 struct spi_master *master = dev_get_drvdata(dev); 1841 1842 clk_prepare_enable(cqspi->clk); 1843 cqspi_wait_idle(cqspi); 1844 cqspi_controller_init(cqspi); 1845 1846 cqspi->current_cs = -1; 1847 cqspi->sclk = 0; 1848 1849 return spi_master_resume(master); 1850 } 1851 1852 static DEFINE_SIMPLE_DEV_PM_OPS(cqspi_dev_pm_ops, cqspi_suspend, cqspi_resume); 1853 1854 static const struct cqspi_driver_platdata cdns_qspi = { 1855 .quirks = CQSPI_DISABLE_DAC_MODE, 1856 }; 1857 1858 static const struct cqspi_driver_platdata k2g_qspi = { 1859 .quirks = CQSPI_NEEDS_WR_DELAY, 1860 }; 1861 1862 static const struct cqspi_driver_platdata am654_ospi = { 1863 .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 1864 .quirks = CQSPI_NEEDS_WR_DELAY, 1865 }; 1866 1867 static const struct cqspi_driver_platdata intel_lgm_qspi = { 1868 .quirks = CQSPI_DISABLE_DAC_MODE, 1869 }; 1870 1871 static const struct cqspi_driver_platdata socfpga_qspi = { 1872 .quirks = CQSPI_DISABLE_DAC_MODE 1873 | CQSPI_NO_SUPPORT_WR_COMPLETION 1874 | CQSPI_SLOW_SRAM, 1875 }; 1876 1877 static const struct cqspi_driver_platdata versal_ospi = { 1878 .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 1879 .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA, 1880 .indirect_read_dma = cqspi_versal_indirect_read_dma, 1881 .get_dma_status = cqspi_get_versal_dma_status, 1882 }; 1883 1884 static const struct cqspi_driver_platdata jh7110_qspi = { 1885 .quirks = CQSPI_DISABLE_DAC_MODE, 1886 }; 1887 1888 static const struct of_device_id cqspi_dt_ids[] = { 1889 { 1890 .compatible = "cdns,qspi-nor", 1891 .data = &cdns_qspi, 1892 }, 1893 { 1894 .compatible = "ti,k2g-qspi", 1895 .data = &k2g_qspi, 1896 }, 1897 { 1898 .compatible = "ti,am654-ospi", 1899 .data = &am654_ospi, 1900 }, 1901 { 1902 .compatible = "intel,lgm-qspi", 1903 .data = &intel_lgm_qspi, 1904 }, 1905 { 1906 .compatible = "xlnx,versal-ospi-1.0", 1907 .data = &versal_ospi, 1908 }, 1909 { 1910 .compatible = "intel,socfpga-qspi", 1911 .data = &socfpga_qspi, 1912 }, 1913 { 1914 .compatible = "starfive,jh7110-qspi", 1915 .data = &jh7110_qspi, 1916 }, 1917 { /* end of table */ } 1918 }; 1919 1920 MODULE_DEVICE_TABLE(of, cqspi_dt_ids); 1921 1922 static struct platform_driver cqspi_platform_driver = { 1923 .probe = cqspi_probe, 1924 .remove_new = cqspi_remove, 1925 .driver = { 1926 .name = CQSPI_NAME, 1927 .pm = &cqspi_dev_pm_ops, 1928 .of_match_table = cqspi_dt_ids, 1929 }, 1930 }; 1931 1932 module_platform_driver(cqspi_platform_driver); 1933 1934 MODULE_DESCRIPTION("Cadence QSPI Controller Driver"); 1935 MODULE_LICENSE("GPL v2"); 1936 MODULE_ALIAS("platform:" CQSPI_NAME); 1937 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>"); 1938 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>"); 1939 MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>"); 1940 MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>"); 1941 MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>"); 1942