1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Driver for Cadence QSPI Controller 4 // 5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved. 6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved. 7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 8 9 #include <linux/clk.h> 10 #include <linux/completion.h> 11 #include <linux/delay.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/dmaengine.h> 14 #include <linux/err.h> 15 #include <linux/errno.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/iopoll.h> 19 #include <linux/jiffies.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/of_device.h> 23 #include <linux/of.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/reset.h> 27 #include <linux/sched.h> 28 #include <linux/spi/spi.h> 29 #include <linux/spi/spi-mem.h> 30 #include <linux/timer.h> 31 32 #define CQSPI_NAME "cadence-qspi" 33 #define CQSPI_MAX_CHIPSELECT 16 34 35 /* Quirks */ 36 #define CQSPI_NEEDS_WR_DELAY BIT(0) 37 #define CQSPI_DISABLE_DAC_MODE BIT(1) 38 39 /* Capabilities */ 40 #define CQSPI_SUPPORTS_OCTAL BIT(0) 41 42 struct cqspi_st; 43 44 struct cqspi_flash_pdata { 45 struct cqspi_st *cqspi; 46 u32 clk_rate; 47 u32 read_delay; 48 u32 tshsl_ns; 49 u32 tsd2d_ns; 50 u32 tchsh_ns; 51 u32 tslch_ns; 52 u8 inst_width; 53 u8 addr_width; 54 u8 data_width; 55 bool dtr; 56 u8 cs; 57 }; 58 59 struct cqspi_st { 60 struct platform_device *pdev; 61 62 struct clk *clk; 63 unsigned int sclk; 64 65 void __iomem *iobase; 66 void __iomem *ahb_base; 67 resource_size_t ahb_size; 68 struct completion transfer_complete; 69 70 struct dma_chan *rx_chan; 71 struct completion rx_dma_complete; 72 dma_addr_t mmap_phys_base; 73 74 int current_cs; 75 unsigned long master_ref_clk_hz; 76 bool is_decoded_cs; 77 u32 fifo_depth; 78 u32 fifo_width; 79 u32 num_chipselect; 80 bool rclk_en; 81 u32 trigger_address; 82 u32 wr_delay; 83 bool use_direct_mode; 84 struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; 85 }; 86 87 struct cqspi_driver_platdata { 88 u32 hwcaps_mask; 89 u8 quirks; 90 }; 91 92 /* Operation timeout value */ 93 #define CQSPI_TIMEOUT_MS 500 94 #define CQSPI_READ_TIMEOUT_MS 10 95 96 /* Instruction type */ 97 #define CQSPI_INST_TYPE_SINGLE 0 98 #define CQSPI_INST_TYPE_DUAL 1 99 #define CQSPI_INST_TYPE_QUAD 2 100 #define CQSPI_INST_TYPE_OCTAL 3 101 102 #define CQSPI_DUMMY_CLKS_PER_BYTE 8 103 #define CQSPI_DUMMY_BYTES_MAX 4 104 #define CQSPI_DUMMY_CLKS_MAX 31 105 106 #define CQSPI_STIG_DATA_LEN_MAX 8 107 108 /* Register map */ 109 #define CQSPI_REG_CONFIG 0x00 110 #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0) 111 #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7) 112 #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9) 113 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 114 #define CQSPI_REG_CONFIG_DMA_MASK BIT(15) 115 #define CQSPI_REG_CONFIG_BAUD_LSB 19 116 #define CQSPI_REG_CONFIG_DTR_PROTO BIT(24) 117 #define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30) 118 #define CQSPI_REG_CONFIG_IDLE_LSB 31 119 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF 120 #define CQSPI_REG_CONFIG_BAUD_MASK 0xF 121 122 #define CQSPI_REG_RD_INSTR 0x04 123 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 124 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 125 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 126 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 127 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 128 #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 129 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 130 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 131 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 132 #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F 133 134 #define CQSPI_REG_WR_INSTR 0x08 135 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 136 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12 137 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16 138 139 #define CQSPI_REG_DELAY 0x0C 140 #define CQSPI_REG_DELAY_TSLCH_LSB 0 141 #define CQSPI_REG_DELAY_TCHSH_LSB 8 142 #define CQSPI_REG_DELAY_TSD2D_LSB 16 143 #define CQSPI_REG_DELAY_TSHSL_LSB 24 144 #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF 145 #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF 146 #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF 147 #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF 148 149 #define CQSPI_REG_READCAPTURE 0x10 150 #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0 151 #define CQSPI_REG_READCAPTURE_DELAY_LSB 1 152 #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF 153 154 #define CQSPI_REG_SIZE 0x14 155 #define CQSPI_REG_SIZE_ADDRESS_LSB 0 156 #define CQSPI_REG_SIZE_PAGE_LSB 4 157 #define CQSPI_REG_SIZE_BLOCK_LSB 16 158 #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF 159 #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF 160 #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F 161 162 #define CQSPI_REG_SRAMPARTITION 0x18 163 #define CQSPI_REG_INDIRECTTRIGGER 0x1C 164 165 #define CQSPI_REG_DMA 0x20 166 #define CQSPI_REG_DMA_SINGLE_LSB 0 167 #define CQSPI_REG_DMA_BURST_LSB 8 168 #define CQSPI_REG_DMA_SINGLE_MASK 0xFF 169 #define CQSPI_REG_DMA_BURST_MASK 0xFF 170 171 #define CQSPI_REG_REMAP 0x24 172 #define CQSPI_REG_MODE_BIT 0x28 173 174 #define CQSPI_REG_SDRAMLEVEL 0x2C 175 #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 176 #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 177 #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF 178 #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF 179 180 #define CQSPI_REG_WR_COMPLETION_CTRL 0x38 181 #define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14) 182 183 #define CQSPI_REG_IRQSTATUS 0x40 184 #define CQSPI_REG_IRQMASK 0x44 185 186 #define CQSPI_REG_INDIRECTRD 0x60 187 #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0) 188 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1) 189 #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5) 190 191 #define CQSPI_REG_INDIRECTRDWATERMARK 0x64 192 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 193 #define CQSPI_REG_INDIRECTRDBYTES 0x6C 194 195 #define CQSPI_REG_CMDCTRL 0x90 196 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0) 197 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1) 198 #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 199 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 200 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 201 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 202 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 203 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 204 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 205 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 206 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 207 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 208 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 209 #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F 210 211 #define CQSPI_REG_INDIRECTWR 0x70 212 #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0) 213 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1) 214 #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5) 215 216 #define CQSPI_REG_INDIRECTWRWATERMARK 0x74 217 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 218 #define CQSPI_REG_INDIRECTWRBYTES 0x7C 219 220 #define CQSPI_REG_CMDADDRESS 0x94 221 #define CQSPI_REG_CMDREADDATALOWER 0xA0 222 #define CQSPI_REG_CMDREADDATAUPPER 0xA4 223 #define CQSPI_REG_CMDWRITEDATALOWER 0xA8 224 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC 225 226 #define CQSPI_REG_POLLING_STATUS 0xB0 227 #define CQSPI_REG_POLLING_STATUS_DUMMY_LSB 16 228 229 #define CQSPI_REG_OP_EXT_LOWER 0xE0 230 #define CQSPI_REG_OP_EXT_READ_LSB 24 231 #define CQSPI_REG_OP_EXT_WRITE_LSB 16 232 #define CQSPI_REG_OP_EXT_STIG_LSB 0 233 234 /* Interrupt status bits */ 235 #define CQSPI_REG_IRQ_MODE_ERR BIT(0) 236 #define CQSPI_REG_IRQ_UNDERFLOW BIT(1) 237 #define CQSPI_REG_IRQ_IND_COMP BIT(2) 238 #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3) 239 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4) 240 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5) 241 #define CQSPI_REG_IRQ_WATERMARK BIT(6) 242 #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12) 243 244 #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \ 245 CQSPI_REG_IRQ_IND_SRAM_FULL | \ 246 CQSPI_REG_IRQ_IND_COMP) 247 248 #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \ 249 CQSPI_REG_IRQ_WATERMARK | \ 250 CQSPI_REG_IRQ_UNDERFLOW) 251 252 #define CQSPI_IRQ_STATUS_MASK 0x1FFFF 253 254 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr) 255 { 256 u32 val; 257 258 return readl_relaxed_poll_timeout(reg, val, 259 (((clr ? ~val : val) & mask) == mask), 260 10, CQSPI_TIMEOUT_MS * 1000); 261 } 262 263 static bool cqspi_is_idle(struct cqspi_st *cqspi) 264 { 265 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 266 267 return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB); 268 } 269 270 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi) 271 { 272 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL); 273 274 reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB; 275 return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK; 276 } 277 278 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev) 279 { 280 struct cqspi_st *cqspi = dev; 281 unsigned int irq_status; 282 283 /* Read interrupt status */ 284 irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS); 285 286 /* Clear interrupt */ 287 writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS); 288 289 irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR; 290 291 if (irq_status) 292 complete(&cqspi->transfer_complete); 293 294 return IRQ_HANDLED; 295 } 296 297 static unsigned int cqspi_calc_rdreg(struct cqspi_flash_pdata *f_pdata) 298 { 299 u32 rdreg = 0; 300 301 rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; 302 rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; 303 rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; 304 305 return rdreg; 306 } 307 308 static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op, bool dtr) 309 { 310 unsigned int dummy_clk; 311 312 if (!op->dummy.nbytes) 313 return 0; 314 315 dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth); 316 if (dtr) 317 dummy_clk /= 2; 318 319 return dummy_clk; 320 } 321 322 static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata, 323 const struct spi_mem_op *op) 324 { 325 f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE; 326 f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE; 327 f_pdata->data_width = CQSPI_INST_TYPE_SINGLE; 328 f_pdata->dtr = op->data.dtr && op->cmd.dtr && op->addr.dtr; 329 330 switch (op->data.buswidth) { 331 case 0: 332 break; 333 case 1: 334 f_pdata->data_width = CQSPI_INST_TYPE_SINGLE; 335 break; 336 case 2: 337 f_pdata->data_width = CQSPI_INST_TYPE_DUAL; 338 break; 339 case 4: 340 f_pdata->data_width = CQSPI_INST_TYPE_QUAD; 341 break; 342 case 8: 343 f_pdata->data_width = CQSPI_INST_TYPE_OCTAL; 344 break; 345 default: 346 return -EINVAL; 347 } 348 349 /* Right now we only support 8-8-8 DTR mode. */ 350 if (f_pdata->dtr) { 351 switch (op->cmd.buswidth) { 352 case 0: 353 break; 354 case 8: 355 f_pdata->inst_width = CQSPI_INST_TYPE_OCTAL; 356 break; 357 default: 358 return -EINVAL; 359 } 360 361 switch (op->addr.buswidth) { 362 case 0: 363 break; 364 case 8: 365 f_pdata->addr_width = CQSPI_INST_TYPE_OCTAL; 366 break; 367 default: 368 return -EINVAL; 369 } 370 371 switch (op->data.buswidth) { 372 case 0: 373 break; 374 case 8: 375 f_pdata->data_width = CQSPI_INST_TYPE_OCTAL; 376 break; 377 default: 378 return -EINVAL; 379 } 380 } 381 382 return 0; 383 } 384 385 static int cqspi_wait_idle(struct cqspi_st *cqspi) 386 { 387 const unsigned int poll_idle_retry = 3; 388 unsigned int count = 0; 389 unsigned long timeout; 390 391 timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS); 392 while (1) { 393 /* 394 * Read few times in succession to ensure the controller 395 * is indeed idle, that is, the bit does not transition 396 * low again. 397 */ 398 if (cqspi_is_idle(cqspi)) 399 count++; 400 else 401 count = 0; 402 403 if (count >= poll_idle_retry) 404 return 0; 405 406 if (time_after(jiffies, timeout)) { 407 /* Timeout, in busy mode. */ 408 dev_err(&cqspi->pdev->dev, 409 "QSPI is still busy after %dms timeout.\n", 410 CQSPI_TIMEOUT_MS); 411 return -ETIMEDOUT; 412 } 413 414 cpu_relax(); 415 } 416 } 417 418 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg) 419 { 420 void __iomem *reg_base = cqspi->iobase; 421 int ret; 422 423 /* Write the CMDCTRL without start execution. */ 424 writel(reg, reg_base + CQSPI_REG_CMDCTRL); 425 /* Start execute */ 426 reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK; 427 writel(reg, reg_base + CQSPI_REG_CMDCTRL); 428 429 /* Polling for completion. */ 430 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL, 431 CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1); 432 if (ret) { 433 dev_err(&cqspi->pdev->dev, 434 "Flash command execution timed out.\n"); 435 return ret; 436 } 437 438 /* Polling QSPI idle status. */ 439 return cqspi_wait_idle(cqspi); 440 } 441 442 static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata, 443 const struct spi_mem_op *op, 444 unsigned int shift) 445 { 446 struct cqspi_st *cqspi = f_pdata->cqspi; 447 void __iomem *reg_base = cqspi->iobase; 448 unsigned int reg; 449 u8 ext; 450 451 if (op->cmd.nbytes != 2) 452 return -EINVAL; 453 454 /* Opcode extension is the LSB. */ 455 ext = op->cmd.opcode & 0xff; 456 457 reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER); 458 reg &= ~(0xff << shift); 459 reg |= ext << shift; 460 writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER); 461 462 return 0; 463 } 464 465 static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata, 466 const struct spi_mem_op *op, unsigned int shift, 467 bool enable) 468 { 469 struct cqspi_st *cqspi = f_pdata->cqspi; 470 void __iomem *reg_base = cqspi->iobase; 471 unsigned int reg; 472 int ret; 473 474 reg = readl(reg_base + CQSPI_REG_CONFIG); 475 476 /* 477 * We enable dual byte opcode here. The callers have to set up the 478 * extension opcode based on which type of operation it is. 479 */ 480 if (enable) { 481 reg |= CQSPI_REG_CONFIG_DTR_PROTO; 482 reg |= CQSPI_REG_CONFIG_DUAL_OPCODE; 483 484 /* Set up command opcode extension. */ 485 ret = cqspi_setup_opcode_ext(f_pdata, op, shift); 486 if (ret) 487 return ret; 488 } else { 489 reg &= ~CQSPI_REG_CONFIG_DTR_PROTO; 490 reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE; 491 } 492 493 writel(reg, reg_base + CQSPI_REG_CONFIG); 494 495 return cqspi_wait_idle(cqspi); 496 } 497 498 static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, 499 const struct spi_mem_op *op) 500 { 501 struct cqspi_st *cqspi = f_pdata->cqspi; 502 void __iomem *reg_base = cqspi->iobase; 503 u8 *rxbuf = op->data.buf.in; 504 u8 opcode; 505 size_t n_rx = op->data.nbytes; 506 unsigned int rdreg; 507 unsigned int reg; 508 unsigned int dummy_clk; 509 size_t read_len; 510 int status; 511 512 status = cqspi_set_protocol(f_pdata, op); 513 if (status) 514 return status; 515 516 status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB, 517 f_pdata->dtr); 518 if (status) 519 return status; 520 521 if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) { 522 dev_err(&cqspi->pdev->dev, 523 "Invalid input argument, len %zu rxbuf 0x%p\n", 524 n_rx, rxbuf); 525 return -EINVAL; 526 } 527 528 if (f_pdata->dtr) 529 opcode = op->cmd.opcode >> 8; 530 else 531 opcode = op->cmd.opcode; 532 533 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 534 535 rdreg = cqspi_calc_rdreg(f_pdata); 536 writel(rdreg, reg_base + CQSPI_REG_RD_INSTR); 537 538 dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr); 539 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 540 return -EOPNOTSUPP; 541 542 if (dummy_clk) 543 reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK) 544 << CQSPI_REG_CMDCTRL_DUMMY_LSB; 545 546 reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); 547 548 /* 0 means 1 byte. */ 549 reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) 550 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); 551 status = cqspi_exec_flash_cmd(cqspi, reg); 552 if (status) 553 return status; 554 555 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER); 556 557 /* Put the read value into rx_buf */ 558 read_len = (n_rx > 4) ? 4 : n_rx; 559 memcpy(rxbuf, ®, read_len); 560 rxbuf += read_len; 561 562 if (n_rx > 4) { 563 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER); 564 565 read_len = n_rx - read_len; 566 memcpy(rxbuf, ®, read_len); 567 } 568 569 return 0; 570 } 571 572 static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata, 573 const struct spi_mem_op *op) 574 { 575 struct cqspi_st *cqspi = f_pdata->cqspi; 576 void __iomem *reg_base = cqspi->iobase; 577 u8 opcode; 578 const u8 *txbuf = op->data.buf.out; 579 size_t n_tx = op->data.nbytes; 580 unsigned int reg; 581 unsigned int data; 582 size_t write_len; 583 int ret; 584 585 ret = cqspi_set_protocol(f_pdata, op); 586 if (ret) 587 return ret; 588 589 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB, 590 f_pdata->dtr); 591 if (ret) 592 return ret; 593 594 if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) { 595 dev_err(&cqspi->pdev->dev, 596 "Invalid input argument, cmdlen %zu txbuf 0x%p\n", 597 n_tx, txbuf); 598 return -EINVAL; 599 } 600 601 reg = cqspi_calc_rdreg(f_pdata); 602 writel(reg, reg_base + CQSPI_REG_RD_INSTR); 603 604 if (f_pdata->dtr) 605 opcode = op->cmd.opcode >> 8; 606 else 607 opcode = op->cmd.opcode; 608 609 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 610 611 if (op->addr.nbytes) { 612 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 613 reg |= ((op->addr.nbytes - 1) & 614 CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) 615 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; 616 617 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); 618 } 619 620 if (n_tx) { 621 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB); 622 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) 623 << CQSPI_REG_CMDCTRL_WR_BYTES_LSB; 624 data = 0; 625 write_len = (n_tx > 4) ? 4 : n_tx; 626 memcpy(&data, txbuf, write_len); 627 txbuf += write_len; 628 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER); 629 630 if (n_tx > 4) { 631 data = 0; 632 write_len = n_tx - 4; 633 memcpy(&data, txbuf, write_len); 634 writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER); 635 } 636 } 637 638 return cqspi_exec_flash_cmd(cqspi, reg); 639 } 640 641 static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata, 642 const struct spi_mem_op *op) 643 { 644 struct cqspi_st *cqspi = f_pdata->cqspi; 645 void __iomem *reg_base = cqspi->iobase; 646 unsigned int dummy_clk = 0; 647 unsigned int reg; 648 int ret; 649 u8 opcode; 650 651 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB, 652 f_pdata->dtr); 653 if (ret) 654 return ret; 655 656 if (f_pdata->dtr) 657 opcode = op->cmd.opcode >> 8; 658 else 659 opcode = op->cmd.opcode; 660 661 reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB; 662 reg |= cqspi_calc_rdreg(f_pdata); 663 664 /* Setup dummy clock cycles */ 665 dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr); 666 667 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 668 return -EOPNOTSUPP; 669 670 if (dummy_clk) 671 reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK) 672 << CQSPI_REG_RD_INSTR_DUMMY_LSB; 673 674 writel(reg, reg_base + CQSPI_REG_RD_INSTR); 675 676 /* Set address width */ 677 reg = readl(reg_base + CQSPI_REG_SIZE); 678 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 679 reg |= (op->addr.nbytes - 1); 680 writel(reg, reg_base + CQSPI_REG_SIZE); 681 return 0; 682 } 683 684 static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, 685 u8 *rxbuf, loff_t from_addr, 686 const size_t n_rx) 687 { 688 struct cqspi_st *cqspi = f_pdata->cqspi; 689 struct device *dev = &cqspi->pdev->dev; 690 void __iomem *reg_base = cqspi->iobase; 691 void __iomem *ahb_base = cqspi->ahb_base; 692 unsigned int remaining = n_rx; 693 unsigned int mod_bytes = n_rx % 4; 694 unsigned int bytes_to_read = 0; 695 u8 *rxbuf_end = rxbuf + n_rx; 696 int ret = 0; 697 698 writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 699 writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES); 700 701 /* Clear all interrupts. */ 702 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 703 704 writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK); 705 706 reinit_completion(&cqspi->transfer_complete); 707 writel(CQSPI_REG_INDIRECTRD_START_MASK, 708 reg_base + CQSPI_REG_INDIRECTRD); 709 710 while (remaining > 0) { 711 if (!wait_for_completion_timeout(&cqspi->transfer_complete, 712 msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) 713 ret = -ETIMEDOUT; 714 715 bytes_to_read = cqspi_get_rd_sram_level(cqspi); 716 717 if (ret && bytes_to_read == 0) { 718 dev_err(dev, "Indirect read timeout, no bytes\n"); 719 goto failrd; 720 } 721 722 while (bytes_to_read != 0) { 723 unsigned int word_remain = round_down(remaining, 4); 724 725 bytes_to_read *= cqspi->fifo_width; 726 bytes_to_read = bytes_to_read > remaining ? 727 remaining : bytes_to_read; 728 bytes_to_read = round_down(bytes_to_read, 4); 729 /* Read 4 byte word chunks then single bytes */ 730 if (bytes_to_read) { 731 ioread32_rep(ahb_base, rxbuf, 732 (bytes_to_read / 4)); 733 } else if (!word_remain && mod_bytes) { 734 unsigned int temp = ioread32(ahb_base); 735 736 bytes_to_read = mod_bytes; 737 memcpy(rxbuf, &temp, min((unsigned int) 738 (rxbuf_end - rxbuf), 739 bytes_to_read)); 740 } 741 rxbuf += bytes_to_read; 742 remaining -= bytes_to_read; 743 bytes_to_read = cqspi_get_rd_sram_level(cqspi); 744 } 745 746 if (remaining > 0) 747 reinit_completion(&cqspi->transfer_complete); 748 } 749 750 /* Check indirect done status */ 751 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD, 752 CQSPI_REG_INDIRECTRD_DONE_MASK, 0); 753 if (ret) { 754 dev_err(dev, "Indirect read completion error (%i)\n", ret); 755 goto failrd; 756 } 757 758 /* Disable interrupt */ 759 writel(0, reg_base + CQSPI_REG_IRQMASK); 760 761 /* Clear indirect completion status */ 762 writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD); 763 764 return 0; 765 766 failrd: 767 /* Disable interrupt */ 768 writel(0, reg_base + CQSPI_REG_IRQMASK); 769 770 /* Cancel the indirect read */ 771 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 772 reg_base + CQSPI_REG_INDIRECTRD); 773 return ret; 774 } 775 776 static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata, 777 const struct spi_mem_op *op) 778 { 779 unsigned int reg; 780 int ret; 781 struct cqspi_st *cqspi = f_pdata->cqspi; 782 void __iomem *reg_base = cqspi->iobase; 783 u8 opcode; 784 785 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB, 786 f_pdata->dtr); 787 if (ret) 788 return ret; 789 790 if (f_pdata->dtr) 791 opcode = op->cmd.opcode >> 8; 792 else 793 opcode = op->cmd.opcode; 794 795 /* Set opcode. */ 796 reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; 797 reg |= f_pdata->data_width << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; 798 reg |= f_pdata->addr_width << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; 799 writel(reg, reg_base + CQSPI_REG_WR_INSTR); 800 reg = cqspi_calc_rdreg(f_pdata); 801 writel(reg, reg_base + CQSPI_REG_RD_INSTR); 802 803 /* 804 * SPI NAND flashes require the address of the status register to be 805 * passed in the Read SR command. Also, some SPI NOR flashes like the 806 * cypress Semper flash expect a 4-byte dummy address in the Read SR 807 * command in DTR mode. 808 * 809 * But this controller does not support address phase in the Read SR 810 * command when doing auto-HW polling. So, disable write completion 811 * polling on the controller's side. spinand and spi-nor will take 812 * care of polling the status register. 813 */ 814 reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL); 815 reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL; 816 writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL); 817 818 reg = readl(reg_base + CQSPI_REG_SIZE); 819 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 820 reg |= (op->addr.nbytes - 1); 821 writel(reg, reg_base + CQSPI_REG_SIZE); 822 return 0; 823 } 824 825 static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, 826 loff_t to_addr, const u8 *txbuf, 827 const size_t n_tx) 828 { 829 struct cqspi_st *cqspi = f_pdata->cqspi; 830 struct device *dev = &cqspi->pdev->dev; 831 void __iomem *reg_base = cqspi->iobase; 832 unsigned int remaining = n_tx; 833 unsigned int write_bytes; 834 int ret; 835 836 writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR); 837 writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES); 838 839 /* Clear all interrupts. */ 840 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 841 842 writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK); 843 844 reinit_completion(&cqspi->transfer_complete); 845 writel(CQSPI_REG_INDIRECTWR_START_MASK, 846 reg_base + CQSPI_REG_INDIRECTWR); 847 /* 848 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access 849 * Controller programming sequence, couple of cycles of 850 * QSPI_REF_CLK delay is required for the above bit to 851 * be internally synchronized by the QSPI module. Provide 5 852 * cycles of delay. 853 */ 854 if (cqspi->wr_delay) 855 ndelay(cqspi->wr_delay); 856 857 while (remaining > 0) { 858 size_t write_words, mod_bytes; 859 860 write_bytes = remaining; 861 write_words = write_bytes / 4; 862 mod_bytes = write_bytes % 4; 863 /* Write 4 bytes at a time then single bytes. */ 864 if (write_words) { 865 iowrite32_rep(cqspi->ahb_base, txbuf, write_words); 866 txbuf += (write_words * 4); 867 } 868 if (mod_bytes) { 869 unsigned int temp = 0xFFFFFFFF; 870 871 memcpy(&temp, txbuf, mod_bytes); 872 iowrite32(temp, cqspi->ahb_base); 873 txbuf += mod_bytes; 874 } 875 876 if (!wait_for_completion_timeout(&cqspi->transfer_complete, 877 msecs_to_jiffies(CQSPI_TIMEOUT_MS))) { 878 dev_err(dev, "Indirect write timeout\n"); 879 ret = -ETIMEDOUT; 880 goto failwr; 881 } 882 883 remaining -= write_bytes; 884 885 if (remaining > 0) 886 reinit_completion(&cqspi->transfer_complete); 887 } 888 889 /* Check indirect done status */ 890 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR, 891 CQSPI_REG_INDIRECTWR_DONE_MASK, 0); 892 if (ret) { 893 dev_err(dev, "Indirect write completion error (%i)\n", ret); 894 goto failwr; 895 } 896 897 /* Disable interrupt. */ 898 writel(0, reg_base + CQSPI_REG_IRQMASK); 899 900 /* Clear indirect completion status */ 901 writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR); 902 903 cqspi_wait_idle(cqspi); 904 905 return 0; 906 907 failwr: 908 /* Disable interrupt. */ 909 writel(0, reg_base + CQSPI_REG_IRQMASK); 910 911 /* Cancel the indirect write */ 912 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 913 reg_base + CQSPI_REG_INDIRECTWR); 914 return ret; 915 } 916 917 static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata) 918 { 919 struct cqspi_st *cqspi = f_pdata->cqspi; 920 void __iomem *reg_base = cqspi->iobase; 921 unsigned int chip_select = f_pdata->cs; 922 unsigned int reg; 923 924 reg = readl(reg_base + CQSPI_REG_CONFIG); 925 if (cqspi->is_decoded_cs) { 926 reg |= CQSPI_REG_CONFIG_DECODE_MASK; 927 } else { 928 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; 929 930 /* Convert CS if without decoder. 931 * CS0 to 4b'1110 932 * CS1 to 4b'1101 933 * CS2 to 4b'1011 934 * CS3 to 4b'0111 935 */ 936 chip_select = 0xF & ~(1 << chip_select); 937 } 938 939 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK 940 << CQSPI_REG_CONFIG_CHIPSELECT_LSB); 941 reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK) 942 << CQSPI_REG_CONFIG_CHIPSELECT_LSB; 943 writel(reg, reg_base + CQSPI_REG_CONFIG); 944 } 945 946 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz, 947 const unsigned int ns_val) 948 { 949 unsigned int ticks; 950 951 ticks = ref_clk_hz / 1000; /* kHz */ 952 ticks = DIV_ROUND_UP(ticks * ns_val, 1000000); 953 954 return ticks; 955 } 956 957 static void cqspi_delay(struct cqspi_flash_pdata *f_pdata) 958 { 959 struct cqspi_st *cqspi = f_pdata->cqspi; 960 void __iomem *iobase = cqspi->iobase; 961 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 962 unsigned int tshsl, tchsh, tslch, tsd2d; 963 unsigned int reg; 964 unsigned int tsclk; 965 966 /* calculate the number of ref ticks for one sclk tick */ 967 tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk); 968 969 tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns); 970 /* this particular value must be at least one sclk */ 971 if (tshsl < tsclk) 972 tshsl = tsclk; 973 974 tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns); 975 tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns); 976 tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns); 977 978 reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK) 979 << CQSPI_REG_DELAY_TSHSL_LSB; 980 reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK) 981 << CQSPI_REG_DELAY_TCHSH_LSB; 982 reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK) 983 << CQSPI_REG_DELAY_TSLCH_LSB; 984 reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK) 985 << CQSPI_REG_DELAY_TSD2D_LSB; 986 writel(reg, iobase + CQSPI_REG_DELAY); 987 } 988 989 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi) 990 { 991 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 992 void __iomem *reg_base = cqspi->iobase; 993 u32 reg, div; 994 995 /* Recalculate the baudrate divisor based on QSPI specification. */ 996 div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1; 997 998 reg = readl(reg_base + CQSPI_REG_CONFIG); 999 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); 1000 reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB; 1001 writel(reg, reg_base + CQSPI_REG_CONFIG); 1002 } 1003 1004 static void cqspi_readdata_capture(struct cqspi_st *cqspi, 1005 const bool bypass, 1006 const unsigned int delay) 1007 { 1008 void __iomem *reg_base = cqspi->iobase; 1009 unsigned int reg; 1010 1011 reg = readl(reg_base + CQSPI_REG_READCAPTURE); 1012 1013 if (bypass) 1014 reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 1015 else 1016 reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 1017 1018 reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK 1019 << CQSPI_REG_READCAPTURE_DELAY_LSB); 1020 1021 reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK) 1022 << CQSPI_REG_READCAPTURE_DELAY_LSB; 1023 1024 writel(reg, reg_base + CQSPI_REG_READCAPTURE); 1025 } 1026 1027 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable) 1028 { 1029 void __iomem *reg_base = cqspi->iobase; 1030 unsigned int reg; 1031 1032 reg = readl(reg_base + CQSPI_REG_CONFIG); 1033 1034 if (enable) 1035 reg |= CQSPI_REG_CONFIG_ENABLE_MASK; 1036 else 1037 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; 1038 1039 writel(reg, reg_base + CQSPI_REG_CONFIG); 1040 } 1041 1042 static void cqspi_configure(struct cqspi_flash_pdata *f_pdata, 1043 unsigned long sclk) 1044 { 1045 struct cqspi_st *cqspi = f_pdata->cqspi; 1046 int switch_cs = (cqspi->current_cs != f_pdata->cs); 1047 int switch_ck = (cqspi->sclk != sclk); 1048 1049 if (switch_cs || switch_ck) 1050 cqspi_controller_enable(cqspi, 0); 1051 1052 /* Switch chip select. */ 1053 if (switch_cs) { 1054 cqspi->current_cs = f_pdata->cs; 1055 cqspi_chipselect(f_pdata); 1056 } 1057 1058 /* Setup baudrate divisor and delays */ 1059 if (switch_ck) { 1060 cqspi->sclk = sclk; 1061 cqspi_config_baudrate_div(cqspi); 1062 cqspi_delay(f_pdata); 1063 cqspi_readdata_capture(cqspi, !cqspi->rclk_en, 1064 f_pdata->read_delay); 1065 } 1066 1067 if (switch_cs || switch_ck) 1068 cqspi_controller_enable(cqspi, 1); 1069 } 1070 1071 static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata, 1072 const struct spi_mem_op *op) 1073 { 1074 struct cqspi_st *cqspi = f_pdata->cqspi; 1075 loff_t to = op->addr.val; 1076 size_t len = op->data.nbytes; 1077 const u_char *buf = op->data.buf.out; 1078 int ret; 1079 1080 ret = cqspi_set_protocol(f_pdata, op); 1081 if (ret) 1082 return ret; 1083 1084 ret = cqspi_write_setup(f_pdata, op); 1085 if (ret) 1086 return ret; 1087 1088 /* 1089 * Some flashes like the Cypress Semper flash expect a dummy 4-byte 1090 * address (all 0s) with the read status register command in DTR mode. 1091 * But this controller does not support sending dummy address bytes to 1092 * the flash when it is polling the write completion register in DTR 1093 * mode. So, we can not use direct mode when in DTR mode for writing 1094 * data. 1095 */ 1096 if (!f_pdata->dtr && cqspi->use_direct_mode && 1097 ((to + len) <= cqspi->ahb_size)) { 1098 memcpy_toio(cqspi->ahb_base + to, buf, len); 1099 return cqspi_wait_idle(cqspi); 1100 } 1101 1102 return cqspi_indirect_write_execute(f_pdata, to, buf, len); 1103 } 1104 1105 static void cqspi_rx_dma_callback(void *param) 1106 { 1107 struct cqspi_st *cqspi = param; 1108 1109 complete(&cqspi->rx_dma_complete); 1110 } 1111 1112 static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata, 1113 u_char *buf, loff_t from, size_t len) 1114 { 1115 struct cqspi_st *cqspi = f_pdata->cqspi; 1116 struct device *dev = &cqspi->pdev->dev; 1117 enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; 1118 dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from; 1119 int ret = 0; 1120 struct dma_async_tx_descriptor *tx; 1121 dma_cookie_t cookie; 1122 dma_addr_t dma_dst; 1123 struct device *ddev; 1124 1125 if (!cqspi->rx_chan || !virt_addr_valid(buf)) { 1126 memcpy_fromio(buf, cqspi->ahb_base + from, len); 1127 return 0; 1128 } 1129 1130 ddev = cqspi->rx_chan->device->dev; 1131 dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE); 1132 if (dma_mapping_error(ddev, dma_dst)) { 1133 dev_err(dev, "dma mapping failed\n"); 1134 return -ENOMEM; 1135 } 1136 tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src, 1137 len, flags); 1138 if (!tx) { 1139 dev_err(dev, "device_prep_dma_memcpy error\n"); 1140 ret = -EIO; 1141 goto err_unmap; 1142 } 1143 1144 tx->callback = cqspi_rx_dma_callback; 1145 tx->callback_param = cqspi; 1146 cookie = tx->tx_submit(tx); 1147 reinit_completion(&cqspi->rx_dma_complete); 1148 1149 ret = dma_submit_error(cookie); 1150 if (ret) { 1151 dev_err(dev, "dma_submit_error %d\n", cookie); 1152 ret = -EIO; 1153 goto err_unmap; 1154 } 1155 1156 dma_async_issue_pending(cqspi->rx_chan); 1157 if (!wait_for_completion_timeout(&cqspi->rx_dma_complete, 1158 msecs_to_jiffies(max_t(size_t, len, 500)))) { 1159 dmaengine_terminate_sync(cqspi->rx_chan); 1160 dev_err(dev, "DMA wait_for_completion_timeout\n"); 1161 ret = -ETIMEDOUT; 1162 goto err_unmap; 1163 } 1164 1165 err_unmap: 1166 dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE); 1167 1168 return ret; 1169 } 1170 1171 static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata, 1172 const struct spi_mem_op *op) 1173 { 1174 struct cqspi_st *cqspi = f_pdata->cqspi; 1175 loff_t from = op->addr.val; 1176 size_t len = op->data.nbytes; 1177 u_char *buf = op->data.buf.in; 1178 int ret; 1179 1180 ret = cqspi_set_protocol(f_pdata, op); 1181 if (ret) 1182 return ret; 1183 1184 ret = cqspi_read_setup(f_pdata, op); 1185 if (ret) 1186 return ret; 1187 1188 if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) 1189 return cqspi_direct_read_execute(f_pdata, buf, from, len); 1190 1191 return cqspi_indirect_read_execute(f_pdata, buf, from, len); 1192 } 1193 1194 static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op) 1195 { 1196 struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); 1197 struct cqspi_flash_pdata *f_pdata; 1198 1199 f_pdata = &cqspi->f_pdata[mem->spi->chip_select]; 1200 cqspi_configure(f_pdata, mem->spi->max_speed_hz); 1201 1202 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { 1203 if (!op->addr.nbytes) 1204 return cqspi_command_read(f_pdata, op); 1205 1206 return cqspi_read(f_pdata, op); 1207 } 1208 1209 if (!op->addr.nbytes || !op->data.buf.out) 1210 return cqspi_command_write(f_pdata, op); 1211 1212 return cqspi_write(f_pdata, op); 1213 } 1214 1215 static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) 1216 { 1217 int ret; 1218 1219 ret = cqspi_mem_process(mem, op); 1220 if (ret) 1221 dev_err(&mem->spi->dev, "operation failed with %d\n", ret); 1222 1223 return ret; 1224 } 1225 1226 static bool cqspi_supports_mem_op(struct spi_mem *mem, 1227 const struct spi_mem_op *op) 1228 { 1229 bool all_true, all_false; 1230 1231 all_true = op->cmd.dtr && op->addr.dtr && op->dummy.dtr && 1232 op->data.dtr; 1233 all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && 1234 !op->data.dtr; 1235 1236 /* Mixed DTR modes not supported. */ 1237 if (!(all_true || all_false)) 1238 return false; 1239 1240 if (all_true) 1241 return spi_mem_dtr_supports_op(mem, op); 1242 else 1243 return spi_mem_default_supports_op(mem, op); 1244 } 1245 1246 static int cqspi_of_get_flash_pdata(struct platform_device *pdev, 1247 struct cqspi_flash_pdata *f_pdata, 1248 struct device_node *np) 1249 { 1250 if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) { 1251 dev_err(&pdev->dev, "couldn't determine read-delay\n"); 1252 return -ENXIO; 1253 } 1254 1255 if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) { 1256 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n"); 1257 return -ENXIO; 1258 } 1259 1260 if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) { 1261 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n"); 1262 return -ENXIO; 1263 } 1264 1265 if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) { 1266 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n"); 1267 return -ENXIO; 1268 } 1269 1270 if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) { 1271 dev_err(&pdev->dev, "couldn't determine tslch-ns\n"); 1272 return -ENXIO; 1273 } 1274 1275 if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) { 1276 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n"); 1277 return -ENXIO; 1278 } 1279 1280 return 0; 1281 } 1282 1283 static int cqspi_of_get_pdata(struct cqspi_st *cqspi) 1284 { 1285 struct device *dev = &cqspi->pdev->dev; 1286 struct device_node *np = dev->of_node; 1287 1288 cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); 1289 1290 if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { 1291 dev_err(dev, "couldn't determine fifo-depth\n"); 1292 return -ENXIO; 1293 } 1294 1295 if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) { 1296 dev_err(dev, "couldn't determine fifo-width\n"); 1297 return -ENXIO; 1298 } 1299 1300 if (of_property_read_u32(np, "cdns,trigger-address", 1301 &cqspi->trigger_address)) { 1302 dev_err(dev, "couldn't determine trigger-address\n"); 1303 return -ENXIO; 1304 } 1305 1306 if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) 1307 cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT; 1308 1309 cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); 1310 1311 return 0; 1312 } 1313 1314 static void cqspi_controller_init(struct cqspi_st *cqspi) 1315 { 1316 u32 reg; 1317 1318 cqspi_controller_enable(cqspi, 0); 1319 1320 /* Configure the remap address register, no remap */ 1321 writel(0, cqspi->iobase + CQSPI_REG_REMAP); 1322 1323 /* Disable all interrupts. */ 1324 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); 1325 1326 /* Configure the SRAM split to 1:1 . */ 1327 writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); 1328 1329 /* Load indirect trigger address. */ 1330 writel(cqspi->trigger_address, 1331 cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); 1332 1333 /* Program read watermark -- 1/2 of the FIFO. */ 1334 writel(cqspi->fifo_depth * cqspi->fifo_width / 2, 1335 cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); 1336 /* Program write watermark -- 1/8 of the FIFO. */ 1337 writel(cqspi->fifo_depth * cqspi->fifo_width / 8, 1338 cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); 1339 1340 /* Disable direct access controller */ 1341 if (!cqspi->use_direct_mode) { 1342 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 1343 reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL; 1344 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 1345 } 1346 1347 cqspi_controller_enable(cqspi, 1); 1348 } 1349 1350 static int cqspi_request_mmap_dma(struct cqspi_st *cqspi) 1351 { 1352 dma_cap_mask_t mask; 1353 1354 dma_cap_zero(mask); 1355 dma_cap_set(DMA_MEMCPY, mask); 1356 1357 cqspi->rx_chan = dma_request_chan_by_mask(&mask); 1358 if (IS_ERR(cqspi->rx_chan)) { 1359 int ret = PTR_ERR(cqspi->rx_chan); 1360 cqspi->rx_chan = NULL; 1361 return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n"); 1362 } 1363 init_completion(&cqspi->rx_dma_complete); 1364 1365 return 0; 1366 } 1367 1368 static const char *cqspi_get_name(struct spi_mem *mem) 1369 { 1370 struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); 1371 struct device *dev = &cqspi->pdev->dev; 1372 1373 return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select); 1374 } 1375 1376 static const struct spi_controller_mem_ops cqspi_mem_ops = { 1377 .exec_op = cqspi_exec_mem_op, 1378 .get_name = cqspi_get_name, 1379 .supports_op = cqspi_supports_mem_op, 1380 }; 1381 1382 static int cqspi_setup_flash(struct cqspi_st *cqspi) 1383 { 1384 struct platform_device *pdev = cqspi->pdev; 1385 struct device *dev = &pdev->dev; 1386 struct device_node *np = dev->of_node; 1387 struct cqspi_flash_pdata *f_pdata; 1388 unsigned int cs; 1389 int ret; 1390 1391 /* Get flash device data */ 1392 for_each_available_child_of_node(dev->of_node, np) { 1393 ret = of_property_read_u32(np, "reg", &cs); 1394 if (ret) { 1395 dev_err(dev, "Couldn't determine chip select.\n"); 1396 of_node_put(np); 1397 return ret; 1398 } 1399 1400 if (cs >= CQSPI_MAX_CHIPSELECT) { 1401 dev_err(dev, "Chip select %d out of range.\n", cs); 1402 of_node_put(np); 1403 return -EINVAL; 1404 } 1405 1406 f_pdata = &cqspi->f_pdata[cs]; 1407 f_pdata->cqspi = cqspi; 1408 f_pdata->cs = cs; 1409 1410 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np); 1411 if (ret) { 1412 of_node_put(np); 1413 return ret; 1414 } 1415 } 1416 1417 return 0; 1418 } 1419 1420 static int cqspi_probe(struct platform_device *pdev) 1421 { 1422 const struct cqspi_driver_platdata *ddata; 1423 struct reset_control *rstc, *rstc_ocp; 1424 struct device *dev = &pdev->dev; 1425 struct spi_master *master; 1426 struct resource *res_ahb; 1427 struct cqspi_st *cqspi; 1428 struct resource *res; 1429 int ret; 1430 int irq; 1431 1432 master = spi_alloc_master(&pdev->dev, sizeof(*cqspi)); 1433 if (!master) { 1434 dev_err(&pdev->dev, "spi_alloc_master failed\n"); 1435 return -ENOMEM; 1436 } 1437 master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; 1438 master->mem_ops = &cqspi_mem_ops; 1439 master->dev.of_node = pdev->dev.of_node; 1440 1441 cqspi = spi_master_get_devdata(master); 1442 1443 cqspi->pdev = pdev; 1444 platform_set_drvdata(pdev, cqspi); 1445 1446 /* Obtain configuration from OF. */ 1447 ret = cqspi_of_get_pdata(cqspi); 1448 if (ret) { 1449 dev_err(dev, "Cannot get mandatory OF data.\n"); 1450 ret = -ENODEV; 1451 goto probe_master_put; 1452 } 1453 1454 /* Obtain QSPI clock. */ 1455 cqspi->clk = devm_clk_get(dev, NULL); 1456 if (IS_ERR(cqspi->clk)) { 1457 dev_err(dev, "Cannot claim QSPI clock.\n"); 1458 ret = PTR_ERR(cqspi->clk); 1459 goto probe_master_put; 1460 } 1461 1462 /* Obtain and remap controller address. */ 1463 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1464 cqspi->iobase = devm_ioremap_resource(dev, res); 1465 if (IS_ERR(cqspi->iobase)) { 1466 dev_err(dev, "Cannot remap controller address.\n"); 1467 ret = PTR_ERR(cqspi->iobase); 1468 goto probe_master_put; 1469 } 1470 1471 /* Obtain and remap AHB address. */ 1472 res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1473 cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb); 1474 if (IS_ERR(cqspi->ahb_base)) { 1475 dev_err(dev, "Cannot remap AHB address.\n"); 1476 ret = PTR_ERR(cqspi->ahb_base); 1477 goto probe_master_put; 1478 } 1479 cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start; 1480 cqspi->ahb_size = resource_size(res_ahb); 1481 1482 init_completion(&cqspi->transfer_complete); 1483 1484 /* Obtain IRQ line. */ 1485 irq = platform_get_irq(pdev, 0); 1486 if (irq < 0) { 1487 ret = -ENXIO; 1488 goto probe_master_put; 1489 } 1490 1491 pm_runtime_enable(dev); 1492 ret = pm_runtime_get_sync(dev); 1493 if (ret < 0) { 1494 pm_runtime_put_noidle(dev); 1495 goto probe_master_put; 1496 } 1497 1498 ret = clk_prepare_enable(cqspi->clk); 1499 if (ret) { 1500 dev_err(dev, "Cannot enable QSPI clock.\n"); 1501 goto probe_clk_failed; 1502 } 1503 1504 /* Obtain QSPI reset control */ 1505 rstc = devm_reset_control_get_optional_exclusive(dev, "qspi"); 1506 if (IS_ERR(rstc)) { 1507 ret = PTR_ERR(rstc); 1508 dev_err(dev, "Cannot get QSPI reset.\n"); 1509 goto probe_reset_failed; 1510 } 1511 1512 rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); 1513 if (IS_ERR(rstc_ocp)) { 1514 ret = PTR_ERR(rstc_ocp); 1515 dev_err(dev, "Cannot get QSPI OCP reset.\n"); 1516 goto probe_reset_failed; 1517 } 1518 1519 reset_control_assert(rstc); 1520 reset_control_deassert(rstc); 1521 1522 reset_control_assert(rstc_ocp); 1523 reset_control_deassert(rstc_ocp); 1524 1525 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); 1526 master->max_speed_hz = cqspi->master_ref_clk_hz; 1527 ddata = of_device_get_match_data(dev); 1528 if (ddata) { 1529 if (ddata->quirks & CQSPI_NEEDS_WR_DELAY) 1530 cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, 1531 cqspi->master_ref_clk_hz); 1532 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL) 1533 master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; 1534 if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) 1535 cqspi->use_direct_mode = true; 1536 } 1537 1538 ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0, 1539 pdev->name, cqspi); 1540 if (ret) { 1541 dev_err(dev, "Cannot request IRQ.\n"); 1542 goto probe_reset_failed; 1543 } 1544 1545 cqspi_wait_idle(cqspi); 1546 cqspi_controller_init(cqspi); 1547 cqspi->current_cs = -1; 1548 cqspi->sclk = 0; 1549 1550 master->num_chipselect = cqspi->num_chipselect; 1551 1552 ret = cqspi_setup_flash(cqspi); 1553 if (ret) { 1554 dev_err(dev, "failed to setup flash parameters %d\n", ret); 1555 goto probe_setup_failed; 1556 } 1557 1558 if (cqspi->use_direct_mode) { 1559 ret = cqspi_request_mmap_dma(cqspi); 1560 if (ret == -EPROBE_DEFER) 1561 goto probe_setup_failed; 1562 } 1563 1564 ret = devm_spi_register_master(dev, master); 1565 if (ret) { 1566 dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret); 1567 goto probe_setup_failed; 1568 } 1569 1570 return 0; 1571 probe_setup_failed: 1572 cqspi_controller_enable(cqspi, 0); 1573 probe_reset_failed: 1574 clk_disable_unprepare(cqspi->clk); 1575 probe_clk_failed: 1576 pm_runtime_put_sync(dev); 1577 pm_runtime_disable(dev); 1578 probe_master_put: 1579 spi_master_put(master); 1580 return ret; 1581 } 1582 1583 static int cqspi_remove(struct platform_device *pdev) 1584 { 1585 struct cqspi_st *cqspi = platform_get_drvdata(pdev); 1586 1587 cqspi_controller_enable(cqspi, 0); 1588 1589 if (cqspi->rx_chan) 1590 dma_release_channel(cqspi->rx_chan); 1591 1592 clk_disable_unprepare(cqspi->clk); 1593 1594 pm_runtime_put_sync(&pdev->dev); 1595 pm_runtime_disable(&pdev->dev); 1596 1597 return 0; 1598 } 1599 1600 #ifdef CONFIG_PM_SLEEP 1601 static int cqspi_suspend(struct device *dev) 1602 { 1603 struct cqspi_st *cqspi = dev_get_drvdata(dev); 1604 1605 cqspi_controller_enable(cqspi, 0); 1606 return 0; 1607 } 1608 1609 static int cqspi_resume(struct device *dev) 1610 { 1611 struct cqspi_st *cqspi = dev_get_drvdata(dev); 1612 1613 cqspi_controller_enable(cqspi, 1); 1614 return 0; 1615 } 1616 1617 static const struct dev_pm_ops cqspi__dev_pm_ops = { 1618 .suspend = cqspi_suspend, 1619 .resume = cqspi_resume, 1620 }; 1621 1622 #define CQSPI_DEV_PM_OPS (&cqspi__dev_pm_ops) 1623 #else 1624 #define CQSPI_DEV_PM_OPS NULL 1625 #endif 1626 1627 static const struct cqspi_driver_platdata cdns_qspi = { 1628 .quirks = CQSPI_DISABLE_DAC_MODE, 1629 }; 1630 1631 static const struct cqspi_driver_platdata k2g_qspi = { 1632 .quirks = CQSPI_NEEDS_WR_DELAY, 1633 }; 1634 1635 static const struct cqspi_driver_platdata am654_ospi = { 1636 .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 1637 .quirks = CQSPI_NEEDS_WR_DELAY, 1638 }; 1639 1640 static const struct cqspi_driver_platdata intel_lgm_qspi = { 1641 .quirks = CQSPI_DISABLE_DAC_MODE, 1642 }; 1643 1644 static const struct of_device_id cqspi_dt_ids[] = { 1645 { 1646 .compatible = "cdns,qspi-nor", 1647 .data = &cdns_qspi, 1648 }, 1649 { 1650 .compatible = "ti,k2g-qspi", 1651 .data = &k2g_qspi, 1652 }, 1653 { 1654 .compatible = "ti,am654-ospi", 1655 .data = &am654_ospi, 1656 }, 1657 { 1658 .compatible = "intel,lgm-qspi", 1659 .data = &intel_lgm_qspi, 1660 }, 1661 { /* end of table */ } 1662 }; 1663 1664 MODULE_DEVICE_TABLE(of, cqspi_dt_ids); 1665 1666 static struct platform_driver cqspi_platform_driver = { 1667 .probe = cqspi_probe, 1668 .remove = cqspi_remove, 1669 .driver = { 1670 .name = CQSPI_NAME, 1671 .pm = CQSPI_DEV_PM_OPS, 1672 .of_match_table = cqspi_dt_ids, 1673 }, 1674 }; 1675 1676 module_platform_driver(cqspi_platform_driver); 1677 1678 MODULE_DESCRIPTION("Cadence QSPI Controller Driver"); 1679 MODULE_LICENSE("GPL v2"); 1680 MODULE_ALIAS("platform:" CQSPI_NAME); 1681 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>"); 1682 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>"); 1683 MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>"); 1684 MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>"); 1685 MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>"); 1686