131fb632bSRamuthevar Vadivel Murugan // SPDX-License-Identifier: GPL-2.0-only 231fb632bSRamuthevar Vadivel Murugan // 331fb632bSRamuthevar Vadivel Murugan // Driver for Cadence QSPI Controller 431fb632bSRamuthevar Vadivel Murugan // 531fb632bSRamuthevar Vadivel Murugan // Copyright Altera Corporation (C) 2012-2014. All rights reserved. 631fb632bSRamuthevar Vadivel Murugan // Copyright Intel Corporation (C) 2019-2020. All rights reserved. 731fb632bSRamuthevar Vadivel Murugan // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 831fb632bSRamuthevar Vadivel Murugan 931fb632bSRamuthevar Vadivel Murugan #include <linux/clk.h> 1031fb632bSRamuthevar Vadivel Murugan #include <linux/completion.h> 1131fb632bSRamuthevar Vadivel Murugan #include <linux/delay.h> 1231fb632bSRamuthevar Vadivel Murugan #include <linux/dma-mapping.h> 1331fb632bSRamuthevar Vadivel Murugan #include <linux/dmaengine.h> 1431fb632bSRamuthevar Vadivel Murugan #include <linux/err.h> 1531fb632bSRamuthevar Vadivel Murugan #include <linux/errno.h> 1609e393e3SSai Krishna Potthuri #include <linux/firmware/xlnx-zynqmp.h> 1731fb632bSRamuthevar Vadivel Murugan #include <linux/interrupt.h> 1831fb632bSRamuthevar Vadivel Murugan #include <linux/io.h> 1931fb632bSRamuthevar Vadivel Murugan #include <linux/iopoll.h> 2031fb632bSRamuthevar Vadivel Murugan #include <linux/jiffies.h> 2131fb632bSRamuthevar Vadivel Murugan #include <linux/kernel.h> 2297e4827dSMatthias Schiffer #include <linux/log2.h> 2331fb632bSRamuthevar Vadivel Murugan #include <linux/module.h> 2431fb632bSRamuthevar Vadivel Murugan #include <linux/of_device.h> 2531fb632bSRamuthevar Vadivel Murugan #include <linux/of.h> 2631fb632bSRamuthevar Vadivel Murugan #include <linux/platform_device.h> 2731fb632bSRamuthevar Vadivel Murugan #include <linux/pm_runtime.h> 2831fb632bSRamuthevar Vadivel Murugan #include <linux/reset.h> 2931fb632bSRamuthevar Vadivel Murugan #include <linux/sched.h> 3031fb632bSRamuthevar Vadivel Murugan #include <linux/spi/spi.h> 3131fb632bSRamuthevar Vadivel Murugan #include <linux/spi/spi-mem.h> 3231fb632bSRamuthevar Vadivel Murugan #include <linux/timer.h> 3331fb632bSRamuthevar Vadivel Murugan 3431fb632bSRamuthevar Vadivel Murugan #define CQSPI_NAME "cadence-qspi" 3531fb632bSRamuthevar Vadivel Murugan #define CQSPI_MAX_CHIPSELECT 16 3631fb632bSRamuthevar Vadivel Murugan 3731fb632bSRamuthevar Vadivel Murugan /* Quirks */ 3831fb632bSRamuthevar Vadivel Murugan #define CQSPI_NEEDS_WR_DELAY BIT(0) 3931fb632bSRamuthevar Vadivel Murugan #define CQSPI_DISABLE_DAC_MODE BIT(1) 401a6f854fSSai Krishna Potthuri #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) 4198d948ebSDinh Nguyen #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) 429ee5b6d5SNiravkumar L Rabara #define CQSPI_SLOW_SRAM BIT(4) 4331fb632bSRamuthevar Vadivel Murugan 4431fb632bSRamuthevar Vadivel Murugan /* Capabilities */ 4531fb632bSRamuthevar Vadivel Murugan #define CQSPI_SUPPORTS_OCTAL BIT(0) 4631fb632bSRamuthevar Vadivel Murugan 4728ac902aSMatthias Schiffer #define CQSPI_OP_WIDTH(part) ((part).nbytes ? ilog2((part).buswidth) : 0) 4828ac902aSMatthias Schiffer 4931fb632bSRamuthevar Vadivel Murugan struct cqspi_st; 5031fb632bSRamuthevar Vadivel Murugan 5131fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata { 5231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi; 5331fb632bSRamuthevar Vadivel Murugan u32 clk_rate; 5431fb632bSRamuthevar Vadivel Murugan u32 read_delay; 5531fb632bSRamuthevar Vadivel Murugan u32 tshsl_ns; 5631fb632bSRamuthevar Vadivel Murugan u32 tsd2d_ns; 5731fb632bSRamuthevar Vadivel Murugan u32 tchsh_ns; 5831fb632bSRamuthevar Vadivel Murugan u32 tslch_ns; 5931fb632bSRamuthevar Vadivel Murugan u8 cs; 6031fb632bSRamuthevar Vadivel Murugan }; 6131fb632bSRamuthevar Vadivel Murugan 6231fb632bSRamuthevar Vadivel Murugan struct cqspi_st { 6331fb632bSRamuthevar Vadivel Murugan struct platform_device *pdev; 64606e5d40SVaishnav Achath struct spi_master *master; 6531fb632bSRamuthevar Vadivel Murugan struct clk *clk; 6631fb632bSRamuthevar Vadivel Murugan unsigned int sclk; 6731fb632bSRamuthevar Vadivel Murugan 6831fb632bSRamuthevar Vadivel Murugan void __iomem *iobase; 6931fb632bSRamuthevar Vadivel Murugan void __iomem *ahb_base; 7031fb632bSRamuthevar Vadivel Murugan resource_size_t ahb_size; 7131fb632bSRamuthevar Vadivel Murugan struct completion transfer_complete; 7231fb632bSRamuthevar Vadivel Murugan 7331fb632bSRamuthevar Vadivel Murugan struct dma_chan *rx_chan; 7431fb632bSRamuthevar Vadivel Murugan struct completion rx_dma_complete; 7531fb632bSRamuthevar Vadivel Murugan dma_addr_t mmap_phys_base; 7631fb632bSRamuthevar Vadivel Murugan 7731fb632bSRamuthevar Vadivel Murugan int current_cs; 7831fb632bSRamuthevar Vadivel Murugan unsigned long master_ref_clk_hz; 7931fb632bSRamuthevar Vadivel Murugan bool is_decoded_cs; 8031fb632bSRamuthevar Vadivel Murugan u32 fifo_depth; 8131fb632bSRamuthevar Vadivel Murugan u32 fifo_width; 82b436fb7dSRamuthevar Vadivel Murugan u32 num_chipselect; 8331fb632bSRamuthevar Vadivel Murugan bool rclk_en; 8431fb632bSRamuthevar Vadivel Murugan u32 trigger_address; 8531fb632bSRamuthevar Vadivel Murugan u32 wr_delay; 8631fb632bSRamuthevar Vadivel Murugan bool use_direct_mode; 8731fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; 881a6f854fSSai Krishna Potthuri bool use_dma_read; 8909e393e3SSai Krishna Potthuri u32 pd_dev_id; 9098d948ebSDinh Nguyen bool wr_completion; 919ee5b6d5SNiravkumar L Rabara bool slow_sram; 9231fb632bSRamuthevar Vadivel Murugan }; 9331fb632bSRamuthevar Vadivel Murugan 9431fb632bSRamuthevar Vadivel Murugan struct cqspi_driver_platdata { 9531fb632bSRamuthevar Vadivel Murugan u32 hwcaps_mask; 9631fb632bSRamuthevar Vadivel Murugan u8 quirks; 971a6f854fSSai Krishna Potthuri int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata, 981a6f854fSSai Krishna Potthuri u_char *rxbuf, loff_t from_addr, size_t n_rx); 991a6f854fSSai Krishna Potthuri u32 (*get_dma_status)(struct cqspi_st *cqspi); 10031fb632bSRamuthevar Vadivel Murugan }; 10131fb632bSRamuthevar Vadivel Murugan 10231fb632bSRamuthevar Vadivel Murugan /* Operation timeout value */ 10331fb632bSRamuthevar Vadivel Murugan #define CQSPI_TIMEOUT_MS 500 10431fb632bSRamuthevar Vadivel Murugan #define CQSPI_READ_TIMEOUT_MS 10 10531fb632bSRamuthevar Vadivel Murugan 10631fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_CLKS_PER_BYTE 8 10731fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_BYTES_MAX 4 10831fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_CLKS_MAX 31 10931fb632bSRamuthevar Vadivel Murugan 11031fb632bSRamuthevar Vadivel Murugan #define CQSPI_STIG_DATA_LEN_MAX 8 11131fb632bSRamuthevar Vadivel Murugan 11231fb632bSRamuthevar Vadivel Murugan /* Register map */ 11331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG 0x00 11431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0) 11531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7) 11631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9) 11731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 11831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_DMA_MASK BIT(15) 11931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_BAUD_LSB 19 120f453f293SPratyush Yadav #define CQSPI_REG_CONFIG_DTR_PROTO BIT(24) 121f453f293SPratyush Yadav #define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30) 12231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_IDLE_LSB 31 12331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF 12431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_BAUD_MASK 0xF 12531fb632bSRamuthevar Vadivel Murugan 12631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR 0x04 12731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 12831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 12931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 13031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 13131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 13231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 13331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 13431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 13531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 13631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F 13731fb632bSRamuthevar Vadivel Murugan 13831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR 0x08 13931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 14031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12 14131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16 14231fb632bSRamuthevar Vadivel Murugan 14331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY 0x0C 14431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSLCH_LSB 0 14531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TCHSH_LSB 8 14631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSD2D_LSB 16 14731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSHSL_LSB 24 14831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF 14931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF 15031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF 15131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF 15231fb632bSRamuthevar Vadivel Murugan 15331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE 0x10 15431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0 15531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_DELAY_LSB 1 15631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF 15731fb632bSRamuthevar Vadivel Murugan 15831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE 0x14 15931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_ADDRESS_LSB 0 16031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_PAGE_LSB 4 16131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_BLOCK_LSB 16 16231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF 16331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF 16431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F 16531fb632bSRamuthevar Vadivel Murugan 16631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SRAMPARTITION 0x18 16731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTTRIGGER 0x1C 16831fb632bSRamuthevar Vadivel Murugan 16931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA 0x20 17031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_SINGLE_LSB 0 17131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_BURST_LSB 8 17231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_SINGLE_MASK 0xFF 17331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_BURST_MASK 0xFF 17431fb632bSRamuthevar Vadivel Murugan 17531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_REMAP 0x24 17631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_MODE_BIT 0x28 17731fb632bSRamuthevar Vadivel Murugan 17831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL 0x2C 17931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 18031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 18131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF 18231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF 18331fb632bSRamuthevar Vadivel Murugan 184f453f293SPratyush Yadav #define CQSPI_REG_WR_COMPLETION_CTRL 0x38 185f453f293SPratyush Yadav #define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14) 186f453f293SPratyush Yadav 18731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQSTATUS 0x40 18831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQMASK 0x44 18931fb632bSRamuthevar Vadivel Murugan 19031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD 0x60 19131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0) 19231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1) 19331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5) 19431fb632bSRamuthevar Vadivel Murugan 19531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDWATERMARK 0x64 19631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 19731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDBYTES 0x6C 19831fb632bSRamuthevar Vadivel Murugan 19931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL 0x90 20031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0) 20131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1) 202888d517bSPratyush Yadav #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 20331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 20431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 20531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 20631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 20731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 20831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 20931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 21031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 21131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 21231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 213888d517bSPratyush Yadav #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F 21431fb632bSRamuthevar Vadivel Murugan 21531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR 0x70 21631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0) 21731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1) 21831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5) 21931fb632bSRamuthevar Vadivel Murugan 22031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRWATERMARK 0x74 22131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 22231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRBYTES 0x7C 22331fb632bSRamuthevar Vadivel Murugan 2241a6f854fSSai Krishna Potthuri #define CQSPI_REG_INDTRIG_ADDRRANGE 0x80 2251a6f854fSSai Krishna Potthuri 22631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDADDRESS 0x94 22731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDREADDATALOWER 0xA0 22831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDREADDATAUPPER 0xA4 22931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDWRITEDATALOWER 0xA8 23031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC 23131fb632bSRamuthevar Vadivel Murugan 232f453f293SPratyush Yadav #define CQSPI_REG_POLLING_STATUS 0xB0 233f453f293SPratyush Yadav #define CQSPI_REG_POLLING_STATUS_DUMMY_LSB 16 234f453f293SPratyush Yadav 235f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_LOWER 0xE0 236f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_READ_LSB 24 237f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_WRITE_LSB 16 238f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_STIG_LSB 0 239f453f293SPratyush Yadav 2401a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_SRC_ADDR 0x1000 2411a6f854fSSai Krishna Potthuri 2421a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_ADDR 0x1800 2431a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_SIZE 0x1804 2441a6f854fSSai Krishna Potthuri 2451a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_CTRL 0x180C 2461a6f854fSSai Krishna Potthuri 2471a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_I_STS 0x1814 2481a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_I_EN 0x1818 2491a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_I_DIS 0x181C 2501a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_DONE_MASK BIT(1) 2511a6f854fSSai Krishna Potthuri 2521a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB 0x1828 2531a6f854fSSai Krishna Potthuri 2541a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL 0xF43FFA00 2551a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL 0x6 2561a6f854fSSai Krishna Potthuri 25731fb632bSRamuthevar Vadivel Murugan /* Interrupt status bits */ 25831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_MODE_ERR BIT(0) 25931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_UNDERFLOW BIT(1) 26031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_COMP BIT(2) 26131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3) 26231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4) 26331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5) 26431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_WATERMARK BIT(6) 26531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12) 26631fb632bSRamuthevar Vadivel Murugan 26731fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \ 26831fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_IND_SRAM_FULL | \ 26931fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_IND_COMP) 27031fb632bSRamuthevar Vadivel Murugan 27131fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \ 27231fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_WATERMARK | \ 27331fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_UNDERFLOW) 27431fb632bSRamuthevar Vadivel Murugan 27531fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_STATUS_MASK 0x1FFFF 2761a6f854fSSai Krishna Potthuri #define CQSPI_DMA_UNALIGN 0x3 2771a6f854fSSai Krishna Potthuri 2781a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_VAL 0x602 27931fb632bSRamuthevar Vadivel Murugan 28031fb632bSRamuthevar Vadivel Murugan static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr) 28131fb632bSRamuthevar Vadivel Murugan { 28231fb632bSRamuthevar Vadivel Murugan u32 val; 28331fb632bSRamuthevar Vadivel Murugan 28431fb632bSRamuthevar Vadivel Murugan return readl_relaxed_poll_timeout(reg, val, 28531fb632bSRamuthevar Vadivel Murugan (((clr ? ~val : val) & mask) == mask), 28631fb632bSRamuthevar Vadivel Murugan 10, CQSPI_TIMEOUT_MS * 1000); 28731fb632bSRamuthevar Vadivel Murugan } 28831fb632bSRamuthevar Vadivel Murugan 28931fb632bSRamuthevar Vadivel Murugan static bool cqspi_is_idle(struct cqspi_st *cqspi) 29031fb632bSRamuthevar Vadivel Murugan { 29131fb632bSRamuthevar Vadivel Murugan u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 29231fb632bSRamuthevar Vadivel Murugan 29331890269SJay Fang return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB); 29431fb632bSRamuthevar Vadivel Murugan } 29531fb632bSRamuthevar Vadivel Murugan 29631fb632bSRamuthevar Vadivel Murugan static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi) 29731fb632bSRamuthevar Vadivel Murugan { 29831fb632bSRamuthevar Vadivel Murugan u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL); 29931fb632bSRamuthevar Vadivel Murugan 30031fb632bSRamuthevar Vadivel Murugan reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB; 30131fb632bSRamuthevar Vadivel Murugan return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK; 30231fb632bSRamuthevar Vadivel Murugan } 30331fb632bSRamuthevar Vadivel Murugan 3041a6f854fSSai Krishna Potthuri static u32 cqspi_get_versal_dma_status(struct cqspi_st *cqspi) 3051a6f854fSSai Krishna Potthuri { 3061a6f854fSSai Krishna Potthuri u32 dma_status; 3071a6f854fSSai Krishna Potthuri 3081a6f854fSSai Krishna Potthuri dma_status = readl(cqspi->iobase + 3091a6f854fSSai Krishna Potthuri CQSPI_REG_VERSAL_DMA_DST_I_STS); 3101a6f854fSSai Krishna Potthuri writel(dma_status, cqspi->iobase + 3111a6f854fSSai Krishna Potthuri CQSPI_REG_VERSAL_DMA_DST_I_STS); 3121a6f854fSSai Krishna Potthuri 3131a6f854fSSai Krishna Potthuri return dma_status & CQSPI_REG_VERSAL_DMA_DST_DONE_MASK; 3141a6f854fSSai Krishna Potthuri } 3151a6f854fSSai Krishna Potthuri 31631fb632bSRamuthevar Vadivel Murugan static irqreturn_t cqspi_irq_handler(int this_irq, void *dev) 31731fb632bSRamuthevar Vadivel Murugan { 31831fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev; 31931fb632bSRamuthevar Vadivel Murugan unsigned int irq_status; 3201a6f854fSSai Krishna Potthuri struct device *device = &cqspi->pdev->dev; 3211a6f854fSSai Krishna Potthuri const struct cqspi_driver_platdata *ddata; 3221a6f854fSSai Krishna Potthuri 3231a6f854fSSai Krishna Potthuri ddata = of_device_get_match_data(device); 32431fb632bSRamuthevar Vadivel Murugan 32531fb632bSRamuthevar Vadivel Murugan /* Read interrupt status */ 32631fb632bSRamuthevar Vadivel Murugan irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS); 32731fb632bSRamuthevar Vadivel Murugan 32831fb632bSRamuthevar Vadivel Murugan /* Clear interrupt */ 32931fb632bSRamuthevar Vadivel Murugan writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS); 33031fb632bSRamuthevar Vadivel Murugan 3311a6f854fSSai Krishna Potthuri if (cqspi->use_dma_read && ddata && ddata->get_dma_status) { 3321a6f854fSSai Krishna Potthuri if (ddata->get_dma_status(cqspi)) { 3331a6f854fSSai Krishna Potthuri complete(&cqspi->transfer_complete); 3341a6f854fSSai Krishna Potthuri return IRQ_HANDLED; 3351a6f854fSSai Krishna Potthuri } 3361a6f854fSSai Krishna Potthuri } 3371a6f854fSSai Krishna Potthuri 3389ee5b6d5SNiravkumar L Rabara else if (!cqspi->slow_sram) 33931fb632bSRamuthevar Vadivel Murugan irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR; 3409ee5b6d5SNiravkumar L Rabara else 3419ee5b6d5SNiravkumar L Rabara irq_status &= CQSPI_REG_IRQ_WATERMARK | CQSPI_IRQ_MASK_WR; 34231fb632bSRamuthevar Vadivel Murugan 34331fb632bSRamuthevar Vadivel Murugan if (irq_status) 34431fb632bSRamuthevar Vadivel Murugan complete(&cqspi->transfer_complete); 34531fb632bSRamuthevar Vadivel Murugan 34631fb632bSRamuthevar Vadivel Murugan return IRQ_HANDLED; 34731fb632bSRamuthevar Vadivel Murugan } 34831fb632bSRamuthevar Vadivel Murugan 34928ac902aSMatthias Schiffer static unsigned int cqspi_calc_rdreg(const struct spi_mem_op *op) 35031fb632bSRamuthevar Vadivel Murugan { 35131fb632bSRamuthevar Vadivel Murugan u32 rdreg = 0; 35231fb632bSRamuthevar Vadivel Murugan 35328ac902aSMatthias Schiffer rdreg |= CQSPI_OP_WIDTH(op->cmd) << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; 35428ac902aSMatthias Schiffer rdreg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; 35528ac902aSMatthias Schiffer rdreg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; 35631fb632bSRamuthevar Vadivel Murugan 35731fb632bSRamuthevar Vadivel Murugan return rdreg; 35831fb632bSRamuthevar Vadivel Murugan } 35931fb632bSRamuthevar Vadivel Murugan 36028ac902aSMatthias Schiffer static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op) 361888d517bSPratyush Yadav { 3620ccfd1baSYoshitaka Ikeda unsigned int dummy_clk; 363888d517bSPratyush Yadav 3640e85ee89SYoshitaka Ikeda if (!op->dummy.nbytes) 3650e85ee89SYoshitaka Ikeda return 0; 3660e85ee89SYoshitaka Ikeda 3677512eaf5SPratyush Yadav dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth); 36828ac902aSMatthias Schiffer if (op->cmd.dtr) 369f453f293SPratyush Yadav dummy_clk /= 2; 370888d517bSPratyush Yadav 371888d517bSPratyush Yadav return dummy_clk; 372888d517bSPratyush Yadav } 373888d517bSPratyush Yadav 37431fb632bSRamuthevar Vadivel Murugan static int cqspi_wait_idle(struct cqspi_st *cqspi) 37531fb632bSRamuthevar Vadivel Murugan { 37631fb632bSRamuthevar Vadivel Murugan const unsigned int poll_idle_retry = 3; 37731fb632bSRamuthevar Vadivel Murugan unsigned int count = 0; 37831fb632bSRamuthevar Vadivel Murugan unsigned long timeout; 37931fb632bSRamuthevar Vadivel Murugan 38031fb632bSRamuthevar Vadivel Murugan timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS); 38131fb632bSRamuthevar Vadivel Murugan while (1) { 38231fb632bSRamuthevar Vadivel Murugan /* 38331fb632bSRamuthevar Vadivel Murugan * Read few times in succession to ensure the controller 38431fb632bSRamuthevar Vadivel Murugan * is indeed idle, that is, the bit does not transition 38531fb632bSRamuthevar Vadivel Murugan * low again. 38631fb632bSRamuthevar Vadivel Murugan */ 38731fb632bSRamuthevar Vadivel Murugan if (cqspi_is_idle(cqspi)) 38831fb632bSRamuthevar Vadivel Murugan count++; 38931fb632bSRamuthevar Vadivel Murugan else 39031fb632bSRamuthevar Vadivel Murugan count = 0; 39131fb632bSRamuthevar Vadivel Murugan 39231fb632bSRamuthevar Vadivel Murugan if (count >= poll_idle_retry) 39331fb632bSRamuthevar Vadivel Murugan return 0; 39431fb632bSRamuthevar Vadivel Murugan 39531fb632bSRamuthevar Vadivel Murugan if (time_after(jiffies, timeout)) { 39631fb632bSRamuthevar Vadivel Murugan /* Timeout, in busy mode. */ 39731fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 39831fb632bSRamuthevar Vadivel Murugan "QSPI is still busy after %dms timeout.\n", 39931fb632bSRamuthevar Vadivel Murugan CQSPI_TIMEOUT_MS); 40031fb632bSRamuthevar Vadivel Murugan return -ETIMEDOUT; 40131fb632bSRamuthevar Vadivel Murugan } 40231fb632bSRamuthevar Vadivel Murugan 40331fb632bSRamuthevar Vadivel Murugan cpu_relax(); 40431fb632bSRamuthevar Vadivel Murugan } 40531fb632bSRamuthevar Vadivel Murugan } 40631fb632bSRamuthevar Vadivel Murugan 40731fb632bSRamuthevar Vadivel Murugan static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg) 40831fb632bSRamuthevar Vadivel Murugan { 40931fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 41031fb632bSRamuthevar Vadivel Murugan int ret; 41131fb632bSRamuthevar Vadivel Murugan 41231fb632bSRamuthevar Vadivel Murugan /* Write the CMDCTRL without start execution. */ 41331fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CMDCTRL); 41431fb632bSRamuthevar Vadivel Murugan /* Start execute */ 41531fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK; 41631fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CMDCTRL); 41731fb632bSRamuthevar Vadivel Murugan 41831fb632bSRamuthevar Vadivel Murugan /* Polling for completion. */ 41931fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL, 42031fb632bSRamuthevar Vadivel Murugan CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1); 42131fb632bSRamuthevar Vadivel Murugan if (ret) { 42231fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 42331fb632bSRamuthevar Vadivel Murugan "Flash command execution timed out.\n"); 42431fb632bSRamuthevar Vadivel Murugan return ret; 42531fb632bSRamuthevar Vadivel Murugan } 42631fb632bSRamuthevar Vadivel Murugan 42731fb632bSRamuthevar Vadivel Murugan /* Polling QSPI idle status. */ 42831fb632bSRamuthevar Vadivel Murugan return cqspi_wait_idle(cqspi); 42931fb632bSRamuthevar Vadivel Murugan } 43031fb632bSRamuthevar Vadivel Murugan 431f453f293SPratyush Yadav static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata, 432f453f293SPratyush Yadav const struct spi_mem_op *op, 433f453f293SPratyush Yadav unsigned int shift) 434f453f293SPratyush Yadav { 435f453f293SPratyush Yadav struct cqspi_st *cqspi = f_pdata->cqspi; 436f453f293SPratyush Yadav void __iomem *reg_base = cqspi->iobase; 437f453f293SPratyush Yadav unsigned int reg; 438f453f293SPratyush Yadav u8 ext; 439f453f293SPratyush Yadav 440f453f293SPratyush Yadav if (op->cmd.nbytes != 2) 441f453f293SPratyush Yadav return -EINVAL; 442f453f293SPratyush Yadav 443f453f293SPratyush Yadav /* Opcode extension is the LSB. */ 444f453f293SPratyush Yadav ext = op->cmd.opcode & 0xff; 445f453f293SPratyush Yadav 446f453f293SPratyush Yadav reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER); 447f453f293SPratyush Yadav reg &= ~(0xff << shift); 448f453f293SPratyush Yadav reg |= ext << shift; 449f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER); 450f453f293SPratyush Yadav 451f453f293SPratyush Yadav return 0; 452f453f293SPratyush Yadav } 453f453f293SPratyush Yadav 454f453f293SPratyush Yadav static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata, 45528ac902aSMatthias Schiffer const struct spi_mem_op *op, unsigned int shift) 456f453f293SPratyush Yadav { 457f453f293SPratyush Yadav struct cqspi_st *cqspi = f_pdata->cqspi; 458f453f293SPratyush Yadav void __iomem *reg_base = cqspi->iobase; 459f453f293SPratyush Yadav unsigned int reg; 460f453f293SPratyush Yadav int ret; 461f453f293SPratyush Yadav 462f453f293SPratyush Yadav reg = readl(reg_base + CQSPI_REG_CONFIG); 463f453f293SPratyush Yadav 464f453f293SPratyush Yadav /* 465f453f293SPratyush Yadav * We enable dual byte opcode here. The callers have to set up the 466f453f293SPratyush Yadav * extension opcode based on which type of operation it is. 467f453f293SPratyush Yadav */ 46828ac902aSMatthias Schiffer if (op->cmd.dtr) { 469f453f293SPratyush Yadav reg |= CQSPI_REG_CONFIG_DTR_PROTO; 470f453f293SPratyush Yadav reg |= CQSPI_REG_CONFIG_DUAL_OPCODE; 471f453f293SPratyush Yadav 472f453f293SPratyush Yadav /* Set up command opcode extension. */ 473f453f293SPratyush Yadav ret = cqspi_setup_opcode_ext(f_pdata, op, shift); 474f453f293SPratyush Yadav if (ret) 475f453f293SPratyush Yadav return ret; 476f453f293SPratyush Yadav } else { 477f453f293SPratyush Yadav reg &= ~CQSPI_REG_CONFIG_DTR_PROTO; 478f453f293SPratyush Yadav reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE; 479f453f293SPratyush Yadav } 480f453f293SPratyush Yadav 481f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_CONFIG); 482f453f293SPratyush Yadav 483f453f293SPratyush Yadav return cqspi_wait_idle(cqspi); 484f453f293SPratyush Yadav } 485f453f293SPratyush Yadav 48631fb632bSRamuthevar Vadivel Murugan static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, 48731fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 48831fb632bSRamuthevar Vadivel Murugan { 48931fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 49031fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 49131fb632bSRamuthevar Vadivel Murugan u8 *rxbuf = op->data.buf.in; 492f453f293SPratyush Yadav u8 opcode; 49331fb632bSRamuthevar Vadivel Murugan size_t n_rx = op->data.nbytes; 49431fb632bSRamuthevar Vadivel Murugan unsigned int rdreg; 49531fb632bSRamuthevar Vadivel Murugan unsigned int reg; 496888d517bSPratyush Yadav unsigned int dummy_clk; 49731fb632bSRamuthevar Vadivel Murugan size_t read_len; 49831fb632bSRamuthevar Vadivel Murugan int status; 49931fb632bSRamuthevar Vadivel Murugan 50028ac902aSMatthias Schiffer status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB); 501f453f293SPratyush Yadav if (status) 502f453f293SPratyush Yadav return status; 503f453f293SPratyush Yadav 50431fb632bSRamuthevar Vadivel Murugan if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) { 50531fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 50631fb632bSRamuthevar Vadivel Murugan "Invalid input argument, len %zu rxbuf 0x%p\n", 50731fb632bSRamuthevar Vadivel Murugan n_rx, rxbuf); 50831fb632bSRamuthevar Vadivel Murugan return -EINVAL; 50931fb632bSRamuthevar Vadivel Murugan } 51031fb632bSRamuthevar Vadivel Murugan 51128ac902aSMatthias Schiffer if (op->cmd.dtr) 512f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 513f453f293SPratyush Yadav else 514f453f293SPratyush Yadav opcode = op->cmd.opcode; 515f453f293SPratyush Yadav 51631fb632bSRamuthevar Vadivel Murugan reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 51731fb632bSRamuthevar Vadivel Murugan 51828ac902aSMatthias Schiffer rdreg = cqspi_calc_rdreg(op); 51931fb632bSRamuthevar Vadivel Murugan writel(rdreg, reg_base + CQSPI_REG_RD_INSTR); 52031fb632bSRamuthevar Vadivel Murugan 52128ac902aSMatthias Schiffer dummy_clk = cqspi_calc_dummy(op); 522888d517bSPratyush Yadav if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 523888d517bSPratyush Yadav return -EOPNOTSUPP; 524888d517bSPratyush Yadav 525888d517bSPratyush Yadav if (dummy_clk) 526888d517bSPratyush Yadav reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK) 527888d517bSPratyush Yadav << CQSPI_REG_CMDCTRL_DUMMY_LSB; 528888d517bSPratyush Yadav 52931fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); 53031fb632bSRamuthevar Vadivel Murugan 53131fb632bSRamuthevar Vadivel Murugan /* 0 means 1 byte. */ 53231fb632bSRamuthevar Vadivel Murugan reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) 53331fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); 53431fb632bSRamuthevar Vadivel Murugan status = cqspi_exec_flash_cmd(cqspi, reg); 53531fb632bSRamuthevar Vadivel Murugan if (status) 53631fb632bSRamuthevar Vadivel Murugan return status; 53731fb632bSRamuthevar Vadivel Murugan 53831fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER); 53931fb632bSRamuthevar Vadivel Murugan 54031fb632bSRamuthevar Vadivel Murugan /* Put the read value into rx_buf */ 54131fb632bSRamuthevar Vadivel Murugan read_len = (n_rx > 4) ? 4 : n_rx; 54231fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, ®, read_len); 54331fb632bSRamuthevar Vadivel Murugan rxbuf += read_len; 54431fb632bSRamuthevar Vadivel Murugan 54531fb632bSRamuthevar Vadivel Murugan if (n_rx > 4) { 54631fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER); 54731fb632bSRamuthevar Vadivel Murugan 54831fb632bSRamuthevar Vadivel Murugan read_len = n_rx - read_len; 54931fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, ®, read_len); 55031fb632bSRamuthevar Vadivel Murugan } 55131fb632bSRamuthevar Vadivel Murugan 55231fb632bSRamuthevar Vadivel Murugan return 0; 55331fb632bSRamuthevar Vadivel Murugan } 55431fb632bSRamuthevar Vadivel Murugan 55531fb632bSRamuthevar Vadivel Murugan static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata, 55631fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 55731fb632bSRamuthevar Vadivel Murugan { 55831fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 55931fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 560f453f293SPratyush Yadav u8 opcode; 56131fb632bSRamuthevar Vadivel Murugan const u8 *txbuf = op->data.buf.out; 56231fb632bSRamuthevar Vadivel Murugan size_t n_tx = op->data.nbytes; 56331fb632bSRamuthevar Vadivel Murugan unsigned int reg; 56431fb632bSRamuthevar Vadivel Murugan unsigned int data; 56531fb632bSRamuthevar Vadivel Murugan size_t write_len; 566f453f293SPratyush Yadav int ret; 567f453f293SPratyush Yadav 56828ac902aSMatthias Schiffer ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB); 569f453f293SPratyush Yadav if (ret) 570f453f293SPratyush Yadav return ret; 57131fb632bSRamuthevar Vadivel Murugan 57231fb632bSRamuthevar Vadivel Murugan if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) { 57331fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 57431fb632bSRamuthevar Vadivel Murugan "Invalid input argument, cmdlen %zu txbuf 0x%p\n", 57531fb632bSRamuthevar Vadivel Murugan n_tx, txbuf); 57631fb632bSRamuthevar Vadivel Murugan return -EINVAL; 57731fb632bSRamuthevar Vadivel Murugan } 57831fb632bSRamuthevar Vadivel Murugan 57928ac902aSMatthias Schiffer reg = cqspi_calc_rdreg(op); 580f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_RD_INSTR); 581f453f293SPratyush Yadav 58228ac902aSMatthias Schiffer if (op->cmd.dtr) 583f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 584f453f293SPratyush Yadav else 585f453f293SPratyush Yadav opcode = op->cmd.opcode; 586f453f293SPratyush Yadav 58731fb632bSRamuthevar Vadivel Murugan reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 58831fb632bSRamuthevar Vadivel Murugan 58931fb632bSRamuthevar Vadivel Murugan if (op->addr.nbytes) { 59031fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 59131fb632bSRamuthevar Vadivel Murugan reg |= ((op->addr.nbytes - 1) & 59231fb632bSRamuthevar Vadivel Murugan CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) 59331fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; 59431fb632bSRamuthevar Vadivel Murugan 59531fb632bSRamuthevar Vadivel Murugan writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); 59631fb632bSRamuthevar Vadivel Murugan } 59731fb632bSRamuthevar Vadivel Murugan 59831fb632bSRamuthevar Vadivel Murugan if (n_tx) { 59931fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB); 60031fb632bSRamuthevar Vadivel Murugan reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) 60131fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_WR_BYTES_LSB; 60231fb632bSRamuthevar Vadivel Murugan data = 0; 60331fb632bSRamuthevar Vadivel Murugan write_len = (n_tx > 4) ? 4 : n_tx; 60431fb632bSRamuthevar Vadivel Murugan memcpy(&data, txbuf, write_len); 60531fb632bSRamuthevar Vadivel Murugan txbuf += write_len; 60631fb632bSRamuthevar Vadivel Murugan writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER); 60731fb632bSRamuthevar Vadivel Murugan 60831fb632bSRamuthevar Vadivel Murugan if (n_tx > 4) { 60931fb632bSRamuthevar Vadivel Murugan data = 0; 61031fb632bSRamuthevar Vadivel Murugan write_len = n_tx - 4; 61131fb632bSRamuthevar Vadivel Murugan memcpy(&data, txbuf, write_len); 61231fb632bSRamuthevar Vadivel Murugan writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER); 61331fb632bSRamuthevar Vadivel Murugan } 61431fb632bSRamuthevar Vadivel Murugan } 61531fb632bSRamuthevar Vadivel Murugan 61631fb632bSRamuthevar Vadivel Murugan return cqspi_exec_flash_cmd(cqspi, reg); 61731fb632bSRamuthevar Vadivel Murugan } 61831fb632bSRamuthevar Vadivel Murugan 61931fb632bSRamuthevar Vadivel Murugan static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata, 62031fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 62131fb632bSRamuthevar Vadivel Murugan { 62231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 62331fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 62431fb632bSRamuthevar Vadivel Murugan unsigned int dummy_clk = 0; 62531fb632bSRamuthevar Vadivel Murugan unsigned int reg; 626f453f293SPratyush Yadav int ret; 627f453f293SPratyush Yadav u8 opcode; 62831fb632bSRamuthevar Vadivel Murugan 62928ac902aSMatthias Schiffer ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB); 630f453f293SPratyush Yadav if (ret) 631f453f293SPratyush Yadav return ret; 632f453f293SPratyush Yadav 63328ac902aSMatthias Schiffer if (op->cmd.dtr) 634f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 635f453f293SPratyush Yadav else 636f453f293SPratyush Yadav opcode = op->cmd.opcode; 637f453f293SPratyush Yadav 638f453f293SPratyush Yadav reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB; 63928ac902aSMatthias Schiffer reg |= cqspi_calc_rdreg(op); 64031fb632bSRamuthevar Vadivel Murugan 64131fb632bSRamuthevar Vadivel Murugan /* Setup dummy clock cycles */ 64228ac902aSMatthias Schiffer dummy_clk = cqspi_calc_dummy(op); 643888d517bSPratyush Yadav 64431fb632bSRamuthevar Vadivel Murugan if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 645ceeda328SPratyush Yadav return -EOPNOTSUPP; 64631fb632bSRamuthevar Vadivel Murugan 64731fb632bSRamuthevar Vadivel Murugan if (dummy_clk) 64831fb632bSRamuthevar Vadivel Murugan reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK) 64931fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_RD_INSTR_DUMMY_LSB; 65031fb632bSRamuthevar Vadivel Murugan 65131fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_RD_INSTR); 65231fb632bSRamuthevar Vadivel Murugan 65331fb632bSRamuthevar Vadivel Murugan /* Set address width */ 65431fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_SIZE); 65531fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 65631fb632bSRamuthevar Vadivel Murugan reg |= (op->addr.nbytes - 1); 65731fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_SIZE); 65831fb632bSRamuthevar Vadivel Murugan return 0; 65931fb632bSRamuthevar Vadivel Murugan } 66031fb632bSRamuthevar Vadivel Murugan 66131fb632bSRamuthevar Vadivel Murugan static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, 66231fb632bSRamuthevar Vadivel Murugan u8 *rxbuf, loff_t from_addr, 66331fb632bSRamuthevar Vadivel Murugan const size_t n_rx) 66431fb632bSRamuthevar Vadivel Murugan { 66531fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 66631fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 66731fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 66831fb632bSRamuthevar Vadivel Murugan void __iomem *ahb_base = cqspi->ahb_base; 66931fb632bSRamuthevar Vadivel Murugan unsigned int remaining = n_rx; 67031fb632bSRamuthevar Vadivel Murugan unsigned int mod_bytes = n_rx % 4; 67131fb632bSRamuthevar Vadivel Murugan unsigned int bytes_to_read = 0; 67231fb632bSRamuthevar Vadivel Murugan u8 *rxbuf_end = rxbuf + n_rx; 67331fb632bSRamuthevar Vadivel Murugan int ret = 0; 67431fb632bSRamuthevar Vadivel Murugan 67531fb632bSRamuthevar Vadivel Murugan writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 67631fb632bSRamuthevar Vadivel Murugan writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES); 67731fb632bSRamuthevar Vadivel Murugan 67831fb632bSRamuthevar Vadivel Murugan /* Clear all interrupts. */ 67931fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 68031fb632bSRamuthevar Vadivel Murugan 6819ee5b6d5SNiravkumar L Rabara /* 6829ee5b6d5SNiravkumar L Rabara * On SoCFPGA platform reading the SRAM is slow due to 6839ee5b6d5SNiravkumar L Rabara * hardware limitation and causing read interrupt storm to CPU, 6849ee5b6d5SNiravkumar L Rabara * so enabling only watermark interrupt to disable all read 6859ee5b6d5SNiravkumar L Rabara * interrupts later as we want to run "bytes to read" loop with 6869ee5b6d5SNiravkumar L Rabara * all the read interrupts disabled for max performance. 6879ee5b6d5SNiravkumar L Rabara */ 6889ee5b6d5SNiravkumar L Rabara 6899ee5b6d5SNiravkumar L Rabara if (!cqspi->slow_sram) 69031fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK); 6919ee5b6d5SNiravkumar L Rabara else 6929ee5b6d5SNiravkumar L Rabara writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK); 69331fb632bSRamuthevar Vadivel Murugan 69431fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 69531fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTRD_START_MASK, 69631fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTRD); 69731fb632bSRamuthevar Vadivel Murugan 69831fb632bSRamuthevar Vadivel Murugan while (remaining > 0) { 69931fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->transfer_complete, 70031fb632bSRamuthevar Vadivel Murugan msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) 70131fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 70231fb632bSRamuthevar Vadivel Murugan 7039ee5b6d5SNiravkumar L Rabara /* 7049ee5b6d5SNiravkumar L Rabara * Disable all read interrupts until 7059ee5b6d5SNiravkumar L Rabara * we are out of "bytes to read" 7069ee5b6d5SNiravkumar L Rabara */ 7079ee5b6d5SNiravkumar L Rabara if (cqspi->slow_sram) 7089ee5b6d5SNiravkumar L Rabara writel(0x0, reg_base + CQSPI_REG_IRQMASK); 7099ee5b6d5SNiravkumar L Rabara 71031fb632bSRamuthevar Vadivel Murugan bytes_to_read = cqspi_get_rd_sram_level(cqspi); 71131fb632bSRamuthevar Vadivel Murugan 71231fb632bSRamuthevar Vadivel Murugan if (ret && bytes_to_read == 0) { 71331fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect read timeout, no bytes\n"); 71431fb632bSRamuthevar Vadivel Murugan goto failrd; 71531fb632bSRamuthevar Vadivel Murugan } 71631fb632bSRamuthevar Vadivel Murugan 71731fb632bSRamuthevar Vadivel Murugan while (bytes_to_read != 0) { 71831fb632bSRamuthevar Vadivel Murugan unsigned int word_remain = round_down(remaining, 4); 71931fb632bSRamuthevar Vadivel Murugan 72031fb632bSRamuthevar Vadivel Murugan bytes_to_read *= cqspi->fifo_width; 72131fb632bSRamuthevar Vadivel Murugan bytes_to_read = bytes_to_read > remaining ? 72231fb632bSRamuthevar Vadivel Murugan remaining : bytes_to_read; 72331fb632bSRamuthevar Vadivel Murugan bytes_to_read = round_down(bytes_to_read, 4); 72431fb632bSRamuthevar Vadivel Murugan /* Read 4 byte word chunks then single bytes */ 72531fb632bSRamuthevar Vadivel Murugan if (bytes_to_read) { 72631fb632bSRamuthevar Vadivel Murugan ioread32_rep(ahb_base, rxbuf, 72731fb632bSRamuthevar Vadivel Murugan (bytes_to_read / 4)); 72831fb632bSRamuthevar Vadivel Murugan } else if (!word_remain && mod_bytes) { 72931fb632bSRamuthevar Vadivel Murugan unsigned int temp = ioread32(ahb_base); 73031fb632bSRamuthevar Vadivel Murugan 73131fb632bSRamuthevar Vadivel Murugan bytes_to_read = mod_bytes; 73231fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, &temp, min((unsigned int) 73331fb632bSRamuthevar Vadivel Murugan (rxbuf_end - rxbuf), 73431fb632bSRamuthevar Vadivel Murugan bytes_to_read)); 73531fb632bSRamuthevar Vadivel Murugan } 73631fb632bSRamuthevar Vadivel Murugan rxbuf += bytes_to_read; 73731fb632bSRamuthevar Vadivel Murugan remaining -= bytes_to_read; 73831fb632bSRamuthevar Vadivel Murugan bytes_to_read = cqspi_get_rd_sram_level(cqspi); 73931fb632bSRamuthevar Vadivel Murugan } 74031fb632bSRamuthevar Vadivel Murugan 7419ee5b6d5SNiravkumar L Rabara if (remaining > 0) { 74231fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 7439ee5b6d5SNiravkumar L Rabara if (cqspi->slow_sram) 7449ee5b6d5SNiravkumar L Rabara writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK); 7459ee5b6d5SNiravkumar L Rabara } 74631fb632bSRamuthevar Vadivel Murugan } 74731fb632bSRamuthevar Vadivel Murugan 74831fb632bSRamuthevar Vadivel Murugan /* Check indirect done status */ 74931fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD, 75031fb632bSRamuthevar Vadivel Murugan CQSPI_REG_INDIRECTRD_DONE_MASK, 0); 75131fb632bSRamuthevar Vadivel Murugan if (ret) { 75231fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect read completion error (%i)\n", ret); 75331fb632bSRamuthevar Vadivel Murugan goto failrd; 75431fb632bSRamuthevar Vadivel Murugan } 75531fb632bSRamuthevar Vadivel Murugan 75631fb632bSRamuthevar Vadivel Murugan /* Disable interrupt */ 75731fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 75831fb632bSRamuthevar Vadivel Murugan 75931fb632bSRamuthevar Vadivel Murugan /* Clear indirect completion status */ 76031fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD); 76131fb632bSRamuthevar Vadivel Murugan 76231fb632bSRamuthevar Vadivel Murugan return 0; 76331fb632bSRamuthevar Vadivel Murugan 76431fb632bSRamuthevar Vadivel Murugan failrd: 76531fb632bSRamuthevar Vadivel Murugan /* Disable interrupt */ 76631fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 76731fb632bSRamuthevar Vadivel Murugan 76831fb632bSRamuthevar Vadivel Murugan /* Cancel the indirect read */ 76931fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 77031fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTRD); 77131fb632bSRamuthevar Vadivel Murugan return ret; 77231fb632bSRamuthevar Vadivel Murugan } 77331fb632bSRamuthevar Vadivel Murugan 7741a6f854fSSai Krishna Potthuri static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata, 7751a6f854fSSai Krishna Potthuri u_char *rxbuf, loff_t from_addr, 7761a6f854fSSai Krishna Potthuri size_t n_rx) 7771a6f854fSSai Krishna Potthuri { 7781a6f854fSSai Krishna Potthuri struct cqspi_st *cqspi = f_pdata->cqspi; 7791a6f854fSSai Krishna Potthuri struct device *dev = &cqspi->pdev->dev; 7801a6f854fSSai Krishna Potthuri void __iomem *reg_base = cqspi->iobase; 7811a6f854fSSai Krishna Potthuri u32 reg, bytes_to_dma; 7821a6f854fSSai Krishna Potthuri loff_t addr = from_addr; 7831a6f854fSSai Krishna Potthuri void *buf = rxbuf; 7841a6f854fSSai Krishna Potthuri dma_addr_t dma_addr; 7851a6f854fSSai Krishna Potthuri u8 bytes_rem; 7861a6f854fSSai Krishna Potthuri int ret = 0; 7871a6f854fSSai Krishna Potthuri 7881a6f854fSSai Krishna Potthuri bytes_rem = n_rx % 4; 7891a6f854fSSai Krishna Potthuri bytes_to_dma = (n_rx - bytes_rem); 7901a6f854fSSai Krishna Potthuri 7911a6f854fSSai Krishna Potthuri if (!bytes_to_dma) 7921a6f854fSSai Krishna Potthuri goto nondmard; 7931a6f854fSSai Krishna Potthuri 7941a6f854fSSai Krishna Potthuri ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA); 7951a6f854fSSai Krishna Potthuri if (ret) 7961a6f854fSSai Krishna Potthuri return ret; 7971a6f854fSSai Krishna Potthuri 7981a6f854fSSai Krishna Potthuri reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 7991a6f854fSSai Krishna Potthuri reg |= CQSPI_REG_CONFIG_DMA_MASK; 8001a6f854fSSai Krishna Potthuri writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 8011a6f854fSSai Krishna Potthuri 8021a6f854fSSai Krishna Potthuri dma_addr = dma_map_single(dev, rxbuf, bytes_to_dma, DMA_FROM_DEVICE); 8031a6f854fSSai Krishna Potthuri if (dma_mapping_error(dev, dma_addr)) { 8041a6f854fSSai Krishna Potthuri dev_err(dev, "dma mapping failed\n"); 8051a6f854fSSai Krishna Potthuri return -ENOMEM; 8061a6f854fSSai Krishna Potthuri } 8071a6f854fSSai Krishna Potthuri 8081a6f854fSSai Krishna Potthuri writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 8091a6f854fSSai Krishna Potthuri writel(bytes_to_dma, reg_base + CQSPI_REG_INDIRECTRDBYTES); 8101a6f854fSSai Krishna Potthuri writel(CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL, 8111a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_INDTRIG_ADDRRANGE); 8121a6f854fSSai Krishna Potthuri 8131a6f854fSSai Krishna Potthuri /* Clear all interrupts. */ 8141a6f854fSSai Krishna Potthuri writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 8151a6f854fSSai Krishna Potthuri 8161a6f854fSSai Krishna Potthuri /* Enable DMA done interrupt */ 8171a6f854fSSai Krishna Potthuri writel(CQSPI_REG_VERSAL_DMA_DST_DONE_MASK, 8181a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_VERSAL_DMA_DST_I_EN); 8191a6f854fSSai Krishna Potthuri 8201a6f854fSSai Krishna Potthuri /* Default DMA periph configuration */ 8211a6f854fSSai Krishna Potthuri writel(CQSPI_REG_VERSAL_DMA_VAL, reg_base + CQSPI_REG_DMA); 8221a6f854fSSai Krishna Potthuri 8231a6f854fSSai Krishna Potthuri /* Configure DMA Dst address */ 8241a6f854fSSai Krishna Potthuri writel(lower_32_bits(dma_addr), 8251a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR); 8261a6f854fSSai Krishna Potthuri writel(upper_32_bits(dma_addr), 8271a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB); 8281a6f854fSSai Krishna Potthuri 8291a6f854fSSai Krishna Potthuri /* Configure DMA Src address */ 8301a6f854fSSai Krishna Potthuri writel(cqspi->trigger_address, reg_base + 8311a6f854fSSai Krishna Potthuri CQSPI_REG_VERSAL_DMA_SRC_ADDR); 8321a6f854fSSai Krishna Potthuri 8331a6f854fSSai Krishna Potthuri /* Set DMA destination size */ 8341a6f854fSSai Krishna Potthuri writel(bytes_to_dma, reg_base + CQSPI_REG_VERSAL_DMA_DST_SIZE); 8351a6f854fSSai Krishna Potthuri 8361a6f854fSSai Krishna Potthuri /* Set DMA destination control */ 8371a6f854fSSai Krishna Potthuri writel(CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL, 8381a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_VERSAL_DMA_DST_CTRL); 8391a6f854fSSai Krishna Potthuri 8401a6f854fSSai Krishna Potthuri writel(CQSPI_REG_INDIRECTRD_START_MASK, 8411a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_INDIRECTRD); 8421a6f854fSSai Krishna Potthuri 8431a6f854fSSai Krishna Potthuri reinit_completion(&cqspi->transfer_complete); 8441a6f854fSSai Krishna Potthuri 8451a6f854fSSai Krishna Potthuri if (!wait_for_completion_timeout(&cqspi->transfer_complete, 8461a6f854fSSai Krishna Potthuri msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) { 8471a6f854fSSai Krishna Potthuri ret = -ETIMEDOUT; 8481a6f854fSSai Krishna Potthuri goto failrd; 8491a6f854fSSai Krishna Potthuri } 8501a6f854fSSai Krishna Potthuri 8511a6f854fSSai Krishna Potthuri /* Disable DMA interrupt */ 8521a6f854fSSai Krishna Potthuri writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS); 8531a6f854fSSai Krishna Potthuri 8541a6f854fSSai Krishna Potthuri /* Clear indirect completion status */ 8551a6f854fSSai Krishna Potthuri writel(CQSPI_REG_INDIRECTRD_DONE_MASK, 8561a6f854fSSai Krishna Potthuri cqspi->iobase + CQSPI_REG_INDIRECTRD); 8571a6f854fSSai Krishna Potthuri dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE); 8581a6f854fSSai Krishna Potthuri 8591a6f854fSSai Krishna Potthuri reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 8601a6f854fSSai Krishna Potthuri reg &= ~CQSPI_REG_CONFIG_DMA_MASK; 8611a6f854fSSai Krishna Potthuri writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 8621a6f854fSSai Krishna Potthuri 8631a6f854fSSai Krishna Potthuri ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, 8641a6f854fSSai Krishna Potthuri PM_OSPI_MUX_SEL_LINEAR); 8651a6f854fSSai Krishna Potthuri if (ret) 8661a6f854fSSai Krishna Potthuri return ret; 8671a6f854fSSai Krishna Potthuri 8681a6f854fSSai Krishna Potthuri nondmard: 8691a6f854fSSai Krishna Potthuri if (bytes_rem) { 8701a6f854fSSai Krishna Potthuri addr += bytes_to_dma; 8711a6f854fSSai Krishna Potthuri buf += bytes_to_dma; 8721a6f854fSSai Krishna Potthuri ret = cqspi_indirect_read_execute(f_pdata, buf, addr, 8731a6f854fSSai Krishna Potthuri bytes_rem); 8741a6f854fSSai Krishna Potthuri if (ret) 8751a6f854fSSai Krishna Potthuri return ret; 8761a6f854fSSai Krishna Potthuri } 8771a6f854fSSai Krishna Potthuri 8781a6f854fSSai Krishna Potthuri return 0; 8791a6f854fSSai Krishna Potthuri 8801a6f854fSSai Krishna Potthuri failrd: 8811a6f854fSSai Krishna Potthuri /* Disable DMA interrupt */ 8821a6f854fSSai Krishna Potthuri writel(0x0, reg_base + CQSPI_REG_VERSAL_DMA_DST_I_DIS); 8831a6f854fSSai Krishna Potthuri 8841a6f854fSSai Krishna Potthuri /* Cancel the indirect read */ 8851a6f854fSSai Krishna Potthuri writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 8861a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_INDIRECTRD); 8871a6f854fSSai Krishna Potthuri 888d9c55c95SArnd Bergmann dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE); 8891a6f854fSSai Krishna Potthuri 8901a6f854fSSai Krishna Potthuri reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 8911a6f854fSSai Krishna Potthuri reg &= ~CQSPI_REG_CONFIG_DMA_MASK; 8921a6f854fSSai Krishna Potthuri writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 8931a6f854fSSai Krishna Potthuri 8941a6f854fSSai Krishna Potthuri zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR); 8951a6f854fSSai Krishna Potthuri 8961a6f854fSSai Krishna Potthuri return ret; 8971a6f854fSSai Krishna Potthuri } 8981a6f854fSSai Krishna Potthuri 89931fb632bSRamuthevar Vadivel Murugan static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata, 90031fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 90131fb632bSRamuthevar Vadivel Murugan { 90231fb632bSRamuthevar Vadivel Murugan unsigned int reg; 903f453f293SPratyush Yadav int ret; 90431fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 90531fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 906f453f293SPratyush Yadav u8 opcode; 907f453f293SPratyush Yadav 90828ac902aSMatthias Schiffer ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB); 909f453f293SPratyush Yadav if (ret) 910f453f293SPratyush Yadav return ret; 911f453f293SPratyush Yadav 91228ac902aSMatthias Schiffer if (op->cmd.dtr) 913f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 914f453f293SPratyush Yadav else 915f453f293SPratyush Yadav opcode = op->cmd.opcode; 91631fb632bSRamuthevar Vadivel Murugan 91731fb632bSRamuthevar Vadivel Murugan /* Set opcode. */ 918f453f293SPratyush Yadav reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; 91928ac902aSMatthias Schiffer reg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; 92028ac902aSMatthias Schiffer reg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; 92131fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_WR_INSTR); 92228ac902aSMatthias Schiffer reg = cqspi_calc_rdreg(op); 92331fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_RD_INSTR); 92431fb632bSRamuthevar Vadivel Murugan 925f453f293SPratyush Yadav /* 9269cb2ff11SApurva Nandan * SPI NAND flashes require the address of the status register to be 9279cb2ff11SApurva Nandan * passed in the Read SR command. Also, some SPI NOR flashes like the 9289cb2ff11SApurva Nandan * cypress Semper flash expect a 4-byte dummy address in the Read SR 9299cb2ff11SApurva Nandan * command in DTR mode. 9309cb2ff11SApurva Nandan * 9319cb2ff11SApurva Nandan * But this controller does not support address phase in the Read SR 9329cb2ff11SApurva Nandan * command when doing auto-HW polling. So, disable write completion 9339cb2ff11SApurva Nandan * polling on the controller's side. spinand and spi-nor will take 9349cb2ff11SApurva Nandan * care of polling the status register. 935f453f293SPratyush Yadav */ 93698d948ebSDinh Nguyen if (cqspi->wr_completion) { 937f453f293SPratyush Yadav reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL); 938f453f293SPratyush Yadav reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL; 939f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL); 94098d948ebSDinh Nguyen } 941f453f293SPratyush Yadav 94231fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_SIZE); 94331fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 94431fb632bSRamuthevar Vadivel Murugan reg |= (op->addr.nbytes - 1); 94531fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_SIZE); 94631fb632bSRamuthevar Vadivel Murugan return 0; 94731fb632bSRamuthevar Vadivel Murugan } 94831fb632bSRamuthevar Vadivel Murugan 94931fb632bSRamuthevar Vadivel Murugan static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, 95031fb632bSRamuthevar Vadivel Murugan loff_t to_addr, const u8 *txbuf, 95131fb632bSRamuthevar Vadivel Murugan const size_t n_tx) 95231fb632bSRamuthevar Vadivel Murugan { 95331fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 95431fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 95531fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 95631fb632bSRamuthevar Vadivel Murugan unsigned int remaining = n_tx; 95731fb632bSRamuthevar Vadivel Murugan unsigned int write_bytes; 95831fb632bSRamuthevar Vadivel Murugan int ret; 95931fb632bSRamuthevar Vadivel Murugan 96031fb632bSRamuthevar Vadivel Murugan writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR); 96131fb632bSRamuthevar Vadivel Murugan writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES); 96231fb632bSRamuthevar Vadivel Murugan 96331fb632bSRamuthevar Vadivel Murugan /* Clear all interrupts. */ 96431fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 96531fb632bSRamuthevar Vadivel Murugan 96631fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK); 96731fb632bSRamuthevar Vadivel Murugan 96831fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 96931fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_START_MASK, 97031fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTWR); 97131fb632bSRamuthevar Vadivel Murugan /* 97231fb632bSRamuthevar Vadivel Murugan * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access 97331fb632bSRamuthevar Vadivel Murugan * Controller programming sequence, couple of cycles of 97431fb632bSRamuthevar Vadivel Murugan * QSPI_REF_CLK delay is required for the above bit to 97531fb632bSRamuthevar Vadivel Murugan * be internally synchronized by the QSPI module. Provide 5 97631fb632bSRamuthevar Vadivel Murugan * cycles of delay. 97731fb632bSRamuthevar Vadivel Murugan */ 97831fb632bSRamuthevar Vadivel Murugan if (cqspi->wr_delay) 97931fb632bSRamuthevar Vadivel Murugan ndelay(cqspi->wr_delay); 98031fb632bSRamuthevar Vadivel Murugan 98131fb632bSRamuthevar Vadivel Murugan while (remaining > 0) { 98231fb632bSRamuthevar Vadivel Murugan size_t write_words, mod_bytes; 98331fb632bSRamuthevar Vadivel Murugan 98431fb632bSRamuthevar Vadivel Murugan write_bytes = remaining; 98531fb632bSRamuthevar Vadivel Murugan write_words = write_bytes / 4; 98631fb632bSRamuthevar Vadivel Murugan mod_bytes = write_bytes % 4; 98731fb632bSRamuthevar Vadivel Murugan /* Write 4 bytes at a time then single bytes. */ 98831fb632bSRamuthevar Vadivel Murugan if (write_words) { 98931fb632bSRamuthevar Vadivel Murugan iowrite32_rep(cqspi->ahb_base, txbuf, write_words); 99031fb632bSRamuthevar Vadivel Murugan txbuf += (write_words * 4); 99131fb632bSRamuthevar Vadivel Murugan } 99231fb632bSRamuthevar Vadivel Murugan if (mod_bytes) { 99331fb632bSRamuthevar Vadivel Murugan unsigned int temp = 0xFFFFFFFF; 99431fb632bSRamuthevar Vadivel Murugan 99531fb632bSRamuthevar Vadivel Murugan memcpy(&temp, txbuf, mod_bytes); 99631fb632bSRamuthevar Vadivel Murugan iowrite32(temp, cqspi->ahb_base); 99731fb632bSRamuthevar Vadivel Murugan txbuf += mod_bytes; 99831fb632bSRamuthevar Vadivel Murugan } 99931fb632bSRamuthevar Vadivel Murugan 100031fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->transfer_complete, 100131fb632bSRamuthevar Vadivel Murugan msecs_to_jiffies(CQSPI_TIMEOUT_MS))) { 100231fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect write timeout\n"); 100331fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 100431fb632bSRamuthevar Vadivel Murugan goto failwr; 100531fb632bSRamuthevar Vadivel Murugan } 100631fb632bSRamuthevar Vadivel Murugan 100731fb632bSRamuthevar Vadivel Murugan remaining -= write_bytes; 100831fb632bSRamuthevar Vadivel Murugan 100931fb632bSRamuthevar Vadivel Murugan if (remaining > 0) 101031fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 101131fb632bSRamuthevar Vadivel Murugan } 101231fb632bSRamuthevar Vadivel Murugan 101331fb632bSRamuthevar Vadivel Murugan /* Check indirect done status */ 101431fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR, 101531fb632bSRamuthevar Vadivel Murugan CQSPI_REG_INDIRECTWR_DONE_MASK, 0); 101631fb632bSRamuthevar Vadivel Murugan if (ret) { 101731fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect write completion error (%i)\n", ret); 101831fb632bSRamuthevar Vadivel Murugan goto failwr; 101931fb632bSRamuthevar Vadivel Murugan } 102031fb632bSRamuthevar Vadivel Murugan 102131fb632bSRamuthevar Vadivel Murugan /* Disable interrupt. */ 102231fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 102331fb632bSRamuthevar Vadivel Murugan 102431fb632bSRamuthevar Vadivel Murugan /* Clear indirect completion status */ 102531fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR); 102631fb632bSRamuthevar Vadivel Murugan 102731fb632bSRamuthevar Vadivel Murugan cqspi_wait_idle(cqspi); 102831fb632bSRamuthevar Vadivel Murugan 102931fb632bSRamuthevar Vadivel Murugan return 0; 103031fb632bSRamuthevar Vadivel Murugan 103131fb632bSRamuthevar Vadivel Murugan failwr: 103231fb632bSRamuthevar Vadivel Murugan /* Disable interrupt. */ 103331fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 103431fb632bSRamuthevar Vadivel Murugan 103531fb632bSRamuthevar Vadivel Murugan /* Cancel the indirect write */ 103631fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 103731fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTWR); 103831fb632bSRamuthevar Vadivel Murugan return ret; 103931fb632bSRamuthevar Vadivel Murugan } 104031fb632bSRamuthevar Vadivel Murugan 104131fb632bSRamuthevar Vadivel Murugan static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata) 104231fb632bSRamuthevar Vadivel Murugan { 104331fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 104431fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 104531fb632bSRamuthevar Vadivel Murugan unsigned int chip_select = f_pdata->cs; 104631fb632bSRamuthevar Vadivel Murugan unsigned int reg; 104731fb632bSRamuthevar Vadivel Murugan 104831fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG); 104931fb632bSRamuthevar Vadivel Murugan if (cqspi->is_decoded_cs) { 105031fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CONFIG_DECODE_MASK; 105131fb632bSRamuthevar Vadivel Murugan } else { 105231fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; 105331fb632bSRamuthevar Vadivel Murugan 105431fb632bSRamuthevar Vadivel Murugan /* Convert CS if without decoder. 105531fb632bSRamuthevar Vadivel Murugan * CS0 to 4b'1110 105631fb632bSRamuthevar Vadivel Murugan * CS1 to 4b'1101 105731fb632bSRamuthevar Vadivel Murugan * CS2 to 4b'1011 105831fb632bSRamuthevar Vadivel Murugan * CS3 to 4b'0111 105931fb632bSRamuthevar Vadivel Murugan */ 106031fb632bSRamuthevar Vadivel Murugan chip_select = 0xF & ~(1 << chip_select); 106131fb632bSRamuthevar Vadivel Murugan } 106231fb632bSRamuthevar Vadivel Murugan 106331fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK 106431fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CONFIG_CHIPSELECT_LSB); 106531fb632bSRamuthevar Vadivel Murugan reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK) 106631fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CONFIG_CHIPSELECT_LSB; 106731fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG); 106831fb632bSRamuthevar Vadivel Murugan } 106931fb632bSRamuthevar Vadivel Murugan 107031fb632bSRamuthevar Vadivel Murugan static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz, 107131fb632bSRamuthevar Vadivel Murugan const unsigned int ns_val) 107231fb632bSRamuthevar Vadivel Murugan { 107331fb632bSRamuthevar Vadivel Murugan unsigned int ticks; 107431fb632bSRamuthevar Vadivel Murugan 107531fb632bSRamuthevar Vadivel Murugan ticks = ref_clk_hz / 1000; /* kHz */ 107631fb632bSRamuthevar Vadivel Murugan ticks = DIV_ROUND_UP(ticks * ns_val, 1000000); 107731fb632bSRamuthevar Vadivel Murugan 107831fb632bSRamuthevar Vadivel Murugan return ticks; 107931fb632bSRamuthevar Vadivel Murugan } 108031fb632bSRamuthevar Vadivel Murugan 108131fb632bSRamuthevar Vadivel Murugan static void cqspi_delay(struct cqspi_flash_pdata *f_pdata) 108231fb632bSRamuthevar Vadivel Murugan { 108331fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 108431fb632bSRamuthevar Vadivel Murugan void __iomem *iobase = cqspi->iobase; 108531fb632bSRamuthevar Vadivel Murugan const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 108631fb632bSRamuthevar Vadivel Murugan unsigned int tshsl, tchsh, tslch, tsd2d; 108731fb632bSRamuthevar Vadivel Murugan unsigned int reg; 108831fb632bSRamuthevar Vadivel Murugan unsigned int tsclk; 108931fb632bSRamuthevar Vadivel Murugan 109031fb632bSRamuthevar Vadivel Murugan /* calculate the number of ref ticks for one sclk tick */ 109131fb632bSRamuthevar Vadivel Murugan tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk); 109231fb632bSRamuthevar Vadivel Murugan 109331fb632bSRamuthevar Vadivel Murugan tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns); 109431fb632bSRamuthevar Vadivel Murugan /* this particular value must be at least one sclk */ 109531fb632bSRamuthevar Vadivel Murugan if (tshsl < tsclk) 109631fb632bSRamuthevar Vadivel Murugan tshsl = tsclk; 109731fb632bSRamuthevar Vadivel Murugan 109831fb632bSRamuthevar Vadivel Murugan tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns); 109931fb632bSRamuthevar Vadivel Murugan tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns); 110031fb632bSRamuthevar Vadivel Murugan tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns); 110131fb632bSRamuthevar Vadivel Murugan 110231fb632bSRamuthevar Vadivel Murugan reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK) 110331fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSHSL_LSB; 110431fb632bSRamuthevar Vadivel Murugan reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK) 110531fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TCHSH_LSB; 110631fb632bSRamuthevar Vadivel Murugan reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK) 110731fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSLCH_LSB; 110831fb632bSRamuthevar Vadivel Murugan reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK) 110931fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSD2D_LSB; 111031fb632bSRamuthevar Vadivel Murugan writel(reg, iobase + CQSPI_REG_DELAY); 111131fb632bSRamuthevar Vadivel Murugan } 111231fb632bSRamuthevar Vadivel Murugan 111331fb632bSRamuthevar Vadivel Murugan static void cqspi_config_baudrate_div(struct cqspi_st *cqspi) 111431fb632bSRamuthevar Vadivel Murugan { 111531fb632bSRamuthevar Vadivel Murugan const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 111631fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 111731fb632bSRamuthevar Vadivel Murugan u32 reg, div; 111831fb632bSRamuthevar Vadivel Murugan 111931fb632bSRamuthevar Vadivel Murugan /* Recalculate the baudrate divisor based on QSPI specification. */ 112031fb632bSRamuthevar Vadivel Murugan div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1; 112131fb632bSRamuthevar Vadivel Murugan 1122*f8fc65e5SNathan Barrett-Morrison /* Maximum baud divisor */ 1123*f8fc65e5SNathan Barrett-Morrison if (div > CQSPI_REG_CONFIG_BAUD_MASK) { 1124*f8fc65e5SNathan Barrett-Morrison div = CQSPI_REG_CONFIG_BAUD_MASK; 1125*f8fc65e5SNathan Barrett-Morrison dev_warn(&cqspi->pdev->dev, 1126*f8fc65e5SNathan Barrett-Morrison "Unable to adjust clock <= %d hz. Reduced to %d hz\n", 1127*f8fc65e5SNathan Barrett-Morrison cqspi->sclk, ref_clk_hz/((div+1)*2)); 1128*f8fc65e5SNathan Barrett-Morrison } 1129*f8fc65e5SNathan Barrett-Morrison 113031fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG); 113131fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); 113231fb632bSRamuthevar Vadivel Murugan reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB; 113331fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG); 113431fb632bSRamuthevar Vadivel Murugan } 113531fb632bSRamuthevar Vadivel Murugan 113631fb632bSRamuthevar Vadivel Murugan static void cqspi_readdata_capture(struct cqspi_st *cqspi, 113731fb632bSRamuthevar Vadivel Murugan const bool bypass, 113831fb632bSRamuthevar Vadivel Murugan const unsigned int delay) 113931fb632bSRamuthevar Vadivel Murugan { 114031fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 114131fb632bSRamuthevar Vadivel Murugan unsigned int reg; 114231fb632bSRamuthevar Vadivel Murugan 114331fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_READCAPTURE); 114431fb632bSRamuthevar Vadivel Murugan 114531fb632bSRamuthevar Vadivel Murugan if (bypass) 114631fb632bSRamuthevar Vadivel Murugan reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 114731fb632bSRamuthevar Vadivel Murugan else 114831fb632bSRamuthevar Vadivel Murugan reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 114931fb632bSRamuthevar Vadivel Murugan 115031fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK 115131fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_READCAPTURE_DELAY_LSB); 115231fb632bSRamuthevar Vadivel Murugan 115331fb632bSRamuthevar Vadivel Murugan reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK) 115431fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_READCAPTURE_DELAY_LSB; 115531fb632bSRamuthevar Vadivel Murugan 115631fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_READCAPTURE); 115731fb632bSRamuthevar Vadivel Murugan } 115831fb632bSRamuthevar Vadivel Murugan 115931fb632bSRamuthevar Vadivel Murugan static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable) 116031fb632bSRamuthevar Vadivel Murugan { 116131fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 116231fb632bSRamuthevar Vadivel Murugan unsigned int reg; 116331fb632bSRamuthevar Vadivel Murugan 116431fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG); 116531fb632bSRamuthevar Vadivel Murugan 116631fb632bSRamuthevar Vadivel Murugan if (enable) 116731fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CONFIG_ENABLE_MASK; 116831fb632bSRamuthevar Vadivel Murugan else 116931fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; 117031fb632bSRamuthevar Vadivel Murugan 117131fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG); 117231fb632bSRamuthevar Vadivel Murugan } 117331fb632bSRamuthevar Vadivel Murugan 117431fb632bSRamuthevar Vadivel Murugan static void cqspi_configure(struct cqspi_flash_pdata *f_pdata, 117531fb632bSRamuthevar Vadivel Murugan unsigned long sclk) 117631fb632bSRamuthevar Vadivel Murugan { 117731fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 117831fb632bSRamuthevar Vadivel Murugan int switch_cs = (cqspi->current_cs != f_pdata->cs); 117931fb632bSRamuthevar Vadivel Murugan int switch_ck = (cqspi->sclk != sclk); 118031fb632bSRamuthevar Vadivel Murugan 118131fb632bSRamuthevar Vadivel Murugan if (switch_cs || switch_ck) 118231fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 118331fb632bSRamuthevar Vadivel Murugan 118431fb632bSRamuthevar Vadivel Murugan /* Switch chip select. */ 118531fb632bSRamuthevar Vadivel Murugan if (switch_cs) { 118631fb632bSRamuthevar Vadivel Murugan cqspi->current_cs = f_pdata->cs; 118731fb632bSRamuthevar Vadivel Murugan cqspi_chipselect(f_pdata); 118831fb632bSRamuthevar Vadivel Murugan } 118931fb632bSRamuthevar Vadivel Murugan 119031fb632bSRamuthevar Vadivel Murugan /* Setup baudrate divisor and delays */ 119131fb632bSRamuthevar Vadivel Murugan if (switch_ck) { 119231fb632bSRamuthevar Vadivel Murugan cqspi->sclk = sclk; 119331fb632bSRamuthevar Vadivel Murugan cqspi_config_baudrate_div(cqspi); 119431fb632bSRamuthevar Vadivel Murugan cqspi_delay(f_pdata); 119531fb632bSRamuthevar Vadivel Murugan cqspi_readdata_capture(cqspi, !cqspi->rclk_en, 119631fb632bSRamuthevar Vadivel Murugan f_pdata->read_delay); 119731fb632bSRamuthevar Vadivel Murugan } 119831fb632bSRamuthevar Vadivel Murugan 119931fb632bSRamuthevar Vadivel Murugan if (switch_cs || switch_ck) 120031fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1); 120131fb632bSRamuthevar Vadivel Murugan } 120231fb632bSRamuthevar Vadivel Murugan 120331fb632bSRamuthevar Vadivel Murugan static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata, 120431fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 120531fb632bSRamuthevar Vadivel Murugan { 120631fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 120731fb632bSRamuthevar Vadivel Murugan loff_t to = op->addr.val; 120831fb632bSRamuthevar Vadivel Murugan size_t len = op->data.nbytes; 120931fb632bSRamuthevar Vadivel Murugan const u_char *buf = op->data.buf.out; 121031fb632bSRamuthevar Vadivel Murugan int ret; 121131fb632bSRamuthevar Vadivel Murugan 121231fb632bSRamuthevar Vadivel Murugan ret = cqspi_write_setup(f_pdata, op); 121331fb632bSRamuthevar Vadivel Murugan if (ret) 121431fb632bSRamuthevar Vadivel Murugan return ret; 121531fb632bSRamuthevar Vadivel Murugan 1216f453f293SPratyush Yadav /* 1217f453f293SPratyush Yadav * Some flashes like the Cypress Semper flash expect a dummy 4-byte 1218f453f293SPratyush Yadav * address (all 0s) with the read status register command in DTR mode. 1219f453f293SPratyush Yadav * But this controller does not support sending dummy address bytes to 1220f453f293SPratyush Yadav * the flash when it is polling the write completion register in DTR 1221f453f293SPratyush Yadav * mode. So, we can not use direct mode when in DTR mode for writing 1222f453f293SPratyush Yadav * data. 1223f453f293SPratyush Yadav */ 122428ac902aSMatthias Schiffer if (!op->cmd.dtr && cqspi->use_direct_mode && 1225f453f293SPratyush Yadav ((to + len) <= cqspi->ahb_size)) { 122631fb632bSRamuthevar Vadivel Murugan memcpy_toio(cqspi->ahb_base + to, buf, len); 122731fb632bSRamuthevar Vadivel Murugan return cqspi_wait_idle(cqspi); 122831fb632bSRamuthevar Vadivel Murugan } 122931fb632bSRamuthevar Vadivel Murugan 123031fb632bSRamuthevar Vadivel Murugan return cqspi_indirect_write_execute(f_pdata, to, buf, len); 123131fb632bSRamuthevar Vadivel Murugan } 123231fb632bSRamuthevar Vadivel Murugan 123331fb632bSRamuthevar Vadivel Murugan static void cqspi_rx_dma_callback(void *param) 123431fb632bSRamuthevar Vadivel Murugan { 123531fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = param; 123631fb632bSRamuthevar Vadivel Murugan 123731fb632bSRamuthevar Vadivel Murugan complete(&cqspi->rx_dma_complete); 123831fb632bSRamuthevar Vadivel Murugan } 123931fb632bSRamuthevar Vadivel Murugan 124031fb632bSRamuthevar Vadivel Murugan static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata, 124131fb632bSRamuthevar Vadivel Murugan u_char *buf, loff_t from, size_t len) 124231fb632bSRamuthevar Vadivel Murugan { 124331fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 124431fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 124531fb632bSRamuthevar Vadivel Murugan enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; 124631fb632bSRamuthevar Vadivel Murugan dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from; 124731fb632bSRamuthevar Vadivel Murugan int ret = 0; 124831fb632bSRamuthevar Vadivel Murugan struct dma_async_tx_descriptor *tx; 124931fb632bSRamuthevar Vadivel Murugan dma_cookie_t cookie; 125031fb632bSRamuthevar Vadivel Murugan dma_addr_t dma_dst; 125183048015SVignesh Raghavendra struct device *ddev; 125231fb632bSRamuthevar Vadivel Murugan 125331fb632bSRamuthevar Vadivel Murugan if (!cqspi->rx_chan || !virt_addr_valid(buf)) { 125431fb632bSRamuthevar Vadivel Murugan memcpy_fromio(buf, cqspi->ahb_base + from, len); 125531fb632bSRamuthevar Vadivel Murugan return 0; 125631fb632bSRamuthevar Vadivel Murugan } 125731fb632bSRamuthevar Vadivel Murugan 125883048015SVignesh Raghavendra ddev = cqspi->rx_chan->device->dev; 125983048015SVignesh Raghavendra dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE); 126083048015SVignesh Raghavendra if (dma_mapping_error(ddev, dma_dst)) { 126131fb632bSRamuthevar Vadivel Murugan dev_err(dev, "dma mapping failed\n"); 126231fb632bSRamuthevar Vadivel Murugan return -ENOMEM; 126331fb632bSRamuthevar Vadivel Murugan } 126431fb632bSRamuthevar Vadivel Murugan tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src, 126531fb632bSRamuthevar Vadivel Murugan len, flags); 126631fb632bSRamuthevar Vadivel Murugan if (!tx) { 126731fb632bSRamuthevar Vadivel Murugan dev_err(dev, "device_prep_dma_memcpy error\n"); 126831fb632bSRamuthevar Vadivel Murugan ret = -EIO; 126931fb632bSRamuthevar Vadivel Murugan goto err_unmap; 127031fb632bSRamuthevar Vadivel Murugan } 127131fb632bSRamuthevar Vadivel Murugan 127231fb632bSRamuthevar Vadivel Murugan tx->callback = cqspi_rx_dma_callback; 127331fb632bSRamuthevar Vadivel Murugan tx->callback_param = cqspi; 127431fb632bSRamuthevar Vadivel Murugan cookie = tx->tx_submit(tx); 127531fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->rx_dma_complete); 127631fb632bSRamuthevar Vadivel Murugan 127731fb632bSRamuthevar Vadivel Murugan ret = dma_submit_error(cookie); 127831fb632bSRamuthevar Vadivel Murugan if (ret) { 127931fb632bSRamuthevar Vadivel Murugan dev_err(dev, "dma_submit_error %d\n", cookie); 128031fb632bSRamuthevar Vadivel Murugan ret = -EIO; 128131fb632bSRamuthevar Vadivel Murugan goto err_unmap; 128231fb632bSRamuthevar Vadivel Murugan } 128331fb632bSRamuthevar Vadivel Murugan 128431fb632bSRamuthevar Vadivel Murugan dma_async_issue_pending(cqspi->rx_chan); 128531fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->rx_dma_complete, 12862ef0170eSPratyush Yadav msecs_to_jiffies(max_t(size_t, len, 500)))) { 128731fb632bSRamuthevar Vadivel Murugan dmaengine_terminate_sync(cqspi->rx_chan); 128831fb632bSRamuthevar Vadivel Murugan dev_err(dev, "DMA wait_for_completion_timeout\n"); 128931fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 129031fb632bSRamuthevar Vadivel Murugan goto err_unmap; 129131fb632bSRamuthevar Vadivel Murugan } 129231fb632bSRamuthevar Vadivel Murugan 129331fb632bSRamuthevar Vadivel Murugan err_unmap: 129483048015SVignesh Raghavendra dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE); 129531fb632bSRamuthevar Vadivel Murugan 129631fb632bSRamuthevar Vadivel Murugan return ret; 129731fb632bSRamuthevar Vadivel Murugan } 129831fb632bSRamuthevar Vadivel Murugan 129931fb632bSRamuthevar Vadivel Murugan static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata, 130031fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 130131fb632bSRamuthevar Vadivel Murugan { 130231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 13031a6f854fSSai Krishna Potthuri struct device *dev = &cqspi->pdev->dev; 13041a6f854fSSai Krishna Potthuri const struct cqspi_driver_platdata *ddata; 130531fb632bSRamuthevar Vadivel Murugan loff_t from = op->addr.val; 130631fb632bSRamuthevar Vadivel Murugan size_t len = op->data.nbytes; 130731fb632bSRamuthevar Vadivel Murugan u_char *buf = op->data.buf.in; 13081a6f854fSSai Krishna Potthuri u64 dma_align = (u64)(uintptr_t)buf; 130931fb632bSRamuthevar Vadivel Murugan int ret; 131031fb632bSRamuthevar Vadivel Murugan 13111a6f854fSSai Krishna Potthuri ddata = of_device_get_match_data(dev); 131231fb632bSRamuthevar Vadivel Murugan 131331fb632bSRamuthevar Vadivel Murugan ret = cqspi_read_setup(f_pdata, op); 131431fb632bSRamuthevar Vadivel Murugan if (ret) 131531fb632bSRamuthevar Vadivel Murugan return ret; 131631fb632bSRamuthevar Vadivel Murugan 131731fb632bSRamuthevar Vadivel Murugan if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) 131831fb632bSRamuthevar Vadivel Murugan return cqspi_direct_read_execute(f_pdata, buf, from, len); 131931fb632bSRamuthevar Vadivel Murugan 13201a6f854fSSai Krishna Potthuri if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma && 13211a6f854fSSai Krishna Potthuri virt_addr_valid(buf) && ((dma_align & CQSPI_DMA_UNALIGN) == 0)) 13221a6f854fSSai Krishna Potthuri return ddata->indirect_read_dma(f_pdata, buf, from, len); 13231a6f854fSSai Krishna Potthuri 132431fb632bSRamuthevar Vadivel Murugan return cqspi_indirect_read_execute(f_pdata, buf, from, len); 132531fb632bSRamuthevar Vadivel Murugan } 132631fb632bSRamuthevar Vadivel Murugan 132731fb632bSRamuthevar Vadivel Murugan static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op) 132831fb632bSRamuthevar Vadivel Murugan { 132931fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); 133031fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata; 133131fb632bSRamuthevar Vadivel Murugan 133231fb632bSRamuthevar Vadivel Murugan f_pdata = &cqspi->f_pdata[mem->spi->chip_select]; 133331fb632bSRamuthevar Vadivel Murugan cqspi_configure(f_pdata, mem->spi->max_speed_hz); 133431fb632bSRamuthevar Vadivel Murugan 133531fb632bSRamuthevar Vadivel Murugan if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { 133631fb632bSRamuthevar Vadivel Murugan if (!op->addr.nbytes) 133731fb632bSRamuthevar Vadivel Murugan return cqspi_command_read(f_pdata, op); 133831fb632bSRamuthevar Vadivel Murugan 133931fb632bSRamuthevar Vadivel Murugan return cqspi_read(f_pdata, op); 134031fb632bSRamuthevar Vadivel Murugan } 134131fb632bSRamuthevar Vadivel Murugan 134231fb632bSRamuthevar Vadivel Murugan if (!op->addr.nbytes || !op->data.buf.out) 134331fb632bSRamuthevar Vadivel Murugan return cqspi_command_write(f_pdata, op); 134431fb632bSRamuthevar Vadivel Murugan 134531fb632bSRamuthevar Vadivel Murugan return cqspi_write(f_pdata, op); 134631fb632bSRamuthevar Vadivel Murugan } 134731fb632bSRamuthevar Vadivel Murugan 134831fb632bSRamuthevar Vadivel Murugan static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) 134931fb632bSRamuthevar Vadivel Murugan { 135031fb632bSRamuthevar Vadivel Murugan int ret; 135131fb632bSRamuthevar Vadivel Murugan 135231fb632bSRamuthevar Vadivel Murugan ret = cqspi_mem_process(mem, op); 135331fb632bSRamuthevar Vadivel Murugan if (ret) 135431fb632bSRamuthevar Vadivel Murugan dev_err(&mem->spi->dev, "operation failed with %d\n", ret); 135531fb632bSRamuthevar Vadivel Murugan 135631fb632bSRamuthevar Vadivel Murugan return ret; 135731fb632bSRamuthevar Vadivel Murugan } 135831fb632bSRamuthevar Vadivel Murugan 1359a273596bSPratyush Yadav static bool cqspi_supports_mem_op(struct spi_mem *mem, 1360a273596bSPratyush Yadav const struct spi_mem_op *op) 1361a273596bSPratyush Yadav { 1362f453f293SPratyush Yadav bool all_true, all_false; 1363f453f293SPratyush Yadav 13640395be96SApurva Nandan /* 13650395be96SApurva Nandan * op->dummy.dtr is required for converting nbytes into ncycles. 13660395be96SApurva Nandan * Also, don't check the dtr field of the op phase having zero nbytes. 13670395be96SApurva Nandan */ 13680395be96SApurva Nandan all_true = op->cmd.dtr && 13690395be96SApurva Nandan (!op->addr.nbytes || op->addr.dtr) && 13700395be96SApurva Nandan (!op->dummy.nbytes || op->dummy.dtr) && 13710395be96SApurva Nandan (!op->data.nbytes || op->data.dtr); 13720395be96SApurva Nandan 1373f453f293SPratyush Yadav all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && 1374f453f293SPratyush Yadav !op->data.dtr; 1375f453f293SPratyush Yadav 1376f1d388f2SMatthias Schiffer if (all_true) { 1377f1d388f2SMatthias Schiffer /* Right now we only support 8-8-8 DTR mode. */ 1378f1d388f2SMatthias Schiffer if (op->cmd.nbytes && op->cmd.buswidth != 8) 1379f453f293SPratyush Yadav return false; 1380f1d388f2SMatthias Schiffer if (op->addr.nbytes && op->addr.buswidth != 8) 1381f1d388f2SMatthias Schiffer return false; 1382f1d388f2SMatthias Schiffer if (op->data.nbytes && op->data.buswidth != 8) 1383f1d388f2SMatthias Schiffer return false; 13841aeda096SMatthias Schiffer } else if (!all_false) { 1385f1d388f2SMatthias Schiffer /* Mixed DTR modes are not supported. */ 1386f1d388f2SMatthias Schiffer return false; 1387f1d388f2SMatthias Schiffer } 1388f453f293SPratyush Yadav 1389d2275139SPratyush Yadav return spi_mem_default_supports_op(mem, op); 1390a273596bSPratyush Yadav } 1391a273596bSPratyush Yadav 139231fb632bSRamuthevar Vadivel Murugan static int cqspi_of_get_flash_pdata(struct platform_device *pdev, 139331fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata, 139431fb632bSRamuthevar Vadivel Murugan struct device_node *np) 139531fb632bSRamuthevar Vadivel Murugan { 139631fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) { 139731fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine read-delay\n"); 139831fb632bSRamuthevar Vadivel Murugan return -ENXIO; 139931fb632bSRamuthevar Vadivel Murugan } 140031fb632bSRamuthevar Vadivel Murugan 140131fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) { 140231fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tshsl-ns\n"); 140331fb632bSRamuthevar Vadivel Murugan return -ENXIO; 140431fb632bSRamuthevar Vadivel Murugan } 140531fb632bSRamuthevar Vadivel Murugan 140631fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) { 140731fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n"); 140831fb632bSRamuthevar Vadivel Murugan return -ENXIO; 140931fb632bSRamuthevar Vadivel Murugan } 141031fb632bSRamuthevar Vadivel Murugan 141131fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) { 141231fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tchsh-ns\n"); 141331fb632bSRamuthevar Vadivel Murugan return -ENXIO; 141431fb632bSRamuthevar Vadivel Murugan } 141531fb632bSRamuthevar Vadivel Murugan 141631fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) { 141731fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tslch-ns\n"); 141831fb632bSRamuthevar Vadivel Murugan return -ENXIO; 141931fb632bSRamuthevar Vadivel Murugan } 142031fb632bSRamuthevar Vadivel Murugan 142131fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) { 142231fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n"); 142331fb632bSRamuthevar Vadivel Murugan return -ENXIO; 142431fb632bSRamuthevar Vadivel Murugan } 142531fb632bSRamuthevar Vadivel Murugan 142631fb632bSRamuthevar Vadivel Murugan return 0; 142731fb632bSRamuthevar Vadivel Murugan } 142831fb632bSRamuthevar Vadivel Murugan 142931fb632bSRamuthevar Vadivel Murugan static int cqspi_of_get_pdata(struct cqspi_st *cqspi) 143031fb632bSRamuthevar Vadivel Murugan { 143131fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 143231fb632bSRamuthevar Vadivel Murugan struct device_node *np = dev->of_node; 143309e393e3SSai Krishna Potthuri u32 id[2]; 143431fb632bSRamuthevar Vadivel Murugan 143531fb632bSRamuthevar Vadivel Murugan cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); 143631fb632bSRamuthevar Vadivel Murugan 143731fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { 143831fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine fifo-depth\n"); 143931fb632bSRamuthevar Vadivel Murugan return -ENXIO; 144031fb632bSRamuthevar Vadivel Murugan } 144131fb632bSRamuthevar Vadivel Murugan 144231fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) { 144331fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine fifo-width\n"); 144431fb632bSRamuthevar Vadivel Murugan return -ENXIO; 144531fb632bSRamuthevar Vadivel Murugan } 144631fb632bSRamuthevar Vadivel Murugan 144731fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,trigger-address", 144831fb632bSRamuthevar Vadivel Murugan &cqspi->trigger_address)) { 144931fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine trigger-address\n"); 145031fb632bSRamuthevar Vadivel Murugan return -ENXIO; 145131fb632bSRamuthevar Vadivel Murugan } 145231fb632bSRamuthevar Vadivel Murugan 1453b436fb7dSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) 1454b436fb7dSRamuthevar Vadivel Murugan cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT; 1455b436fb7dSRamuthevar Vadivel Murugan 145631fb632bSRamuthevar Vadivel Murugan cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); 145731fb632bSRamuthevar Vadivel Murugan 145809e393e3SSai Krishna Potthuri if (!of_property_read_u32_array(np, "power-domains", id, 145909e393e3SSai Krishna Potthuri ARRAY_SIZE(id))) 146009e393e3SSai Krishna Potthuri cqspi->pd_dev_id = id[1]; 146109e393e3SSai Krishna Potthuri 146231fb632bSRamuthevar Vadivel Murugan return 0; 146331fb632bSRamuthevar Vadivel Murugan } 146431fb632bSRamuthevar Vadivel Murugan 146531fb632bSRamuthevar Vadivel Murugan static void cqspi_controller_init(struct cqspi_st *cqspi) 146631fb632bSRamuthevar Vadivel Murugan { 146731fb632bSRamuthevar Vadivel Murugan u32 reg; 146831fb632bSRamuthevar Vadivel Murugan 146931fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 147031fb632bSRamuthevar Vadivel Murugan 147131fb632bSRamuthevar Vadivel Murugan /* Configure the remap address register, no remap */ 147231fb632bSRamuthevar Vadivel Murugan writel(0, cqspi->iobase + CQSPI_REG_REMAP); 147331fb632bSRamuthevar Vadivel Murugan 147431fb632bSRamuthevar Vadivel Murugan /* Disable all interrupts. */ 147531fb632bSRamuthevar Vadivel Murugan writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); 147631fb632bSRamuthevar Vadivel Murugan 147731fb632bSRamuthevar Vadivel Murugan /* Configure the SRAM split to 1:1 . */ 147831fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); 147931fb632bSRamuthevar Vadivel Murugan 148031fb632bSRamuthevar Vadivel Murugan /* Load indirect trigger address. */ 148131fb632bSRamuthevar Vadivel Murugan writel(cqspi->trigger_address, 148231fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); 148331fb632bSRamuthevar Vadivel Murugan 148431fb632bSRamuthevar Vadivel Murugan /* Program read watermark -- 1/2 of the FIFO. */ 148531fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth * cqspi->fifo_width / 2, 148631fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); 148731fb632bSRamuthevar Vadivel Murugan /* Program write watermark -- 1/8 of the FIFO. */ 148831fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth * cqspi->fifo_width / 8, 148931fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); 149031fb632bSRamuthevar Vadivel Murugan 1491ad2775dcSRamuthevar Vadivel Murugan /* Disable direct access controller */ 1492ad2775dcSRamuthevar Vadivel Murugan if (!cqspi->use_direct_mode) { 149331fb632bSRamuthevar Vadivel Murugan reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 1494ad2775dcSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL; 149531fb632bSRamuthevar Vadivel Murugan writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 1496ad2775dcSRamuthevar Vadivel Murugan } 149731fb632bSRamuthevar Vadivel Murugan 14981a6f854fSSai Krishna Potthuri /* Enable DMA interface */ 14991a6f854fSSai Krishna Potthuri if (cqspi->use_dma_read) { 15001a6f854fSSai Krishna Potthuri reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 15011a6f854fSSai Krishna Potthuri reg |= CQSPI_REG_CONFIG_DMA_MASK; 15021a6f854fSSai Krishna Potthuri writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 15031a6f854fSSai Krishna Potthuri } 15041a6f854fSSai Krishna Potthuri 150531fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1); 150631fb632bSRamuthevar Vadivel Murugan } 150731fb632bSRamuthevar Vadivel Murugan 150831fb632bSRamuthevar Vadivel Murugan static int cqspi_request_mmap_dma(struct cqspi_st *cqspi) 150931fb632bSRamuthevar Vadivel Murugan { 151031fb632bSRamuthevar Vadivel Murugan dma_cap_mask_t mask; 151131fb632bSRamuthevar Vadivel Murugan 151231fb632bSRamuthevar Vadivel Murugan dma_cap_zero(mask); 151331fb632bSRamuthevar Vadivel Murugan dma_cap_set(DMA_MEMCPY, mask); 151431fb632bSRamuthevar Vadivel Murugan 151531fb632bSRamuthevar Vadivel Murugan cqspi->rx_chan = dma_request_chan_by_mask(&mask); 151631fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->rx_chan)) { 151731fb632bSRamuthevar Vadivel Murugan int ret = PTR_ERR(cqspi->rx_chan); 151876159e2fSIan Abbott 151931fb632bSRamuthevar Vadivel Murugan cqspi->rx_chan = NULL; 1520436a5c20SKrzysztof Kozlowski return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n"); 152131fb632bSRamuthevar Vadivel Murugan } 152231fb632bSRamuthevar Vadivel Murugan init_completion(&cqspi->rx_dma_complete); 152331fb632bSRamuthevar Vadivel Murugan 152431fb632bSRamuthevar Vadivel Murugan return 0; 152531fb632bSRamuthevar Vadivel Murugan } 152631fb632bSRamuthevar Vadivel Murugan 15272ea370a9SVignesh Raghavendra static const char *cqspi_get_name(struct spi_mem *mem) 15282ea370a9SVignesh Raghavendra { 15292ea370a9SVignesh Raghavendra struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); 15302ea370a9SVignesh Raghavendra struct device *dev = &cqspi->pdev->dev; 15312ea370a9SVignesh Raghavendra 15322ea370a9SVignesh Raghavendra return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select); 15332ea370a9SVignesh Raghavendra } 15342ea370a9SVignesh Raghavendra 153531fb632bSRamuthevar Vadivel Murugan static const struct spi_controller_mem_ops cqspi_mem_ops = { 153631fb632bSRamuthevar Vadivel Murugan .exec_op = cqspi_exec_mem_op, 15372ea370a9SVignesh Raghavendra .get_name = cqspi_get_name, 1538a273596bSPratyush Yadav .supports_op = cqspi_supports_mem_op, 153931fb632bSRamuthevar Vadivel Murugan }; 154031fb632bSRamuthevar Vadivel Murugan 1541a9be4549SMiquel Raynal static const struct spi_controller_mem_caps cqspi_mem_caps = { 1542a9be4549SMiquel Raynal .dtr = true, 1543a9be4549SMiquel Raynal }; 1544a9be4549SMiquel Raynal 154531fb632bSRamuthevar Vadivel Murugan static int cqspi_setup_flash(struct cqspi_st *cqspi) 154631fb632bSRamuthevar Vadivel Murugan { 154731fb632bSRamuthevar Vadivel Murugan struct platform_device *pdev = cqspi->pdev; 154831fb632bSRamuthevar Vadivel Murugan struct device *dev = &pdev->dev; 154931fb632bSRamuthevar Vadivel Murugan struct device_node *np = dev->of_node; 155031fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata; 155131fb632bSRamuthevar Vadivel Murugan unsigned int cs; 155231fb632bSRamuthevar Vadivel Murugan int ret; 155331fb632bSRamuthevar Vadivel Murugan 155431fb632bSRamuthevar Vadivel Murugan /* Get flash device data */ 155531fb632bSRamuthevar Vadivel Murugan for_each_available_child_of_node(dev->of_node, np) { 155631fb632bSRamuthevar Vadivel Murugan ret = of_property_read_u32(np, "reg", &cs); 155731fb632bSRamuthevar Vadivel Murugan if (ret) { 155831fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Couldn't determine chip select.\n"); 155987d62d8fSJunlin Yang of_node_put(np); 156031fb632bSRamuthevar Vadivel Murugan return ret; 156131fb632bSRamuthevar Vadivel Murugan } 156231fb632bSRamuthevar Vadivel Murugan 156331fb632bSRamuthevar Vadivel Murugan if (cs >= CQSPI_MAX_CHIPSELECT) { 156431fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Chip select %d out of range.\n", cs); 156587d62d8fSJunlin Yang of_node_put(np); 156631fb632bSRamuthevar Vadivel Murugan return -EINVAL; 156731fb632bSRamuthevar Vadivel Murugan } 156831fb632bSRamuthevar Vadivel Murugan 156931fb632bSRamuthevar Vadivel Murugan f_pdata = &cqspi->f_pdata[cs]; 157031fb632bSRamuthevar Vadivel Murugan f_pdata->cqspi = cqspi; 157131fb632bSRamuthevar Vadivel Murugan f_pdata->cs = cs; 157231fb632bSRamuthevar Vadivel Murugan 157331fb632bSRamuthevar Vadivel Murugan ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np); 157487d62d8fSJunlin Yang if (ret) { 157587d62d8fSJunlin Yang of_node_put(np); 157631fb632bSRamuthevar Vadivel Murugan return ret; 157731fb632bSRamuthevar Vadivel Murugan } 157887d62d8fSJunlin Yang } 157931fb632bSRamuthevar Vadivel Murugan 158031fb632bSRamuthevar Vadivel Murugan return 0; 158131fb632bSRamuthevar Vadivel Murugan } 158231fb632bSRamuthevar Vadivel Murugan 158331fb632bSRamuthevar Vadivel Murugan static int cqspi_probe(struct platform_device *pdev) 158431fb632bSRamuthevar Vadivel Murugan { 158531fb632bSRamuthevar Vadivel Murugan const struct cqspi_driver_platdata *ddata; 158631fb632bSRamuthevar Vadivel Murugan struct reset_control *rstc, *rstc_ocp; 158731fb632bSRamuthevar Vadivel Murugan struct device *dev = &pdev->dev; 158831fb632bSRamuthevar Vadivel Murugan struct spi_master *master; 158931fb632bSRamuthevar Vadivel Murugan struct resource *res_ahb; 159031fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi; 159131fb632bSRamuthevar Vadivel Murugan int ret; 159231fb632bSRamuthevar Vadivel Murugan int irq; 159331fb632bSRamuthevar Vadivel Murugan 1594606e5d40SVaishnav Achath master = devm_spi_alloc_master(&pdev->dev, sizeof(*cqspi)); 159531fb632bSRamuthevar Vadivel Murugan if (!master) { 159631fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "spi_alloc_master failed\n"); 159731fb632bSRamuthevar Vadivel Murugan return -ENOMEM; 159831fb632bSRamuthevar Vadivel Murugan } 159931fb632bSRamuthevar Vadivel Murugan master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; 160031fb632bSRamuthevar Vadivel Murugan master->mem_ops = &cqspi_mem_ops; 1601a9be4549SMiquel Raynal master->mem_caps = &cqspi_mem_caps; 160231fb632bSRamuthevar Vadivel Murugan master->dev.of_node = pdev->dev.of_node; 160331fb632bSRamuthevar Vadivel Murugan 160431fb632bSRamuthevar Vadivel Murugan cqspi = spi_master_get_devdata(master); 160531fb632bSRamuthevar Vadivel Murugan 160631fb632bSRamuthevar Vadivel Murugan cqspi->pdev = pdev; 1607606e5d40SVaishnav Achath cqspi->master = master; 1608ea94191eSMeng Li platform_set_drvdata(pdev, cqspi); 160931fb632bSRamuthevar Vadivel Murugan 161031fb632bSRamuthevar Vadivel Murugan /* Obtain configuration from OF. */ 161131fb632bSRamuthevar Vadivel Murugan ret = cqspi_of_get_pdata(cqspi); 161231fb632bSRamuthevar Vadivel Murugan if (ret) { 161331fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get mandatory OF data.\n"); 161473d5fe04SVaishnav Achath return -ENODEV; 161531fb632bSRamuthevar Vadivel Murugan } 161631fb632bSRamuthevar Vadivel Murugan 161731fb632bSRamuthevar Vadivel Murugan /* Obtain QSPI clock. */ 161831fb632bSRamuthevar Vadivel Murugan cqspi->clk = devm_clk_get(dev, NULL); 161931fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->clk)) { 162031fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot claim QSPI clock.\n"); 162131fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->clk); 162273d5fe04SVaishnav Achath return ret; 162331fb632bSRamuthevar Vadivel Murugan } 162431fb632bSRamuthevar Vadivel Murugan 162531fb632bSRamuthevar Vadivel Murugan /* Obtain and remap controller address. */ 16264e12ef2bSYang Yingliang cqspi->iobase = devm_platform_ioremap_resource(pdev, 0); 162731fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->iobase)) { 162831fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot remap controller address.\n"); 162931fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->iobase); 163073d5fe04SVaishnav Achath return ret; 163131fb632bSRamuthevar Vadivel Murugan } 163231fb632bSRamuthevar Vadivel Murugan 163331fb632bSRamuthevar Vadivel Murugan /* Obtain and remap AHB address. */ 16344e12ef2bSYang Yingliang cqspi->ahb_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res_ahb); 163531fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->ahb_base)) { 163631fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot remap AHB address.\n"); 163731fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->ahb_base); 163873d5fe04SVaishnav Achath return ret; 163931fb632bSRamuthevar Vadivel Murugan } 164031fb632bSRamuthevar Vadivel Murugan cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start; 164131fb632bSRamuthevar Vadivel Murugan cqspi->ahb_size = resource_size(res_ahb); 164231fb632bSRamuthevar Vadivel Murugan 164331fb632bSRamuthevar Vadivel Murugan init_completion(&cqspi->transfer_complete); 164431fb632bSRamuthevar Vadivel Murugan 164531fb632bSRamuthevar Vadivel Murugan /* Obtain IRQ line. */ 164631fb632bSRamuthevar Vadivel Murugan irq = platform_get_irq(pdev, 0); 164773d5fe04SVaishnav Achath if (irq < 0) 164873d5fe04SVaishnav Achath return -ENXIO; 164931fb632bSRamuthevar Vadivel Murugan 165031fb632bSRamuthevar Vadivel Murugan pm_runtime_enable(dev); 1651b7be05d5SMinghao Chi ret = pm_runtime_resume_and_get(dev); 1652b7be05d5SMinghao Chi if (ret < 0) 16534d0ef0a1SZhang Qilong goto probe_pm_failed; 165431fb632bSRamuthevar Vadivel Murugan 165531fb632bSRamuthevar Vadivel Murugan ret = clk_prepare_enable(cqspi->clk); 165631fb632bSRamuthevar Vadivel Murugan if (ret) { 165731fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot enable QSPI clock.\n"); 165831fb632bSRamuthevar Vadivel Murugan goto probe_clk_failed; 165931fb632bSRamuthevar Vadivel Murugan } 166031fb632bSRamuthevar Vadivel Murugan 166131fb632bSRamuthevar Vadivel Murugan /* Obtain QSPI reset control */ 166231fb632bSRamuthevar Vadivel Murugan rstc = devm_reset_control_get_optional_exclusive(dev, "qspi"); 166331fb632bSRamuthevar Vadivel Murugan if (IS_ERR(rstc)) { 1664ac9978fcSZhihao Cheng ret = PTR_ERR(rstc); 166531fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get QSPI reset.\n"); 166631fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 166731fb632bSRamuthevar Vadivel Murugan } 166831fb632bSRamuthevar Vadivel Murugan 166931fb632bSRamuthevar Vadivel Murugan rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); 167031fb632bSRamuthevar Vadivel Murugan if (IS_ERR(rstc_ocp)) { 1671ac9978fcSZhihao Cheng ret = PTR_ERR(rstc_ocp); 167231fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get QSPI OCP reset.\n"); 167331fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 167431fb632bSRamuthevar Vadivel Murugan } 167531fb632bSRamuthevar Vadivel Murugan 167631fb632bSRamuthevar Vadivel Murugan reset_control_assert(rstc); 167731fb632bSRamuthevar Vadivel Murugan reset_control_deassert(rstc); 167831fb632bSRamuthevar Vadivel Murugan 167931fb632bSRamuthevar Vadivel Murugan reset_control_assert(rstc_ocp); 168031fb632bSRamuthevar Vadivel Murugan reset_control_deassert(rstc_ocp); 168131fb632bSRamuthevar Vadivel Murugan 168231fb632bSRamuthevar Vadivel Murugan cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); 16833a5c09c8SPratyush Yadav master->max_speed_hz = cqspi->master_ref_clk_hz; 168498d948ebSDinh Nguyen 168598d948ebSDinh Nguyen /* write completion is supported by default */ 168698d948ebSDinh Nguyen cqspi->wr_completion = true; 168798d948ebSDinh Nguyen 168831fb632bSRamuthevar Vadivel Murugan ddata = of_device_get_match_data(dev); 168931fb632bSRamuthevar Vadivel Murugan if (ddata) { 169031fb632bSRamuthevar Vadivel Murugan if (ddata->quirks & CQSPI_NEEDS_WR_DELAY) 1691f453f293SPratyush Yadav cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, 169231fb632bSRamuthevar Vadivel Murugan cqspi->master_ref_clk_hz); 169331fb632bSRamuthevar Vadivel Murugan if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL) 1694f453f293SPratyush Yadav master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; 169531fb632bSRamuthevar Vadivel Murugan if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) 169631fb632bSRamuthevar Vadivel Murugan cqspi->use_direct_mode = true; 16971a6f854fSSai Krishna Potthuri if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA) 16981a6f854fSSai Krishna Potthuri cqspi->use_dma_read = true; 169998d948ebSDinh Nguyen if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION) 170098d948ebSDinh Nguyen cqspi->wr_completion = false; 17019ee5b6d5SNiravkumar L Rabara if (ddata->quirks & CQSPI_SLOW_SRAM) 17029ee5b6d5SNiravkumar L Rabara cqspi->slow_sram = true; 17031a6f854fSSai Krishna Potthuri 170409e393e3SSai Krishna Potthuri if (of_device_is_compatible(pdev->dev.of_node, 17051a6f854fSSai Krishna Potthuri "xlnx,versal-ospi-1.0")) 17061a6f854fSSai Krishna Potthuri dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); 170731fb632bSRamuthevar Vadivel Murugan } 170831fb632bSRamuthevar Vadivel Murugan 170931fb632bSRamuthevar Vadivel Murugan ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0, 171031fb632bSRamuthevar Vadivel Murugan pdev->name, cqspi); 171131fb632bSRamuthevar Vadivel Murugan if (ret) { 171231fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot request IRQ.\n"); 171331fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 171431fb632bSRamuthevar Vadivel Murugan } 171531fb632bSRamuthevar Vadivel Murugan 171631fb632bSRamuthevar Vadivel Murugan cqspi_wait_idle(cqspi); 171731fb632bSRamuthevar Vadivel Murugan cqspi_controller_init(cqspi); 171831fb632bSRamuthevar Vadivel Murugan cqspi->current_cs = -1; 171931fb632bSRamuthevar Vadivel Murugan cqspi->sclk = 0; 172031fb632bSRamuthevar Vadivel Murugan 1721b436fb7dSRamuthevar Vadivel Murugan master->num_chipselect = cqspi->num_chipselect; 1722b436fb7dSRamuthevar Vadivel Murugan 172331fb632bSRamuthevar Vadivel Murugan ret = cqspi_setup_flash(cqspi); 172431fb632bSRamuthevar Vadivel Murugan if (ret) { 172531fb632bSRamuthevar Vadivel Murugan dev_err(dev, "failed to setup flash parameters %d\n", ret); 172631fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 172731fb632bSRamuthevar Vadivel Murugan } 172831fb632bSRamuthevar Vadivel Murugan 172931fb632bSRamuthevar Vadivel Murugan if (cqspi->use_direct_mode) { 173031fb632bSRamuthevar Vadivel Murugan ret = cqspi_request_mmap_dma(cqspi); 173131fb632bSRamuthevar Vadivel Murugan if (ret == -EPROBE_DEFER) 173231fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 173331fb632bSRamuthevar Vadivel Murugan } 173431fb632bSRamuthevar Vadivel Murugan 1735606e5d40SVaishnav Achath ret = spi_register_master(master); 173631fb632bSRamuthevar Vadivel Murugan if (ret) { 173731fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret); 173831fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 173931fb632bSRamuthevar Vadivel Murugan } 174031fb632bSRamuthevar Vadivel Murugan 174131fb632bSRamuthevar Vadivel Murugan return 0; 174231fb632bSRamuthevar Vadivel Murugan probe_setup_failed: 174331fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 174431fb632bSRamuthevar Vadivel Murugan probe_reset_failed: 174531fb632bSRamuthevar Vadivel Murugan clk_disable_unprepare(cqspi->clk); 174631fb632bSRamuthevar Vadivel Murugan probe_clk_failed: 174731fb632bSRamuthevar Vadivel Murugan pm_runtime_put_sync(dev); 17484d0ef0a1SZhang Qilong probe_pm_failed: 174931fb632bSRamuthevar Vadivel Murugan pm_runtime_disable(dev); 175031fb632bSRamuthevar Vadivel Murugan return ret; 175131fb632bSRamuthevar Vadivel Murugan } 175231fb632bSRamuthevar Vadivel Murugan 175331fb632bSRamuthevar Vadivel Murugan static int cqspi_remove(struct platform_device *pdev) 175431fb632bSRamuthevar Vadivel Murugan { 175531fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = platform_get_drvdata(pdev); 175631fb632bSRamuthevar Vadivel Murugan 1757606e5d40SVaishnav Achath spi_unregister_master(cqspi->master); 175831fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 175931fb632bSRamuthevar Vadivel Murugan 176031fb632bSRamuthevar Vadivel Murugan if (cqspi->rx_chan) 176131fb632bSRamuthevar Vadivel Murugan dma_release_channel(cqspi->rx_chan); 176231fb632bSRamuthevar Vadivel Murugan 176331fb632bSRamuthevar Vadivel Murugan clk_disable_unprepare(cqspi->clk); 176431fb632bSRamuthevar Vadivel Murugan 176531fb632bSRamuthevar Vadivel Murugan pm_runtime_put_sync(&pdev->dev); 176631fb632bSRamuthevar Vadivel Murugan pm_runtime_disable(&pdev->dev); 176731fb632bSRamuthevar Vadivel Murugan 176831fb632bSRamuthevar Vadivel Murugan return 0; 176931fb632bSRamuthevar Vadivel Murugan } 177031fb632bSRamuthevar Vadivel Murugan 177131fb632bSRamuthevar Vadivel Murugan #ifdef CONFIG_PM_SLEEP 177231fb632bSRamuthevar Vadivel Murugan static int cqspi_suspend(struct device *dev) 177331fb632bSRamuthevar Vadivel Murugan { 177431fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev_get_drvdata(dev); 177531fb632bSRamuthevar Vadivel Murugan 177631fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 177731fb632bSRamuthevar Vadivel Murugan return 0; 177831fb632bSRamuthevar Vadivel Murugan } 177931fb632bSRamuthevar Vadivel Murugan 178031fb632bSRamuthevar Vadivel Murugan static int cqspi_resume(struct device *dev) 178131fb632bSRamuthevar Vadivel Murugan { 178231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev_get_drvdata(dev); 178331fb632bSRamuthevar Vadivel Murugan 178431fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1); 178531fb632bSRamuthevar Vadivel Murugan return 0; 178631fb632bSRamuthevar Vadivel Murugan } 178731fb632bSRamuthevar Vadivel Murugan 178831fb632bSRamuthevar Vadivel Murugan static const struct dev_pm_ops cqspi__dev_pm_ops = { 178931fb632bSRamuthevar Vadivel Murugan .suspend = cqspi_suspend, 179031fb632bSRamuthevar Vadivel Murugan .resume = cqspi_resume, 179131fb632bSRamuthevar Vadivel Murugan }; 179231fb632bSRamuthevar Vadivel Murugan 179331fb632bSRamuthevar Vadivel Murugan #define CQSPI_DEV_PM_OPS (&cqspi__dev_pm_ops) 179431fb632bSRamuthevar Vadivel Murugan #else 179531fb632bSRamuthevar Vadivel Murugan #define CQSPI_DEV_PM_OPS NULL 179631fb632bSRamuthevar Vadivel Murugan #endif 179731fb632bSRamuthevar Vadivel Murugan 179831fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata cdns_qspi = { 179931fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_DISABLE_DAC_MODE, 180031fb632bSRamuthevar Vadivel Murugan }; 180131fb632bSRamuthevar Vadivel Murugan 180231fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata k2g_qspi = { 180331fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_NEEDS_WR_DELAY, 180431fb632bSRamuthevar Vadivel Murugan }; 180531fb632bSRamuthevar Vadivel Murugan 180631fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata am654_ospi = { 180731fb632bSRamuthevar Vadivel Murugan .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 180831fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_NEEDS_WR_DELAY, 180931fb632bSRamuthevar Vadivel Murugan }; 181031fb632bSRamuthevar Vadivel Murugan 1811ad2775dcSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata intel_lgm_qspi = { 1812ad2775dcSRamuthevar Vadivel Murugan .quirks = CQSPI_DISABLE_DAC_MODE, 1813ad2775dcSRamuthevar Vadivel Murugan }; 1814ad2775dcSRamuthevar Vadivel Murugan 181598d948ebSDinh Nguyen static const struct cqspi_driver_platdata socfpga_qspi = { 18169ee5b6d5SNiravkumar L Rabara .quirks = CQSPI_DISABLE_DAC_MODE 18179ee5b6d5SNiravkumar L Rabara | CQSPI_NO_SUPPORT_WR_COMPLETION 18189ee5b6d5SNiravkumar L Rabara | CQSPI_SLOW_SRAM, 181998d948ebSDinh Nguyen }; 182098d948ebSDinh Nguyen 182109e393e3SSai Krishna Potthuri static const struct cqspi_driver_platdata versal_ospi = { 182209e393e3SSai Krishna Potthuri .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 18231a6f854fSSai Krishna Potthuri .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA, 18241a6f854fSSai Krishna Potthuri .indirect_read_dma = cqspi_versal_indirect_read_dma, 18251a6f854fSSai Krishna Potthuri .get_dma_status = cqspi_get_versal_dma_status, 182609e393e3SSai Krishna Potthuri }; 182709e393e3SSai Krishna Potthuri 182831fb632bSRamuthevar Vadivel Murugan static const struct of_device_id cqspi_dt_ids[] = { 182931fb632bSRamuthevar Vadivel Murugan { 183031fb632bSRamuthevar Vadivel Murugan .compatible = "cdns,qspi-nor", 183131fb632bSRamuthevar Vadivel Murugan .data = &cdns_qspi, 183231fb632bSRamuthevar Vadivel Murugan }, 183331fb632bSRamuthevar Vadivel Murugan { 183431fb632bSRamuthevar Vadivel Murugan .compatible = "ti,k2g-qspi", 183531fb632bSRamuthevar Vadivel Murugan .data = &k2g_qspi, 183631fb632bSRamuthevar Vadivel Murugan }, 183731fb632bSRamuthevar Vadivel Murugan { 183831fb632bSRamuthevar Vadivel Murugan .compatible = "ti,am654-ospi", 183931fb632bSRamuthevar Vadivel Murugan .data = &am654_ospi, 184031fb632bSRamuthevar Vadivel Murugan }, 1841ab2d2875SRamuthevar Vadivel Murugan { 1842ab2d2875SRamuthevar Vadivel Murugan .compatible = "intel,lgm-qspi", 1843ad2775dcSRamuthevar Vadivel Murugan .data = &intel_lgm_qspi, 1844ab2d2875SRamuthevar Vadivel Murugan }, 184509e393e3SSai Krishna Potthuri { 184609e393e3SSai Krishna Potthuri .compatible = "xlnx,versal-ospi-1.0", 18470d868829SIan Abbott .data = &versal_ospi, 184809e393e3SSai Krishna Potthuri }, 184998d948ebSDinh Nguyen { 185098d948ebSDinh Nguyen .compatible = "intel,socfpga-qspi", 18510d868829SIan Abbott .data = &socfpga_qspi, 185298d948ebSDinh Nguyen }, 185331fb632bSRamuthevar Vadivel Murugan { /* end of table */ } 185431fb632bSRamuthevar Vadivel Murugan }; 185531fb632bSRamuthevar Vadivel Murugan 185631fb632bSRamuthevar Vadivel Murugan MODULE_DEVICE_TABLE(of, cqspi_dt_ids); 185731fb632bSRamuthevar Vadivel Murugan 185831fb632bSRamuthevar Vadivel Murugan static struct platform_driver cqspi_platform_driver = { 185931fb632bSRamuthevar Vadivel Murugan .probe = cqspi_probe, 186031fb632bSRamuthevar Vadivel Murugan .remove = cqspi_remove, 186131fb632bSRamuthevar Vadivel Murugan .driver = { 186231fb632bSRamuthevar Vadivel Murugan .name = CQSPI_NAME, 186331fb632bSRamuthevar Vadivel Murugan .pm = CQSPI_DEV_PM_OPS, 186431fb632bSRamuthevar Vadivel Murugan .of_match_table = cqspi_dt_ids, 186531fb632bSRamuthevar Vadivel Murugan }, 186631fb632bSRamuthevar Vadivel Murugan }; 186731fb632bSRamuthevar Vadivel Murugan 186831fb632bSRamuthevar Vadivel Murugan module_platform_driver(cqspi_platform_driver); 186931fb632bSRamuthevar Vadivel Murugan 187031fb632bSRamuthevar Vadivel Murugan MODULE_DESCRIPTION("Cadence QSPI Controller Driver"); 187131fb632bSRamuthevar Vadivel Murugan MODULE_LICENSE("GPL v2"); 187231fb632bSRamuthevar Vadivel Murugan MODULE_ALIAS("platform:" CQSPI_NAME); 187331fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>"); 187431fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>"); 187531fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>"); 187631fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>"); 1877f453f293SPratyush Yadav MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>"); 1878