131fb632bSRamuthevar Vadivel Murugan // SPDX-License-Identifier: GPL-2.0-only 231fb632bSRamuthevar Vadivel Murugan // 331fb632bSRamuthevar Vadivel Murugan // Driver for Cadence QSPI Controller 431fb632bSRamuthevar Vadivel Murugan // 531fb632bSRamuthevar Vadivel Murugan // Copyright Altera Corporation (C) 2012-2014. All rights reserved. 631fb632bSRamuthevar Vadivel Murugan // Copyright Intel Corporation (C) 2019-2020. All rights reserved. 731fb632bSRamuthevar Vadivel Murugan // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 831fb632bSRamuthevar Vadivel Murugan 931fb632bSRamuthevar Vadivel Murugan #include <linux/clk.h> 1031fb632bSRamuthevar Vadivel Murugan #include <linux/completion.h> 1131fb632bSRamuthevar Vadivel Murugan #include <linux/delay.h> 1231fb632bSRamuthevar Vadivel Murugan #include <linux/dma-mapping.h> 1331fb632bSRamuthevar Vadivel Murugan #include <linux/dmaengine.h> 1431fb632bSRamuthevar Vadivel Murugan #include <linux/err.h> 1531fb632bSRamuthevar Vadivel Murugan #include <linux/errno.h> 1609e393e3SSai Krishna Potthuri #include <linux/firmware/xlnx-zynqmp.h> 1731fb632bSRamuthevar Vadivel Murugan #include <linux/interrupt.h> 1831fb632bSRamuthevar Vadivel Murugan #include <linux/io.h> 1931fb632bSRamuthevar Vadivel Murugan #include <linux/iopoll.h> 2031fb632bSRamuthevar Vadivel Murugan #include <linux/jiffies.h> 2131fb632bSRamuthevar Vadivel Murugan #include <linux/kernel.h> 2297e4827dSMatthias Schiffer #include <linux/log2.h> 2331fb632bSRamuthevar Vadivel Murugan #include <linux/module.h> 2431fb632bSRamuthevar Vadivel Murugan #include <linux/of_device.h> 2531fb632bSRamuthevar Vadivel Murugan #include <linux/of.h> 2631fb632bSRamuthevar Vadivel Murugan #include <linux/platform_device.h> 2731fb632bSRamuthevar Vadivel Murugan #include <linux/pm_runtime.h> 2831fb632bSRamuthevar Vadivel Murugan #include <linux/reset.h> 2931fb632bSRamuthevar Vadivel Murugan #include <linux/sched.h> 3031fb632bSRamuthevar Vadivel Murugan #include <linux/spi/spi.h> 3131fb632bSRamuthevar Vadivel Murugan #include <linux/spi/spi-mem.h> 3231fb632bSRamuthevar Vadivel Murugan #include <linux/timer.h> 3331fb632bSRamuthevar Vadivel Murugan 3431fb632bSRamuthevar Vadivel Murugan #define CQSPI_NAME "cadence-qspi" 3531fb632bSRamuthevar Vadivel Murugan #define CQSPI_MAX_CHIPSELECT 16 3631fb632bSRamuthevar Vadivel Murugan 3731fb632bSRamuthevar Vadivel Murugan /* Quirks */ 3831fb632bSRamuthevar Vadivel Murugan #define CQSPI_NEEDS_WR_DELAY BIT(0) 3931fb632bSRamuthevar Vadivel Murugan #define CQSPI_DISABLE_DAC_MODE BIT(1) 401a6f854fSSai Krishna Potthuri #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) 4198d948ebSDinh Nguyen #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) 429ee5b6d5SNiravkumar L Rabara #define CQSPI_SLOW_SRAM BIT(4) 4331fb632bSRamuthevar Vadivel Murugan 4431fb632bSRamuthevar Vadivel Murugan /* Capabilities */ 4531fb632bSRamuthevar Vadivel Murugan #define CQSPI_SUPPORTS_OCTAL BIT(0) 4631fb632bSRamuthevar Vadivel Murugan 4728ac902aSMatthias Schiffer #define CQSPI_OP_WIDTH(part) ((part).nbytes ? ilog2((part).buswidth) : 0) 4828ac902aSMatthias Schiffer 4931fb632bSRamuthevar Vadivel Murugan struct cqspi_st; 5031fb632bSRamuthevar Vadivel Murugan 5131fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata { 5231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi; 5331fb632bSRamuthevar Vadivel Murugan u32 clk_rate; 5431fb632bSRamuthevar Vadivel Murugan u32 read_delay; 5531fb632bSRamuthevar Vadivel Murugan u32 tshsl_ns; 5631fb632bSRamuthevar Vadivel Murugan u32 tsd2d_ns; 5731fb632bSRamuthevar Vadivel Murugan u32 tchsh_ns; 5831fb632bSRamuthevar Vadivel Murugan u32 tslch_ns; 5931fb632bSRamuthevar Vadivel Murugan u8 cs; 6031fb632bSRamuthevar Vadivel Murugan }; 6131fb632bSRamuthevar Vadivel Murugan 6231fb632bSRamuthevar Vadivel Murugan struct cqspi_st { 6331fb632bSRamuthevar Vadivel Murugan struct platform_device *pdev; 64606e5d40SVaishnav Achath struct spi_master *master; 6531fb632bSRamuthevar Vadivel Murugan struct clk *clk; 6631fb632bSRamuthevar Vadivel Murugan unsigned int sclk; 6731fb632bSRamuthevar Vadivel Murugan 6831fb632bSRamuthevar Vadivel Murugan void __iomem *iobase; 6931fb632bSRamuthevar Vadivel Murugan void __iomem *ahb_base; 7031fb632bSRamuthevar Vadivel Murugan resource_size_t ahb_size; 7131fb632bSRamuthevar Vadivel Murugan struct completion transfer_complete; 7231fb632bSRamuthevar Vadivel Murugan 7331fb632bSRamuthevar Vadivel Murugan struct dma_chan *rx_chan; 7431fb632bSRamuthevar Vadivel Murugan struct completion rx_dma_complete; 7531fb632bSRamuthevar Vadivel Murugan dma_addr_t mmap_phys_base; 7631fb632bSRamuthevar Vadivel Murugan 7731fb632bSRamuthevar Vadivel Murugan int current_cs; 7831fb632bSRamuthevar Vadivel Murugan unsigned long master_ref_clk_hz; 7931fb632bSRamuthevar Vadivel Murugan bool is_decoded_cs; 8031fb632bSRamuthevar Vadivel Murugan u32 fifo_depth; 8131fb632bSRamuthevar Vadivel Murugan u32 fifo_width; 82b436fb7dSRamuthevar Vadivel Murugan u32 num_chipselect; 8331fb632bSRamuthevar Vadivel Murugan bool rclk_en; 8431fb632bSRamuthevar Vadivel Murugan u32 trigger_address; 8531fb632bSRamuthevar Vadivel Murugan u32 wr_delay; 8631fb632bSRamuthevar Vadivel Murugan bool use_direct_mode; 87*e8c51b16SDhruva Gole bool use_direct_mode_wr; 8831fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; 891a6f854fSSai Krishna Potthuri bool use_dma_read; 9009e393e3SSai Krishna Potthuri u32 pd_dev_id; 9198d948ebSDinh Nguyen bool wr_completion; 929ee5b6d5SNiravkumar L Rabara bool slow_sram; 9331fb632bSRamuthevar Vadivel Murugan }; 9431fb632bSRamuthevar Vadivel Murugan 9531fb632bSRamuthevar Vadivel Murugan struct cqspi_driver_platdata { 9631fb632bSRamuthevar Vadivel Murugan u32 hwcaps_mask; 9731fb632bSRamuthevar Vadivel Murugan u8 quirks; 981a6f854fSSai Krishna Potthuri int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata, 991a6f854fSSai Krishna Potthuri u_char *rxbuf, loff_t from_addr, size_t n_rx); 1001a6f854fSSai Krishna Potthuri u32 (*get_dma_status)(struct cqspi_st *cqspi); 10131fb632bSRamuthevar Vadivel Murugan }; 10231fb632bSRamuthevar Vadivel Murugan 10331fb632bSRamuthevar Vadivel Murugan /* Operation timeout value */ 10431fb632bSRamuthevar Vadivel Murugan #define CQSPI_TIMEOUT_MS 500 10531fb632bSRamuthevar Vadivel Murugan #define CQSPI_READ_TIMEOUT_MS 10 10631fb632bSRamuthevar Vadivel Murugan 10731fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_CLKS_PER_BYTE 8 10831fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_BYTES_MAX 4 10931fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_CLKS_MAX 31 11031fb632bSRamuthevar Vadivel Murugan 11131fb632bSRamuthevar Vadivel Murugan #define CQSPI_STIG_DATA_LEN_MAX 8 11231fb632bSRamuthevar Vadivel Murugan 11331fb632bSRamuthevar Vadivel Murugan /* Register map */ 11431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG 0x00 11531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0) 11631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7) 11731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9) 11831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 11931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_DMA_MASK BIT(15) 12031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_BAUD_LSB 19 121f453f293SPratyush Yadav #define CQSPI_REG_CONFIG_DTR_PROTO BIT(24) 122f453f293SPratyush Yadav #define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30) 12331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_IDLE_LSB 31 12431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF 12531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_BAUD_MASK 0xF 12631fb632bSRamuthevar Vadivel Murugan 12731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR 0x04 12831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 12931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 13031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 13131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 13231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 13331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 13431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 13531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 13631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 13731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F 13831fb632bSRamuthevar Vadivel Murugan 13931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR 0x08 14031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 14131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12 14231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16 14331fb632bSRamuthevar Vadivel Murugan 14431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY 0x0C 14531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSLCH_LSB 0 14631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TCHSH_LSB 8 14731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSD2D_LSB 16 14831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSHSL_LSB 24 14931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF 15031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF 15131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF 15231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF 15331fb632bSRamuthevar Vadivel Murugan 15431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE 0x10 15531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0 15631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_DELAY_LSB 1 15731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF 15831fb632bSRamuthevar Vadivel Murugan 15931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE 0x14 16031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_ADDRESS_LSB 0 16131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_PAGE_LSB 4 16231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_BLOCK_LSB 16 16331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF 16431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF 16531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F 16631fb632bSRamuthevar Vadivel Murugan 16731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SRAMPARTITION 0x18 16831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTTRIGGER 0x1C 16931fb632bSRamuthevar Vadivel Murugan 17031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA 0x20 17131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_SINGLE_LSB 0 17231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_BURST_LSB 8 17331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_SINGLE_MASK 0xFF 17431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_BURST_MASK 0xFF 17531fb632bSRamuthevar Vadivel Murugan 17631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_REMAP 0x24 17731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_MODE_BIT 0x28 17831fb632bSRamuthevar Vadivel Murugan 17931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL 0x2C 18031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 18131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 18231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF 18331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF 18431fb632bSRamuthevar Vadivel Murugan 185f453f293SPratyush Yadav #define CQSPI_REG_WR_COMPLETION_CTRL 0x38 186f453f293SPratyush Yadav #define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14) 187f453f293SPratyush Yadav 18831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQSTATUS 0x40 18931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQMASK 0x44 19031fb632bSRamuthevar Vadivel Murugan 19131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD 0x60 19231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0) 19331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1) 19431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5) 19531fb632bSRamuthevar Vadivel Murugan 19631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDWATERMARK 0x64 19731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 19831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDBYTES 0x6C 19931fb632bSRamuthevar Vadivel Murugan 20031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL 0x90 20131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0) 20231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1) 203888d517bSPratyush Yadav #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 20431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 20531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 20631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 20731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 20831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 20931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 21031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 21131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 21231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 21331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 214888d517bSPratyush Yadav #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F 21531fb632bSRamuthevar Vadivel Murugan 21631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR 0x70 21731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0) 21831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1) 21931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5) 22031fb632bSRamuthevar Vadivel Murugan 22131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRWATERMARK 0x74 22231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 22331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRBYTES 0x7C 22431fb632bSRamuthevar Vadivel Murugan 2251a6f854fSSai Krishna Potthuri #define CQSPI_REG_INDTRIG_ADDRRANGE 0x80 2261a6f854fSSai Krishna Potthuri 22731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDADDRESS 0x94 22831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDREADDATALOWER 0xA0 22931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDREADDATAUPPER 0xA4 23031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDWRITEDATALOWER 0xA8 23131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC 23231fb632bSRamuthevar Vadivel Murugan 233f453f293SPratyush Yadav #define CQSPI_REG_POLLING_STATUS 0xB0 234f453f293SPratyush Yadav #define CQSPI_REG_POLLING_STATUS_DUMMY_LSB 16 235f453f293SPratyush Yadav 236f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_LOWER 0xE0 237f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_READ_LSB 24 238f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_WRITE_LSB 16 239f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_STIG_LSB 0 240f453f293SPratyush Yadav 2411a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_SRC_ADDR 0x1000 2421a6f854fSSai Krishna Potthuri 2431a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_ADDR 0x1800 2441a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_SIZE 0x1804 2451a6f854fSSai Krishna Potthuri 2461a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_CTRL 0x180C 2471a6f854fSSai Krishna Potthuri 2481a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_I_STS 0x1814 2491a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_I_EN 0x1818 2501a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_I_DIS 0x181C 2511a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_DONE_MASK BIT(1) 2521a6f854fSSai Krishna Potthuri 2531a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB 0x1828 2541a6f854fSSai Krishna Potthuri 2551a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL 0xF43FFA00 2561a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL 0x6 2571a6f854fSSai Krishna Potthuri 25831fb632bSRamuthevar Vadivel Murugan /* Interrupt status bits */ 25931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_MODE_ERR BIT(0) 26031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_UNDERFLOW BIT(1) 26131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_COMP BIT(2) 26231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3) 26331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4) 26431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5) 26531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_WATERMARK BIT(6) 26631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12) 26731fb632bSRamuthevar Vadivel Murugan 26831fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \ 26931fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_IND_SRAM_FULL | \ 27031fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_IND_COMP) 27131fb632bSRamuthevar Vadivel Murugan 27231fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \ 27331fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_WATERMARK | \ 27431fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_UNDERFLOW) 27531fb632bSRamuthevar Vadivel Murugan 27631fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_STATUS_MASK 0x1FFFF 2771a6f854fSSai Krishna Potthuri #define CQSPI_DMA_UNALIGN 0x3 2781a6f854fSSai Krishna Potthuri 2791a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_VAL 0x602 28031fb632bSRamuthevar Vadivel Murugan 28131fb632bSRamuthevar Vadivel Murugan static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr) 28231fb632bSRamuthevar Vadivel Murugan { 28331fb632bSRamuthevar Vadivel Murugan u32 val; 28431fb632bSRamuthevar Vadivel Murugan 28531fb632bSRamuthevar Vadivel Murugan return readl_relaxed_poll_timeout(reg, val, 28631fb632bSRamuthevar Vadivel Murugan (((clr ? ~val : val) & mask) == mask), 28731fb632bSRamuthevar Vadivel Murugan 10, CQSPI_TIMEOUT_MS * 1000); 28831fb632bSRamuthevar Vadivel Murugan } 28931fb632bSRamuthevar Vadivel Murugan 29031fb632bSRamuthevar Vadivel Murugan static bool cqspi_is_idle(struct cqspi_st *cqspi) 29131fb632bSRamuthevar Vadivel Murugan { 29231fb632bSRamuthevar Vadivel Murugan u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 29331fb632bSRamuthevar Vadivel Murugan 29431890269SJay Fang return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB); 29531fb632bSRamuthevar Vadivel Murugan } 29631fb632bSRamuthevar Vadivel Murugan 29731fb632bSRamuthevar Vadivel Murugan static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi) 29831fb632bSRamuthevar Vadivel Murugan { 29931fb632bSRamuthevar Vadivel Murugan u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL); 30031fb632bSRamuthevar Vadivel Murugan 30131fb632bSRamuthevar Vadivel Murugan reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB; 30231fb632bSRamuthevar Vadivel Murugan return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK; 30331fb632bSRamuthevar Vadivel Murugan } 30431fb632bSRamuthevar Vadivel Murugan 3051a6f854fSSai Krishna Potthuri static u32 cqspi_get_versal_dma_status(struct cqspi_st *cqspi) 3061a6f854fSSai Krishna Potthuri { 3071a6f854fSSai Krishna Potthuri u32 dma_status; 3081a6f854fSSai Krishna Potthuri 3091a6f854fSSai Krishna Potthuri dma_status = readl(cqspi->iobase + 3101a6f854fSSai Krishna Potthuri CQSPI_REG_VERSAL_DMA_DST_I_STS); 3111a6f854fSSai Krishna Potthuri writel(dma_status, cqspi->iobase + 3121a6f854fSSai Krishna Potthuri CQSPI_REG_VERSAL_DMA_DST_I_STS); 3131a6f854fSSai Krishna Potthuri 3141a6f854fSSai Krishna Potthuri return dma_status & CQSPI_REG_VERSAL_DMA_DST_DONE_MASK; 3151a6f854fSSai Krishna Potthuri } 3161a6f854fSSai Krishna Potthuri 31731fb632bSRamuthevar Vadivel Murugan static irqreturn_t cqspi_irq_handler(int this_irq, void *dev) 31831fb632bSRamuthevar Vadivel Murugan { 31931fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev; 32031fb632bSRamuthevar Vadivel Murugan unsigned int irq_status; 3211a6f854fSSai Krishna Potthuri struct device *device = &cqspi->pdev->dev; 3221a6f854fSSai Krishna Potthuri const struct cqspi_driver_platdata *ddata; 3231a6f854fSSai Krishna Potthuri 3241a6f854fSSai Krishna Potthuri ddata = of_device_get_match_data(device); 32531fb632bSRamuthevar Vadivel Murugan 32631fb632bSRamuthevar Vadivel Murugan /* Read interrupt status */ 32731fb632bSRamuthevar Vadivel Murugan irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS); 32831fb632bSRamuthevar Vadivel Murugan 32931fb632bSRamuthevar Vadivel Murugan /* Clear interrupt */ 33031fb632bSRamuthevar Vadivel Murugan writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS); 33131fb632bSRamuthevar Vadivel Murugan 3321a6f854fSSai Krishna Potthuri if (cqspi->use_dma_read && ddata && ddata->get_dma_status) { 3331a6f854fSSai Krishna Potthuri if (ddata->get_dma_status(cqspi)) { 3341a6f854fSSai Krishna Potthuri complete(&cqspi->transfer_complete); 3351a6f854fSSai Krishna Potthuri return IRQ_HANDLED; 3361a6f854fSSai Krishna Potthuri } 3371a6f854fSSai Krishna Potthuri } 3381a6f854fSSai Krishna Potthuri 3399ee5b6d5SNiravkumar L Rabara else if (!cqspi->slow_sram) 34031fb632bSRamuthevar Vadivel Murugan irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR; 3419ee5b6d5SNiravkumar L Rabara else 3429ee5b6d5SNiravkumar L Rabara irq_status &= CQSPI_REG_IRQ_WATERMARK | CQSPI_IRQ_MASK_WR; 34331fb632bSRamuthevar Vadivel Murugan 34431fb632bSRamuthevar Vadivel Murugan if (irq_status) 34531fb632bSRamuthevar Vadivel Murugan complete(&cqspi->transfer_complete); 34631fb632bSRamuthevar Vadivel Murugan 34731fb632bSRamuthevar Vadivel Murugan return IRQ_HANDLED; 34831fb632bSRamuthevar Vadivel Murugan } 34931fb632bSRamuthevar Vadivel Murugan 35028ac902aSMatthias Schiffer static unsigned int cqspi_calc_rdreg(const struct spi_mem_op *op) 35131fb632bSRamuthevar Vadivel Murugan { 35231fb632bSRamuthevar Vadivel Murugan u32 rdreg = 0; 35331fb632bSRamuthevar Vadivel Murugan 35428ac902aSMatthias Schiffer rdreg |= CQSPI_OP_WIDTH(op->cmd) << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; 35528ac902aSMatthias Schiffer rdreg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; 35628ac902aSMatthias Schiffer rdreg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; 35731fb632bSRamuthevar Vadivel Murugan 35831fb632bSRamuthevar Vadivel Murugan return rdreg; 35931fb632bSRamuthevar Vadivel Murugan } 36031fb632bSRamuthevar Vadivel Murugan 36128ac902aSMatthias Schiffer static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op) 362888d517bSPratyush Yadav { 3630ccfd1baSYoshitaka Ikeda unsigned int dummy_clk; 364888d517bSPratyush Yadav 3650e85ee89SYoshitaka Ikeda if (!op->dummy.nbytes) 3660e85ee89SYoshitaka Ikeda return 0; 3670e85ee89SYoshitaka Ikeda 3687512eaf5SPratyush Yadav dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth); 36928ac902aSMatthias Schiffer if (op->cmd.dtr) 370f453f293SPratyush Yadav dummy_clk /= 2; 371888d517bSPratyush Yadav 372888d517bSPratyush Yadav return dummy_clk; 373888d517bSPratyush Yadav } 374888d517bSPratyush Yadav 37531fb632bSRamuthevar Vadivel Murugan static int cqspi_wait_idle(struct cqspi_st *cqspi) 37631fb632bSRamuthevar Vadivel Murugan { 37731fb632bSRamuthevar Vadivel Murugan const unsigned int poll_idle_retry = 3; 37831fb632bSRamuthevar Vadivel Murugan unsigned int count = 0; 37931fb632bSRamuthevar Vadivel Murugan unsigned long timeout; 38031fb632bSRamuthevar Vadivel Murugan 38131fb632bSRamuthevar Vadivel Murugan timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS); 38231fb632bSRamuthevar Vadivel Murugan while (1) { 38331fb632bSRamuthevar Vadivel Murugan /* 38431fb632bSRamuthevar Vadivel Murugan * Read few times in succession to ensure the controller 38531fb632bSRamuthevar Vadivel Murugan * is indeed idle, that is, the bit does not transition 38631fb632bSRamuthevar Vadivel Murugan * low again. 38731fb632bSRamuthevar Vadivel Murugan */ 38831fb632bSRamuthevar Vadivel Murugan if (cqspi_is_idle(cqspi)) 38931fb632bSRamuthevar Vadivel Murugan count++; 39031fb632bSRamuthevar Vadivel Murugan else 39131fb632bSRamuthevar Vadivel Murugan count = 0; 39231fb632bSRamuthevar Vadivel Murugan 39331fb632bSRamuthevar Vadivel Murugan if (count >= poll_idle_retry) 39431fb632bSRamuthevar Vadivel Murugan return 0; 39531fb632bSRamuthevar Vadivel Murugan 39631fb632bSRamuthevar Vadivel Murugan if (time_after(jiffies, timeout)) { 39731fb632bSRamuthevar Vadivel Murugan /* Timeout, in busy mode. */ 39831fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 39931fb632bSRamuthevar Vadivel Murugan "QSPI is still busy after %dms timeout.\n", 40031fb632bSRamuthevar Vadivel Murugan CQSPI_TIMEOUT_MS); 40131fb632bSRamuthevar Vadivel Murugan return -ETIMEDOUT; 40231fb632bSRamuthevar Vadivel Murugan } 40331fb632bSRamuthevar Vadivel Murugan 40431fb632bSRamuthevar Vadivel Murugan cpu_relax(); 40531fb632bSRamuthevar Vadivel Murugan } 40631fb632bSRamuthevar Vadivel Murugan } 40731fb632bSRamuthevar Vadivel Murugan 40831fb632bSRamuthevar Vadivel Murugan static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg) 40931fb632bSRamuthevar Vadivel Murugan { 41031fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 41131fb632bSRamuthevar Vadivel Murugan int ret; 41231fb632bSRamuthevar Vadivel Murugan 41331fb632bSRamuthevar Vadivel Murugan /* Write the CMDCTRL without start execution. */ 41431fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CMDCTRL); 41531fb632bSRamuthevar Vadivel Murugan /* Start execute */ 41631fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK; 41731fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CMDCTRL); 41831fb632bSRamuthevar Vadivel Murugan 41931fb632bSRamuthevar Vadivel Murugan /* Polling for completion. */ 42031fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL, 42131fb632bSRamuthevar Vadivel Murugan CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1); 42231fb632bSRamuthevar Vadivel Murugan if (ret) { 42331fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 42431fb632bSRamuthevar Vadivel Murugan "Flash command execution timed out.\n"); 42531fb632bSRamuthevar Vadivel Murugan return ret; 42631fb632bSRamuthevar Vadivel Murugan } 42731fb632bSRamuthevar Vadivel Murugan 42831fb632bSRamuthevar Vadivel Murugan /* Polling QSPI idle status. */ 42931fb632bSRamuthevar Vadivel Murugan return cqspi_wait_idle(cqspi); 43031fb632bSRamuthevar Vadivel Murugan } 43131fb632bSRamuthevar Vadivel Murugan 432f453f293SPratyush Yadav static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata, 433f453f293SPratyush Yadav const struct spi_mem_op *op, 434f453f293SPratyush Yadav unsigned int shift) 435f453f293SPratyush Yadav { 436f453f293SPratyush Yadav struct cqspi_st *cqspi = f_pdata->cqspi; 437f453f293SPratyush Yadav void __iomem *reg_base = cqspi->iobase; 438f453f293SPratyush Yadav unsigned int reg; 439f453f293SPratyush Yadav u8 ext; 440f453f293SPratyush Yadav 441f453f293SPratyush Yadav if (op->cmd.nbytes != 2) 442f453f293SPratyush Yadav return -EINVAL; 443f453f293SPratyush Yadav 444f453f293SPratyush Yadav /* Opcode extension is the LSB. */ 445f453f293SPratyush Yadav ext = op->cmd.opcode & 0xff; 446f453f293SPratyush Yadav 447f453f293SPratyush Yadav reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER); 448f453f293SPratyush Yadav reg &= ~(0xff << shift); 449f453f293SPratyush Yadav reg |= ext << shift; 450f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER); 451f453f293SPratyush Yadav 452f453f293SPratyush Yadav return 0; 453f453f293SPratyush Yadav } 454f453f293SPratyush Yadav 455f453f293SPratyush Yadav static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata, 45628ac902aSMatthias Schiffer const struct spi_mem_op *op, unsigned int shift) 457f453f293SPratyush Yadav { 458f453f293SPratyush Yadav struct cqspi_st *cqspi = f_pdata->cqspi; 459f453f293SPratyush Yadav void __iomem *reg_base = cqspi->iobase; 460f453f293SPratyush Yadav unsigned int reg; 461f453f293SPratyush Yadav int ret; 462f453f293SPratyush Yadav 463f453f293SPratyush Yadav reg = readl(reg_base + CQSPI_REG_CONFIG); 464f453f293SPratyush Yadav 465f453f293SPratyush Yadav /* 466f453f293SPratyush Yadav * We enable dual byte opcode here. The callers have to set up the 467f453f293SPratyush Yadav * extension opcode based on which type of operation it is. 468f453f293SPratyush Yadav */ 46928ac902aSMatthias Schiffer if (op->cmd.dtr) { 470f453f293SPratyush Yadav reg |= CQSPI_REG_CONFIG_DTR_PROTO; 471f453f293SPratyush Yadav reg |= CQSPI_REG_CONFIG_DUAL_OPCODE; 472f453f293SPratyush Yadav 473f453f293SPratyush Yadav /* Set up command opcode extension. */ 474f453f293SPratyush Yadav ret = cqspi_setup_opcode_ext(f_pdata, op, shift); 475f453f293SPratyush Yadav if (ret) 476f453f293SPratyush Yadav return ret; 477f453f293SPratyush Yadav } else { 478f453f293SPratyush Yadav reg &= ~CQSPI_REG_CONFIG_DTR_PROTO; 479f453f293SPratyush Yadav reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE; 480f453f293SPratyush Yadav } 481f453f293SPratyush Yadav 482f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_CONFIG); 483f453f293SPratyush Yadav 484f453f293SPratyush Yadav return cqspi_wait_idle(cqspi); 485f453f293SPratyush Yadav } 486f453f293SPratyush Yadav 48731fb632bSRamuthevar Vadivel Murugan static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, 48831fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 48931fb632bSRamuthevar Vadivel Murugan { 49031fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 49131fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 49231fb632bSRamuthevar Vadivel Murugan u8 *rxbuf = op->data.buf.in; 493f453f293SPratyush Yadav u8 opcode; 49431fb632bSRamuthevar Vadivel Murugan size_t n_rx = op->data.nbytes; 49531fb632bSRamuthevar Vadivel Murugan unsigned int rdreg; 49631fb632bSRamuthevar Vadivel Murugan unsigned int reg; 497888d517bSPratyush Yadav unsigned int dummy_clk; 49831fb632bSRamuthevar Vadivel Murugan size_t read_len; 49931fb632bSRamuthevar Vadivel Murugan int status; 50031fb632bSRamuthevar Vadivel Murugan 50128ac902aSMatthias Schiffer status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB); 502f453f293SPratyush Yadav if (status) 503f453f293SPratyush Yadav return status; 504f453f293SPratyush Yadav 50531fb632bSRamuthevar Vadivel Murugan if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) { 50631fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 50731fb632bSRamuthevar Vadivel Murugan "Invalid input argument, len %zu rxbuf 0x%p\n", 50831fb632bSRamuthevar Vadivel Murugan n_rx, rxbuf); 50931fb632bSRamuthevar Vadivel Murugan return -EINVAL; 51031fb632bSRamuthevar Vadivel Murugan } 51131fb632bSRamuthevar Vadivel Murugan 51228ac902aSMatthias Schiffer if (op->cmd.dtr) 513f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 514f453f293SPratyush Yadav else 515f453f293SPratyush Yadav opcode = op->cmd.opcode; 516f453f293SPratyush Yadav 51731fb632bSRamuthevar Vadivel Murugan reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 51831fb632bSRamuthevar Vadivel Murugan 51928ac902aSMatthias Schiffer rdreg = cqspi_calc_rdreg(op); 52031fb632bSRamuthevar Vadivel Murugan writel(rdreg, reg_base + CQSPI_REG_RD_INSTR); 52131fb632bSRamuthevar Vadivel Murugan 52228ac902aSMatthias Schiffer dummy_clk = cqspi_calc_dummy(op); 523888d517bSPratyush Yadav if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 524888d517bSPratyush Yadav return -EOPNOTSUPP; 525888d517bSPratyush Yadav 526888d517bSPratyush Yadav if (dummy_clk) 527888d517bSPratyush Yadav reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK) 528888d517bSPratyush Yadav << CQSPI_REG_CMDCTRL_DUMMY_LSB; 529888d517bSPratyush Yadav 53031fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); 53131fb632bSRamuthevar Vadivel Murugan 53231fb632bSRamuthevar Vadivel Murugan /* 0 means 1 byte. */ 53331fb632bSRamuthevar Vadivel Murugan reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) 53431fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); 53531fb632bSRamuthevar Vadivel Murugan status = cqspi_exec_flash_cmd(cqspi, reg); 53631fb632bSRamuthevar Vadivel Murugan if (status) 53731fb632bSRamuthevar Vadivel Murugan return status; 53831fb632bSRamuthevar Vadivel Murugan 53931fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER); 54031fb632bSRamuthevar Vadivel Murugan 54131fb632bSRamuthevar Vadivel Murugan /* Put the read value into rx_buf */ 54231fb632bSRamuthevar Vadivel Murugan read_len = (n_rx > 4) ? 4 : n_rx; 54331fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, ®, read_len); 54431fb632bSRamuthevar Vadivel Murugan rxbuf += read_len; 54531fb632bSRamuthevar Vadivel Murugan 54631fb632bSRamuthevar Vadivel Murugan if (n_rx > 4) { 54731fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER); 54831fb632bSRamuthevar Vadivel Murugan 54931fb632bSRamuthevar Vadivel Murugan read_len = n_rx - read_len; 55031fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, ®, read_len); 55131fb632bSRamuthevar Vadivel Murugan } 55231fb632bSRamuthevar Vadivel Murugan 553d4f43a2dSDhruva Gole /* Reset CMD_CTRL Reg once command read completes */ 554d4f43a2dSDhruva Gole writel(0, reg_base + CQSPI_REG_CMDCTRL); 555d4f43a2dSDhruva Gole 55631fb632bSRamuthevar Vadivel Murugan return 0; 55731fb632bSRamuthevar Vadivel Murugan } 55831fb632bSRamuthevar Vadivel Murugan 55931fb632bSRamuthevar Vadivel Murugan static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata, 56031fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 56131fb632bSRamuthevar Vadivel Murugan { 56231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 56331fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 564f453f293SPratyush Yadav u8 opcode; 56531fb632bSRamuthevar Vadivel Murugan const u8 *txbuf = op->data.buf.out; 56631fb632bSRamuthevar Vadivel Murugan size_t n_tx = op->data.nbytes; 56731fb632bSRamuthevar Vadivel Murugan unsigned int reg; 56831fb632bSRamuthevar Vadivel Murugan unsigned int data; 56931fb632bSRamuthevar Vadivel Murugan size_t write_len; 570f453f293SPratyush Yadav int ret; 571f453f293SPratyush Yadav 57228ac902aSMatthias Schiffer ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB); 573f453f293SPratyush Yadav if (ret) 574f453f293SPratyush Yadav return ret; 57531fb632bSRamuthevar Vadivel Murugan 57631fb632bSRamuthevar Vadivel Murugan if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) { 57731fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 57831fb632bSRamuthevar Vadivel Murugan "Invalid input argument, cmdlen %zu txbuf 0x%p\n", 57931fb632bSRamuthevar Vadivel Murugan n_tx, txbuf); 58031fb632bSRamuthevar Vadivel Murugan return -EINVAL; 58131fb632bSRamuthevar Vadivel Murugan } 58231fb632bSRamuthevar Vadivel Murugan 58328ac902aSMatthias Schiffer reg = cqspi_calc_rdreg(op); 584f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_RD_INSTR); 585f453f293SPratyush Yadav 58628ac902aSMatthias Schiffer if (op->cmd.dtr) 587f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 588f453f293SPratyush Yadav else 589f453f293SPratyush Yadav opcode = op->cmd.opcode; 590f453f293SPratyush Yadav 59131fb632bSRamuthevar Vadivel Murugan reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 59231fb632bSRamuthevar Vadivel Murugan 59331fb632bSRamuthevar Vadivel Murugan if (op->addr.nbytes) { 59431fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 59531fb632bSRamuthevar Vadivel Murugan reg |= ((op->addr.nbytes - 1) & 59631fb632bSRamuthevar Vadivel Murugan CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) 59731fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; 59831fb632bSRamuthevar Vadivel Murugan 59931fb632bSRamuthevar Vadivel Murugan writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); 60031fb632bSRamuthevar Vadivel Murugan } 60131fb632bSRamuthevar Vadivel Murugan 60231fb632bSRamuthevar Vadivel Murugan if (n_tx) { 60331fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB); 60431fb632bSRamuthevar Vadivel Murugan reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) 60531fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_WR_BYTES_LSB; 60631fb632bSRamuthevar Vadivel Murugan data = 0; 60731fb632bSRamuthevar Vadivel Murugan write_len = (n_tx > 4) ? 4 : n_tx; 60831fb632bSRamuthevar Vadivel Murugan memcpy(&data, txbuf, write_len); 60931fb632bSRamuthevar Vadivel Murugan txbuf += write_len; 61031fb632bSRamuthevar Vadivel Murugan writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER); 61131fb632bSRamuthevar Vadivel Murugan 61231fb632bSRamuthevar Vadivel Murugan if (n_tx > 4) { 61331fb632bSRamuthevar Vadivel Murugan data = 0; 61431fb632bSRamuthevar Vadivel Murugan write_len = n_tx - 4; 61531fb632bSRamuthevar Vadivel Murugan memcpy(&data, txbuf, write_len); 61631fb632bSRamuthevar Vadivel Murugan writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER); 61731fb632bSRamuthevar Vadivel Murugan } 61831fb632bSRamuthevar Vadivel Murugan } 61931fb632bSRamuthevar Vadivel Murugan 620d4f43a2dSDhruva Gole ret = cqspi_exec_flash_cmd(cqspi, reg); 621d4f43a2dSDhruva Gole 622d4f43a2dSDhruva Gole /* Reset CMD_CTRL Reg once command write completes */ 623d4f43a2dSDhruva Gole writel(0, reg_base + CQSPI_REG_CMDCTRL); 624d4f43a2dSDhruva Gole 625d4f43a2dSDhruva Gole return ret; 62631fb632bSRamuthevar Vadivel Murugan } 62731fb632bSRamuthevar Vadivel Murugan 62831fb632bSRamuthevar Vadivel Murugan static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata, 62931fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 63031fb632bSRamuthevar Vadivel Murugan { 63131fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 63231fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 63331fb632bSRamuthevar Vadivel Murugan unsigned int dummy_clk = 0; 63431fb632bSRamuthevar Vadivel Murugan unsigned int reg; 635f453f293SPratyush Yadav int ret; 636f453f293SPratyush Yadav u8 opcode; 63731fb632bSRamuthevar Vadivel Murugan 63828ac902aSMatthias Schiffer ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB); 639f453f293SPratyush Yadav if (ret) 640f453f293SPratyush Yadav return ret; 641f453f293SPratyush Yadav 64228ac902aSMatthias Schiffer if (op->cmd.dtr) 643f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 644f453f293SPratyush Yadav else 645f453f293SPratyush Yadav opcode = op->cmd.opcode; 646f453f293SPratyush Yadav 647f453f293SPratyush Yadav reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB; 64828ac902aSMatthias Schiffer reg |= cqspi_calc_rdreg(op); 64931fb632bSRamuthevar Vadivel Murugan 65031fb632bSRamuthevar Vadivel Murugan /* Setup dummy clock cycles */ 65128ac902aSMatthias Schiffer dummy_clk = cqspi_calc_dummy(op); 652888d517bSPratyush Yadav 65331fb632bSRamuthevar Vadivel Murugan if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 654ceeda328SPratyush Yadav return -EOPNOTSUPP; 65531fb632bSRamuthevar Vadivel Murugan 65631fb632bSRamuthevar Vadivel Murugan if (dummy_clk) 65731fb632bSRamuthevar Vadivel Murugan reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK) 65831fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_RD_INSTR_DUMMY_LSB; 65931fb632bSRamuthevar Vadivel Murugan 66031fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_RD_INSTR); 66131fb632bSRamuthevar Vadivel Murugan 66231fb632bSRamuthevar Vadivel Murugan /* Set address width */ 66331fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_SIZE); 66431fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 66531fb632bSRamuthevar Vadivel Murugan reg |= (op->addr.nbytes - 1); 66631fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_SIZE); 66731fb632bSRamuthevar Vadivel Murugan return 0; 66831fb632bSRamuthevar Vadivel Murugan } 66931fb632bSRamuthevar Vadivel Murugan 67031fb632bSRamuthevar Vadivel Murugan static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, 67131fb632bSRamuthevar Vadivel Murugan u8 *rxbuf, loff_t from_addr, 67231fb632bSRamuthevar Vadivel Murugan const size_t n_rx) 67331fb632bSRamuthevar Vadivel Murugan { 67431fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 67531fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 67631fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 67731fb632bSRamuthevar Vadivel Murugan void __iomem *ahb_base = cqspi->ahb_base; 67831fb632bSRamuthevar Vadivel Murugan unsigned int remaining = n_rx; 67931fb632bSRamuthevar Vadivel Murugan unsigned int mod_bytes = n_rx % 4; 68031fb632bSRamuthevar Vadivel Murugan unsigned int bytes_to_read = 0; 68131fb632bSRamuthevar Vadivel Murugan u8 *rxbuf_end = rxbuf + n_rx; 68231fb632bSRamuthevar Vadivel Murugan int ret = 0; 68331fb632bSRamuthevar Vadivel Murugan 68431fb632bSRamuthevar Vadivel Murugan writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 68531fb632bSRamuthevar Vadivel Murugan writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES); 68631fb632bSRamuthevar Vadivel Murugan 68731fb632bSRamuthevar Vadivel Murugan /* Clear all interrupts. */ 68831fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 68931fb632bSRamuthevar Vadivel Murugan 6909ee5b6d5SNiravkumar L Rabara /* 6919ee5b6d5SNiravkumar L Rabara * On SoCFPGA platform reading the SRAM is slow due to 6929ee5b6d5SNiravkumar L Rabara * hardware limitation and causing read interrupt storm to CPU, 6939ee5b6d5SNiravkumar L Rabara * so enabling only watermark interrupt to disable all read 6949ee5b6d5SNiravkumar L Rabara * interrupts later as we want to run "bytes to read" loop with 6959ee5b6d5SNiravkumar L Rabara * all the read interrupts disabled for max performance. 6969ee5b6d5SNiravkumar L Rabara */ 6979ee5b6d5SNiravkumar L Rabara 6989ee5b6d5SNiravkumar L Rabara if (!cqspi->slow_sram) 69931fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK); 7009ee5b6d5SNiravkumar L Rabara else 7019ee5b6d5SNiravkumar L Rabara writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK); 70231fb632bSRamuthevar Vadivel Murugan 70331fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 70431fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTRD_START_MASK, 70531fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTRD); 70631fb632bSRamuthevar Vadivel Murugan 70731fb632bSRamuthevar Vadivel Murugan while (remaining > 0) { 70831fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->transfer_complete, 70931fb632bSRamuthevar Vadivel Murugan msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) 71031fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 71131fb632bSRamuthevar Vadivel Murugan 7129ee5b6d5SNiravkumar L Rabara /* 7139ee5b6d5SNiravkumar L Rabara * Disable all read interrupts until 7149ee5b6d5SNiravkumar L Rabara * we are out of "bytes to read" 7159ee5b6d5SNiravkumar L Rabara */ 7169ee5b6d5SNiravkumar L Rabara if (cqspi->slow_sram) 7179ee5b6d5SNiravkumar L Rabara writel(0x0, reg_base + CQSPI_REG_IRQMASK); 7189ee5b6d5SNiravkumar L Rabara 71931fb632bSRamuthevar Vadivel Murugan bytes_to_read = cqspi_get_rd_sram_level(cqspi); 72031fb632bSRamuthevar Vadivel Murugan 72131fb632bSRamuthevar Vadivel Murugan if (ret && bytes_to_read == 0) { 72231fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect read timeout, no bytes\n"); 72331fb632bSRamuthevar Vadivel Murugan goto failrd; 72431fb632bSRamuthevar Vadivel Murugan } 72531fb632bSRamuthevar Vadivel Murugan 72631fb632bSRamuthevar Vadivel Murugan while (bytes_to_read != 0) { 72731fb632bSRamuthevar Vadivel Murugan unsigned int word_remain = round_down(remaining, 4); 72831fb632bSRamuthevar Vadivel Murugan 72931fb632bSRamuthevar Vadivel Murugan bytes_to_read *= cqspi->fifo_width; 73031fb632bSRamuthevar Vadivel Murugan bytes_to_read = bytes_to_read > remaining ? 73131fb632bSRamuthevar Vadivel Murugan remaining : bytes_to_read; 73231fb632bSRamuthevar Vadivel Murugan bytes_to_read = round_down(bytes_to_read, 4); 73331fb632bSRamuthevar Vadivel Murugan /* Read 4 byte word chunks then single bytes */ 73431fb632bSRamuthevar Vadivel Murugan if (bytes_to_read) { 73531fb632bSRamuthevar Vadivel Murugan ioread32_rep(ahb_base, rxbuf, 73631fb632bSRamuthevar Vadivel Murugan (bytes_to_read / 4)); 73731fb632bSRamuthevar Vadivel Murugan } else if (!word_remain && mod_bytes) { 73831fb632bSRamuthevar Vadivel Murugan unsigned int temp = ioread32(ahb_base); 73931fb632bSRamuthevar Vadivel Murugan 74031fb632bSRamuthevar Vadivel Murugan bytes_to_read = mod_bytes; 74131fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, &temp, min((unsigned int) 74231fb632bSRamuthevar Vadivel Murugan (rxbuf_end - rxbuf), 74331fb632bSRamuthevar Vadivel Murugan bytes_to_read)); 74431fb632bSRamuthevar Vadivel Murugan } 74531fb632bSRamuthevar Vadivel Murugan rxbuf += bytes_to_read; 74631fb632bSRamuthevar Vadivel Murugan remaining -= bytes_to_read; 74731fb632bSRamuthevar Vadivel Murugan bytes_to_read = cqspi_get_rd_sram_level(cqspi); 74831fb632bSRamuthevar Vadivel Murugan } 74931fb632bSRamuthevar Vadivel Murugan 7509ee5b6d5SNiravkumar L Rabara if (remaining > 0) { 75131fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 7529ee5b6d5SNiravkumar L Rabara if (cqspi->slow_sram) 7539ee5b6d5SNiravkumar L Rabara writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK); 7549ee5b6d5SNiravkumar L Rabara } 75531fb632bSRamuthevar Vadivel Murugan } 75631fb632bSRamuthevar Vadivel Murugan 75731fb632bSRamuthevar Vadivel Murugan /* Check indirect done status */ 75831fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD, 75931fb632bSRamuthevar Vadivel Murugan CQSPI_REG_INDIRECTRD_DONE_MASK, 0); 76031fb632bSRamuthevar Vadivel Murugan if (ret) { 76131fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect read completion error (%i)\n", ret); 76231fb632bSRamuthevar Vadivel Murugan goto failrd; 76331fb632bSRamuthevar Vadivel Murugan } 76431fb632bSRamuthevar Vadivel Murugan 76531fb632bSRamuthevar Vadivel Murugan /* Disable interrupt */ 76631fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 76731fb632bSRamuthevar Vadivel Murugan 76831fb632bSRamuthevar Vadivel Murugan /* Clear indirect completion status */ 76931fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD); 77031fb632bSRamuthevar Vadivel Murugan 77131fb632bSRamuthevar Vadivel Murugan return 0; 77231fb632bSRamuthevar Vadivel Murugan 77331fb632bSRamuthevar Vadivel Murugan failrd: 77431fb632bSRamuthevar Vadivel Murugan /* Disable interrupt */ 77531fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 77631fb632bSRamuthevar Vadivel Murugan 77731fb632bSRamuthevar Vadivel Murugan /* Cancel the indirect read */ 77831fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 77931fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTRD); 78031fb632bSRamuthevar Vadivel Murugan return ret; 78131fb632bSRamuthevar Vadivel Murugan } 78231fb632bSRamuthevar Vadivel Murugan 7831a6f854fSSai Krishna Potthuri static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata, 7841a6f854fSSai Krishna Potthuri u_char *rxbuf, loff_t from_addr, 7851a6f854fSSai Krishna Potthuri size_t n_rx) 7861a6f854fSSai Krishna Potthuri { 7871a6f854fSSai Krishna Potthuri struct cqspi_st *cqspi = f_pdata->cqspi; 7881a6f854fSSai Krishna Potthuri struct device *dev = &cqspi->pdev->dev; 7891a6f854fSSai Krishna Potthuri void __iomem *reg_base = cqspi->iobase; 7901a6f854fSSai Krishna Potthuri u32 reg, bytes_to_dma; 7911a6f854fSSai Krishna Potthuri loff_t addr = from_addr; 7921a6f854fSSai Krishna Potthuri void *buf = rxbuf; 7931a6f854fSSai Krishna Potthuri dma_addr_t dma_addr; 7941a6f854fSSai Krishna Potthuri u8 bytes_rem; 7951a6f854fSSai Krishna Potthuri int ret = 0; 7961a6f854fSSai Krishna Potthuri 7971a6f854fSSai Krishna Potthuri bytes_rem = n_rx % 4; 7981a6f854fSSai Krishna Potthuri bytes_to_dma = (n_rx - bytes_rem); 7991a6f854fSSai Krishna Potthuri 8001a6f854fSSai Krishna Potthuri if (!bytes_to_dma) 8011a6f854fSSai Krishna Potthuri goto nondmard; 8021a6f854fSSai Krishna Potthuri 8031a6f854fSSai Krishna Potthuri ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA); 8041a6f854fSSai Krishna Potthuri if (ret) 8051a6f854fSSai Krishna Potthuri return ret; 8061a6f854fSSai Krishna Potthuri 8071a6f854fSSai Krishna Potthuri reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 8081a6f854fSSai Krishna Potthuri reg |= CQSPI_REG_CONFIG_DMA_MASK; 8091a6f854fSSai Krishna Potthuri writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 8101a6f854fSSai Krishna Potthuri 8111a6f854fSSai Krishna Potthuri dma_addr = dma_map_single(dev, rxbuf, bytes_to_dma, DMA_FROM_DEVICE); 8121a6f854fSSai Krishna Potthuri if (dma_mapping_error(dev, dma_addr)) { 8131a6f854fSSai Krishna Potthuri dev_err(dev, "dma mapping failed\n"); 8141a6f854fSSai Krishna Potthuri return -ENOMEM; 8151a6f854fSSai Krishna Potthuri } 8161a6f854fSSai Krishna Potthuri 8171a6f854fSSai Krishna Potthuri writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 8181a6f854fSSai Krishna Potthuri writel(bytes_to_dma, reg_base + CQSPI_REG_INDIRECTRDBYTES); 8191a6f854fSSai Krishna Potthuri writel(CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL, 8201a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_INDTRIG_ADDRRANGE); 8211a6f854fSSai Krishna Potthuri 8221a6f854fSSai Krishna Potthuri /* Clear all interrupts. */ 8231a6f854fSSai Krishna Potthuri writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 8241a6f854fSSai Krishna Potthuri 8251a6f854fSSai Krishna Potthuri /* Enable DMA done interrupt */ 8261a6f854fSSai Krishna Potthuri writel(CQSPI_REG_VERSAL_DMA_DST_DONE_MASK, 8271a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_VERSAL_DMA_DST_I_EN); 8281a6f854fSSai Krishna Potthuri 8291a6f854fSSai Krishna Potthuri /* Default DMA periph configuration */ 8301a6f854fSSai Krishna Potthuri writel(CQSPI_REG_VERSAL_DMA_VAL, reg_base + CQSPI_REG_DMA); 8311a6f854fSSai Krishna Potthuri 8321a6f854fSSai Krishna Potthuri /* Configure DMA Dst address */ 8331a6f854fSSai Krishna Potthuri writel(lower_32_bits(dma_addr), 8341a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR); 8351a6f854fSSai Krishna Potthuri writel(upper_32_bits(dma_addr), 8361a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB); 8371a6f854fSSai Krishna Potthuri 8381a6f854fSSai Krishna Potthuri /* Configure DMA Src address */ 8391a6f854fSSai Krishna Potthuri writel(cqspi->trigger_address, reg_base + 8401a6f854fSSai Krishna Potthuri CQSPI_REG_VERSAL_DMA_SRC_ADDR); 8411a6f854fSSai Krishna Potthuri 8421a6f854fSSai Krishna Potthuri /* Set DMA destination size */ 8431a6f854fSSai Krishna Potthuri writel(bytes_to_dma, reg_base + CQSPI_REG_VERSAL_DMA_DST_SIZE); 8441a6f854fSSai Krishna Potthuri 8451a6f854fSSai Krishna Potthuri /* Set DMA destination control */ 8461a6f854fSSai Krishna Potthuri writel(CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL, 8471a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_VERSAL_DMA_DST_CTRL); 8481a6f854fSSai Krishna Potthuri 8491a6f854fSSai Krishna Potthuri writel(CQSPI_REG_INDIRECTRD_START_MASK, 8501a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_INDIRECTRD); 8511a6f854fSSai Krishna Potthuri 8521a6f854fSSai Krishna Potthuri reinit_completion(&cqspi->transfer_complete); 8531a6f854fSSai Krishna Potthuri 8541a6f854fSSai Krishna Potthuri if (!wait_for_completion_timeout(&cqspi->transfer_complete, 8551a6f854fSSai Krishna Potthuri msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) { 8561a6f854fSSai Krishna Potthuri ret = -ETIMEDOUT; 8571a6f854fSSai Krishna Potthuri goto failrd; 8581a6f854fSSai Krishna Potthuri } 8591a6f854fSSai Krishna Potthuri 8601a6f854fSSai Krishna Potthuri /* Disable DMA interrupt */ 8611a6f854fSSai Krishna Potthuri writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS); 8621a6f854fSSai Krishna Potthuri 8631a6f854fSSai Krishna Potthuri /* Clear indirect completion status */ 8641a6f854fSSai Krishna Potthuri writel(CQSPI_REG_INDIRECTRD_DONE_MASK, 8651a6f854fSSai Krishna Potthuri cqspi->iobase + CQSPI_REG_INDIRECTRD); 8661a6f854fSSai Krishna Potthuri dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE); 8671a6f854fSSai Krishna Potthuri 8681a6f854fSSai Krishna Potthuri reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 8691a6f854fSSai Krishna Potthuri reg &= ~CQSPI_REG_CONFIG_DMA_MASK; 8701a6f854fSSai Krishna Potthuri writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 8711a6f854fSSai Krishna Potthuri 8721a6f854fSSai Krishna Potthuri ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, 8731a6f854fSSai Krishna Potthuri PM_OSPI_MUX_SEL_LINEAR); 8741a6f854fSSai Krishna Potthuri if (ret) 8751a6f854fSSai Krishna Potthuri return ret; 8761a6f854fSSai Krishna Potthuri 8771a6f854fSSai Krishna Potthuri nondmard: 8781a6f854fSSai Krishna Potthuri if (bytes_rem) { 8791a6f854fSSai Krishna Potthuri addr += bytes_to_dma; 8801a6f854fSSai Krishna Potthuri buf += bytes_to_dma; 8811a6f854fSSai Krishna Potthuri ret = cqspi_indirect_read_execute(f_pdata, buf, addr, 8821a6f854fSSai Krishna Potthuri bytes_rem); 8831a6f854fSSai Krishna Potthuri if (ret) 8841a6f854fSSai Krishna Potthuri return ret; 8851a6f854fSSai Krishna Potthuri } 8861a6f854fSSai Krishna Potthuri 8871a6f854fSSai Krishna Potthuri return 0; 8881a6f854fSSai Krishna Potthuri 8891a6f854fSSai Krishna Potthuri failrd: 8901a6f854fSSai Krishna Potthuri /* Disable DMA interrupt */ 8911a6f854fSSai Krishna Potthuri writel(0x0, reg_base + CQSPI_REG_VERSAL_DMA_DST_I_DIS); 8921a6f854fSSai Krishna Potthuri 8931a6f854fSSai Krishna Potthuri /* Cancel the indirect read */ 8941a6f854fSSai Krishna Potthuri writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 8951a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_INDIRECTRD); 8961a6f854fSSai Krishna Potthuri 897d9c55c95SArnd Bergmann dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE); 8981a6f854fSSai Krishna Potthuri 8991a6f854fSSai Krishna Potthuri reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 9001a6f854fSSai Krishna Potthuri reg &= ~CQSPI_REG_CONFIG_DMA_MASK; 9011a6f854fSSai Krishna Potthuri writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 9021a6f854fSSai Krishna Potthuri 9031a6f854fSSai Krishna Potthuri zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR); 9041a6f854fSSai Krishna Potthuri 9051a6f854fSSai Krishna Potthuri return ret; 9061a6f854fSSai Krishna Potthuri } 9071a6f854fSSai Krishna Potthuri 90831fb632bSRamuthevar Vadivel Murugan static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata, 90931fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 91031fb632bSRamuthevar Vadivel Murugan { 91131fb632bSRamuthevar Vadivel Murugan unsigned int reg; 912f453f293SPratyush Yadav int ret; 91331fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 91431fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 915f453f293SPratyush Yadav u8 opcode; 916f453f293SPratyush Yadav 91728ac902aSMatthias Schiffer ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB); 918f453f293SPratyush Yadav if (ret) 919f453f293SPratyush Yadav return ret; 920f453f293SPratyush Yadav 92128ac902aSMatthias Schiffer if (op->cmd.dtr) 922f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 923f453f293SPratyush Yadav else 924f453f293SPratyush Yadav opcode = op->cmd.opcode; 92531fb632bSRamuthevar Vadivel Murugan 92631fb632bSRamuthevar Vadivel Murugan /* Set opcode. */ 927f453f293SPratyush Yadav reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; 92828ac902aSMatthias Schiffer reg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; 92928ac902aSMatthias Schiffer reg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; 93031fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_WR_INSTR); 93128ac902aSMatthias Schiffer reg = cqspi_calc_rdreg(op); 93231fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_RD_INSTR); 93331fb632bSRamuthevar Vadivel Murugan 934f453f293SPratyush Yadav /* 9359cb2ff11SApurva Nandan * SPI NAND flashes require the address of the status register to be 9369cb2ff11SApurva Nandan * passed in the Read SR command. Also, some SPI NOR flashes like the 9379cb2ff11SApurva Nandan * cypress Semper flash expect a 4-byte dummy address in the Read SR 9389cb2ff11SApurva Nandan * command in DTR mode. 9399cb2ff11SApurva Nandan * 9409cb2ff11SApurva Nandan * But this controller does not support address phase in the Read SR 9419cb2ff11SApurva Nandan * command when doing auto-HW polling. So, disable write completion 9429cb2ff11SApurva Nandan * polling on the controller's side. spinand and spi-nor will take 9439cb2ff11SApurva Nandan * care of polling the status register. 944f453f293SPratyush Yadav */ 94598d948ebSDinh Nguyen if (cqspi->wr_completion) { 946f453f293SPratyush Yadav reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL); 947f453f293SPratyush Yadav reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL; 948f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL); 949*e8c51b16SDhruva Gole /* 950*e8c51b16SDhruva Gole * DAC mode require auto polling as flash needs to be polled 951*e8c51b16SDhruva Gole * for write completion in case of bubble in SPI transaction 952*e8c51b16SDhruva Gole * due to slow CPU/DMA master. 953*e8c51b16SDhruva Gole */ 954*e8c51b16SDhruva Gole cqspi->use_direct_mode_wr = false; 95598d948ebSDinh Nguyen } 956f453f293SPratyush Yadav 95731fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_SIZE); 95831fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 95931fb632bSRamuthevar Vadivel Murugan reg |= (op->addr.nbytes - 1); 96031fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_SIZE); 96131fb632bSRamuthevar Vadivel Murugan return 0; 96231fb632bSRamuthevar Vadivel Murugan } 96331fb632bSRamuthevar Vadivel Murugan 96431fb632bSRamuthevar Vadivel Murugan static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, 96531fb632bSRamuthevar Vadivel Murugan loff_t to_addr, const u8 *txbuf, 96631fb632bSRamuthevar Vadivel Murugan const size_t n_tx) 96731fb632bSRamuthevar Vadivel Murugan { 96831fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 96931fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 97031fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 97131fb632bSRamuthevar Vadivel Murugan unsigned int remaining = n_tx; 97231fb632bSRamuthevar Vadivel Murugan unsigned int write_bytes; 97331fb632bSRamuthevar Vadivel Murugan int ret; 97431fb632bSRamuthevar Vadivel Murugan 97531fb632bSRamuthevar Vadivel Murugan writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR); 97631fb632bSRamuthevar Vadivel Murugan writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES); 97731fb632bSRamuthevar Vadivel Murugan 97831fb632bSRamuthevar Vadivel Murugan /* Clear all interrupts. */ 97931fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 98031fb632bSRamuthevar Vadivel Murugan 98131fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK); 98231fb632bSRamuthevar Vadivel Murugan 98331fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 98431fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_START_MASK, 98531fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTWR); 98631fb632bSRamuthevar Vadivel Murugan /* 98731fb632bSRamuthevar Vadivel Murugan * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access 98831fb632bSRamuthevar Vadivel Murugan * Controller programming sequence, couple of cycles of 98931fb632bSRamuthevar Vadivel Murugan * QSPI_REF_CLK delay is required for the above bit to 99031fb632bSRamuthevar Vadivel Murugan * be internally synchronized by the QSPI module. Provide 5 99131fb632bSRamuthevar Vadivel Murugan * cycles of delay. 99231fb632bSRamuthevar Vadivel Murugan */ 99331fb632bSRamuthevar Vadivel Murugan if (cqspi->wr_delay) 99431fb632bSRamuthevar Vadivel Murugan ndelay(cqspi->wr_delay); 99531fb632bSRamuthevar Vadivel Murugan 99631fb632bSRamuthevar Vadivel Murugan while (remaining > 0) { 99731fb632bSRamuthevar Vadivel Murugan size_t write_words, mod_bytes; 99831fb632bSRamuthevar Vadivel Murugan 99931fb632bSRamuthevar Vadivel Murugan write_bytes = remaining; 100031fb632bSRamuthevar Vadivel Murugan write_words = write_bytes / 4; 100131fb632bSRamuthevar Vadivel Murugan mod_bytes = write_bytes % 4; 100231fb632bSRamuthevar Vadivel Murugan /* Write 4 bytes at a time then single bytes. */ 100331fb632bSRamuthevar Vadivel Murugan if (write_words) { 100431fb632bSRamuthevar Vadivel Murugan iowrite32_rep(cqspi->ahb_base, txbuf, write_words); 100531fb632bSRamuthevar Vadivel Murugan txbuf += (write_words * 4); 100631fb632bSRamuthevar Vadivel Murugan } 100731fb632bSRamuthevar Vadivel Murugan if (mod_bytes) { 100831fb632bSRamuthevar Vadivel Murugan unsigned int temp = 0xFFFFFFFF; 100931fb632bSRamuthevar Vadivel Murugan 101031fb632bSRamuthevar Vadivel Murugan memcpy(&temp, txbuf, mod_bytes); 101131fb632bSRamuthevar Vadivel Murugan iowrite32(temp, cqspi->ahb_base); 101231fb632bSRamuthevar Vadivel Murugan txbuf += mod_bytes; 101331fb632bSRamuthevar Vadivel Murugan } 101431fb632bSRamuthevar Vadivel Murugan 101531fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->transfer_complete, 101631fb632bSRamuthevar Vadivel Murugan msecs_to_jiffies(CQSPI_TIMEOUT_MS))) { 101731fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect write timeout\n"); 101831fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 101931fb632bSRamuthevar Vadivel Murugan goto failwr; 102031fb632bSRamuthevar Vadivel Murugan } 102131fb632bSRamuthevar Vadivel Murugan 102231fb632bSRamuthevar Vadivel Murugan remaining -= write_bytes; 102331fb632bSRamuthevar Vadivel Murugan 102431fb632bSRamuthevar Vadivel Murugan if (remaining > 0) 102531fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 102631fb632bSRamuthevar Vadivel Murugan } 102731fb632bSRamuthevar Vadivel Murugan 102831fb632bSRamuthevar Vadivel Murugan /* Check indirect done status */ 102931fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR, 103031fb632bSRamuthevar Vadivel Murugan CQSPI_REG_INDIRECTWR_DONE_MASK, 0); 103131fb632bSRamuthevar Vadivel Murugan if (ret) { 103231fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect write completion error (%i)\n", ret); 103331fb632bSRamuthevar Vadivel Murugan goto failwr; 103431fb632bSRamuthevar Vadivel Murugan } 103531fb632bSRamuthevar Vadivel Murugan 103631fb632bSRamuthevar Vadivel Murugan /* Disable interrupt. */ 103731fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 103831fb632bSRamuthevar Vadivel Murugan 103931fb632bSRamuthevar Vadivel Murugan /* Clear indirect completion status */ 104031fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR); 104131fb632bSRamuthevar Vadivel Murugan 104231fb632bSRamuthevar Vadivel Murugan cqspi_wait_idle(cqspi); 104331fb632bSRamuthevar Vadivel Murugan 104431fb632bSRamuthevar Vadivel Murugan return 0; 104531fb632bSRamuthevar Vadivel Murugan 104631fb632bSRamuthevar Vadivel Murugan failwr: 104731fb632bSRamuthevar Vadivel Murugan /* Disable interrupt. */ 104831fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 104931fb632bSRamuthevar Vadivel Murugan 105031fb632bSRamuthevar Vadivel Murugan /* Cancel the indirect write */ 105131fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 105231fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTWR); 105331fb632bSRamuthevar Vadivel Murugan return ret; 105431fb632bSRamuthevar Vadivel Murugan } 105531fb632bSRamuthevar Vadivel Murugan 105631fb632bSRamuthevar Vadivel Murugan static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata) 105731fb632bSRamuthevar Vadivel Murugan { 105831fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 105931fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 106031fb632bSRamuthevar Vadivel Murugan unsigned int chip_select = f_pdata->cs; 106131fb632bSRamuthevar Vadivel Murugan unsigned int reg; 106231fb632bSRamuthevar Vadivel Murugan 106331fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG); 106431fb632bSRamuthevar Vadivel Murugan if (cqspi->is_decoded_cs) { 106531fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CONFIG_DECODE_MASK; 106631fb632bSRamuthevar Vadivel Murugan } else { 106731fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; 106831fb632bSRamuthevar Vadivel Murugan 106931fb632bSRamuthevar Vadivel Murugan /* Convert CS if without decoder. 107031fb632bSRamuthevar Vadivel Murugan * CS0 to 4b'1110 107131fb632bSRamuthevar Vadivel Murugan * CS1 to 4b'1101 107231fb632bSRamuthevar Vadivel Murugan * CS2 to 4b'1011 107331fb632bSRamuthevar Vadivel Murugan * CS3 to 4b'0111 107431fb632bSRamuthevar Vadivel Murugan */ 107531fb632bSRamuthevar Vadivel Murugan chip_select = 0xF & ~(1 << chip_select); 107631fb632bSRamuthevar Vadivel Murugan } 107731fb632bSRamuthevar Vadivel Murugan 107831fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK 107931fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CONFIG_CHIPSELECT_LSB); 108031fb632bSRamuthevar Vadivel Murugan reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK) 108131fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CONFIG_CHIPSELECT_LSB; 108231fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG); 108331fb632bSRamuthevar Vadivel Murugan } 108431fb632bSRamuthevar Vadivel Murugan 108531fb632bSRamuthevar Vadivel Murugan static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz, 108631fb632bSRamuthevar Vadivel Murugan const unsigned int ns_val) 108731fb632bSRamuthevar Vadivel Murugan { 108831fb632bSRamuthevar Vadivel Murugan unsigned int ticks; 108931fb632bSRamuthevar Vadivel Murugan 109031fb632bSRamuthevar Vadivel Murugan ticks = ref_clk_hz / 1000; /* kHz */ 109131fb632bSRamuthevar Vadivel Murugan ticks = DIV_ROUND_UP(ticks * ns_val, 1000000); 109231fb632bSRamuthevar Vadivel Murugan 109331fb632bSRamuthevar Vadivel Murugan return ticks; 109431fb632bSRamuthevar Vadivel Murugan } 109531fb632bSRamuthevar Vadivel Murugan 109631fb632bSRamuthevar Vadivel Murugan static void cqspi_delay(struct cqspi_flash_pdata *f_pdata) 109731fb632bSRamuthevar Vadivel Murugan { 109831fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 109931fb632bSRamuthevar Vadivel Murugan void __iomem *iobase = cqspi->iobase; 110031fb632bSRamuthevar Vadivel Murugan const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 110131fb632bSRamuthevar Vadivel Murugan unsigned int tshsl, tchsh, tslch, tsd2d; 110231fb632bSRamuthevar Vadivel Murugan unsigned int reg; 110331fb632bSRamuthevar Vadivel Murugan unsigned int tsclk; 110431fb632bSRamuthevar Vadivel Murugan 110531fb632bSRamuthevar Vadivel Murugan /* calculate the number of ref ticks for one sclk tick */ 110631fb632bSRamuthevar Vadivel Murugan tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk); 110731fb632bSRamuthevar Vadivel Murugan 110831fb632bSRamuthevar Vadivel Murugan tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns); 110931fb632bSRamuthevar Vadivel Murugan /* this particular value must be at least one sclk */ 111031fb632bSRamuthevar Vadivel Murugan if (tshsl < tsclk) 111131fb632bSRamuthevar Vadivel Murugan tshsl = tsclk; 111231fb632bSRamuthevar Vadivel Murugan 111331fb632bSRamuthevar Vadivel Murugan tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns); 111431fb632bSRamuthevar Vadivel Murugan tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns); 111531fb632bSRamuthevar Vadivel Murugan tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns); 111631fb632bSRamuthevar Vadivel Murugan 111731fb632bSRamuthevar Vadivel Murugan reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK) 111831fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSHSL_LSB; 111931fb632bSRamuthevar Vadivel Murugan reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK) 112031fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TCHSH_LSB; 112131fb632bSRamuthevar Vadivel Murugan reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK) 112231fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSLCH_LSB; 112331fb632bSRamuthevar Vadivel Murugan reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK) 112431fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSD2D_LSB; 112531fb632bSRamuthevar Vadivel Murugan writel(reg, iobase + CQSPI_REG_DELAY); 112631fb632bSRamuthevar Vadivel Murugan } 112731fb632bSRamuthevar Vadivel Murugan 112831fb632bSRamuthevar Vadivel Murugan static void cqspi_config_baudrate_div(struct cqspi_st *cqspi) 112931fb632bSRamuthevar Vadivel Murugan { 113031fb632bSRamuthevar Vadivel Murugan const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 113131fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 113231fb632bSRamuthevar Vadivel Murugan u32 reg, div; 113331fb632bSRamuthevar Vadivel Murugan 113431fb632bSRamuthevar Vadivel Murugan /* Recalculate the baudrate divisor based on QSPI specification. */ 113531fb632bSRamuthevar Vadivel Murugan div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1; 113631fb632bSRamuthevar Vadivel Murugan 1137f8fc65e5SNathan Barrett-Morrison /* Maximum baud divisor */ 1138f8fc65e5SNathan Barrett-Morrison if (div > CQSPI_REG_CONFIG_BAUD_MASK) { 1139f8fc65e5SNathan Barrett-Morrison div = CQSPI_REG_CONFIG_BAUD_MASK; 1140f8fc65e5SNathan Barrett-Morrison dev_warn(&cqspi->pdev->dev, 1141f8fc65e5SNathan Barrett-Morrison "Unable to adjust clock <= %d hz. Reduced to %d hz\n", 1142f8fc65e5SNathan Barrett-Morrison cqspi->sclk, ref_clk_hz/((div+1)*2)); 1143f8fc65e5SNathan Barrett-Morrison } 1144f8fc65e5SNathan Barrett-Morrison 114531fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG); 114631fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); 114731fb632bSRamuthevar Vadivel Murugan reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB; 114831fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG); 114931fb632bSRamuthevar Vadivel Murugan } 115031fb632bSRamuthevar Vadivel Murugan 115131fb632bSRamuthevar Vadivel Murugan static void cqspi_readdata_capture(struct cqspi_st *cqspi, 115231fb632bSRamuthevar Vadivel Murugan const bool bypass, 115331fb632bSRamuthevar Vadivel Murugan const unsigned int delay) 115431fb632bSRamuthevar Vadivel Murugan { 115531fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 115631fb632bSRamuthevar Vadivel Murugan unsigned int reg; 115731fb632bSRamuthevar Vadivel Murugan 115831fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_READCAPTURE); 115931fb632bSRamuthevar Vadivel Murugan 116031fb632bSRamuthevar Vadivel Murugan if (bypass) 116131fb632bSRamuthevar Vadivel Murugan reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 116231fb632bSRamuthevar Vadivel Murugan else 116331fb632bSRamuthevar Vadivel Murugan reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 116431fb632bSRamuthevar Vadivel Murugan 116531fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK 116631fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_READCAPTURE_DELAY_LSB); 116731fb632bSRamuthevar Vadivel Murugan 116831fb632bSRamuthevar Vadivel Murugan reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK) 116931fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_READCAPTURE_DELAY_LSB; 117031fb632bSRamuthevar Vadivel Murugan 117131fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_READCAPTURE); 117231fb632bSRamuthevar Vadivel Murugan } 117331fb632bSRamuthevar Vadivel Murugan 117431fb632bSRamuthevar Vadivel Murugan static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable) 117531fb632bSRamuthevar Vadivel Murugan { 117631fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 117731fb632bSRamuthevar Vadivel Murugan unsigned int reg; 117831fb632bSRamuthevar Vadivel Murugan 117931fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG); 118031fb632bSRamuthevar Vadivel Murugan 118131fb632bSRamuthevar Vadivel Murugan if (enable) 118231fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CONFIG_ENABLE_MASK; 118331fb632bSRamuthevar Vadivel Murugan else 118431fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; 118531fb632bSRamuthevar Vadivel Murugan 118631fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG); 118731fb632bSRamuthevar Vadivel Murugan } 118831fb632bSRamuthevar Vadivel Murugan 118931fb632bSRamuthevar Vadivel Murugan static void cqspi_configure(struct cqspi_flash_pdata *f_pdata, 119031fb632bSRamuthevar Vadivel Murugan unsigned long sclk) 119131fb632bSRamuthevar Vadivel Murugan { 119231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 119331fb632bSRamuthevar Vadivel Murugan int switch_cs = (cqspi->current_cs != f_pdata->cs); 119431fb632bSRamuthevar Vadivel Murugan int switch_ck = (cqspi->sclk != sclk); 119531fb632bSRamuthevar Vadivel Murugan 119631fb632bSRamuthevar Vadivel Murugan if (switch_cs || switch_ck) 119731fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 119831fb632bSRamuthevar Vadivel Murugan 119931fb632bSRamuthevar Vadivel Murugan /* Switch chip select. */ 120031fb632bSRamuthevar Vadivel Murugan if (switch_cs) { 120131fb632bSRamuthevar Vadivel Murugan cqspi->current_cs = f_pdata->cs; 120231fb632bSRamuthevar Vadivel Murugan cqspi_chipselect(f_pdata); 120331fb632bSRamuthevar Vadivel Murugan } 120431fb632bSRamuthevar Vadivel Murugan 120531fb632bSRamuthevar Vadivel Murugan /* Setup baudrate divisor and delays */ 120631fb632bSRamuthevar Vadivel Murugan if (switch_ck) { 120731fb632bSRamuthevar Vadivel Murugan cqspi->sclk = sclk; 120831fb632bSRamuthevar Vadivel Murugan cqspi_config_baudrate_div(cqspi); 120931fb632bSRamuthevar Vadivel Murugan cqspi_delay(f_pdata); 121031fb632bSRamuthevar Vadivel Murugan cqspi_readdata_capture(cqspi, !cqspi->rclk_en, 121131fb632bSRamuthevar Vadivel Murugan f_pdata->read_delay); 121231fb632bSRamuthevar Vadivel Murugan } 121331fb632bSRamuthevar Vadivel Murugan 121431fb632bSRamuthevar Vadivel Murugan if (switch_cs || switch_ck) 121531fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1); 121631fb632bSRamuthevar Vadivel Murugan } 121731fb632bSRamuthevar Vadivel Murugan 121831fb632bSRamuthevar Vadivel Murugan static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata, 121931fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 122031fb632bSRamuthevar Vadivel Murugan { 122131fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 122231fb632bSRamuthevar Vadivel Murugan loff_t to = op->addr.val; 122331fb632bSRamuthevar Vadivel Murugan size_t len = op->data.nbytes; 122431fb632bSRamuthevar Vadivel Murugan const u_char *buf = op->data.buf.out; 122531fb632bSRamuthevar Vadivel Murugan int ret; 122631fb632bSRamuthevar Vadivel Murugan 122731fb632bSRamuthevar Vadivel Murugan ret = cqspi_write_setup(f_pdata, op); 122831fb632bSRamuthevar Vadivel Murugan if (ret) 122931fb632bSRamuthevar Vadivel Murugan return ret; 123031fb632bSRamuthevar Vadivel Murugan 1231f453f293SPratyush Yadav /* 1232f453f293SPratyush Yadav * Some flashes like the Cypress Semper flash expect a dummy 4-byte 1233f453f293SPratyush Yadav * address (all 0s) with the read status register command in DTR mode. 1234f453f293SPratyush Yadav * But this controller does not support sending dummy address bytes to 1235f453f293SPratyush Yadav * the flash when it is polling the write completion register in DTR 1236f453f293SPratyush Yadav * mode. So, we can not use direct mode when in DTR mode for writing 1237f453f293SPratyush Yadav * data. 1238f453f293SPratyush Yadav */ 123928ac902aSMatthias Schiffer if (!op->cmd.dtr && cqspi->use_direct_mode && 1240*e8c51b16SDhruva Gole cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) { 124131fb632bSRamuthevar Vadivel Murugan memcpy_toio(cqspi->ahb_base + to, buf, len); 124231fb632bSRamuthevar Vadivel Murugan return cqspi_wait_idle(cqspi); 124331fb632bSRamuthevar Vadivel Murugan } 124431fb632bSRamuthevar Vadivel Murugan 124531fb632bSRamuthevar Vadivel Murugan return cqspi_indirect_write_execute(f_pdata, to, buf, len); 124631fb632bSRamuthevar Vadivel Murugan } 124731fb632bSRamuthevar Vadivel Murugan 124831fb632bSRamuthevar Vadivel Murugan static void cqspi_rx_dma_callback(void *param) 124931fb632bSRamuthevar Vadivel Murugan { 125031fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = param; 125131fb632bSRamuthevar Vadivel Murugan 125231fb632bSRamuthevar Vadivel Murugan complete(&cqspi->rx_dma_complete); 125331fb632bSRamuthevar Vadivel Murugan } 125431fb632bSRamuthevar Vadivel Murugan 125531fb632bSRamuthevar Vadivel Murugan static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata, 125631fb632bSRamuthevar Vadivel Murugan u_char *buf, loff_t from, size_t len) 125731fb632bSRamuthevar Vadivel Murugan { 125831fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 125931fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 126031fb632bSRamuthevar Vadivel Murugan enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; 126131fb632bSRamuthevar Vadivel Murugan dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from; 126231fb632bSRamuthevar Vadivel Murugan int ret = 0; 126331fb632bSRamuthevar Vadivel Murugan struct dma_async_tx_descriptor *tx; 126431fb632bSRamuthevar Vadivel Murugan dma_cookie_t cookie; 126531fb632bSRamuthevar Vadivel Murugan dma_addr_t dma_dst; 126683048015SVignesh Raghavendra struct device *ddev; 126731fb632bSRamuthevar Vadivel Murugan 126831fb632bSRamuthevar Vadivel Murugan if (!cqspi->rx_chan || !virt_addr_valid(buf)) { 126931fb632bSRamuthevar Vadivel Murugan memcpy_fromio(buf, cqspi->ahb_base + from, len); 127031fb632bSRamuthevar Vadivel Murugan return 0; 127131fb632bSRamuthevar Vadivel Murugan } 127231fb632bSRamuthevar Vadivel Murugan 127383048015SVignesh Raghavendra ddev = cqspi->rx_chan->device->dev; 127483048015SVignesh Raghavendra dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE); 127583048015SVignesh Raghavendra if (dma_mapping_error(ddev, dma_dst)) { 127631fb632bSRamuthevar Vadivel Murugan dev_err(dev, "dma mapping failed\n"); 127731fb632bSRamuthevar Vadivel Murugan return -ENOMEM; 127831fb632bSRamuthevar Vadivel Murugan } 127931fb632bSRamuthevar Vadivel Murugan tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src, 128031fb632bSRamuthevar Vadivel Murugan len, flags); 128131fb632bSRamuthevar Vadivel Murugan if (!tx) { 128231fb632bSRamuthevar Vadivel Murugan dev_err(dev, "device_prep_dma_memcpy error\n"); 128331fb632bSRamuthevar Vadivel Murugan ret = -EIO; 128431fb632bSRamuthevar Vadivel Murugan goto err_unmap; 128531fb632bSRamuthevar Vadivel Murugan } 128631fb632bSRamuthevar Vadivel Murugan 128731fb632bSRamuthevar Vadivel Murugan tx->callback = cqspi_rx_dma_callback; 128831fb632bSRamuthevar Vadivel Murugan tx->callback_param = cqspi; 128931fb632bSRamuthevar Vadivel Murugan cookie = tx->tx_submit(tx); 129031fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->rx_dma_complete); 129131fb632bSRamuthevar Vadivel Murugan 129231fb632bSRamuthevar Vadivel Murugan ret = dma_submit_error(cookie); 129331fb632bSRamuthevar Vadivel Murugan if (ret) { 129431fb632bSRamuthevar Vadivel Murugan dev_err(dev, "dma_submit_error %d\n", cookie); 129531fb632bSRamuthevar Vadivel Murugan ret = -EIO; 129631fb632bSRamuthevar Vadivel Murugan goto err_unmap; 129731fb632bSRamuthevar Vadivel Murugan } 129831fb632bSRamuthevar Vadivel Murugan 129931fb632bSRamuthevar Vadivel Murugan dma_async_issue_pending(cqspi->rx_chan); 130031fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->rx_dma_complete, 13012ef0170eSPratyush Yadav msecs_to_jiffies(max_t(size_t, len, 500)))) { 130231fb632bSRamuthevar Vadivel Murugan dmaengine_terminate_sync(cqspi->rx_chan); 130331fb632bSRamuthevar Vadivel Murugan dev_err(dev, "DMA wait_for_completion_timeout\n"); 130431fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 130531fb632bSRamuthevar Vadivel Murugan goto err_unmap; 130631fb632bSRamuthevar Vadivel Murugan } 130731fb632bSRamuthevar Vadivel Murugan 130831fb632bSRamuthevar Vadivel Murugan err_unmap: 130983048015SVignesh Raghavendra dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE); 131031fb632bSRamuthevar Vadivel Murugan 131131fb632bSRamuthevar Vadivel Murugan return ret; 131231fb632bSRamuthevar Vadivel Murugan } 131331fb632bSRamuthevar Vadivel Murugan 131431fb632bSRamuthevar Vadivel Murugan static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata, 131531fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 131631fb632bSRamuthevar Vadivel Murugan { 131731fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 13181a6f854fSSai Krishna Potthuri struct device *dev = &cqspi->pdev->dev; 13191a6f854fSSai Krishna Potthuri const struct cqspi_driver_platdata *ddata; 132031fb632bSRamuthevar Vadivel Murugan loff_t from = op->addr.val; 132131fb632bSRamuthevar Vadivel Murugan size_t len = op->data.nbytes; 132231fb632bSRamuthevar Vadivel Murugan u_char *buf = op->data.buf.in; 13231a6f854fSSai Krishna Potthuri u64 dma_align = (u64)(uintptr_t)buf; 132431fb632bSRamuthevar Vadivel Murugan int ret; 132531fb632bSRamuthevar Vadivel Murugan 13261a6f854fSSai Krishna Potthuri ddata = of_device_get_match_data(dev); 132731fb632bSRamuthevar Vadivel Murugan 132831fb632bSRamuthevar Vadivel Murugan ret = cqspi_read_setup(f_pdata, op); 132931fb632bSRamuthevar Vadivel Murugan if (ret) 133031fb632bSRamuthevar Vadivel Murugan return ret; 133131fb632bSRamuthevar Vadivel Murugan 133231fb632bSRamuthevar Vadivel Murugan if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) 133331fb632bSRamuthevar Vadivel Murugan return cqspi_direct_read_execute(f_pdata, buf, from, len); 133431fb632bSRamuthevar Vadivel Murugan 13351a6f854fSSai Krishna Potthuri if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma && 13361a6f854fSSai Krishna Potthuri virt_addr_valid(buf) && ((dma_align & CQSPI_DMA_UNALIGN) == 0)) 13371a6f854fSSai Krishna Potthuri return ddata->indirect_read_dma(f_pdata, buf, from, len); 13381a6f854fSSai Krishna Potthuri 133931fb632bSRamuthevar Vadivel Murugan return cqspi_indirect_read_execute(f_pdata, buf, from, len); 134031fb632bSRamuthevar Vadivel Murugan } 134131fb632bSRamuthevar Vadivel Murugan 134231fb632bSRamuthevar Vadivel Murugan static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op) 134331fb632bSRamuthevar Vadivel Murugan { 134431fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); 134531fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata; 134631fb632bSRamuthevar Vadivel Murugan 134731fb632bSRamuthevar Vadivel Murugan f_pdata = &cqspi->f_pdata[mem->spi->chip_select]; 134831fb632bSRamuthevar Vadivel Murugan cqspi_configure(f_pdata, mem->spi->max_speed_hz); 134931fb632bSRamuthevar Vadivel Murugan 135031fb632bSRamuthevar Vadivel Murugan if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { 135131fb632bSRamuthevar Vadivel Murugan if (!op->addr.nbytes) 135231fb632bSRamuthevar Vadivel Murugan return cqspi_command_read(f_pdata, op); 135331fb632bSRamuthevar Vadivel Murugan 135431fb632bSRamuthevar Vadivel Murugan return cqspi_read(f_pdata, op); 135531fb632bSRamuthevar Vadivel Murugan } 135631fb632bSRamuthevar Vadivel Murugan 135731fb632bSRamuthevar Vadivel Murugan if (!op->addr.nbytes || !op->data.buf.out) 135831fb632bSRamuthevar Vadivel Murugan return cqspi_command_write(f_pdata, op); 135931fb632bSRamuthevar Vadivel Murugan 136031fb632bSRamuthevar Vadivel Murugan return cqspi_write(f_pdata, op); 136131fb632bSRamuthevar Vadivel Murugan } 136231fb632bSRamuthevar Vadivel Murugan 136331fb632bSRamuthevar Vadivel Murugan static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) 136431fb632bSRamuthevar Vadivel Murugan { 136531fb632bSRamuthevar Vadivel Murugan int ret; 136631fb632bSRamuthevar Vadivel Murugan 136731fb632bSRamuthevar Vadivel Murugan ret = cqspi_mem_process(mem, op); 136831fb632bSRamuthevar Vadivel Murugan if (ret) 136931fb632bSRamuthevar Vadivel Murugan dev_err(&mem->spi->dev, "operation failed with %d\n", ret); 137031fb632bSRamuthevar Vadivel Murugan 137131fb632bSRamuthevar Vadivel Murugan return ret; 137231fb632bSRamuthevar Vadivel Murugan } 137331fb632bSRamuthevar Vadivel Murugan 1374a273596bSPratyush Yadav static bool cqspi_supports_mem_op(struct spi_mem *mem, 1375a273596bSPratyush Yadav const struct spi_mem_op *op) 1376a273596bSPratyush Yadav { 1377f453f293SPratyush Yadav bool all_true, all_false; 1378f453f293SPratyush Yadav 13790395be96SApurva Nandan /* 13800395be96SApurva Nandan * op->dummy.dtr is required for converting nbytes into ncycles. 13810395be96SApurva Nandan * Also, don't check the dtr field of the op phase having zero nbytes. 13820395be96SApurva Nandan */ 13830395be96SApurva Nandan all_true = op->cmd.dtr && 13840395be96SApurva Nandan (!op->addr.nbytes || op->addr.dtr) && 13850395be96SApurva Nandan (!op->dummy.nbytes || op->dummy.dtr) && 13860395be96SApurva Nandan (!op->data.nbytes || op->data.dtr); 13870395be96SApurva Nandan 1388f453f293SPratyush Yadav all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && 1389f453f293SPratyush Yadav !op->data.dtr; 1390f453f293SPratyush Yadav 1391f1d388f2SMatthias Schiffer if (all_true) { 1392f1d388f2SMatthias Schiffer /* Right now we only support 8-8-8 DTR mode. */ 1393f1d388f2SMatthias Schiffer if (op->cmd.nbytes && op->cmd.buswidth != 8) 1394f453f293SPratyush Yadav return false; 1395f1d388f2SMatthias Schiffer if (op->addr.nbytes && op->addr.buswidth != 8) 1396f1d388f2SMatthias Schiffer return false; 1397f1d388f2SMatthias Schiffer if (op->data.nbytes && op->data.buswidth != 8) 1398f1d388f2SMatthias Schiffer return false; 13991aeda096SMatthias Schiffer } else if (!all_false) { 1400f1d388f2SMatthias Schiffer /* Mixed DTR modes are not supported. */ 1401f1d388f2SMatthias Schiffer return false; 1402f1d388f2SMatthias Schiffer } 1403f453f293SPratyush Yadav 1404d2275139SPratyush Yadav return spi_mem_default_supports_op(mem, op); 1405a273596bSPratyush Yadav } 1406a273596bSPratyush Yadav 140731fb632bSRamuthevar Vadivel Murugan static int cqspi_of_get_flash_pdata(struct platform_device *pdev, 140831fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata, 140931fb632bSRamuthevar Vadivel Murugan struct device_node *np) 141031fb632bSRamuthevar Vadivel Murugan { 141131fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) { 141231fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine read-delay\n"); 141331fb632bSRamuthevar Vadivel Murugan return -ENXIO; 141431fb632bSRamuthevar Vadivel Murugan } 141531fb632bSRamuthevar Vadivel Murugan 141631fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) { 141731fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tshsl-ns\n"); 141831fb632bSRamuthevar Vadivel Murugan return -ENXIO; 141931fb632bSRamuthevar Vadivel Murugan } 142031fb632bSRamuthevar Vadivel Murugan 142131fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) { 142231fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n"); 142331fb632bSRamuthevar Vadivel Murugan return -ENXIO; 142431fb632bSRamuthevar Vadivel Murugan } 142531fb632bSRamuthevar Vadivel Murugan 142631fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) { 142731fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tchsh-ns\n"); 142831fb632bSRamuthevar Vadivel Murugan return -ENXIO; 142931fb632bSRamuthevar Vadivel Murugan } 143031fb632bSRamuthevar Vadivel Murugan 143131fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) { 143231fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tslch-ns\n"); 143331fb632bSRamuthevar Vadivel Murugan return -ENXIO; 143431fb632bSRamuthevar Vadivel Murugan } 143531fb632bSRamuthevar Vadivel Murugan 143631fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) { 143731fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n"); 143831fb632bSRamuthevar Vadivel Murugan return -ENXIO; 143931fb632bSRamuthevar Vadivel Murugan } 144031fb632bSRamuthevar Vadivel Murugan 144131fb632bSRamuthevar Vadivel Murugan return 0; 144231fb632bSRamuthevar Vadivel Murugan } 144331fb632bSRamuthevar Vadivel Murugan 144431fb632bSRamuthevar Vadivel Murugan static int cqspi_of_get_pdata(struct cqspi_st *cqspi) 144531fb632bSRamuthevar Vadivel Murugan { 144631fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 144731fb632bSRamuthevar Vadivel Murugan struct device_node *np = dev->of_node; 144809e393e3SSai Krishna Potthuri u32 id[2]; 144931fb632bSRamuthevar Vadivel Murugan 145031fb632bSRamuthevar Vadivel Murugan cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); 145131fb632bSRamuthevar Vadivel Murugan 145231fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { 145331fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine fifo-depth\n"); 145431fb632bSRamuthevar Vadivel Murugan return -ENXIO; 145531fb632bSRamuthevar Vadivel Murugan } 145631fb632bSRamuthevar Vadivel Murugan 145731fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) { 145831fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine fifo-width\n"); 145931fb632bSRamuthevar Vadivel Murugan return -ENXIO; 146031fb632bSRamuthevar Vadivel Murugan } 146131fb632bSRamuthevar Vadivel Murugan 146231fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,trigger-address", 146331fb632bSRamuthevar Vadivel Murugan &cqspi->trigger_address)) { 146431fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine trigger-address\n"); 146531fb632bSRamuthevar Vadivel Murugan return -ENXIO; 146631fb632bSRamuthevar Vadivel Murugan } 146731fb632bSRamuthevar Vadivel Murugan 1468b436fb7dSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) 1469b436fb7dSRamuthevar Vadivel Murugan cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT; 1470b436fb7dSRamuthevar Vadivel Murugan 147131fb632bSRamuthevar Vadivel Murugan cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); 147231fb632bSRamuthevar Vadivel Murugan 147309e393e3SSai Krishna Potthuri if (!of_property_read_u32_array(np, "power-domains", id, 147409e393e3SSai Krishna Potthuri ARRAY_SIZE(id))) 147509e393e3SSai Krishna Potthuri cqspi->pd_dev_id = id[1]; 147609e393e3SSai Krishna Potthuri 147731fb632bSRamuthevar Vadivel Murugan return 0; 147831fb632bSRamuthevar Vadivel Murugan } 147931fb632bSRamuthevar Vadivel Murugan 148031fb632bSRamuthevar Vadivel Murugan static void cqspi_controller_init(struct cqspi_st *cqspi) 148131fb632bSRamuthevar Vadivel Murugan { 148231fb632bSRamuthevar Vadivel Murugan u32 reg; 148331fb632bSRamuthevar Vadivel Murugan 148431fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 148531fb632bSRamuthevar Vadivel Murugan 148631fb632bSRamuthevar Vadivel Murugan /* Configure the remap address register, no remap */ 148731fb632bSRamuthevar Vadivel Murugan writel(0, cqspi->iobase + CQSPI_REG_REMAP); 148831fb632bSRamuthevar Vadivel Murugan 148931fb632bSRamuthevar Vadivel Murugan /* Disable all interrupts. */ 149031fb632bSRamuthevar Vadivel Murugan writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); 149131fb632bSRamuthevar Vadivel Murugan 149231fb632bSRamuthevar Vadivel Murugan /* Configure the SRAM split to 1:1 . */ 149331fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); 149431fb632bSRamuthevar Vadivel Murugan 149531fb632bSRamuthevar Vadivel Murugan /* Load indirect trigger address. */ 149631fb632bSRamuthevar Vadivel Murugan writel(cqspi->trigger_address, 149731fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); 149831fb632bSRamuthevar Vadivel Murugan 149931fb632bSRamuthevar Vadivel Murugan /* Program read watermark -- 1/2 of the FIFO. */ 150031fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth * cqspi->fifo_width / 2, 150131fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); 150231fb632bSRamuthevar Vadivel Murugan /* Program write watermark -- 1/8 of the FIFO. */ 150331fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth * cqspi->fifo_width / 8, 150431fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); 150531fb632bSRamuthevar Vadivel Murugan 1506ad2775dcSRamuthevar Vadivel Murugan /* Disable direct access controller */ 1507ad2775dcSRamuthevar Vadivel Murugan if (!cqspi->use_direct_mode) { 150831fb632bSRamuthevar Vadivel Murugan reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 1509ad2775dcSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL; 151031fb632bSRamuthevar Vadivel Murugan writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 1511ad2775dcSRamuthevar Vadivel Murugan } 151231fb632bSRamuthevar Vadivel Murugan 15131a6f854fSSai Krishna Potthuri /* Enable DMA interface */ 15141a6f854fSSai Krishna Potthuri if (cqspi->use_dma_read) { 15151a6f854fSSai Krishna Potthuri reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 15161a6f854fSSai Krishna Potthuri reg |= CQSPI_REG_CONFIG_DMA_MASK; 15171a6f854fSSai Krishna Potthuri writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 15181a6f854fSSai Krishna Potthuri } 15191a6f854fSSai Krishna Potthuri 152031fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1); 152131fb632bSRamuthevar Vadivel Murugan } 152231fb632bSRamuthevar Vadivel Murugan 152331fb632bSRamuthevar Vadivel Murugan static int cqspi_request_mmap_dma(struct cqspi_st *cqspi) 152431fb632bSRamuthevar Vadivel Murugan { 152531fb632bSRamuthevar Vadivel Murugan dma_cap_mask_t mask; 152631fb632bSRamuthevar Vadivel Murugan 152731fb632bSRamuthevar Vadivel Murugan dma_cap_zero(mask); 152831fb632bSRamuthevar Vadivel Murugan dma_cap_set(DMA_MEMCPY, mask); 152931fb632bSRamuthevar Vadivel Murugan 153031fb632bSRamuthevar Vadivel Murugan cqspi->rx_chan = dma_request_chan_by_mask(&mask); 153131fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->rx_chan)) { 153231fb632bSRamuthevar Vadivel Murugan int ret = PTR_ERR(cqspi->rx_chan); 153376159e2fSIan Abbott 153431fb632bSRamuthevar Vadivel Murugan cqspi->rx_chan = NULL; 1535436a5c20SKrzysztof Kozlowski return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n"); 153631fb632bSRamuthevar Vadivel Murugan } 153731fb632bSRamuthevar Vadivel Murugan init_completion(&cqspi->rx_dma_complete); 153831fb632bSRamuthevar Vadivel Murugan 153931fb632bSRamuthevar Vadivel Murugan return 0; 154031fb632bSRamuthevar Vadivel Murugan } 154131fb632bSRamuthevar Vadivel Murugan 15422ea370a9SVignesh Raghavendra static const char *cqspi_get_name(struct spi_mem *mem) 15432ea370a9SVignesh Raghavendra { 15442ea370a9SVignesh Raghavendra struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); 15452ea370a9SVignesh Raghavendra struct device *dev = &cqspi->pdev->dev; 15462ea370a9SVignesh Raghavendra 15472ea370a9SVignesh Raghavendra return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select); 15482ea370a9SVignesh Raghavendra } 15492ea370a9SVignesh Raghavendra 155031fb632bSRamuthevar Vadivel Murugan static const struct spi_controller_mem_ops cqspi_mem_ops = { 155131fb632bSRamuthevar Vadivel Murugan .exec_op = cqspi_exec_mem_op, 15522ea370a9SVignesh Raghavendra .get_name = cqspi_get_name, 1553a273596bSPratyush Yadav .supports_op = cqspi_supports_mem_op, 155431fb632bSRamuthevar Vadivel Murugan }; 155531fb632bSRamuthevar Vadivel Murugan 1556a9be4549SMiquel Raynal static const struct spi_controller_mem_caps cqspi_mem_caps = { 1557a9be4549SMiquel Raynal .dtr = true, 1558a9be4549SMiquel Raynal }; 1559a9be4549SMiquel Raynal 156031fb632bSRamuthevar Vadivel Murugan static int cqspi_setup_flash(struct cqspi_st *cqspi) 156131fb632bSRamuthevar Vadivel Murugan { 156231fb632bSRamuthevar Vadivel Murugan struct platform_device *pdev = cqspi->pdev; 156331fb632bSRamuthevar Vadivel Murugan struct device *dev = &pdev->dev; 156431fb632bSRamuthevar Vadivel Murugan struct device_node *np = dev->of_node; 156531fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata; 156631fb632bSRamuthevar Vadivel Murugan unsigned int cs; 156731fb632bSRamuthevar Vadivel Murugan int ret; 156831fb632bSRamuthevar Vadivel Murugan 156931fb632bSRamuthevar Vadivel Murugan /* Get flash device data */ 157031fb632bSRamuthevar Vadivel Murugan for_each_available_child_of_node(dev->of_node, np) { 157131fb632bSRamuthevar Vadivel Murugan ret = of_property_read_u32(np, "reg", &cs); 157231fb632bSRamuthevar Vadivel Murugan if (ret) { 157331fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Couldn't determine chip select.\n"); 157487d62d8fSJunlin Yang of_node_put(np); 157531fb632bSRamuthevar Vadivel Murugan return ret; 157631fb632bSRamuthevar Vadivel Murugan } 157731fb632bSRamuthevar Vadivel Murugan 157831fb632bSRamuthevar Vadivel Murugan if (cs >= CQSPI_MAX_CHIPSELECT) { 157931fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Chip select %d out of range.\n", cs); 158087d62d8fSJunlin Yang of_node_put(np); 158131fb632bSRamuthevar Vadivel Murugan return -EINVAL; 158231fb632bSRamuthevar Vadivel Murugan } 158331fb632bSRamuthevar Vadivel Murugan 158431fb632bSRamuthevar Vadivel Murugan f_pdata = &cqspi->f_pdata[cs]; 158531fb632bSRamuthevar Vadivel Murugan f_pdata->cqspi = cqspi; 158631fb632bSRamuthevar Vadivel Murugan f_pdata->cs = cs; 158731fb632bSRamuthevar Vadivel Murugan 158831fb632bSRamuthevar Vadivel Murugan ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np); 158987d62d8fSJunlin Yang if (ret) { 159087d62d8fSJunlin Yang of_node_put(np); 159131fb632bSRamuthevar Vadivel Murugan return ret; 159231fb632bSRamuthevar Vadivel Murugan } 159387d62d8fSJunlin Yang } 159431fb632bSRamuthevar Vadivel Murugan 159531fb632bSRamuthevar Vadivel Murugan return 0; 159631fb632bSRamuthevar Vadivel Murugan } 159731fb632bSRamuthevar Vadivel Murugan 159831fb632bSRamuthevar Vadivel Murugan static int cqspi_probe(struct platform_device *pdev) 159931fb632bSRamuthevar Vadivel Murugan { 160031fb632bSRamuthevar Vadivel Murugan const struct cqspi_driver_platdata *ddata; 160131fb632bSRamuthevar Vadivel Murugan struct reset_control *rstc, *rstc_ocp; 160231fb632bSRamuthevar Vadivel Murugan struct device *dev = &pdev->dev; 160331fb632bSRamuthevar Vadivel Murugan struct spi_master *master; 160431fb632bSRamuthevar Vadivel Murugan struct resource *res_ahb; 160531fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi; 160631fb632bSRamuthevar Vadivel Murugan int ret; 160731fb632bSRamuthevar Vadivel Murugan int irq; 160831fb632bSRamuthevar Vadivel Murugan 1609606e5d40SVaishnav Achath master = devm_spi_alloc_master(&pdev->dev, sizeof(*cqspi)); 161031fb632bSRamuthevar Vadivel Murugan if (!master) { 161131fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "spi_alloc_master failed\n"); 161231fb632bSRamuthevar Vadivel Murugan return -ENOMEM; 161331fb632bSRamuthevar Vadivel Murugan } 161431fb632bSRamuthevar Vadivel Murugan master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; 161531fb632bSRamuthevar Vadivel Murugan master->mem_ops = &cqspi_mem_ops; 1616a9be4549SMiquel Raynal master->mem_caps = &cqspi_mem_caps; 161731fb632bSRamuthevar Vadivel Murugan master->dev.of_node = pdev->dev.of_node; 161831fb632bSRamuthevar Vadivel Murugan 161931fb632bSRamuthevar Vadivel Murugan cqspi = spi_master_get_devdata(master); 162031fb632bSRamuthevar Vadivel Murugan 162131fb632bSRamuthevar Vadivel Murugan cqspi->pdev = pdev; 1622606e5d40SVaishnav Achath cqspi->master = master; 1623ea94191eSMeng Li platform_set_drvdata(pdev, cqspi); 162431fb632bSRamuthevar Vadivel Murugan 162531fb632bSRamuthevar Vadivel Murugan /* Obtain configuration from OF. */ 162631fb632bSRamuthevar Vadivel Murugan ret = cqspi_of_get_pdata(cqspi); 162731fb632bSRamuthevar Vadivel Murugan if (ret) { 162831fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get mandatory OF data.\n"); 162973d5fe04SVaishnav Achath return -ENODEV; 163031fb632bSRamuthevar Vadivel Murugan } 163131fb632bSRamuthevar Vadivel Murugan 163231fb632bSRamuthevar Vadivel Murugan /* Obtain QSPI clock. */ 163331fb632bSRamuthevar Vadivel Murugan cqspi->clk = devm_clk_get(dev, NULL); 163431fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->clk)) { 163531fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot claim QSPI clock.\n"); 163631fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->clk); 163773d5fe04SVaishnav Achath return ret; 163831fb632bSRamuthevar Vadivel Murugan } 163931fb632bSRamuthevar Vadivel Murugan 164031fb632bSRamuthevar Vadivel Murugan /* Obtain and remap controller address. */ 16414e12ef2bSYang Yingliang cqspi->iobase = devm_platform_ioremap_resource(pdev, 0); 164231fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->iobase)) { 164331fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot remap controller address.\n"); 164431fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->iobase); 164573d5fe04SVaishnav Achath return ret; 164631fb632bSRamuthevar Vadivel Murugan } 164731fb632bSRamuthevar Vadivel Murugan 164831fb632bSRamuthevar Vadivel Murugan /* Obtain and remap AHB address. */ 16494e12ef2bSYang Yingliang cqspi->ahb_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res_ahb); 165031fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->ahb_base)) { 165131fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot remap AHB address.\n"); 165231fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->ahb_base); 165373d5fe04SVaishnav Achath return ret; 165431fb632bSRamuthevar Vadivel Murugan } 165531fb632bSRamuthevar Vadivel Murugan cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start; 165631fb632bSRamuthevar Vadivel Murugan cqspi->ahb_size = resource_size(res_ahb); 165731fb632bSRamuthevar Vadivel Murugan 165831fb632bSRamuthevar Vadivel Murugan init_completion(&cqspi->transfer_complete); 165931fb632bSRamuthevar Vadivel Murugan 166031fb632bSRamuthevar Vadivel Murugan /* Obtain IRQ line. */ 166131fb632bSRamuthevar Vadivel Murugan irq = platform_get_irq(pdev, 0); 166273d5fe04SVaishnav Achath if (irq < 0) 166373d5fe04SVaishnav Achath return -ENXIO; 166431fb632bSRamuthevar Vadivel Murugan 166531fb632bSRamuthevar Vadivel Murugan pm_runtime_enable(dev); 1666b7be05d5SMinghao Chi ret = pm_runtime_resume_and_get(dev); 1667b7be05d5SMinghao Chi if (ret < 0) 16684d0ef0a1SZhang Qilong goto probe_pm_failed; 166931fb632bSRamuthevar Vadivel Murugan 167031fb632bSRamuthevar Vadivel Murugan ret = clk_prepare_enable(cqspi->clk); 167131fb632bSRamuthevar Vadivel Murugan if (ret) { 167231fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot enable QSPI clock.\n"); 167331fb632bSRamuthevar Vadivel Murugan goto probe_clk_failed; 167431fb632bSRamuthevar Vadivel Murugan } 167531fb632bSRamuthevar Vadivel Murugan 167631fb632bSRamuthevar Vadivel Murugan /* Obtain QSPI reset control */ 167731fb632bSRamuthevar Vadivel Murugan rstc = devm_reset_control_get_optional_exclusive(dev, "qspi"); 167831fb632bSRamuthevar Vadivel Murugan if (IS_ERR(rstc)) { 1679ac9978fcSZhihao Cheng ret = PTR_ERR(rstc); 168031fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get QSPI reset.\n"); 168131fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 168231fb632bSRamuthevar Vadivel Murugan } 168331fb632bSRamuthevar Vadivel Murugan 168431fb632bSRamuthevar Vadivel Murugan rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); 168531fb632bSRamuthevar Vadivel Murugan if (IS_ERR(rstc_ocp)) { 1686ac9978fcSZhihao Cheng ret = PTR_ERR(rstc_ocp); 168731fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get QSPI OCP reset.\n"); 168831fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 168931fb632bSRamuthevar Vadivel Murugan } 169031fb632bSRamuthevar Vadivel Murugan 169131fb632bSRamuthevar Vadivel Murugan reset_control_assert(rstc); 169231fb632bSRamuthevar Vadivel Murugan reset_control_deassert(rstc); 169331fb632bSRamuthevar Vadivel Murugan 169431fb632bSRamuthevar Vadivel Murugan reset_control_assert(rstc_ocp); 169531fb632bSRamuthevar Vadivel Murugan reset_control_deassert(rstc_ocp); 169631fb632bSRamuthevar Vadivel Murugan 169731fb632bSRamuthevar Vadivel Murugan cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); 16983a5c09c8SPratyush Yadav master->max_speed_hz = cqspi->master_ref_clk_hz; 169998d948ebSDinh Nguyen 170098d948ebSDinh Nguyen /* write completion is supported by default */ 170198d948ebSDinh Nguyen cqspi->wr_completion = true; 170298d948ebSDinh Nguyen 170331fb632bSRamuthevar Vadivel Murugan ddata = of_device_get_match_data(dev); 170431fb632bSRamuthevar Vadivel Murugan if (ddata) { 170531fb632bSRamuthevar Vadivel Murugan if (ddata->quirks & CQSPI_NEEDS_WR_DELAY) 1706f453f293SPratyush Yadav cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, 170731fb632bSRamuthevar Vadivel Murugan cqspi->master_ref_clk_hz); 170831fb632bSRamuthevar Vadivel Murugan if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL) 1709f453f293SPratyush Yadav master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; 1710*e8c51b16SDhruva Gole if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) { 171131fb632bSRamuthevar Vadivel Murugan cqspi->use_direct_mode = true; 1712*e8c51b16SDhruva Gole cqspi->use_direct_mode_wr = true; 1713*e8c51b16SDhruva Gole } 17141a6f854fSSai Krishna Potthuri if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA) 17151a6f854fSSai Krishna Potthuri cqspi->use_dma_read = true; 171698d948ebSDinh Nguyen if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION) 171798d948ebSDinh Nguyen cqspi->wr_completion = false; 17189ee5b6d5SNiravkumar L Rabara if (ddata->quirks & CQSPI_SLOW_SRAM) 17199ee5b6d5SNiravkumar L Rabara cqspi->slow_sram = true; 17201a6f854fSSai Krishna Potthuri 172109e393e3SSai Krishna Potthuri if (of_device_is_compatible(pdev->dev.of_node, 17221a6f854fSSai Krishna Potthuri "xlnx,versal-ospi-1.0")) 17231a6f854fSSai Krishna Potthuri dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); 172431fb632bSRamuthevar Vadivel Murugan } 172531fb632bSRamuthevar Vadivel Murugan 172631fb632bSRamuthevar Vadivel Murugan ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0, 172731fb632bSRamuthevar Vadivel Murugan pdev->name, cqspi); 172831fb632bSRamuthevar Vadivel Murugan if (ret) { 172931fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot request IRQ.\n"); 173031fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 173131fb632bSRamuthevar Vadivel Murugan } 173231fb632bSRamuthevar Vadivel Murugan 173331fb632bSRamuthevar Vadivel Murugan cqspi_wait_idle(cqspi); 173431fb632bSRamuthevar Vadivel Murugan cqspi_controller_init(cqspi); 173531fb632bSRamuthevar Vadivel Murugan cqspi->current_cs = -1; 173631fb632bSRamuthevar Vadivel Murugan cqspi->sclk = 0; 173731fb632bSRamuthevar Vadivel Murugan 1738b436fb7dSRamuthevar Vadivel Murugan master->num_chipselect = cqspi->num_chipselect; 1739b436fb7dSRamuthevar Vadivel Murugan 174031fb632bSRamuthevar Vadivel Murugan ret = cqspi_setup_flash(cqspi); 174131fb632bSRamuthevar Vadivel Murugan if (ret) { 174231fb632bSRamuthevar Vadivel Murugan dev_err(dev, "failed to setup flash parameters %d\n", ret); 174331fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 174431fb632bSRamuthevar Vadivel Murugan } 174531fb632bSRamuthevar Vadivel Murugan 174631fb632bSRamuthevar Vadivel Murugan if (cqspi->use_direct_mode) { 174731fb632bSRamuthevar Vadivel Murugan ret = cqspi_request_mmap_dma(cqspi); 174831fb632bSRamuthevar Vadivel Murugan if (ret == -EPROBE_DEFER) 174931fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 175031fb632bSRamuthevar Vadivel Murugan } 175131fb632bSRamuthevar Vadivel Murugan 1752606e5d40SVaishnav Achath ret = spi_register_master(master); 175331fb632bSRamuthevar Vadivel Murugan if (ret) { 175431fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret); 175531fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 175631fb632bSRamuthevar Vadivel Murugan } 175731fb632bSRamuthevar Vadivel Murugan 175831fb632bSRamuthevar Vadivel Murugan return 0; 175931fb632bSRamuthevar Vadivel Murugan probe_setup_failed: 176031fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 176131fb632bSRamuthevar Vadivel Murugan probe_reset_failed: 176231fb632bSRamuthevar Vadivel Murugan clk_disable_unprepare(cqspi->clk); 176331fb632bSRamuthevar Vadivel Murugan probe_clk_failed: 176431fb632bSRamuthevar Vadivel Murugan pm_runtime_put_sync(dev); 17654d0ef0a1SZhang Qilong probe_pm_failed: 176631fb632bSRamuthevar Vadivel Murugan pm_runtime_disable(dev); 176731fb632bSRamuthevar Vadivel Murugan return ret; 176831fb632bSRamuthevar Vadivel Murugan } 176931fb632bSRamuthevar Vadivel Murugan 177031fb632bSRamuthevar Vadivel Murugan static int cqspi_remove(struct platform_device *pdev) 177131fb632bSRamuthevar Vadivel Murugan { 177231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = platform_get_drvdata(pdev); 177331fb632bSRamuthevar Vadivel Murugan 1774606e5d40SVaishnav Achath spi_unregister_master(cqspi->master); 177531fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 177631fb632bSRamuthevar Vadivel Murugan 177731fb632bSRamuthevar Vadivel Murugan if (cqspi->rx_chan) 177831fb632bSRamuthevar Vadivel Murugan dma_release_channel(cqspi->rx_chan); 177931fb632bSRamuthevar Vadivel Murugan 178031fb632bSRamuthevar Vadivel Murugan clk_disable_unprepare(cqspi->clk); 178131fb632bSRamuthevar Vadivel Murugan 178231fb632bSRamuthevar Vadivel Murugan pm_runtime_put_sync(&pdev->dev); 178331fb632bSRamuthevar Vadivel Murugan pm_runtime_disable(&pdev->dev); 178431fb632bSRamuthevar Vadivel Murugan 178531fb632bSRamuthevar Vadivel Murugan return 0; 178631fb632bSRamuthevar Vadivel Murugan } 178731fb632bSRamuthevar Vadivel Murugan 178831fb632bSRamuthevar Vadivel Murugan #ifdef CONFIG_PM_SLEEP 178931fb632bSRamuthevar Vadivel Murugan static int cqspi_suspend(struct device *dev) 179031fb632bSRamuthevar Vadivel Murugan { 179131fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev_get_drvdata(dev); 179231fb632bSRamuthevar Vadivel Murugan 179331fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 179431fb632bSRamuthevar Vadivel Murugan return 0; 179531fb632bSRamuthevar Vadivel Murugan } 179631fb632bSRamuthevar Vadivel Murugan 179731fb632bSRamuthevar Vadivel Murugan static int cqspi_resume(struct device *dev) 179831fb632bSRamuthevar Vadivel Murugan { 179931fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev_get_drvdata(dev); 180031fb632bSRamuthevar Vadivel Murugan 180131fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1); 180231fb632bSRamuthevar Vadivel Murugan return 0; 180331fb632bSRamuthevar Vadivel Murugan } 180431fb632bSRamuthevar Vadivel Murugan 180531fb632bSRamuthevar Vadivel Murugan static const struct dev_pm_ops cqspi__dev_pm_ops = { 180631fb632bSRamuthevar Vadivel Murugan .suspend = cqspi_suspend, 180731fb632bSRamuthevar Vadivel Murugan .resume = cqspi_resume, 180831fb632bSRamuthevar Vadivel Murugan }; 180931fb632bSRamuthevar Vadivel Murugan 181031fb632bSRamuthevar Vadivel Murugan #define CQSPI_DEV_PM_OPS (&cqspi__dev_pm_ops) 181131fb632bSRamuthevar Vadivel Murugan #else 181231fb632bSRamuthevar Vadivel Murugan #define CQSPI_DEV_PM_OPS NULL 181331fb632bSRamuthevar Vadivel Murugan #endif 181431fb632bSRamuthevar Vadivel Murugan 181531fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata cdns_qspi = { 181631fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_DISABLE_DAC_MODE, 181731fb632bSRamuthevar Vadivel Murugan }; 181831fb632bSRamuthevar Vadivel Murugan 181931fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata k2g_qspi = { 182031fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_NEEDS_WR_DELAY, 182131fb632bSRamuthevar Vadivel Murugan }; 182231fb632bSRamuthevar Vadivel Murugan 182331fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata am654_ospi = { 182431fb632bSRamuthevar Vadivel Murugan .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 182531fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_NEEDS_WR_DELAY, 182631fb632bSRamuthevar Vadivel Murugan }; 182731fb632bSRamuthevar Vadivel Murugan 1828ad2775dcSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata intel_lgm_qspi = { 1829ad2775dcSRamuthevar Vadivel Murugan .quirks = CQSPI_DISABLE_DAC_MODE, 1830ad2775dcSRamuthevar Vadivel Murugan }; 1831ad2775dcSRamuthevar Vadivel Murugan 183298d948ebSDinh Nguyen static const struct cqspi_driver_platdata socfpga_qspi = { 18339ee5b6d5SNiravkumar L Rabara .quirks = CQSPI_DISABLE_DAC_MODE 18349ee5b6d5SNiravkumar L Rabara | CQSPI_NO_SUPPORT_WR_COMPLETION 18359ee5b6d5SNiravkumar L Rabara | CQSPI_SLOW_SRAM, 183698d948ebSDinh Nguyen }; 183798d948ebSDinh Nguyen 183809e393e3SSai Krishna Potthuri static const struct cqspi_driver_platdata versal_ospi = { 183909e393e3SSai Krishna Potthuri .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 18401a6f854fSSai Krishna Potthuri .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA, 18411a6f854fSSai Krishna Potthuri .indirect_read_dma = cqspi_versal_indirect_read_dma, 18421a6f854fSSai Krishna Potthuri .get_dma_status = cqspi_get_versal_dma_status, 184309e393e3SSai Krishna Potthuri }; 184409e393e3SSai Krishna Potthuri 184531fb632bSRamuthevar Vadivel Murugan static const struct of_device_id cqspi_dt_ids[] = { 184631fb632bSRamuthevar Vadivel Murugan { 184731fb632bSRamuthevar Vadivel Murugan .compatible = "cdns,qspi-nor", 184831fb632bSRamuthevar Vadivel Murugan .data = &cdns_qspi, 184931fb632bSRamuthevar Vadivel Murugan }, 185031fb632bSRamuthevar Vadivel Murugan { 185131fb632bSRamuthevar Vadivel Murugan .compatible = "ti,k2g-qspi", 185231fb632bSRamuthevar Vadivel Murugan .data = &k2g_qspi, 185331fb632bSRamuthevar Vadivel Murugan }, 185431fb632bSRamuthevar Vadivel Murugan { 185531fb632bSRamuthevar Vadivel Murugan .compatible = "ti,am654-ospi", 185631fb632bSRamuthevar Vadivel Murugan .data = &am654_ospi, 185731fb632bSRamuthevar Vadivel Murugan }, 1858ab2d2875SRamuthevar Vadivel Murugan { 1859ab2d2875SRamuthevar Vadivel Murugan .compatible = "intel,lgm-qspi", 1860ad2775dcSRamuthevar Vadivel Murugan .data = &intel_lgm_qspi, 1861ab2d2875SRamuthevar Vadivel Murugan }, 186209e393e3SSai Krishna Potthuri { 186309e393e3SSai Krishna Potthuri .compatible = "xlnx,versal-ospi-1.0", 18640d868829SIan Abbott .data = &versal_ospi, 186509e393e3SSai Krishna Potthuri }, 186698d948ebSDinh Nguyen { 186798d948ebSDinh Nguyen .compatible = "intel,socfpga-qspi", 18680d868829SIan Abbott .data = &socfpga_qspi, 186998d948ebSDinh Nguyen }, 187031fb632bSRamuthevar Vadivel Murugan { /* end of table */ } 187131fb632bSRamuthevar Vadivel Murugan }; 187231fb632bSRamuthevar Vadivel Murugan 187331fb632bSRamuthevar Vadivel Murugan MODULE_DEVICE_TABLE(of, cqspi_dt_ids); 187431fb632bSRamuthevar Vadivel Murugan 187531fb632bSRamuthevar Vadivel Murugan static struct platform_driver cqspi_platform_driver = { 187631fb632bSRamuthevar Vadivel Murugan .probe = cqspi_probe, 187731fb632bSRamuthevar Vadivel Murugan .remove = cqspi_remove, 187831fb632bSRamuthevar Vadivel Murugan .driver = { 187931fb632bSRamuthevar Vadivel Murugan .name = CQSPI_NAME, 188031fb632bSRamuthevar Vadivel Murugan .pm = CQSPI_DEV_PM_OPS, 188131fb632bSRamuthevar Vadivel Murugan .of_match_table = cqspi_dt_ids, 188231fb632bSRamuthevar Vadivel Murugan }, 188331fb632bSRamuthevar Vadivel Murugan }; 188431fb632bSRamuthevar Vadivel Murugan 188531fb632bSRamuthevar Vadivel Murugan module_platform_driver(cqspi_platform_driver); 188631fb632bSRamuthevar Vadivel Murugan 188731fb632bSRamuthevar Vadivel Murugan MODULE_DESCRIPTION("Cadence QSPI Controller Driver"); 188831fb632bSRamuthevar Vadivel Murugan MODULE_LICENSE("GPL v2"); 188931fb632bSRamuthevar Vadivel Murugan MODULE_ALIAS("platform:" CQSPI_NAME); 189031fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>"); 189131fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>"); 189231fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>"); 189331fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>"); 1894f453f293SPratyush Yadav MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>"); 1895