131fb632bSRamuthevar Vadivel Murugan // SPDX-License-Identifier: GPL-2.0-only 231fb632bSRamuthevar Vadivel Murugan // 331fb632bSRamuthevar Vadivel Murugan // Driver for Cadence QSPI Controller 431fb632bSRamuthevar Vadivel Murugan // 531fb632bSRamuthevar Vadivel Murugan // Copyright Altera Corporation (C) 2012-2014. All rights reserved. 631fb632bSRamuthevar Vadivel Murugan // Copyright Intel Corporation (C) 2019-2020. All rights reserved. 731fb632bSRamuthevar Vadivel Murugan // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 831fb632bSRamuthevar Vadivel Murugan 931fb632bSRamuthevar Vadivel Murugan #include <linux/clk.h> 1031fb632bSRamuthevar Vadivel Murugan #include <linux/completion.h> 1131fb632bSRamuthevar Vadivel Murugan #include <linux/delay.h> 1231fb632bSRamuthevar Vadivel Murugan #include <linux/dma-mapping.h> 1331fb632bSRamuthevar Vadivel Murugan #include <linux/dmaengine.h> 1431fb632bSRamuthevar Vadivel Murugan #include <linux/err.h> 1531fb632bSRamuthevar Vadivel Murugan #include <linux/errno.h> 1631fb632bSRamuthevar Vadivel Murugan #include <linux/interrupt.h> 1731fb632bSRamuthevar Vadivel Murugan #include <linux/io.h> 1831fb632bSRamuthevar Vadivel Murugan #include <linux/iopoll.h> 1931fb632bSRamuthevar Vadivel Murugan #include <linux/jiffies.h> 2031fb632bSRamuthevar Vadivel Murugan #include <linux/kernel.h> 2131fb632bSRamuthevar Vadivel Murugan #include <linux/module.h> 2231fb632bSRamuthevar Vadivel Murugan #include <linux/of_device.h> 2331fb632bSRamuthevar Vadivel Murugan #include <linux/of.h> 2431fb632bSRamuthevar Vadivel Murugan #include <linux/platform_device.h> 2531fb632bSRamuthevar Vadivel Murugan #include <linux/pm_runtime.h> 2631fb632bSRamuthevar Vadivel Murugan #include <linux/reset.h> 2731fb632bSRamuthevar Vadivel Murugan #include <linux/sched.h> 2831fb632bSRamuthevar Vadivel Murugan #include <linux/spi/spi.h> 2931fb632bSRamuthevar Vadivel Murugan #include <linux/spi/spi-mem.h> 3031fb632bSRamuthevar Vadivel Murugan #include <linux/timer.h> 3131fb632bSRamuthevar Vadivel Murugan 3231fb632bSRamuthevar Vadivel Murugan #define CQSPI_NAME "cadence-qspi" 3331fb632bSRamuthevar Vadivel Murugan #define CQSPI_MAX_CHIPSELECT 16 3431fb632bSRamuthevar Vadivel Murugan 3531fb632bSRamuthevar Vadivel Murugan /* Quirks */ 3631fb632bSRamuthevar Vadivel Murugan #define CQSPI_NEEDS_WR_DELAY BIT(0) 3731fb632bSRamuthevar Vadivel Murugan #define CQSPI_DISABLE_DAC_MODE BIT(1) 3831fb632bSRamuthevar Vadivel Murugan 3931fb632bSRamuthevar Vadivel Murugan /* Capabilities */ 4031fb632bSRamuthevar Vadivel Murugan #define CQSPI_SUPPORTS_OCTAL BIT(0) 4131fb632bSRamuthevar Vadivel Murugan 4231fb632bSRamuthevar Vadivel Murugan struct cqspi_st; 4331fb632bSRamuthevar Vadivel Murugan 4431fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata { 4531fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi; 4631fb632bSRamuthevar Vadivel Murugan u32 clk_rate; 4731fb632bSRamuthevar Vadivel Murugan u32 read_delay; 4831fb632bSRamuthevar Vadivel Murugan u32 tshsl_ns; 4931fb632bSRamuthevar Vadivel Murugan u32 tsd2d_ns; 5031fb632bSRamuthevar Vadivel Murugan u32 tchsh_ns; 5131fb632bSRamuthevar Vadivel Murugan u32 tslch_ns; 5231fb632bSRamuthevar Vadivel Murugan u8 inst_width; 5331fb632bSRamuthevar Vadivel Murugan u8 addr_width; 5431fb632bSRamuthevar Vadivel Murugan u8 data_width; 5531fb632bSRamuthevar Vadivel Murugan u8 cs; 5631fb632bSRamuthevar Vadivel Murugan }; 5731fb632bSRamuthevar Vadivel Murugan 5831fb632bSRamuthevar Vadivel Murugan struct cqspi_st { 5931fb632bSRamuthevar Vadivel Murugan struct platform_device *pdev; 6031fb632bSRamuthevar Vadivel Murugan 6131fb632bSRamuthevar Vadivel Murugan struct clk *clk; 6231fb632bSRamuthevar Vadivel Murugan unsigned int sclk; 6331fb632bSRamuthevar Vadivel Murugan 6431fb632bSRamuthevar Vadivel Murugan void __iomem *iobase; 6531fb632bSRamuthevar Vadivel Murugan void __iomem *ahb_base; 6631fb632bSRamuthevar Vadivel Murugan resource_size_t ahb_size; 6731fb632bSRamuthevar Vadivel Murugan struct completion transfer_complete; 6831fb632bSRamuthevar Vadivel Murugan 6931fb632bSRamuthevar Vadivel Murugan struct dma_chan *rx_chan; 7031fb632bSRamuthevar Vadivel Murugan struct completion rx_dma_complete; 7131fb632bSRamuthevar Vadivel Murugan dma_addr_t mmap_phys_base; 7231fb632bSRamuthevar Vadivel Murugan 7331fb632bSRamuthevar Vadivel Murugan int current_cs; 7431fb632bSRamuthevar Vadivel Murugan unsigned long master_ref_clk_hz; 7531fb632bSRamuthevar Vadivel Murugan bool is_decoded_cs; 7631fb632bSRamuthevar Vadivel Murugan u32 fifo_depth; 7731fb632bSRamuthevar Vadivel Murugan u32 fifo_width; 7831fb632bSRamuthevar Vadivel Murugan bool rclk_en; 7931fb632bSRamuthevar Vadivel Murugan u32 trigger_address; 8031fb632bSRamuthevar Vadivel Murugan u32 wr_delay; 8131fb632bSRamuthevar Vadivel Murugan bool use_direct_mode; 8231fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; 8331fb632bSRamuthevar Vadivel Murugan }; 8431fb632bSRamuthevar Vadivel Murugan 8531fb632bSRamuthevar Vadivel Murugan struct cqspi_driver_platdata { 8631fb632bSRamuthevar Vadivel Murugan u32 hwcaps_mask; 8731fb632bSRamuthevar Vadivel Murugan u8 quirks; 8831fb632bSRamuthevar Vadivel Murugan }; 8931fb632bSRamuthevar Vadivel Murugan 9031fb632bSRamuthevar Vadivel Murugan /* Operation timeout value */ 9131fb632bSRamuthevar Vadivel Murugan #define CQSPI_TIMEOUT_MS 500 9231fb632bSRamuthevar Vadivel Murugan #define CQSPI_READ_TIMEOUT_MS 10 9331fb632bSRamuthevar Vadivel Murugan 9431fb632bSRamuthevar Vadivel Murugan /* Instruction type */ 9531fb632bSRamuthevar Vadivel Murugan #define CQSPI_INST_TYPE_SINGLE 0 9631fb632bSRamuthevar Vadivel Murugan #define CQSPI_INST_TYPE_DUAL 1 9731fb632bSRamuthevar Vadivel Murugan #define CQSPI_INST_TYPE_QUAD 2 9831fb632bSRamuthevar Vadivel Murugan #define CQSPI_INST_TYPE_OCTAL 3 9931fb632bSRamuthevar Vadivel Murugan 10031fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_CLKS_PER_BYTE 8 10131fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_BYTES_MAX 4 10231fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_CLKS_MAX 31 10331fb632bSRamuthevar Vadivel Murugan 10431fb632bSRamuthevar Vadivel Murugan #define CQSPI_STIG_DATA_LEN_MAX 8 10531fb632bSRamuthevar Vadivel Murugan 10631fb632bSRamuthevar Vadivel Murugan /* Register map */ 10731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG 0x00 10831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0) 10931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7) 11031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9) 11131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 11231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_DMA_MASK BIT(15) 11331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_BAUD_LSB 19 11431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_IDLE_LSB 31 11531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF 11631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_BAUD_MASK 0xF 11731fb632bSRamuthevar Vadivel Murugan 11831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR 0x04 11931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 12031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 12131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 12231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 12331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 12431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 12531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 12631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 12731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 12831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F 12931fb632bSRamuthevar Vadivel Murugan 13031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR 0x08 13131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 13231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12 13331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16 13431fb632bSRamuthevar Vadivel Murugan 13531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY 0x0C 13631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSLCH_LSB 0 13731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TCHSH_LSB 8 13831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSD2D_LSB 16 13931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSHSL_LSB 24 14031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF 14131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF 14231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF 14331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF 14431fb632bSRamuthevar Vadivel Murugan 14531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE 0x10 14631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0 14731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_DELAY_LSB 1 14831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF 14931fb632bSRamuthevar Vadivel Murugan 15031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE 0x14 15131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_ADDRESS_LSB 0 15231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_PAGE_LSB 4 15331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_BLOCK_LSB 16 15431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF 15531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF 15631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F 15731fb632bSRamuthevar Vadivel Murugan 15831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SRAMPARTITION 0x18 15931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTTRIGGER 0x1C 16031fb632bSRamuthevar Vadivel Murugan 16131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA 0x20 16231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_SINGLE_LSB 0 16331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_BURST_LSB 8 16431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_SINGLE_MASK 0xFF 16531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_BURST_MASK 0xFF 16631fb632bSRamuthevar Vadivel Murugan 16731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_REMAP 0x24 16831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_MODE_BIT 0x28 16931fb632bSRamuthevar Vadivel Murugan 17031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL 0x2C 17131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 17231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 17331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF 17431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF 17531fb632bSRamuthevar Vadivel Murugan 17631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQSTATUS 0x40 17731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQMASK 0x44 17831fb632bSRamuthevar Vadivel Murugan 17931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD 0x60 18031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0) 18131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1) 18231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5) 18331fb632bSRamuthevar Vadivel Murugan 18431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDWATERMARK 0x64 18531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 18631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDBYTES 0x6C 18731fb632bSRamuthevar Vadivel Murugan 18831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL 0x90 18931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0) 19031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1) 191888d517bSPratyush Yadav #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 19231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 19331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 19431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 19531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 19631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 19731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 19831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 19931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 20031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 20131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 202888d517bSPratyush Yadav #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F 20331fb632bSRamuthevar Vadivel Murugan 20431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR 0x70 20531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0) 20631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1) 20731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5) 20831fb632bSRamuthevar Vadivel Murugan 20931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRWATERMARK 0x74 21031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 21131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRBYTES 0x7C 21231fb632bSRamuthevar Vadivel Murugan 21331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDADDRESS 0x94 21431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDREADDATALOWER 0xA0 21531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDREADDATAUPPER 0xA4 21631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDWRITEDATALOWER 0xA8 21731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC 21831fb632bSRamuthevar Vadivel Murugan 21931fb632bSRamuthevar Vadivel Murugan /* Interrupt status bits */ 22031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_MODE_ERR BIT(0) 22131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_UNDERFLOW BIT(1) 22231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_COMP BIT(2) 22331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3) 22431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4) 22531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5) 22631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_WATERMARK BIT(6) 22731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12) 22831fb632bSRamuthevar Vadivel Murugan 22931fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \ 23031fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_IND_SRAM_FULL | \ 23131fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_IND_COMP) 23231fb632bSRamuthevar Vadivel Murugan 23331fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \ 23431fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_WATERMARK | \ 23531fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_UNDERFLOW) 23631fb632bSRamuthevar Vadivel Murugan 23731fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_STATUS_MASK 0x1FFFF 23831fb632bSRamuthevar Vadivel Murugan 23931fb632bSRamuthevar Vadivel Murugan static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr) 24031fb632bSRamuthevar Vadivel Murugan { 24131fb632bSRamuthevar Vadivel Murugan u32 val; 24231fb632bSRamuthevar Vadivel Murugan 24331fb632bSRamuthevar Vadivel Murugan return readl_relaxed_poll_timeout(reg, val, 24431fb632bSRamuthevar Vadivel Murugan (((clr ? ~val : val) & mask) == mask), 24531fb632bSRamuthevar Vadivel Murugan 10, CQSPI_TIMEOUT_MS * 1000); 24631fb632bSRamuthevar Vadivel Murugan } 24731fb632bSRamuthevar Vadivel Murugan 24831fb632bSRamuthevar Vadivel Murugan static bool cqspi_is_idle(struct cqspi_st *cqspi) 24931fb632bSRamuthevar Vadivel Murugan { 25031fb632bSRamuthevar Vadivel Murugan u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 25131fb632bSRamuthevar Vadivel Murugan 25231fb632bSRamuthevar Vadivel Murugan return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB); 25331fb632bSRamuthevar Vadivel Murugan } 25431fb632bSRamuthevar Vadivel Murugan 25531fb632bSRamuthevar Vadivel Murugan static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi) 25631fb632bSRamuthevar Vadivel Murugan { 25731fb632bSRamuthevar Vadivel Murugan u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL); 25831fb632bSRamuthevar Vadivel Murugan 25931fb632bSRamuthevar Vadivel Murugan reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB; 26031fb632bSRamuthevar Vadivel Murugan return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK; 26131fb632bSRamuthevar Vadivel Murugan } 26231fb632bSRamuthevar Vadivel Murugan 26331fb632bSRamuthevar Vadivel Murugan static irqreturn_t cqspi_irq_handler(int this_irq, void *dev) 26431fb632bSRamuthevar Vadivel Murugan { 26531fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev; 26631fb632bSRamuthevar Vadivel Murugan unsigned int irq_status; 26731fb632bSRamuthevar Vadivel Murugan 26831fb632bSRamuthevar Vadivel Murugan /* Read interrupt status */ 26931fb632bSRamuthevar Vadivel Murugan irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS); 27031fb632bSRamuthevar Vadivel Murugan 27131fb632bSRamuthevar Vadivel Murugan /* Clear interrupt */ 27231fb632bSRamuthevar Vadivel Murugan writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS); 27331fb632bSRamuthevar Vadivel Murugan 27431fb632bSRamuthevar Vadivel Murugan irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR; 27531fb632bSRamuthevar Vadivel Murugan 27631fb632bSRamuthevar Vadivel Murugan if (irq_status) 27731fb632bSRamuthevar Vadivel Murugan complete(&cqspi->transfer_complete); 27831fb632bSRamuthevar Vadivel Murugan 27931fb632bSRamuthevar Vadivel Murugan return IRQ_HANDLED; 28031fb632bSRamuthevar Vadivel Murugan } 28131fb632bSRamuthevar Vadivel Murugan 28231fb632bSRamuthevar Vadivel Murugan static unsigned int cqspi_calc_rdreg(struct cqspi_flash_pdata *f_pdata) 28331fb632bSRamuthevar Vadivel Murugan { 28431fb632bSRamuthevar Vadivel Murugan u32 rdreg = 0; 28531fb632bSRamuthevar Vadivel Murugan 28631fb632bSRamuthevar Vadivel Murugan rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; 28731fb632bSRamuthevar Vadivel Murugan rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; 28831fb632bSRamuthevar Vadivel Murugan rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; 28931fb632bSRamuthevar Vadivel Murugan 29031fb632bSRamuthevar Vadivel Murugan return rdreg; 29131fb632bSRamuthevar Vadivel Murugan } 29231fb632bSRamuthevar Vadivel Murugan 293888d517bSPratyush Yadav static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op) 294888d517bSPratyush Yadav { 295888d517bSPratyush Yadav unsigned int dummy_clk; 296888d517bSPratyush Yadav 2977512eaf5SPratyush Yadav dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth); 298888d517bSPratyush Yadav 299888d517bSPratyush Yadav return dummy_clk; 300888d517bSPratyush Yadav } 301888d517bSPratyush Yadav 30231fb632bSRamuthevar Vadivel Murugan static int cqspi_wait_idle(struct cqspi_st *cqspi) 30331fb632bSRamuthevar Vadivel Murugan { 30431fb632bSRamuthevar Vadivel Murugan const unsigned int poll_idle_retry = 3; 30531fb632bSRamuthevar Vadivel Murugan unsigned int count = 0; 30631fb632bSRamuthevar Vadivel Murugan unsigned long timeout; 30731fb632bSRamuthevar Vadivel Murugan 30831fb632bSRamuthevar Vadivel Murugan timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS); 30931fb632bSRamuthevar Vadivel Murugan while (1) { 31031fb632bSRamuthevar Vadivel Murugan /* 31131fb632bSRamuthevar Vadivel Murugan * Read few times in succession to ensure the controller 31231fb632bSRamuthevar Vadivel Murugan * is indeed idle, that is, the bit does not transition 31331fb632bSRamuthevar Vadivel Murugan * low again. 31431fb632bSRamuthevar Vadivel Murugan */ 31531fb632bSRamuthevar Vadivel Murugan if (cqspi_is_idle(cqspi)) 31631fb632bSRamuthevar Vadivel Murugan count++; 31731fb632bSRamuthevar Vadivel Murugan else 31831fb632bSRamuthevar Vadivel Murugan count = 0; 31931fb632bSRamuthevar Vadivel Murugan 32031fb632bSRamuthevar Vadivel Murugan if (count >= poll_idle_retry) 32131fb632bSRamuthevar Vadivel Murugan return 0; 32231fb632bSRamuthevar Vadivel Murugan 32331fb632bSRamuthevar Vadivel Murugan if (time_after(jiffies, timeout)) { 32431fb632bSRamuthevar Vadivel Murugan /* Timeout, in busy mode. */ 32531fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 32631fb632bSRamuthevar Vadivel Murugan "QSPI is still busy after %dms timeout.\n", 32731fb632bSRamuthevar Vadivel Murugan CQSPI_TIMEOUT_MS); 32831fb632bSRamuthevar Vadivel Murugan return -ETIMEDOUT; 32931fb632bSRamuthevar Vadivel Murugan } 33031fb632bSRamuthevar Vadivel Murugan 33131fb632bSRamuthevar Vadivel Murugan cpu_relax(); 33231fb632bSRamuthevar Vadivel Murugan } 33331fb632bSRamuthevar Vadivel Murugan } 33431fb632bSRamuthevar Vadivel Murugan 33531fb632bSRamuthevar Vadivel Murugan static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg) 33631fb632bSRamuthevar Vadivel Murugan { 33731fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 33831fb632bSRamuthevar Vadivel Murugan int ret; 33931fb632bSRamuthevar Vadivel Murugan 34031fb632bSRamuthevar Vadivel Murugan /* Write the CMDCTRL without start execution. */ 34131fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CMDCTRL); 34231fb632bSRamuthevar Vadivel Murugan /* Start execute */ 34331fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK; 34431fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CMDCTRL); 34531fb632bSRamuthevar Vadivel Murugan 34631fb632bSRamuthevar Vadivel Murugan /* Polling for completion. */ 34731fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL, 34831fb632bSRamuthevar Vadivel Murugan CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1); 34931fb632bSRamuthevar Vadivel Murugan if (ret) { 35031fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 35131fb632bSRamuthevar Vadivel Murugan "Flash command execution timed out.\n"); 35231fb632bSRamuthevar Vadivel Murugan return ret; 35331fb632bSRamuthevar Vadivel Murugan } 35431fb632bSRamuthevar Vadivel Murugan 35531fb632bSRamuthevar Vadivel Murugan /* Polling QSPI idle status. */ 35631fb632bSRamuthevar Vadivel Murugan return cqspi_wait_idle(cqspi); 35731fb632bSRamuthevar Vadivel Murugan } 35831fb632bSRamuthevar Vadivel Murugan 35931fb632bSRamuthevar Vadivel Murugan static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, 36031fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 36131fb632bSRamuthevar Vadivel Murugan { 36231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 36331fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 36431fb632bSRamuthevar Vadivel Murugan u8 *rxbuf = op->data.buf.in; 36531fb632bSRamuthevar Vadivel Murugan u8 opcode = op->cmd.opcode; 36631fb632bSRamuthevar Vadivel Murugan size_t n_rx = op->data.nbytes; 36731fb632bSRamuthevar Vadivel Murugan unsigned int rdreg; 36831fb632bSRamuthevar Vadivel Murugan unsigned int reg; 369888d517bSPratyush Yadav unsigned int dummy_clk; 37031fb632bSRamuthevar Vadivel Murugan size_t read_len; 37131fb632bSRamuthevar Vadivel Murugan int status; 37231fb632bSRamuthevar Vadivel Murugan 37331fb632bSRamuthevar Vadivel Murugan if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) { 37431fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 37531fb632bSRamuthevar Vadivel Murugan "Invalid input argument, len %zu rxbuf 0x%p\n", 37631fb632bSRamuthevar Vadivel Murugan n_rx, rxbuf); 37731fb632bSRamuthevar Vadivel Murugan return -EINVAL; 37831fb632bSRamuthevar Vadivel Murugan } 37931fb632bSRamuthevar Vadivel Murugan 38031fb632bSRamuthevar Vadivel Murugan reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 38131fb632bSRamuthevar Vadivel Murugan 38231fb632bSRamuthevar Vadivel Murugan rdreg = cqspi_calc_rdreg(f_pdata); 38331fb632bSRamuthevar Vadivel Murugan writel(rdreg, reg_base + CQSPI_REG_RD_INSTR); 38431fb632bSRamuthevar Vadivel Murugan 385888d517bSPratyush Yadav dummy_clk = cqspi_calc_dummy(op); 386888d517bSPratyush Yadav if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 387888d517bSPratyush Yadav return -EOPNOTSUPP; 388888d517bSPratyush Yadav 389888d517bSPratyush Yadav if (dummy_clk) 390888d517bSPratyush Yadav reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK) 391888d517bSPratyush Yadav << CQSPI_REG_CMDCTRL_DUMMY_LSB; 392888d517bSPratyush Yadav 39331fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); 39431fb632bSRamuthevar Vadivel Murugan 39531fb632bSRamuthevar Vadivel Murugan /* 0 means 1 byte. */ 39631fb632bSRamuthevar Vadivel Murugan reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) 39731fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); 39831fb632bSRamuthevar Vadivel Murugan status = cqspi_exec_flash_cmd(cqspi, reg); 39931fb632bSRamuthevar Vadivel Murugan if (status) 40031fb632bSRamuthevar Vadivel Murugan return status; 40131fb632bSRamuthevar Vadivel Murugan 40231fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER); 40331fb632bSRamuthevar Vadivel Murugan 40431fb632bSRamuthevar Vadivel Murugan /* Put the read value into rx_buf */ 40531fb632bSRamuthevar Vadivel Murugan read_len = (n_rx > 4) ? 4 : n_rx; 40631fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, ®, read_len); 40731fb632bSRamuthevar Vadivel Murugan rxbuf += read_len; 40831fb632bSRamuthevar Vadivel Murugan 40931fb632bSRamuthevar Vadivel Murugan if (n_rx > 4) { 41031fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER); 41131fb632bSRamuthevar Vadivel Murugan 41231fb632bSRamuthevar Vadivel Murugan read_len = n_rx - read_len; 41331fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, ®, read_len); 41431fb632bSRamuthevar Vadivel Murugan } 41531fb632bSRamuthevar Vadivel Murugan 41631fb632bSRamuthevar Vadivel Murugan return 0; 41731fb632bSRamuthevar Vadivel Murugan } 41831fb632bSRamuthevar Vadivel Murugan 41931fb632bSRamuthevar Vadivel Murugan static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata, 42031fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 42131fb632bSRamuthevar Vadivel Murugan { 42231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 42331fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 42431fb632bSRamuthevar Vadivel Murugan const u8 opcode = op->cmd.opcode; 42531fb632bSRamuthevar Vadivel Murugan const u8 *txbuf = op->data.buf.out; 42631fb632bSRamuthevar Vadivel Murugan size_t n_tx = op->data.nbytes; 42731fb632bSRamuthevar Vadivel Murugan unsigned int reg; 42831fb632bSRamuthevar Vadivel Murugan unsigned int data; 42931fb632bSRamuthevar Vadivel Murugan size_t write_len; 43031fb632bSRamuthevar Vadivel Murugan 43131fb632bSRamuthevar Vadivel Murugan if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) { 43231fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 43331fb632bSRamuthevar Vadivel Murugan "Invalid input argument, cmdlen %zu txbuf 0x%p\n", 43431fb632bSRamuthevar Vadivel Murugan n_tx, txbuf); 43531fb632bSRamuthevar Vadivel Murugan return -EINVAL; 43631fb632bSRamuthevar Vadivel Murugan } 43731fb632bSRamuthevar Vadivel Murugan 43831fb632bSRamuthevar Vadivel Murugan reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 43931fb632bSRamuthevar Vadivel Murugan 44031fb632bSRamuthevar Vadivel Murugan if (op->addr.nbytes) { 44131fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 44231fb632bSRamuthevar Vadivel Murugan reg |= ((op->addr.nbytes - 1) & 44331fb632bSRamuthevar Vadivel Murugan CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) 44431fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; 44531fb632bSRamuthevar Vadivel Murugan 44631fb632bSRamuthevar Vadivel Murugan writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); 44731fb632bSRamuthevar Vadivel Murugan } 44831fb632bSRamuthevar Vadivel Murugan 44931fb632bSRamuthevar Vadivel Murugan if (n_tx) { 45031fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB); 45131fb632bSRamuthevar Vadivel Murugan reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) 45231fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_WR_BYTES_LSB; 45331fb632bSRamuthevar Vadivel Murugan data = 0; 45431fb632bSRamuthevar Vadivel Murugan write_len = (n_tx > 4) ? 4 : n_tx; 45531fb632bSRamuthevar Vadivel Murugan memcpy(&data, txbuf, write_len); 45631fb632bSRamuthevar Vadivel Murugan txbuf += write_len; 45731fb632bSRamuthevar Vadivel Murugan writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER); 45831fb632bSRamuthevar Vadivel Murugan 45931fb632bSRamuthevar Vadivel Murugan if (n_tx > 4) { 46031fb632bSRamuthevar Vadivel Murugan data = 0; 46131fb632bSRamuthevar Vadivel Murugan write_len = n_tx - 4; 46231fb632bSRamuthevar Vadivel Murugan memcpy(&data, txbuf, write_len); 46331fb632bSRamuthevar Vadivel Murugan writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER); 46431fb632bSRamuthevar Vadivel Murugan } 46531fb632bSRamuthevar Vadivel Murugan } 46631fb632bSRamuthevar Vadivel Murugan 46731fb632bSRamuthevar Vadivel Murugan return cqspi_exec_flash_cmd(cqspi, reg); 46831fb632bSRamuthevar Vadivel Murugan } 46931fb632bSRamuthevar Vadivel Murugan 47031fb632bSRamuthevar Vadivel Murugan static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata, 47131fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 47231fb632bSRamuthevar Vadivel Murugan { 47331fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 47431fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 47531fb632bSRamuthevar Vadivel Murugan unsigned int dummy_clk = 0; 47631fb632bSRamuthevar Vadivel Murugan unsigned int reg; 47731fb632bSRamuthevar Vadivel Murugan 47831fb632bSRamuthevar Vadivel Murugan reg = op->cmd.opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB; 47931fb632bSRamuthevar Vadivel Murugan reg |= cqspi_calc_rdreg(f_pdata); 48031fb632bSRamuthevar Vadivel Murugan 48131fb632bSRamuthevar Vadivel Murugan /* Setup dummy clock cycles */ 482888d517bSPratyush Yadav dummy_clk = cqspi_calc_dummy(op); 483888d517bSPratyush Yadav 48431fb632bSRamuthevar Vadivel Murugan if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 485ceeda328SPratyush Yadav return -EOPNOTSUPP; 48631fb632bSRamuthevar Vadivel Murugan 48731fb632bSRamuthevar Vadivel Murugan if (dummy_clk) 48831fb632bSRamuthevar Vadivel Murugan reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK) 48931fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_RD_INSTR_DUMMY_LSB; 49031fb632bSRamuthevar Vadivel Murugan 49131fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_RD_INSTR); 49231fb632bSRamuthevar Vadivel Murugan 49331fb632bSRamuthevar Vadivel Murugan /* Set address width */ 49431fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_SIZE); 49531fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 49631fb632bSRamuthevar Vadivel Murugan reg |= (op->addr.nbytes - 1); 49731fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_SIZE); 49831fb632bSRamuthevar Vadivel Murugan return 0; 49931fb632bSRamuthevar Vadivel Murugan } 50031fb632bSRamuthevar Vadivel Murugan 50131fb632bSRamuthevar Vadivel Murugan static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, 50231fb632bSRamuthevar Vadivel Murugan u8 *rxbuf, loff_t from_addr, 50331fb632bSRamuthevar Vadivel Murugan const size_t n_rx) 50431fb632bSRamuthevar Vadivel Murugan { 50531fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 50631fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 50731fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 50831fb632bSRamuthevar Vadivel Murugan void __iomem *ahb_base = cqspi->ahb_base; 50931fb632bSRamuthevar Vadivel Murugan unsigned int remaining = n_rx; 51031fb632bSRamuthevar Vadivel Murugan unsigned int mod_bytes = n_rx % 4; 51131fb632bSRamuthevar Vadivel Murugan unsigned int bytes_to_read = 0; 51231fb632bSRamuthevar Vadivel Murugan u8 *rxbuf_end = rxbuf + n_rx; 51331fb632bSRamuthevar Vadivel Murugan int ret = 0; 51431fb632bSRamuthevar Vadivel Murugan 51531fb632bSRamuthevar Vadivel Murugan writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 51631fb632bSRamuthevar Vadivel Murugan writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES); 51731fb632bSRamuthevar Vadivel Murugan 51831fb632bSRamuthevar Vadivel Murugan /* Clear all interrupts. */ 51931fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 52031fb632bSRamuthevar Vadivel Murugan 52131fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK); 52231fb632bSRamuthevar Vadivel Murugan 52331fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 52431fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTRD_START_MASK, 52531fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTRD); 52631fb632bSRamuthevar Vadivel Murugan 52731fb632bSRamuthevar Vadivel Murugan while (remaining > 0) { 52831fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->transfer_complete, 52931fb632bSRamuthevar Vadivel Murugan msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) 53031fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 53131fb632bSRamuthevar Vadivel Murugan 53231fb632bSRamuthevar Vadivel Murugan bytes_to_read = cqspi_get_rd_sram_level(cqspi); 53331fb632bSRamuthevar Vadivel Murugan 53431fb632bSRamuthevar Vadivel Murugan if (ret && bytes_to_read == 0) { 53531fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect read timeout, no bytes\n"); 53631fb632bSRamuthevar Vadivel Murugan goto failrd; 53731fb632bSRamuthevar Vadivel Murugan } 53831fb632bSRamuthevar Vadivel Murugan 53931fb632bSRamuthevar Vadivel Murugan while (bytes_to_read != 0) { 54031fb632bSRamuthevar Vadivel Murugan unsigned int word_remain = round_down(remaining, 4); 54131fb632bSRamuthevar Vadivel Murugan 54231fb632bSRamuthevar Vadivel Murugan bytes_to_read *= cqspi->fifo_width; 54331fb632bSRamuthevar Vadivel Murugan bytes_to_read = bytes_to_read > remaining ? 54431fb632bSRamuthevar Vadivel Murugan remaining : bytes_to_read; 54531fb632bSRamuthevar Vadivel Murugan bytes_to_read = round_down(bytes_to_read, 4); 54631fb632bSRamuthevar Vadivel Murugan /* Read 4 byte word chunks then single bytes */ 54731fb632bSRamuthevar Vadivel Murugan if (bytes_to_read) { 54831fb632bSRamuthevar Vadivel Murugan ioread32_rep(ahb_base, rxbuf, 54931fb632bSRamuthevar Vadivel Murugan (bytes_to_read / 4)); 55031fb632bSRamuthevar Vadivel Murugan } else if (!word_remain && mod_bytes) { 55131fb632bSRamuthevar Vadivel Murugan unsigned int temp = ioread32(ahb_base); 55231fb632bSRamuthevar Vadivel Murugan 55331fb632bSRamuthevar Vadivel Murugan bytes_to_read = mod_bytes; 55431fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, &temp, min((unsigned int) 55531fb632bSRamuthevar Vadivel Murugan (rxbuf_end - rxbuf), 55631fb632bSRamuthevar Vadivel Murugan bytes_to_read)); 55731fb632bSRamuthevar Vadivel Murugan } 55831fb632bSRamuthevar Vadivel Murugan rxbuf += bytes_to_read; 55931fb632bSRamuthevar Vadivel Murugan remaining -= bytes_to_read; 56031fb632bSRamuthevar Vadivel Murugan bytes_to_read = cqspi_get_rd_sram_level(cqspi); 56131fb632bSRamuthevar Vadivel Murugan } 56231fb632bSRamuthevar Vadivel Murugan 56331fb632bSRamuthevar Vadivel Murugan if (remaining > 0) 56431fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 56531fb632bSRamuthevar Vadivel Murugan } 56631fb632bSRamuthevar Vadivel Murugan 56731fb632bSRamuthevar Vadivel Murugan /* Check indirect done status */ 56831fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD, 56931fb632bSRamuthevar Vadivel Murugan CQSPI_REG_INDIRECTRD_DONE_MASK, 0); 57031fb632bSRamuthevar Vadivel Murugan if (ret) { 57131fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect read completion error (%i)\n", ret); 57231fb632bSRamuthevar Vadivel Murugan goto failrd; 57331fb632bSRamuthevar Vadivel Murugan } 57431fb632bSRamuthevar Vadivel Murugan 57531fb632bSRamuthevar Vadivel Murugan /* Disable interrupt */ 57631fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 57731fb632bSRamuthevar Vadivel Murugan 57831fb632bSRamuthevar Vadivel Murugan /* Clear indirect completion status */ 57931fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD); 58031fb632bSRamuthevar Vadivel Murugan 58131fb632bSRamuthevar Vadivel Murugan return 0; 58231fb632bSRamuthevar Vadivel Murugan 58331fb632bSRamuthevar Vadivel Murugan failrd: 58431fb632bSRamuthevar Vadivel Murugan /* Disable interrupt */ 58531fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 58631fb632bSRamuthevar Vadivel Murugan 58731fb632bSRamuthevar Vadivel Murugan /* Cancel the indirect read */ 58831fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 58931fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTRD); 59031fb632bSRamuthevar Vadivel Murugan return ret; 59131fb632bSRamuthevar Vadivel Murugan } 59231fb632bSRamuthevar Vadivel Murugan 59331fb632bSRamuthevar Vadivel Murugan static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata, 59431fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 59531fb632bSRamuthevar Vadivel Murugan { 59631fb632bSRamuthevar Vadivel Murugan unsigned int reg; 59731fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 59831fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 59931fb632bSRamuthevar Vadivel Murugan 60031fb632bSRamuthevar Vadivel Murugan /* Set opcode. */ 60131fb632bSRamuthevar Vadivel Murugan reg = op->cmd.opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; 60231fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_WR_INSTR); 60331fb632bSRamuthevar Vadivel Murugan reg = cqspi_calc_rdreg(f_pdata); 60431fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_RD_INSTR); 60531fb632bSRamuthevar Vadivel Murugan 60631fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_SIZE); 60731fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 60831fb632bSRamuthevar Vadivel Murugan reg |= (op->addr.nbytes - 1); 60931fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_SIZE); 61031fb632bSRamuthevar Vadivel Murugan return 0; 61131fb632bSRamuthevar Vadivel Murugan } 61231fb632bSRamuthevar Vadivel Murugan 61331fb632bSRamuthevar Vadivel Murugan static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, 61431fb632bSRamuthevar Vadivel Murugan loff_t to_addr, const u8 *txbuf, 61531fb632bSRamuthevar Vadivel Murugan const size_t n_tx) 61631fb632bSRamuthevar Vadivel Murugan { 61731fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 61831fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 61931fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 62031fb632bSRamuthevar Vadivel Murugan unsigned int remaining = n_tx; 62131fb632bSRamuthevar Vadivel Murugan unsigned int write_bytes; 62231fb632bSRamuthevar Vadivel Murugan int ret; 62331fb632bSRamuthevar Vadivel Murugan 62431fb632bSRamuthevar Vadivel Murugan writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR); 62531fb632bSRamuthevar Vadivel Murugan writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES); 62631fb632bSRamuthevar Vadivel Murugan 62731fb632bSRamuthevar Vadivel Murugan /* Clear all interrupts. */ 62831fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 62931fb632bSRamuthevar Vadivel Murugan 63031fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK); 63131fb632bSRamuthevar Vadivel Murugan 63231fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 63331fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_START_MASK, 63431fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTWR); 63531fb632bSRamuthevar Vadivel Murugan /* 63631fb632bSRamuthevar Vadivel Murugan * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access 63731fb632bSRamuthevar Vadivel Murugan * Controller programming sequence, couple of cycles of 63831fb632bSRamuthevar Vadivel Murugan * QSPI_REF_CLK delay is required for the above bit to 63931fb632bSRamuthevar Vadivel Murugan * be internally synchronized by the QSPI module. Provide 5 64031fb632bSRamuthevar Vadivel Murugan * cycles of delay. 64131fb632bSRamuthevar Vadivel Murugan */ 64231fb632bSRamuthevar Vadivel Murugan if (cqspi->wr_delay) 64331fb632bSRamuthevar Vadivel Murugan ndelay(cqspi->wr_delay); 64431fb632bSRamuthevar Vadivel Murugan 64531fb632bSRamuthevar Vadivel Murugan while (remaining > 0) { 64631fb632bSRamuthevar Vadivel Murugan size_t write_words, mod_bytes; 64731fb632bSRamuthevar Vadivel Murugan 64831fb632bSRamuthevar Vadivel Murugan write_bytes = remaining; 64931fb632bSRamuthevar Vadivel Murugan write_words = write_bytes / 4; 65031fb632bSRamuthevar Vadivel Murugan mod_bytes = write_bytes % 4; 65131fb632bSRamuthevar Vadivel Murugan /* Write 4 bytes at a time then single bytes. */ 65231fb632bSRamuthevar Vadivel Murugan if (write_words) { 65331fb632bSRamuthevar Vadivel Murugan iowrite32_rep(cqspi->ahb_base, txbuf, write_words); 65431fb632bSRamuthevar Vadivel Murugan txbuf += (write_words * 4); 65531fb632bSRamuthevar Vadivel Murugan } 65631fb632bSRamuthevar Vadivel Murugan if (mod_bytes) { 65731fb632bSRamuthevar Vadivel Murugan unsigned int temp = 0xFFFFFFFF; 65831fb632bSRamuthevar Vadivel Murugan 65931fb632bSRamuthevar Vadivel Murugan memcpy(&temp, txbuf, mod_bytes); 66031fb632bSRamuthevar Vadivel Murugan iowrite32(temp, cqspi->ahb_base); 66131fb632bSRamuthevar Vadivel Murugan txbuf += mod_bytes; 66231fb632bSRamuthevar Vadivel Murugan } 66331fb632bSRamuthevar Vadivel Murugan 66431fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->transfer_complete, 66531fb632bSRamuthevar Vadivel Murugan msecs_to_jiffies(CQSPI_TIMEOUT_MS))) { 66631fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect write timeout\n"); 66731fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 66831fb632bSRamuthevar Vadivel Murugan goto failwr; 66931fb632bSRamuthevar Vadivel Murugan } 67031fb632bSRamuthevar Vadivel Murugan 67131fb632bSRamuthevar Vadivel Murugan remaining -= write_bytes; 67231fb632bSRamuthevar Vadivel Murugan 67331fb632bSRamuthevar Vadivel Murugan if (remaining > 0) 67431fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 67531fb632bSRamuthevar Vadivel Murugan } 67631fb632bSRamuthevar Vadivel Murugan 67731fb632bSRamuthevar Vadivel Murugan /* Check indirect done status */ 67831fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR, 67931fb632bSRamuthevar Vadivel Murugan CQSPI_REG_INDIRECTWR_DONE_MASK, 0); 68031fb632bSRamuthevar Vadivel Murugan if (ret) { 68131fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect write completion error (%i)\n", ret); 68231fb632bSRamuthevar Vadivel Murugan goto failwr; 68331fb632bSRamuthevar Vadivel Murugan } 68431fb632bSRamuthevar Vadivel Murugan 68531fb632bSRamuthevar Vadivel Murugan /* Disable interrupt. */ 68631fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 68731fb632bSRamuthevar Vadivel Murugan 68831fb632bSRamuthevar Vadivel Murugan /* Clear indirect completion status */ 68931fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR); 69031fb632bSRamuthevar Vadivel Murugan 69131fb632bSRamuthevar Vadivel Murugan cqspi_wait_idle(cqspi); 69231fb632bSRamuthevar Vadivel Murugan 69331fb632bSRamuthevar Vadivel Murugan return 0; 69431fb632bSRamuthevar Vadivel Murugan 69531fb632bSRamuthevar Vadivel Murugan failwr: 69631fb632bSRamuthevar Vadivel Murugan /* Disable interrupt. */ 69731fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 69831fb632bSRamuthevar Vadivel Murugan 69931fb632bSRamuthevar Vadivel Murugan /* Cancel the indirect write */ 70031fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 70131fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTWR); 70231fb632bSRamuthevar Vadivel Murugan return ret; 70331fb632bSRamuthevar Vadivel Murugan } 70431fb632bSRamuthevar Vadivel Murugan 70531fb632bSRamuthevar Vadivel Murugan static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata) 70631fb632bSRamuthevar Vadivel Murugan { 70731fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 70831fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 70931fb632bSRamuthevar Vadivel Murugan unsigned int chip_select = f_pdata->cs; 71031fb632bSRamuthevar Vadivel Murugan unsigned int reg; 71131fb632bSRamuthevar Vadivel Murugan 71231fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG); 71331fb632bSRamuthevar Vadivel Murugan if (cqspi->is_decoded_cs) { 71431fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CONFIG_DECODE_MASK; 71531fb632bSRamuthevar Vadivel Murugan } else { 71631fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; 71731fb632bSRamuthevar Vadivel Murugan 71831fb632bSRamuthevar Vadivel Murugan /* Convert CS if without decoder. 71931fb632bSRamuthevar Vadivel Murugan * CS0 to 4b'1110 72031fb632bSRamuthevar Vadivel Murugan * CS1 to 4b'1101 72131fb632bSRamuthevar Vadivel Murugan * CS2 to 4b'1011 72231fb632bSRamuthevar Vadivel Murugan * CS3 to 4b'0111 72331fb632bSRamuthevar Vadivel Murugan */ 72431fb632bSRamuthevar Vadivel Murugan chip_select = 0xF & ~(1 << chip_select); 72531fb632bSRamuthevar Vadivel Murugan } 72631fb632bSRamuthevar Vadivel Murugan 72731fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK 72831fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CONFIG_CHIPSELECT_LSB); 72931fb632bSRamuthevar Vadivel Murugan reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK) 73031fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CONFIG_CHIPSELECT_LSB; 73131fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG); 73231fb632bSRamuthevar Vadivel Murugan } 73331fb632bSRamuthevar Vadivel Murugan 73431fb632bSRamuthevar Vadivel Murugan static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz, 73531fb632bSRamuthevar Vadivel Murugan const unsigned int ns_val) 73631fb632bSRamuthevar Vadivel Murugan { 73731fb632bSRamuthevar Vadivel Murugan unsigned int ticks; 73831fb632bSRamuthevar Vadivel Murugan 73931fb632bSRamuthevar Vadivel Murugan ticks = ref_clk_hz / 1000; /* kHz */ 74031fb632bSRamuthevar Vadivel Murugan ticks = DIV_ROUND_UP(ticks * ns_val, 1000000); 74131fb632bSRamuthevar Vadivel Murugan 74231fb632bSRamuthevar Vadivel Murugan return ticks; 74331fb632bSRamuthevar Vadivel Murugan } 74431fb632bSRamuthevar Vadivel Murugan 74531fb632bSRamuthevar Vadivel Murugan static void cqspi_delay(struct cqspi_flash_pdata *f_pdata) 74631fb632bSRamuthevar Vadivel Murugan { 74731fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 74831fb632bSRamuthevar Vadivel Murugan void __iomem *iobase = cqspi->iobase; 74931fb632bSRamuthevar Vadivel Murugan const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 75031fb632bSRamuthevar Vadivel Murugan unsigned int tshsl, tchsh, tslch, tsd2d; 75131fb632bSRamuthevar Vadivel Murugan unsigned int reg; 75231fb632bSRamuthevar Vadivel Murugan unsigned int tsclk; 75331fb632bSRamuthevar Vadivel Murugan 75431fb632bSRamuthevar Vadivel Murugan /* calculate the number of ref ticks for one sclk tick */ 75531fb632bSRamuthevar Vadivel Murugan tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk); 75631fb632bSRamuthevar Vadivel Murugan 75731fb632bSRamuthevar Vadivel Murugan tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns); 75831fb632bSRamuthevar Vadivel Murugan /* this particular value must be at least one sclk */ 75931fb632bSRamuthevar Vadivel Murugan if (tshsl < tsclk) 76031fb632bSRamuthevar Vadivel Murugan tshsl = tsclk; 76131fb632bSRamuthevar Vadivel Murugan 76231fb632bSRamuthevar Vadivel Murugan tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns); 76331fb632bSRamuthevar Vadivel Murugan tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns); 76431fb632bSRamuthevar Vadivel Murugan tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns); 76531fb632bSRamuthevar Vadivel Murugan 76631fb632bSRamuthevar Vadivel Murugan reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK) 76731fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSHSL_LSB; 76831fb632bSRamuthevar Vadivel Murugan reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK) 76931fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TCHSH_LSB; 77031fb632bSRamuthevar Vadivel Murugan reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK) 77131fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSLCH_LSB; 77231fb632bSRamuthevar Vadivel Murugan reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK) 77331fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSD2D_LSB; 77431fb632bSRamuthevar Vadivel Murugan writel(reg, iobase + CQSPI_REG_DELAY); 77531fb632bSRamuthevar Vadivel Murugan } 77631fb632bSRamuthevar Vadivel Murugan 77731fb632bSRamuthevar Vadivel Murugan static void cqspi_config_baudrate_div(struct cqspi_st *cqspi) 77831fb632bSRamuthevar Vadivel Murugan { 77931fb632bSRamuthevar Vadivel Murugan const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 78031fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 78131fb632bSRamuthevar Vadivel Murugan u32 reg, div; 78231fb632bSRamuthevar Vadivel Murugan 78331fb632bSRamuthevar Vadivel Murugan /* Recalculate the baudrate divisor based on QSPI specification. */ 78431fb632bSRamuthevar Vadivel Murugan div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1; 78531fb632bSRamuthevar Vadivel Murugan 78631fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG); 78731fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); 78831fb632bSRamuthevar Vadivel Murugan reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB; 78931fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG); 79031fb632bSRamuthevar Vadivel Murugan } 79131fb632bSRamuthevar Vadivel Murugan 79231fb632bSRamuthevar Vadivel Murugan static void cqspi_readdata_capture(struct cqspi_st *cqspi, 79331fb632bSRamuthevar Vadivel Murugan const bool bypass, 79431fb632bSRamuthevar Vadivel Murugan const unsigned int delay) 79531fb632bSRamuthevar Vadivel Murugan { 79631fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 79731fb632bSRamuthevar Vadivel Murugan unsigned int reg; 79831fb632bSRamuthevar Vadivel Murugan 79931fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_READCAPTURE); 80031fb632bSRamuthevar Vadivel Murugan 80131fb632bSRamuthevar Vadivel Murugan if (bypass) 80231fb632bSRamuthevar Vadivel Murugan reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 80331fb632bSRamuthevar Vadivel Murugan else 80431fb632bSRamuthevar Vadivel Murugan reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 80531fb632bSRamuthevar Vadivel Murugan 80631fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK 80731fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_READCAPTURE_DELAY_LSB); 80831fb632bSRamuthevar Vadivel Murugan 80931fb632bSRamuthevar Vadivel Murugan reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK) 81031fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_READCAPTURE_DELAY_LSB; 81131fb632bSRamuthevar Vadivel Murugan 81231fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_READCAPTURE); 81331fb632bSRamuthevar Vadivel Murugan } 81431fb632bSRamuthevar Vadivel Murugan 81531fb632bSRamuthevar Vadivel Murugan static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable) 81631fb632bSRamuthevar Vadivel Murugan { 81731fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 81831fb632bSRamuthevar Vadivel Murugan unsigned int reg; 81931fb632bSRamuthevar Vadivel Murugan 82031fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG); 82131fb632bSRamuthevar Vadivel Murugan 82231fb632bSRamuthevar Vadivel Murugan if (enable) 82331fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CONFIG_ENABLE_MASK; 82431fb632bSRamuthevar Vadivel Murugan else 82531fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; 82631fb632bSRamuthevar Vadivel Murugan 82731fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG); 82831fb632bSRamuthevar Vadivel Murugan } 82931fb632bSRamuthevar Vadivel Murugan 83031fb632bSRamuthevar Vadivel Murugan static void cqspi_configure(struct cqspi_flash_pdata *f_pdata, 83131fb632bSRamuthevar Vadivel Murugan unsigned long sclk) 83231fb632bSRamuthevar Vadivel Murugan { 83331fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 83431fb632bSRamuthevar Vadivel Murugan int switch_cs = (cqspi->current_cs != f_pdata->cs); 83531fb632bSRamuthevar Vadivel Murugan int switch_ck = (cqspi->sclk != sclk); 83631fb632bSRamuthevar Vadivel Murugan 83731fb632bSRamuthevar Vadivel Murugan if (switch_cs || switch_ck) 83831fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 83931fb632bSRamuthevar Vadivel Murugan 84031fb632bSRamuthevar Vadivel Murugan /* Switch chip select. */ 84131fb632bSRamuthevar Vadivel Murugan if (switch_cs) { 84231fb632bSRamuthevar Vadivel Murugan cqspi->current_cs = f_pdata->cs; 84331fb632bSRamuthevar Vadivel Murugan cqspi_chipselect(f_pdata); 84431fb632bSRamuthevar Vadivel Murugan } 84531fb632bSRamuthevar Vadivel Murugan 84631fb632bSRamuthevar Vadivel Murugan /* Setup baudrate divisor and delays */ 84731fb632bSRamuthevar Vadivel Murugan if (switch_ck) { 84831fb632bSRamuthevar Vadivel Murugan cqspi->sclk = sclk; 84931fb632bSRamuthevar Vadivel Murugan cqspi_config_baudrate_div(cqspi); 85031fb632bSRamuthevar Vadivel Murugan cqspi_delay(f_pdata); 85131fb632bSRamuthevar Vadivel Murugan cqspi_readdata_capture(cqspi, !cqspi->rclk_en, 85231fb632bSRamuthevar Vadivel Murugan f_pdata->read_delay); 85331fb632bSRamuthevar Vadivel Murugan } 85431fb632bSRamuthevar Vadivel Murugan 85531fb632bSRamuthevar Vadivel Murugan if (switch_cs || switch_ck) 85631fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1); 85731fb632bSRamuthevar Vadivel Murugan } 85831fb632bSRamuthevar Vadivel Murugan 85931fb632bSRamuthevar Vadivel Murugan static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata, 86031fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 86131fb632bSRamuthevar Vadivel Murugan { 86231fb632bSRamuthevar Vadivel Murugan f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE; 86331fb632bSRamuthevar Vadivel Murugan f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE; 86431fb632bSRamuthevar Vadivel Murugan f_pdata->data_width = CQSPI_INST_TYPE_SINGLE; 86531fb632bSRamuthevar Vadivel Murugan 86631fb632bSRamuthevar Vadivel Murugan if (op->data.dir == SPI_MEM_DATA_IN) { 86731fb632bSRamuthevar Vadivel Murugan switch (op->data.buswidth) { 86831fb632bSRamuthevar Vadivel Murugan case 1: 86931fb632bSRamuthevar Vadivel Murugan f_pdata->data_width = CQSPI_INST_TYPE_SINGLE; 87031fb632bSRamuthevar Vadivel Murugan break; 87131fb632bSRamuthevar Vadivel Murugan case 2: 87231fb632bSRamuthevar Vadivel Murugan f_pdata->data_width = CQSPI_INST_TYPE_DUAL; 87331fb632bSRamuthevar Vadivel Murugan break; 87431fb632bSRamuthevar Vadivel Murugan case 4: 87531fb632bSRamuthevar Vadivel Murugan f_pdata->data_width = CQSPI_INST_TYPE_QUAD; 87631fb632bSRamuthevar Vadivel Murugan break; 87731fb632bSRamuthevar Vadivel Murugan case 8: 87831fb632bSRamuthevar Vadivel Murugan f_pdata->data_width = CQSPI_INST_TYPE_OCTAL; 87931fb632bSRamuthevar Vadivel Murugan break; 88031fb632bSRamuthevar Vadivel Murugan default: 88131fb632bSRamuthevar Vadivel Murugan return -EINVAL; 88231fb632bSRamuthevar Vadivel Murugan } 88331fb632bSRamuthevar Vadivel Murugan } 88431fb632bSRamuthevar Vadivel Murugan 88531fb632bSRamuthevar Vadivel Murugan return 0; 88631fb632bSRamuthevar Vadivel Murugan } 88731fb632bSRamuthevar Vadivel Murugan 88831fb632bSRamuthevar Vadivel Murugan static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata, 88931fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 89031fb632bSRamuthevar Vadivel Murugan { 89131fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 89231fb632bSRamuthevar Vadivel Murugan loff_t to = op->addr.val; 89331fb632bSRamuthevar Vadivel Murugan size_t len = op->data.nbytes; 89431fb632bSRamuthevar Vadivel Murugan const u_char *buf = op->data.buf.out; 89531fb632bSRamuthevar Vadivel Murugan int ret; 89631fb632bSRamuthevar Vadivel Murugan 89731fb632bSRamuthevar Vadivel Murugan ret = cqspi_set_protocol(f_pdata, op); 89831fb632bSRamuthevar Vadivel Murugan if (ret) 89931fb632bSRamuthevar Vadivel Murugan return ret; 90031fb632bSRamuthevar Vadivel Murugan 90131fb632bSRamuthevar Vadivel Murugan ret = cqspi_write_setup(f_pdata, op); 90231fb632bSRamuthevar Vadivel Murugan if (ret) 90331fb632bSRamuthevar Vadivel Murugan return ret; 90431fb632bSRamuthevar Vadivel Murugan 90531fb632bSRamuthevar Vadivel Murugan if (cqspi->use_direct_mode && ((to + len) <= cqspi->ahb_size)) { 90631fb632bSRamuthevar Vadivel Murugan memcpy_toio(cqspi->ahb_base + to, buf, len); 90731fb632bSRamuthevar Vadivel Murugan return cqspi_wait_idle(cqspi); 90831fb632bSRamuthevar Vadivel Murugan } 90931fb632bSRamuthevar Vadivel Murugan 91031fb632bSRamuthevar Vadivel Murugan return cqspi_indirect_write_execute(f_pdata, to, buf, len); 91131fb632bSRamuthevar Vadivel Murugan } 91231fb632bSRamuthevar Vadivel Murugan 91331fb632bSRamuthevar Vadivel Murugan static void cqspi_rx_dma_callback(void *param) 91431fb632bSRamuthevar Vadivel Murugan { 91531fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = param; 91631fb632bSRamuthevar Vadivel Murugan 91731fb632bSRamuthevar Vadivel Murugan complete(&cqspi->rx_dma_complete); 91831fb632bSRamuthevar Vadivel Murugan } 91931fb632bSRamuthevar Vadivel Murugan 92031fb632bSRamuthevar Vadivel Murugan static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata, 92131fb632bSRamuthevar Vadivel Murugan u_char *buf, loff_t from, size_t len) 92231fb632bSRamuthevar Vadivel Murugan { 92331fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 92431fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 92531fb632bSRamuthevar Vadivel Murugan enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; 92631fb632bSRamuthevar Vadivel Murugan dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from; 92731fb632bSRamuthevar Vadivel Murugan int ret = 0; 92831fb632bSRamuthevar Vadivel Murugan struct dma_async_tx_descriptor *tx; 92931fb632bSRamuthevar Vadivel Murugan dma_cookie_t cookie; 93031fb632bSRamuthevar Vadivel Murugan dma_addr_t dma_dst; 93183048015SVignesh Raghavendra struct device *ddev; 93231fb632bSRamuthevar Vadivel Murugan 93331fb632bSRamuthevar Vadivel Murugan if (!cqspi->rx_chan || !virt_addr_valid(buf)) { 93431fb632bSRamuthevar Vadivel Murugan memcpy_fromio(buf, cqspi->ahb_base + from, len); 93531fb632bSRamuthevar Vadivel Murugan return 0; 93631fb632bSRamuthevar Vadivel Murugan } 93731fb632bSRamuthevar Vadivel Murugan 93883048015SVignesh Raghavendra ddev = cqspi->rx_chan->device->dev; 93983048015SVignesh Raghavendra dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE); 94083048015SVignesh Raghavendra if (dma_mapping_error(ddev, dma_dst)) { 94131fb632bSRamuthevar Vadivel Murugan dev_err(dev, "dma mapping failed\n"); 94231fb632bSRamuthevar Vadivel Murugan return -ENOMEM; 94331fb632bSRamuthevar Vadivel Murugan } 94431fb632bSRamuthevar Vadivel Murugan tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src, 94531fb632bSRamuthevar Vadivel Murugan len, flags); 94631fb632bSRamuthevar Vadivel Murugan if (!tx) { 94731fb632bSRamuthevar Vadivel Murugan dev_err(dev, "device_prep_dma_memcpy error\n"); 94831fb632bSRamuthevar Vadivel Murugan ret = -EIO; 94931fb632bSRamuthevar Vadivel Murugan goto err_unmap; 95031fb632bSRamuthevar Vadivel Murugan } 95131fb632bSRamuthevar Vadivel Murugan 95231fb632bSRamuthevar Vadivel Murugan tx->callback = cqspi_rx_dma_callback; 95331fb632bSRamuthevar Vadivel Murugan tx->callback_param = cqspi; 95431fb632bSRamuthevar Vadivel Murugan cookie = tx->tx_submit(tx); 95531fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->rx_dma_complete); 95631fb632bSRamuthevar Vadivel Murugan 95731fb632bSRamuthevar Vadivel Murugan ret = dma_submit_error(cookie); 95831fb632bSRamuthevar Vadivel Murugan if (ret) { 95931fb632bSRamuthevar Vadivel Murugan dev_err(dev, "dma_submit_error %d\n", cookie); 96031fb632bSRamuthevar Vadivel Murugan ret = -EIO; 96131fb632bSRamuthevar Vadivel Murugan goto err_unmap; 96231fb632bSRamuthevar Vadivel Murugan } 96331fb632bSRamuthevar Vadivel Murugan 96431fb632bSRamuthevar Vadivel Murugan dma_async_issue_pending(cqspi->rx_chan); 96531fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->rx_dma_complete, 96631fb632bSRamuthevar Vadivel Murugan msecs_to_jiffies(len))) { 96731fb632bSRamuthevar Vadivel Murugan dmaengine_terminate_sync(cqspi->rx_chan); 96831fb632bSRamuthevar Vadivel Murugan dev_err(dev, "DMA wait_for_completion_timeout\n"); 96931fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 97031fb632bSRamuthevar Vadivel Murugan goto err_unmap; 97131fb632bSRamuthevar Vadivel Murugan } 97231fb632bSRamuthevar Vadivel Murugan 97331fb632bSRamuthevar Vadivel Murugan err_unmap: 97483048015SVignesh Raghavendra dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE); 97531fb632bSRamuthevar Vadivel Murugan 97631fb632bSRamuthevar Vadivel Murugan return ret; 97731fb632bSRamuthevar Vadivel Murugan } 97831fb632bSRamuthevar Vadivel Murugan 97931fb632bSRamuthevar Vadivel Murugan static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata, 98031fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 98131fb632bSRamuthevar Vadivel Murugan { 98231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 98331fb632bSRamuthevar Vadivel Murugan loff_t from = op->addr.val; 98431fb632bSRamuthevar Vadivel Murugan size_t len = op->data.nbytes; 98531fb632bSRamuthevar Vadivel Murugan u_char *buf = op->data.buf.in; 98631fb632bSRamuthevar Vadivel Murugan int ret; 98731fb632bSRamuthevar Vadivel Murugan 98831fb632bSRamuthevar Vadivel Murugan ret = cqspi_set_protocol(f_pdata, op); 98931fb632bSRamuthevar Vadivel Murugan if (ret) 99031fb632bSRamuthevar Vadivel Murugan return ret; 99131fb632bSRamuthevar Vadivel Murugan 99231fb632bSRamuthevar Vadivel Murugan ret = cqspi_read_setup(f_pdata, op); 99331fb632bSRamuthevar Vadivel Murugan if (ret) 99431fb632bSRamuthevar Vadivel Murugan return ret; 99531fb632bSRamuthevar Vadivel Murugan 99631fb632bSRamuthevar Vadivel Murugan if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) 99731fb632bSRamuthevar Vadivel Murugan return cqspi_direct_read_execute(f_pdata, buf, from, len); 99831fb632bSRamuthevar Vadivel Murugan 99931fb632bSRamuthevar Vadivel Murugan return cqspi_indirect_read_execute(f_pdata, buf, from, len); 100031fb632bSRamuthevar Vadivel Murugan } 100131fb632bSRamuthevar Vadivel Murugan 100231fb632bSRamuthevar Vadivel Murugan static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op) 100331fb632bSRamuthevar Vadivel Murugan { 100431fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); 100531fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata; 100631fb632bSRamuthevar Vadivel Murugan 100731fb632bSRamuthevar Vadivel Murugan f_pdata = &cqspi->f_pdata[mem->spi->chip_select]; 100831fb632bSRamuthevar Vadivel Murugan cqspi_configure(f_pdata, mem->spi->max_speed_hz); 100931fb632bSRamuthevar Vadivel Murugan 101031fb632bSRamuthevar Vadivel Murugan if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { 101131fb632bSRamuthevar Vadivel Murugan if (!op->addr.nbytes) 101231fb632bSRamuthevar Vadivel Murugan return cqspi_command_read(f_pdata, op); 101331fb632bSRamuthevar Vadivel Murugan 101431fb632bSRamuthevar Vadivel Murugan return cqspi_read(f_pdata, op); 101531fb632bSRamuthevar Vadivel Murugan } 101631fb632bSRamuthevar Vadivel Murugan 101731fb632bSRamuthevar Vadivel Murugan if (!op->addr.nbytes || !op->data.buf.out) 101831fb632bSRamuthevar Vadivel Murugan return cqspi_command_write(f_pdata, op); 101931fb632bSRamuthevar Vadivel Murugan 102031fb632bSRamuthevar Vadivel Murugan return cqspi_write(f_pdata, op); 102131fb632bSRamuthevar Vadivel Murugan } 102231fb632bSRamuthevar Vadivel Murugan 102331fb632bSRamuthevar Vadivel Murugan static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) 102431fb632bSRamuthevar Vadivel Murugan { 102531fb632bSRamuthevar Vadivel Murugan int ret; 102631fb632bSRamuthevar Vadivel Murugan 102731fb632bSRamuthevar Vadivel Murugan ret = cqspi_mem_process(mem, op); 102831fb632bSRamuthevar Vadivel Murugan if (ret) 102931fb632bSRamuthevar Vadivel Murugan dev_err(&mem->spi->dev, "operation failed with %d\n", ret); 103031fb632bSRamuthevar Vadivel Murugan 103131fb632bSRamuthevar Vadivel Murugan return ret; 103231fb632bSRamuthevar Vadivel Murugan } 103331fb632bSRamuthevar Vadivel Murugan 1034*a273596bSPratyush Yadav static int cqspi_check_buswidth_req(struct spi_mem *mem, u8 buswidth, bool tx) 1035*a273596bSPratyush Yadav { 1036*a273596bSPratyush Yadav u32 mode = mem->spi->mode; 1037*a273596bSPratyush Yadav 1038*a273596bSPratyush Yadav switch (buswidth) { 1039*a273596bSPratyush Yadav case 1: 1040*a273596bSPratyush Yadav return 0; 1041*a273596bSPratyush Yadav 1042*a273596bSPratyush Yadav case 2: 1043*a273596bSPratyush Yadav if ((tx && 1044*a273596bSPratyush Yadav (mode & (SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL))) || 1045*a273596bSPratyush Yadav (!tx && 1046*a273596bSPratyush Yadav (mode & (SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL)))) 1047*a273596bSPratyush Yadav return 0; 1048*a273596bSPratyush Yadav 1049*a273596bSPratyush Yadav break; 1050*a273596bSPratyush Yadav 1051*a273596bSPratyush Yadav case 4: 1052*a273596bSPratyush Yadav if ((tx && (mode & (SPI_TX_QUAD | SPI_TX_OCTAL))) || 1053*a273596bSPratyush Yadav (!tx && (mode & (SPI_RX_QUAD | SPI_RX_OCTAL)))) 1054*a273596bSPratyush Yadav return 0; 1055*a273596bSPratyush Yadav 1056*a273596bSPratyush Yadav break; 1057*a273596bSPratyush Yadav 1058*a273596bSPratyush Yadav case 8: 1059*a273596bSPratyush Yadav if ((tx && (mode & SPI_TX_OCTAL)) || 1060*a273596bSPratyush Yadav (!tx && (mode & SPI_RX_OCTAL))) 1061*a273596bSPratyush Yadav return 0; 1062*a273596bSPratyush Yadav 1063*a273596bSPratyush Yadav break; 1064*a273596bSPratyush Yadav 1065*a273596bSPratyush Yadav default: 1066*a273596bSPratyush Yadav break; 1067*a273596bSPratyush Yadav } 1068*a273596bSPratyush Yadav 1069*a273596bSPratyush Yadav return -EOPNOTSUPP; 1070*a273596bSPratyush Yadav } 1071*a273596bSPratyush Yadav 1072*a273596bSPratyush Yadav static bool cqspi_supports_mem_op(struct spi_mem *mem, 1073*a273596bSPratyush Yadav const struct spi_mem_op *op) 1074*a273596bSPratyush Yadav { 1075*a273596bSPratyush Yadav if (cqspi_check_buswidth_req(mem, op->cmd.buswidth, true)) 1076*a273596bSPratyush Yadav return false; 1077*a273596bSPratyush Yadav 1078*a273596bSPratyush Yadav if (op->addr.nbytes && 1079*a273596bSPratyush Yadav cqspi_check_buswidth_req(mem, op->addr.buswidth, true)) 1080*a273596bSPratyush Yadav return false; 1081*a273596bSPratyush Yadav 1082*a273596bSPratyush Yadav if (op->dummy.nbytes && 1083*a273596bSPratyush Yadav cqspi_check_buswidth_req(mem, op->dummy.buswidth, true)) 1084*a273596bSPratyush Yadav return false; 1085*a273596bSPratyush Yadav 1086*a273596bSPratyush Yadav if (op->data.nbytes && 1087*a273596bSPratyush Yadav cqspi_check_buswidth_req(mem, op->data.buswidth, 1088*a273596bSPratyush Yadav op->data.dir == SPI_MEM_DATA_OUT)) 1089*a273596bSPratyush Yadav return false; 1090*a273596bSPratyush Yadav 1091*a273596bSPratyush Yadav return true; 1092*a273596bSPratyush Yadav } 1093*a273596bSPratyush Yadav 109431fb632bSRamuthevar Vadivel Murugan static int cqspi_of_get_flash_pdata(struct platform_device *pdev, 109531fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata, 109631fb632bSRamuthevar Vadivel Murugan struct device_node *np) 109731fb632bSRamuthevar Vadivel Murugan { 109831fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) { 109931fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine read-delay\n"); 110031fb632bSRamuthevar Vadivel Murugan return -ENXIO; 110131fb632bSRamuthevar Vadivel Murugan } 110231fb632bSRamuthevar Vadivel Murugan 110331fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) { 110431fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tshsl-ns\n"); 110531fb632bSRamuthevar Vadivel Murugan return -ENXIO; 110631fb632bSRamuthevar Vadivel Murugan } 110731fb632bSRamuthevar Vadivel Murugan 110831fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) { 110931fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n"); 111031fb632bSRamuthevar Vadivel Murugan return -ENXIO; 111131fb632bSRamuthevar Vadivel Murugan } 111231fb632bSRamuthevar Vadivel Murugan 111331fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) { 111431fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tchsh-ns\n"); 111531fb632bSRamuthevar Vadivel Murugan return -ENXIO; 111631fb632bSRamuthevar Vadivel Murugan } 111731fb632bSRamuthevar Vadivel Murugan 111831fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) { 111931fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tslch-ns\n"); 112031fb632bSRamuthevar Vadivel Murugan return -ENXIO; 112131fb632bSRamuthevar Vadivel Murugan } 112231fb632bSRamuthevar Vadivel Murugan 112331fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) { 112431fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n"); 112531fb632bSRamuthevar Vadivel Murugan return -ENXIO; 112631fb632bSRamuthevar Vadivel Murugan } 112731fb632bSRamuthevar Vadivel Murugan 112831fb632bSRamuthevar Vadivel Murugan return 0; 112931fb632bSRamuthevar Vadivel Murugan } 113031fb632bSRamuthevar Vadivel Murugan 113131fb632bSRamuthevar Vadivel Murugan static int cqspi_of_get_pdata(struct cqspi_st *cqspi) 113231fb632bSRamuthevar Vadivel Murugan { 113331fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 113431fb632bSRamuthevar Vadivel Murugan struct device_node *np = dev->of_node; 113531fb632bSRamuthevar Vadivel Murugan 113631fb632bSRamuthevar Vadivel Murugan cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); 113731fb632bSRamuthevar Vadivel Murugan 113831fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { 113931fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine fifo-depth\n"); 114031fb632bSRamuthevar Vadivel Murugan return -ENXIO; 114131fb632bSRamuthevar Vadivel Murugan } 114231fb632bSRamuthevar Vadivel Murugan 114331fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) { 114431fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine fifo-width\n"); 114531fb632bSRamuthevar Vadivel Murugan return -ENXIO; 114631fb632bSRamuthevar Vadivel Murugan } 114731fb632bSRamuthevar Vadivel Murugan 114831fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,trigger-address", 114931fb632bSRamuthevar Vadivel Murugan &cqspi->trigger_address)) { 115031fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine trigger-address\n"); 115131fb632bSRamuthevar Vadivel Murugan return -ENXIO; 115231fb632bSRamuthevar Vadivel Murugan } 115331fb632bSRamuthevar Vadivel Murugan 115431fb632bSRamuthevar Vadivel Murugan cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); 115531fb632bSRamuthevar Vadivel Murugan 115631fb632bSRamuthevar Vadivel Murugan return 0; 115731fb632bSRamuthevar Vadivel Murugan } 115831fb632bSRamuthevar Vadivel Murugan 115931fb632bSRamuthevar Vadivel Murugan static void cqspi_controller_init(struct cqspi_st *cqspi) 116031fb632bSRamuthevar Vadivel Murugan { 116131fb632bSRamuthevar Vadivel Murugan u32 reg; 116231fb632bSRamuthevar Vadivel Murugan 116331fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 116431fb632bSRamuthevar Vadivel Murugan 116531fb632bSRamuthevar Vadivel Murugan /* Configure the remap address register, no remap */ 116631fb632bSRamuthevar Vadivel Murugan writel(0, cqspi->iobase + CQSPI_REG_REMAP); 116731fb632bSRamuthevar Vadivel Murugan 116831fb632bSRamuthevar Vadivel Murugan /* Disable all interrupts. */ 116931fb632bSRamuthevar Vadivel Murugan writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); 117031fb632bSRamuthevar Vadivel Murugan 117131fb632bSRamuthevar Vadivel Murugan /* Configure the SRAM split to 1:1 . */ 117231fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); 117331fb632bSRamuthevar Vadivel Murugan 117431fb632bSRamuthevar Vadivel Murugan /* Load indirect trigger address. */ 117531fb632bSRamuthevar Vadivel Murugan writel(cqspi->trigger_address, 117631fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); 117731fb632bSRamuthevar Vadivel Murugan 117831fb632bSRamuthevar Vadivel Murugan /* Program read watermark -- 1/2 of the FIFO. */ 117931fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth * cqspi->fifo_width / 2, 118031fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); 118131fb632bSRamuthevar Vadivel Murugan /* Program write watermark -- 1/8 of the FIFO. */ 118231fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth * cqspi->fifo_width / 8, 118331fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); 118431fb632bSRamuthevar Vadivel Murugan 118531fb632bSRamuthevar Vadivel Murugan /* Enable Direct Access Controller */ 118631fb632bSRamuthevar Vadivel Murugan reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 118731fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL; 118831fb632bSRamuthevar Vadivel Murugan writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 118931fb632bSRamuthevar Vadivel Murugan 119031fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1); 119131fb632bSRamuthevar Vadivel Murugan } 119231fb632bSRamuthevar Vadivel Murugan 119331fb632bSRamuthevar Vadivel Murugan static int cqspi_request_mmap_dma(struct cqspi_st *cqspi) 119431fb632bSRamuthevar Vadivel Murugan { 119531fb632bSRamuthevar Vadivel Murugan dma_cap_mask_t mask; 119631fb632bSRamuthevar Vadivel Murugan 119731fb632bSRamuthevar Vadivel Murugan dma_cap_zero(mask); 119831fb632bSRamuthevar Vadivel Murugan dma_cap_set(DMA_MEMCPY, mask); 119931fb632bSRamuthevar Vadivel Murugan 120031fb632bSRamuthevar Vadivel Murugan cqspi->rx_chan = dma_request_chan_by_mask(&mask); 120131fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->rx_chan)) { 120231fb632bSRamuthevar Vadivel Murugan int ret = PTR_ERR(cqspi->rx_chan); 120331fb632bSRamuthevar Vadivel Murugan cqspi->rx_chan = NULL; 1204436a5c20SKrzysztof Kozlowski return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n"); 120531fb632bSRamuthevar Vadivel Murugan } 120631fb632bSRamuthevar Vadivel Murugan init_completion(&cqspi->rx_dma_complete); 120731fb632bSRamuthevar Vadivel Murugan 120831fb632bSRamuthevar Vadivel Murugan return 0; 120931fb632bSRamuthevar Vadivel Murugan } 121031fb632bSRamuthevar Vadivel Murugan 12112ea370a9SVignesh Raghavendra static const char *cqspi_get_name(struct spi_mem *mem) 12122ea370a9SVignesh Raghavendra { 12132ea370a9SVignesh Raghavendra struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); 12142ea370a9SVignesh Raghavendra struct device *dev = &cqspi->pdev->dev; 12152ea370a9SVignesh Raghavendra 12162ea370a9SVignesh Raghavendra return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select); 12172ea370a9SVignesh Raghavendra } 12182ea370a9SVignesh Raghavendra 121931fb632bSRamuthevar Vadivel Murugan static const struct spi_controller_mem_ops cqspi_mem_ops = { 122031fb632bSRamuthevar Vadivel Murugan .exec_op = cqspi_exec_mem_op, 12212ea370a9SVignesh Raghavendra .get_name = cqspi_get_name, 1222*a273596bSPratyush Yadav .supports_op = cqspi_supports_mem_op, 122331fb632bSRamuthevar Vadivel Murugan }; 122431fb632bSRamuthevar Vadivel Murugan 122531fb632bSRamuthevar Vadivel Murugan static int cqspi_setup_flash(struct cqspi_st *cqspi) 122631fb632bSRamuthevar Vadivel Murugan { 122731fb632bSRamuthevar Vadivel Murugan struct platform_device *pdev = cqspi->pdev; 122831fb632bSRamuthevar Vadivel Murugan struct device *dev = &pdev->dev; 122931fb632bSRamuthevar Vadivel Murugan struct device_node *np = dev->of_node; 123031fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata; 123131fb632bSRamuthevar Vadivel Murugan unsigned int cs; 123231fb632bSRamuthevar Vadivel Murugan int ret; 123331fb632bSRamuthevar Vadivel Murugan 123431fb632bSRamuthevar Vadivel Murugan /* Get flash device data */ 123531fb632bSRamuthevar Vadivel Murugan for_each_available_child_of_node(dev->of_node, np) { 123631fb632bSRamuthevar Vadivel Murugan ret = of_property_read_u32(np, "reg", &cs); 123731fb632bSRamuthevar Vadivel Murugan if (ret) { 123831fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Couldn't determine chip select.\n"); 123931fb632bSRamuthevar Vadivel Murugan return ret; 124031fb632bSRamuthevar Vadivel Murugan } 124131fb632bSRamuthevar Vadivel Murugan 124231fb632bSRamuthevar Vadivel Murugan if (cs >= CQSPI_MAX_CHIPSELECT) { 124331fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Chip select %d out of range.\n", cs); 124431fb632bSRamuthevar Vadivel Murugan return -EINVAL; 124531fb632bSRamuthevar Vadivel Murugan } 124631fb632bSRamuthevar Vadivel Murugan 124731fb632bSRamuthevar Vadivel Murugan f_pdata = &cqspi->f_pdata[cs]; 124831fb632bSRamuthevar Vadivel Murugan f_pdata->cqspi = cqspi; 124931fb632bSRamuthevar Vadivel Murugan f_pdata->cs = cs; 125031fb632bSRamuthevar Vadivel Murugan 125131fb632bSRamuthevar Vadivel Murugan ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np); 125231fb632bSRamuthevar Vadivel Murugan if (ret) 125331fb632bSRamuthevar Vadivel Murugan return ret; 125431fb632bSRamuthevar Vadivel Murugan } 125531fb632bSRamuthevar Vadivel Murugan 125631fb632bSRamuthevar Vadivel Murugan return 0; 125731fb632bSRamuthevar Vadivel Murugan } 125831fb632bSRamuthevar Vadivel Murugan 125931fb632bSRamuthevar Vadivel Murugan static int cqspi_probe(struct platform_device *pdev) 126031fb632bSRamuthevar Vadivel Murugan { 126131fb632bSRamuthevar Vadivel Murugan const struct cqspi_driver_platdata *ddata; 126231fb632bSRamuthevar Vadivel Murugan struct reset_control *rstc, *rstc_ocp; 126331fb632bSRamuthevar Vadivel Murugan struct device *dev = &pdev->dev; 126431fb632bSRamuthevar Vadivel Murugan struct spi_master *master; 126531fb632bSRamuthevar Vadivel Murugan struct resource *res_ahb; 126631fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi; 126731fb632bSRamuthevar Vadivel Murugan struct resource *res; 126831fb632bSRamuthevar Vadivel Murugan int ret; 126931fb632bSRamuthevar Vadivel Murugan int irq; 127031fb632bSRamuthevar Vadivel Murugan 127131fb632bSRamuthevar Vadivel Murugan master = spi_alloc_master(&pdev->dev, sizeof(*cqspi)); 127231fb632bSRamuthevar Vadivel Murugan if (!master) { 127331fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "spi_alloc_master failed\n"); 127431fb632bSRamuthevar Vadivel Murugan return -ENOMEM; 127531fb632bSRamuthevar Vadivel Murugan } 127631fb632bSRamuthevar Vadivel Murugan master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; 127731fb632bSRamuthevar Vadivel Murugan master->mem_ops = &cqspi_mem_ops; 127831fb632bSRamuthevar Vadivel Murugan master->dev.of_node = pdev->dev.of_node; 127931fb632bSRamuthevar Vadivel Murugan 128031fb632bSRamuthevar Vadivel Murugan cqspi = spi_master_get_devdata(master); 128131fb632bSRamuthevar Vadivel Murugan 128231fb632bSRamuthevar Vadivel Murugan cqspi->pdev = pdev; 128331fb632bSRamuthevar Vadivel Murugan 128431fb632bSRamuthevar Vadivel Murugan /* Obtain configuration from OF. */ 128531fb632bSRamuthevar Vadivel Murugan ret = cqspi_of_get_pdata(cqspi); 128631fb632bSRamuthevar Vadivel Murugan if (ret) { 128731fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get mandatory OF data.\n"); 128831fb632bSRamuthevar Vadivel Murugan ret = -ENODEV; 128931fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 129031fb632bSRamuthevar Vadivel Murugan } 129131fb632bSRamuthevar Vadivel Murugan 129231fb632bSRamuthevar Vadivel Murugan /* Obtain QSPI clock. */ 129331fb632bSRamuthevar Vadivel Murugan cqspi->clk = devm_clk_get(dev, NULL); 129431fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->clk)) { 129531fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot claim QSPI clock.\n"); 129631fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->clk); 129731fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 129831fb632bSRamuthevar Vadivel Murugan } 129931fb632bSRamuthevar Vadivel Murugan 130031fb632bSRamuthevar Vadivel Murugan /* Obtain and remap controller address. */ 130131fb632bSRamuthevar Vadivel Murugan res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 130231fb632bSRamuthevar Vadivel Murugan cqspi->iobase = devm_ioremap_resource(dev, res); 130331fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->iobase)) { 130431fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot remap controller address.\n"); 130531fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->iobase); 130631fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 130731fb632bSRamuthevar Vadivel Murugan } 130831fb632bSRamuthevar Vadivel Murugan 130931fb632bSRamuthevar Vadivel Murugan /* Obtain and remap AHB address. */ 131031fb632bSRamuthevar Vadivel Murugan res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1); 131131fb632bSRamuthevar Vadivel Murugan cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb); 131231fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->ahb_base)) { 131331fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot remap AHB address.\n"); 131431fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->ahb_base); 131531fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 131631fb632bSRamuthevar Vadivel Murugan } 131731fb632bSRamuthevar Vadivel Murugan cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start; 131831fb632bSRamuthevar Vadivel Murugan cqspi->ahb_size = resource_size(res_ahb); 131931fb632bSRamuthevar Vadivel Murugan 132031fb632bSRamuthevar Vadivel Murugan init_completion(&cqspi->transfer_complete); 132131fb632bSRamuthevar Vadivel Murugan 132231fb632bSRamuthevar Vadivel Murugan /* Obtain IRQ line. */ 132331fb632bSRamuthevar Vadivel Murugan irq = platform_get_irq(pdev, 0); 132431fb632bSRamuthevar Vadivel Murugan if (irq < 0) { 132531fb632bSRamuthevar Vadivel Murugan ret = -ENXIO; 132631fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 132731fb632bSRamuthevar Vadivel Murugan } 132831fb632bSRamuthevar Vadivel Murugan 132931fb632bSRamuthevar Vadivel Murugan pm_runtime_enable(dev); 133031fb632bSRamuthevar Vadivel Murugan ret = pm_runtime_get_sync(dev); 133131fb632bSRamuthevar Vadivel Murugan if (ret < 0) { 133231fb632bSRamuthevar Vadivel Murugan pm_runtime_put_noidle(dev); 133331fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 133431fb632bSRamuthevar Vadivel Murugan } 133531fb632bSRamuthevar Vadivel Murugan 133631fb632bSRamuthevar Vadivel Murugan ret = clk_prepare_enable(cqspi->clk); 133731fb632bSRamuthevar Vadivel Murugan if (ret) { 133831fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot enable QSPI clock.\n"); 133931fb632bSRamuthevar Vadivel Murugan goto probe_clk_failed; 134031fb632bSRamuthevar Vadivel Murugan } 134131fb632bSRamuthevar Vadivel Murugan 134231fb632bSRamuthevar Vadivel Murugan /* Obtain QSPI reset control */ 134331fb632bSRamuthevar Vadivel Murugan rstc = devm_reset_control_get_optional_exclusive(dev, "qspi"); 134431fb632bSRamuthevar Vadivel Murugan if (IS_ERR(rstc)) { 1345ac9978fcSZhihao Cheng ret = PTR_ERR(rstc); 134631fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get QSPI reset.\n"); 134731fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 134831fb632bSRamuthevar Vadivel Murugan } 134931fb632bSRamuthevar Vadivel Murugan 135031fb632bSRamuthevar Vadivel Murugan rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); 135131fb632bSRamuthevar Vadivel Murugan if (IS_ERR(rstc_ocp)) { 1352ac9978fcSZhihao Cheng ret = PTR_ERR(rstc_ocp); 135331fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get QSPI OCP reset.\n"); 135431fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 135531fb632bSRamuthevar Vadivel Murugan } 135631fb632bSRamuthevar Vadivel Murugan 135731fb632bSRamuthevar Vadivel Murugan reset_control_assert(rstc); 135831fb632bSRamuthevar Vadivel Murugan reset_control_deassert(rstc); 135931fb632bSRamuthevar Vadivel Murugan 136031fb632bSRamuthevar Vadivel Murugan reset_control_assert(rstc_ocp); 136131fb632bSRamuthevar Vadivel Murugan reset_control_deassert(rstc_ocp); 136231fb632bSRamuthevar Vadivel Murugan 136331fb632bSRamuthevar Vadivel Murugan cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); 13643a5c09c8SPratyush Yadav master->max_speed_hz = cqspi->master_ref_clk_hz; 136531fb632bSRamuthevar Vadivel Murugan ddata = of_device_get_match_data(dev); 136631fb632bSRamuthevar Vadivel Murugan if (ddata) { 136731fb632bSRamuthevar Vadivel Murugan if (ddata->quirks & CQSPI_NEEDS_WR_DELAY) 136831fb632bSRamuthevar Vadivel Murugan cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC, 136931fb632bSRamuthevar Vadivel Murugan cqspi->master_ref_clk_hz); 137031fb632bSRamuthevar Vadivel Murugan if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL) 137131fb632bSRamuthevar Vadivel Murugan master->mode_bits |= SPI_RX_OCTAL; 137231fb632bSRamuthevar Vadivel Murugan if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) 137331fb632bSRamuthevar Vadivel Murugan cqspi->use_direct_mode = true; 137431fb632bSRamuthevar Vadivel Murugan } 137531fb632bSRamuthevar Vadivel Murugan 137631fb632bSRamuthevar Vadivel Murugan ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0, 137731fb632bSRamuthevar Vadivel Murugan pdev->name, cqspi); 137831fb632bSRamuthevar Vadivel Murugan if (ret) { 137931fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot request IRQ.\n"); 138031fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 138131fb632bSRamuthevar Vadivel Murugan } 138231fb632bSRamuthevar Vadivel Murugan 138331fb632bSRamuthevar Vadivel Murugan cqspi_wait_idle(cqspi); 138431fb632bSRamuthevar Vadivel Murugan cqspi_controller_init(cqspi); 138531fb632bSRamuthevar Vadivel Murugan cqspi->current_cs = -1; 138631fb632bSRamuthevar Vadivel Murugan cqspi->sclk = 0; 138731fb632bSRamuthevar Vadivel Murugan 138831fb632bSRamuthevar Vadivel Murugan ret = cqspi_setup_flash(cqspi); 138931fb632bSRamuthevar Vadivel Murugan if (ret) { 139031fb632bSRamuthevar Vadivel Murugan dev_err(dev, "failed to setup flash parameters %d\n", ret); 139131fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 139231fb632bSRamuthevar Vadivel Murugan } 139331fb632bSRamuthevar Vadivel Murugan 139431fb632bSRamuthevar Vadivel Murugan if (cqspi->use_direct_mode) { 139531fb632bSRamuthevar Vadivel Murugan ret = cqspi_request_mmap_dma(cqspi); 139631fb632bSRamuthevar Vadivel Murugan if (ret == -EPROBE_DEFER) 139731fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 139831fb632bSRamuthevar Vadivel Murugan } 139931fb632bSRamuthevar Vadivel Murugan 140031fb632bSRamuthevar Vadivel Murugan ret = devm_spi_register_master(dev, master); 140131fb632bSRamuthevar Vadivel Murugan if (ret) { 140231fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret); 140331fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 140431fb632bSRamuthevar Vadivel Murugan } 140531fb632bSRamuthevar Vadivel Murugan 140631fb632bSRamuthevar Vadivel Murugan return 0; 140731fb632bSRamuthevar Vadivel Murugan probe_setup_failed: 140831fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 140931fb632bSRamuthevar Vadivel Murugan probe_reset_failed: 141031fb632bSRamuthevar Vadivel Murugan clk_disable_unprepare(cqspi->clk); 141131fb632bSRamuthevar Vadivel Murugan probe_clk_failed: 141231fb632bSRamuthevar Vadivel Murugan pm_runtime_put_sync(dev); 141331fb632bSRamuthevar Vadivel Murugan pm_runtime_disable(dev); 141431fb632bSRamuthevar Vadivel Murugan probe_master_put: 141531fb632bSRamuthevar Vadivel Murugan spi_master_put(master); 141631fb632bSRamuthevar Vadivel Murugan return ret; 141731fb632bSRamuthevar Vadivel Murugan } 141831fb632bSRamuthevar Vadivel Murugan 141931fb632bSRamuthevar Vadivel Murugan static int cqspi_remove(struct platform_device *pdev) 142031fb632bSRamuthevar Vadivel Murugan { 142131fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = platform_get_drvdata(pdev); 142231fb632bSRamuthevar Vadivel Murugan 142331fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 142431fb632bSRamuthevar Vadivel Murugan 142531fb632bSRamuthevar Vadivel Murugan if (cqspi->rx_chan) 142631fb632bSRamuthevar Vadivel Murugan dma_release_channel(cqspi->rx_chan); 142731fb632bSRamuthevar Vadivel Murugan 142831fb632bSRamuthevar Vadivel Murugan clk_disable_unprepare(cqspi->clk); 142931fb632bSRamuthevar Vadivel Murugan 143031fb632bSRamuthevar Vadivel Murugan pm_runtime_put_sync(&pdev->dev); 143131fb632bSRamuthevar Vadivel Murugan pm_runtime_disable(&pdev->dev); 143231fb632bSRamuthevar Vadivel Murugan 143331fb632bSRamuthevar Vadivel Murugan return 0; 143431fb632bSRamuthevar Vadivel Murugan } 143531fb632bSRamuthevar Vadivel Murugan 143631fb632bSRamuthevar Vadivel Murugan #ifdef CONFIG_PM_SLEEP 143731fb632bSRamuthevar Vadivel Murugan static int cqspi_suspend(struct device *dev) 143831fb632bSRamuthevar Vadivel Murugan { 143931fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev_get_drvdata(dev); 144031fb632bSRamuthevar Vadivel Murugan 144131fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 144231fb632bSRamuthevar Vadivel Murugan return 0; 144331fb632bSRamuthevar Vadivel Murugan } 144431fb632bSRamuthevar Vadivel Murugan 144531fb632bSRamuthevar Vadivel Murugan static int cqspi_resume(struct device *dev) 144631fb632bSRamuthevar Vadivel Murugan { 144731fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev_get_drvdata(dev); 144831fb632bSRamuthevar Vadivel Murugan 144931fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1); 145031fb632bSRamuthevar Vadivel Murugan return 0; 145131fb632bSRamuthevar Vadivel Murugan } 145231fb632bSRamuthevar Vadivel Murugan 145331fb632bSRamuthevar Vadivel Murugan static const struct dev_pm_ops cqspi__dev_pm_ops = { 145431fb632bSRamuthevar Vadivel Murugan .suspend = cqspi_suspend, 145531fb632bSRamuthevar Vadivel Murugan .resume = cqspi_resume, 145631fb632bSRamuthevar Vadivel Murugan }; 145731fb632bSRamuthevar Vadivel Murugan 145831fb632bSRamuthevar Vadivel Murugan #define CQSPI_DEV_PM_OPS (&cqspi__dev_pm_ops) 145931fb632bSRamuthevar Vadivel Murugan #else 146031fb632bSRamuthevar Vadivel Murugan #define CQSPI_DEV_PM_OPS NULL 146131fb632bSRamuthevar Vadivel Murugan #endif 146231fb632bSRamuthevar Vadivel Murugan 146331fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata cdns_qspi = { 146431fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_DISABLE_DAC_MODE, 146531fb632bSRamuthevar Vadivel Murugan }; 146631fb632bSRamuthevar Vadivel Murugan 146731fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata k2g_qspi = { 146831fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_NEEDS_WR_DELAY, 146931fb632bSRamuthevar Vadivel Murugan }; 147031fb632bSRamuthevar Vadivel Murugan 147131fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata am654_ospi = { 147231fb632bSRamuthevar Vadivel Murugan .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 147331fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_NEEDS_WR_DELAY, 147431fb632bSRamuthevar Vadivel Murugan }; 147531fb632bSRamuthevar Vadivel Murugan 147631fb632bSRamuthevar Vadivel Murugan static const struct of_device_id cqspi_dt_ids[] = { 147731fb632bSRamuthevar Vadivel Murugan { 147831fb632bSRamuthevar Vadivel Murugan .compatible = "cdns,qspi-nor", 147931fb632bSRamuthevar Vadivel Murugan .data = &cdns_qspi, 148031fb632bSRamuthevar Vadivel Murugan }, 148131fb632bSRamuthevar Vadivel Murugan { 148231fb632bSRamuthevar Vadivel Murugan .compatible = "ti,k2g-qspi", 148331fb632bSRamuthevar Vadivel Murugan .data = &k2g_qspi, 148431fb632bSRamuthevar Vadivel Murugan }, 148531fb632bSRamuthevar Vadivel Murugan { 148631fb632bSRamuthevar Vadivel Murugan .compatible = "ti,am654-ospi", 148731fb632bSRamuthevar Vadivel Murugan .data = &am654_ospi, 148831fb632bSRamuthevar Vadivel Murugan }, 148931fb632bSRamuthevar Vadivel Murugan { /* end of table */ } 149031fb632bSRamuthevar Vadivel Murugan }; 149131fb632bSRamuthevar Vadivel Murugan 149231fb632bSRamuthevar Vadivel Murugan MODULE_DEVICE_TABLE(of, cqspi_dt_ids); 149331fb632bSRamuthevar Vadivel Murugan 149431fb632bSRamuthevar Vadivel Murugan static struct platform_driver cqspi_platform_driver = { 149531fb632bSRamuthevar Vadivel Murugan .probe = cqspi_probe, 149631fb632bSRamuthevar Vadivel Murugan .remove = cqspi_remove, 149731fb632bSRamuthevar Vadivel Murugan .driver = { 149831fb632bSRamuthevar Vadivel Murugan .name = CQSPI_NAME, 149931fb632bSRamuthevar Vadivel Murugan .pm = CQSPI_DEV_PM_OPS, 150031fb632bSRamuthevar Vadivel Murugan .of_match_table = cqspi_dt_ids, 150131fb632bSRamuthevar Vadivel Murugan }, 150231fb632bSRamuthevar Vadivel Murugan }; 150331fb632bSRamuthevar Vadivel Murugan 150431fb632bSRamuthevar Vadivel Murugan module_platform_driver(cqspi_platform_driver); 150531fb632bSRamuthevar Vadivel Murugan 150631fb632bSRamuthevar Vadivel Murugan MODULE_DESCRIPTION("Cadence QSPI Controller Driver"); 150731fb632bSRamuthevar Vadivel Murugan MODULE_LICENSE("GPL v2"); 150831fb632bSRamuthevar Vadivel Murugan MODULE_ALIAS("platform:" CQSPI_NAME); 150931fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>"); 151031fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>"); 151131fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>"); 151231fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>"); 1513