131fb632bSRamuthevar Vadivel Murugan // SPDX-License-Identifier: GPL-2.0-only 231fb632bSRamuthevar Vadivel Murugan // 331fb632bSRamuthevar Vadivel Murugan // Driver for Cadence QSPI Controller 431fb632bSRamuthevar Vadivel Murugan // 531fb632bSRamuthevar Vadivel Murugan // Copyright Altera Corporation (C) 2012-2014. All rights reserved. 631fb632bSRamuthevar Vadivel Murugan // Copyright Intel Corporation (C) 2019-2020. All rights reserved. 731fb632bSRamuthevar Vadivel Murugan // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 831fb632bSRamuthevar Vadivel Murugan 931fb632bSRamuthevar Vadivel Murugan #include <linux/clk.h> 1031fb632bSRamuthevar Vadivel Murugan #include <linux/completion.h> 1131fb632bSRamuthevar Vadivel Murugan #include <linux/delay.h> 1231fb632bSRamuthevar Vadivel Murugan #include <linux/dma-mapping.h> 1331fb632bSRamuthevar Vadivel Murugan #include <linux/dmaengine.h> 1431fb632bSRamuthevar Vadivel Murugan #include <linux/err.h> 1531fb632bSRamuthevar Vadivel Murugan #include <linux/errno.h> 1609e393e3SSai Krishna Potthuri #include <linux/firmware/xlnx-zynqmp.h> 1731fb632bSRamuthevar Vadivel Murugan #include <linux/interrupt.h> 1831fb632bSRamuthevar Vadivel Murugan #include <linux/io.h> 1931fb632bSRamuthevar Vadivel Murugan #include <linux/iopoll.h> 2031fb632bSRamuthevar Vadivel Murugan #include <linux/jiffies.h> 2131fb632bSRamuthevar Vadivel Murugan #include <linux/kernel.h> 22*97e4827dSMatthias Schiffer #include <linux/log2.h> 2331fb632bSRamuthevar Vadivel Murugan #include <linux/module.h> 2431fb632bSRamuthevar Vadivel Murugan #include <linux/of_device.h> 2531fb632bSRamuthevar Vadivel Murugan #include <linux/of.h> 2631fb632bSRamuthevar Vadivel Murugan #include <linux/platform_device.h> 2731fb632bSRamuthevar Vadivel Murugan #include <linux/pm_runtime.h> 2831fb632bSRamuthevar Vadivel Murugan #include <linux/reset.h> 2931fb632bSRamuthevar Vadivel Murugan #include <linux/sched.h> 3031fb632bSRamuthevar Vadivel Murugan #include <linux/spi/spi.h> 3131fb632bSRamuthevar Vadivel Murugan #include <linux/spi/spi-mem.h> 3231fb632bSRamuthevar Vadivel Murugan #include <linux/timer.h> 3331fb632bSRamuthevar Vadivel Murugan 3431fb632bSRamuthevar Vadivel Murugan #define CQSPI_NAME "cadence-qspi" 3531fb632bSRamuthevar Vadivel Murugan #define CQSPI_MAX_CHIPSELECT 16 3631fb632bSRamuthevar Vadivel Murugan 3731fb632bSRamuthevar Vadivel Murugan /* Quirks */ 3831fb632bSRamuthevar Vadivel Murugan #define CQSPI_NEEDS_WR_DELAY BIT(0) 3931fb632bSRamuthevar Vadivel Murugan #define CQSPI_DISABLE_DAC_MODE BIT(1) 401a6f854fSSai Krishna Potthuri #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) 4198d948ebSDinh Nguyen #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) 4231fb632bSRamuthevar Vadivel Murugan 4331fb632bSRamuthevar Vadivel Murugan /* Capabilities */ 4431fb632bSRamuthevar Vadivel Murugan #define CQSPI_SUPPORTS_OCTAL BIT(0) 4531fb632bSRamuthevar Vadivel Murugan 4631fb632bSRamuthevar Vadivel Murugan struct cqspi_st; 4731fb632bSRamuthevar Vadivel Murugan 4831fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata { 4931fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi; 5031fb632bSRamuthevar Vadivel Murugan u32 clk_rate; 5131fb632bSRamuthevar Vadivel Murugan u32 read_delay; 5231fb632bSRamuthevar Vadivel Murugan u32 tshsl_ns; 5331fb632bSRamuthevar Vadivel Murugan u32 tsd2d_ns; 5431fb632bSRamuthevar Vadivel Murugan u32 tchsh_ns; 5531fb632bSRamuthevar Vadivel Murugan u32 tslch_ns; 5631fb632bSRamuthevar Vadivel Murugan u8 inst_width; 5731fb632bSRamuthevar Vadivel Murugan u8 addr_width; 5831fb632bSRamuthevar Vadivel Murugan u8 data_width; 59f453f293SPratyush Yadav bool dtr; 6031fb632bSRamuthevar Vadivel Murugan u8 cs; 6131fb632bSRamuthevar Vadivel Murugan }; 6231fb632bSRamuthevar Vadivel Murugan 6331fb632bSRamuthevar Vadivel Murugan struct cqspi_st { 6431fb632bSRamuthevar Vadivel Murugan struct platform_device *pdev; 6531fb632bSRamuthevar Vadivel Murugan 6631fb632bSRamuthevar Vadivel Murugan struct clk *clk; 6731fb632bSRamuthevar Vadivel Murugan unsigned int sclk; 6831fb632bSRamuthevar Vadivel Murugan 6931fb632bSRamuthevar Vadivel Murugan void __iomem *iobase; 7031fb632bSRamuthevar Vadivel Murugan void __iomem *ahb_base; 7131fb632bSRamuthevar Vadivel Murugan resource_size_t ahb_size; 7231fb632bSRamuthevar Vadivel Murugan struct completion transfer_complete; 7331fb632bSRamuthevar Vadivel Murugan 7431fb632bSRamuthevar Vadivel Murugan struct dma_chan *rx_chan; 7531fb632bSRamuthevar Vadivel Murugan struct completion rx_dma_complete; 7631fb632bSRamuthevar Vadivel Murugan dma_addr_t mmap_phys_base; 7731fb632bSRamuthevar Vadivel Murugan 7831fb632bSRamuthevar Vadivel Murugan int current_cs; 7931fb632bSRamuthevar Vadivel Murugan unsigned long master_ref_clk_hz; 8031fb632bSRamuthevar Vadivel Murugan bool is_decoded_cs; 8131fb632bSRamuthevar Vadivel Murugan u32 fifo_depth; 8231fb632bSRamuthevar Vadivel Murugan u32 fifo_width; 83b436fb7dSRamuthevar Vadivel Murugan u32 num_chipselect; 8431fb632bSRamuthevar Vadivel Murugan bool rclk_en; 8531fb632bSRamuthevar Vadivel Murugan u32 trigger_address; 8631fb632bSRamuthevar Vadivel Murugan u32 wr_delay; 8731fb632bSRamuthevar Vadivel Murugan bool use_direct_mode; 8831fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; 891a6f854fSSai Krishna Potthuri bool use_dma_read; 9009e393e3SSai Krishna Potthuri u32 pd_dev_id; 9198d948ebSDinh Nguyen bool wr_completion; 9231fb632bSRamuthevar Vadivel Murugan }; 9331fb632bSRamuthevar Vadivel Murugan 9431fb632bSRamuthevar Vadivel Murugan struct cqspi_driver_platdata { 9531fb632bSRamuthevar Vadivel Murugan u32 hwcaps_mask; 9631fb632bSRamuthevar Vadivel Murugan u8 quirks; 971a6f854fSSai Krishna Potthuri int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata, 981a6f854fSSai Krishna Potthuri u_char *rxbuf, loff_t from_addr, size_t n_rx); 991a6f854fSSai Krishna Potthuri u32 (*get_dma_status)(struct cqspi_st *cqspi); 10031fb632bSRamuthevar Vadivel Murugan }; 10131fb632bSRamuthevar Vadivel Murugan 10231fb632bSRamuthevar Vadivel Murugan /* Operation timeout value */ 10331fb632bSRamuthevar Vadivel Murugan #define CQSPI_TIMEOUT_MS 500 10431fb632bSRamuthevar Vadivel Murugan #define CQSPI_READ_TIMEOUT_MS 10 10531fb632bSRamuthevar Vadivel Murugan 10631fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_CLKS_PER_BYTE 8 10731fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_BYTES_MAX 4 10831fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_CLKS_MAX 31 10931fb632bSRamuthevar Vadivel Murugan 11031fb632bSRamuthevar Vadivel Murugan #define CQSPI_STIG_DATA_LEN_MAX 8 11131fb632bSRamuthevar Vadivel Murugan 11231fb632bSRamuthevar Vadivel Murugan /* Register map */ 11331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG 0x00 11431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0) 11531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7) 11631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9) 11731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 11831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_DMA_MASK BIT(15) 11931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_BAUD_LSB 19 120f453f293SPratyush Yadav #define CQSPI_REG_CONFIG_DTR_PROTO BIT(24) 121f453f293SPratyush Yadav #define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30) 12231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_IDLE_LSB 31 12331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF 12431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_BAUD_MASK 0xF 12531fb632bSRamuthevar Vadivel Murugan 12631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR 0x04 12731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 12831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 12931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 13031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 13131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 13231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 13331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 13431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 13531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 13631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F 13731fb632bSRamuthevar Vadivel Murugan 13831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR 0x08 13931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 14031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12 14131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16 14231fb632bSRamuthevar Vadivel Murugan 14331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY 0x0C 14431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSLCH_LSB 0 14531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TCHSH_LSB 8 14631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSD2D_LSB 16 14731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSHSL_LSB 24 14831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF 14931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF 15031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF 15131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF 15231fb632bSRamuthevar Vadivel Murugan 15331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE 0x10 15431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0 15531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_DELAY_LSB 1 15631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF 15731fb632bSRamuthevar Vadivel Murugan 15831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE 0x14 15931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_ADDRESS_LSB 0 16031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_PAGE_LSB 4 16131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_BLOCK_LSB 16 16231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF 16331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF 16431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F 16531fb632bSRamuthevar Vadivel Murugan 16631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SRAMPARTITION 0x18 16731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTTRIGGER 0x1C 16831fb632bSRamuthevar Vadivel Murugan 16931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA 0x20 17031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_SINGLE_LSB 0 17131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_BURST_LSB 8 17231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_SINGLE_MASK 0xFF 17331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_BURST_MASK 0xFF 17431fb632bSRamuthevar Vadivel Murugan 17531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_REMAP 0x24 17631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_MODE_BIT 0x28 17731fb632bSRamuthevar Vadivel Murugan 17831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL 0x2C 17931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 18031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 18131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF 18231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF 18331fb632bSRamuthevar Vadivel Murugan 184f453f293SPratyush Yadav #define CQSPI_REG_WR_COMPLETION_CTRL 0x38 185f453f293SPratyush Yadav #define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14) 186f453f293SPratyush Yadav 18731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQSTATUS 0x40 18831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQMASK 0x44 18931fb632bSRamuthevar Vadivel Murugan 19031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD 0x60 19131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0) 19231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1) 19331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5) 19431fb632bSRamuthevar Vadivel Murugan 19531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDWATERMARK 0x64 19631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 19731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDBYTES 0x6C 19831fb632bSRamuthevar Vadivel Murugan 19931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL 0x90 20031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0) 20131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1) 202888d517bSPratyush Yadav #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 20331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 20431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 20531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 20631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 20731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 20831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 20931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 21031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 21131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 21231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 213888d517bSPratyush Yadav #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F 21431fb632bSRamuthevar Vadivel Murugan 21531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR 0x70 21631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0) 21731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1) 21831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5) 21931fb632bSRamuthevar Vadivel Murugan 22031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRWATERMARK 0x74 22131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 22231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRBYTES 0x7C 22331fb632bSRamuthevar Vadivel Murugan 2241a6f854fSSai Krishna Potthuri #define CQSPI_REG_INDTRIG_ADDRRANGE 0x80 2251a6f854fSSai Krishna Potthuri 22631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDADDRESS 0x94 22731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDREADDATALOWER 0xA0 22831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDREADDATAUPPER 0xA4 22931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDWRITEDATALOWER 0xA8 23031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC 23131fb632bSRamuthevar Vadivel Murugan 232f453f293SPratyush Yadav #define CQSPI_REG_POLLING_STATUS 0xB0 233f453f293SPratyush Yadav #define CQSPI_REG_POLLING_STATUS_DUMMY_LSB 16 234f453f293SPratyush Yadav 235f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_LOWER 0xE0 236f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_READ_LSB 24 237f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_WRITE_LSB 16 238f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_STIG_LSB 0 239f453f293SPratyush Yadav 2401a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_SRC_ADDR 0x1000 2411a6f854fSSai Krishna Potthuri 2421a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_ADDR 0x1800 2431a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_SIZE 0x1804 2441a6f854fSSai Krishna Potthuri 2451a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_CTRL 0x180C 2461a6f854fSSai Krishna Potthuri 2471a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_I_STS 0x1814 2481a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_I_EN 0x1818 2491a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_I_DIS 0x181C 2501a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_DONE_MASK BIT(1) 2511a6f854fSSai Krishna Potthuri 2521a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB 0x1828 2531a6f854fSSai Krishna Potthuri 2541a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL 0xF43FFA00 2551a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL 0x6 2561a6f854fSSai Krishna Potthuri 25731fb632bSRamuthevar Vadivel Murugan /* Interrupt status bits */ 25831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_MODE_ERR BIT(0) 25931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_UNDERFLOW BIT(1) 26031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_COMP BIT(2) 26131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3) 26231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4) 26331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5) 26431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_WATERMARK BIT(6) 26531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12) 26631fb632bSRamuthevar Vadivel Murugan 26731fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \ 26831fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_IND_SRAM_FULL | \ 26931fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_IND_COMP) 27031fb632bSRamuthevar Vadivel Murugan 27131fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \ 27231fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_WATERMARK | \ 27331fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_UNDERFLOW) 27431fb632bSRamuthevar Vadivel Murugan 27531fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_STATUS_MASK 0x1FFFF 2761a6f854fSSai Krishna Potthuri #define CQSPI_DMA_UNALIGN 0x3 2771a6f854fSSai Krishna Potthuri 2781a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_VAL 0x602 27931fb632bSRamuthevar Vadivel Murugan 28031fb632bSRamuthevar Vadivel Murugan static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr) 28131fb632bSRamuthevar Vadivel Murugan { 28231fb632bSRamuthevar Vadivel Murugan u32 val; 28331fb632bSRamuthevar Vadivel Murugan 28431fb632bSRamuthevar Vadivel Murugan return readl_relaxed_poll_timeout(reg, val, 28531fb632bSRamuthevar Vadivel Murugan (((clr ? ~val : val) & mask) == mask), 28631fb632bSRamuthevar Vadivel Murugan 10, CQSPI_TIMEOUT_MS * 1000); 28731fb632bSRamuthevar Vadivel Murugan } 28831fb632bSRamuthevar Vadivel Murugan 28931fb632bSRamuthevar Vadivel Murugan static bool cqspi_is_idle(struct cqspi_st *cqspi) 29031fb632bSRamuthevar Vadivel Murugan { 29131fb632bSRamuthevar Vadivel Murugan u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 29231fb632bSRamuthevar Vadivel Murugan 29331890269SJay Fang return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB); 29431fb632bSRamuthevar Vadivel Murugan } 29531fb632bSRamuthevar Vadivel Murugan 29631fb632bSRamuthevar Vadivel Murugan static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi) 29731fb632bSRamuthevar Vadivel Murugan { 29831fb632bSRamuthevar Vadivel Murugan u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL); 29931fb632bSRamuthevar Vadivel Murugan 30031fb632bSRamuthevar Vadivel Murugan reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB; 30131fb632bSRamuthevar Vadivel Murugan return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK; 30231fb632bSRamuthevar Vadivel Murugan } 30331fb632bSRamuthevar Vadivel Murugan 3041a6f854fSSai Krishna Potthuri static u32 cqspi_get_versal_dma_status(struct cqspi_st *cqspi) 3051a6f854fSSai Krishna Potthuri { 3061a6f854fSSai Krishna Potthuri u32 dma_status; 3071a6f854fSSai Krishna Potthuri 3081a6f854fSSai Krishna Potthuri dma_status = readl(cqspi->iobase + 3091a6f854fSSai Krishna Potthuri CQSPI_REG_VERSAL_DMA_DST_I_STS); 3101a6f854fSSai Krishna Potthuri writel(dma_status, cqspi->iobase + 3111a6f854fSSai Krishna Potthuri CQSPI_REG_VERSAL_DMA_DST_I_STS); 3121a6f854fSSai Krishna Potthuri 3131a6f854fSSai Krishna Potthuri return dma_status & CQSPI_REG_VERSAL_DMA_DST_DONE_MASK; 3141a6f854fSSai Krishna Potthuri } 3151a6f854fSSai Krishna Potthuri 31631fb632bSRamuthevar Vadivel Murugan static irqreturn_t cqspi_irq_handler(int this_irq, void *dev) 31731fb632bSRamuthevar Vadivel Murugan { 31831fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev; 31931fb632bSRamuthevar Vadivel Murugan unsigned int irq_status; 3201a6f854fSSai Krishna Potthuri struct device *device = &cqspi->pdev->dev; 3211a6f854fSSai Krishna Potthuri const struct cqspi_driver_platdata *ddata; 3221a6f854fSSai Krishna Potthuri 3231a6f854fSSai Krishna Potthuri ddata = of_device_get_match_data(device); 32431fb632bSRamuthevar Vadivel Murugan 32531fb632bSRamuthevar Vadivel Murugan /* Read interrupt status */ 32631fb632bSRamuthevar Vadivel Murugan irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS); 32731fb632bSRamuthevar Vadivel Murugan 32831fb632bSRamuthevar Vadivel Murugan /* Clear interrupt */ 32931fb632bSRamuthevar Vadivel Murugan writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS); 33031fb632bSRamuthevar Vadivel Murugan 3311a6f854fSSai Krishna Potthuri if (cqspi->use_dma_read && ddata && ddata->get_dma_status) { 3321a6f854fSSai Krishna Potthuri if (ddata->get_dma_status(cqspi)) { 3331a6f854fSSai Krishna Potthuri complete(&cqspi->transfer_complete); 3341a6f854fSSai Krishna Potthuri return IRQ_HANDLED; 3351a6f854fSSai Krishna Potthuri } 3361a6f854fSSai Krishna Potthuri } 3371a6f854fSSai Krishna Potthuri 33831fb632bSRamuthevar Vadivel Murugan irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR; 33931fb632bSRamuthevar Vadivel Murugan 34031fb632bSRamuthevar Vadivel Murugan if (irq_status) 34131fb632bSRamuthevar Vadivel Murugan complete(&cqspi->transfer_complete); 34231fb632bSRamuthevar Vadivel Murugan 34331fb632bSRamuthevar Vadivel Murugan return IRQ_HANDLED; 34431fb632bSRamuthevar Vadivel Murugan } 34531fb632bSRamuthevar Vadivel Murugan 34631fb632bSRamuthevar Vadivel Murugan static unsigned int cqspi_calc_rdreg(struct cqspi_flash_pdata *f_pdata) 34731fb632bSRamuthevar Vadivel Murugan { 34831fb632bSRamuthevar Vadivel Murugan u32 rdreg = 0; 34931fb632bSRamuthevar Vadivel Murugan 35031fb632bSRamuthevar Vadivel Murugan rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; 35131fb632bSRamuthevar Vadivel Murugan rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; 35231fb632bSRamuthevar Vadivel Murugan rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; 35331fb632bSRamuthevar Vadivel Murugan 35431fb632bSRamuthevar Vadivel Murugan return rdreg; 35531fb632bSRamuthevar Vadivel Murugan } 35631fb632bSRamuthevar Vadivel Murugan 357f453f293SPratyush Yadav static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op, bool dtr) 358888d517bSPratyush Yadav { 3590ccfd1baSYoshitaka Ikeda unsigned int dummy_clk; 360888d517bSPratyush Yadav 3610e85ee89SYoshitaka Ikeda if (!op->dummy.nbytes) 3620e85ee89SYoshitaka Ikeda return 0; 3630e85ee89SYoshitaka Ikeda 3647512eaf5SPratyush Yadav dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth); 365f453f293SPratyush Yadav if (dtr) 366f453f293SPratyush Yadav dummy_clk /= 2; 367888d517bSPratyush Yadav 368888d517bSPratyush Yadav return dummy_clk; 369888d517bSPratyush Yadav } 370888d517bSPratyush Yadav 371f453f293SPratyush Yadav static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata, 372f453f293SPratyush Yadav const struct spi_mem_op *op) 373f453f293SPratyush Yadav { 3740395be96SApurva Nandan /* 3750395be96SApurva Nandan * For an op to be DTR, cmd phase along with every other non-empty 3760395be96SApurva Nandan * phase should have dtr field set to 1. If an op phase has zero 3770395be96SApurva Nandan * nbytes, ignore its dtr field; otherwise, check its dtr field. 3780395be96SApurva Nandan */ 3790395be96SApurva Nandan f_pdata->dtr = op->cmd.dtr && 3800395be96SApurva Nandan (!op->addr.nbytes || op->addr.dtr) && 3810395be96SApurva Nandan (!op->data.nbytes || op->data.dtr); 382f453f293SPratyush Yadav 383*97e4827dSMatthias Schiffer f_pdata->inst_width = 0; 384*97e4827dSMatthias Schiffer if (op->cmd.buswidth) 385*97e4827dSMatthias Schiffer f_pdata->inst_width = ilog2(op->cmd.buswidth); 386*97e4827dSMatthias Schiffer 387*97e4827dSMatthias Schiffer f_pdata->addr_width = 0; 388*97e4827dSMatthias Schiffer if (op->addr.buswidth) 389*97e4827dSMatthias Schiffer f_pdata->addr_width = ilog2(op->addr.buswidth); 390*97e4827dSMatthias Schiffer 391*97e4827dSMatthias Schiffer f_pdata->data_width = 0; 392*97e4827dSMatthias Schiffer if (op->data.buswidth) 393*97e4827dSMatthias Schiffer f_pdata->data_width = ilog2(op->data.buswidth); 394f453f293SPratyush Yadav 395f453f293SPratyush Yadav /* Right now we only support 8-8-8 DTR mode. */ 396f453f293SPratyush Yadav if (f_pdata->dtr) { 397f453f293SPratyush Yadav switch (op->cmd.buswidth) { 398f453f293SPratyush Yadav case 0: 399f453f293SPratyush Yadav case 8: 400f453f293SPratyush Yadav break; 401f453f293SPratyush Yadav default: 402f453f293SPratyush Yadav return -EINVAL; 403f453f293SPratyush Yadav } 404f453f293SPratyush Yadav 405f453f293SPratyush Yadav switch (op->addr.buswidth) { 406f453f293SPratyush Yadav case 0: 407f453f293SPratyush Yadav case 8: 408f453f293SPratyush Yadav break; 409f453f293SPratyush Yadav default: 410f453f293SPratyush Yadav return -EINVAL; 411f453f293SPratyush Yadav } 412f453f293SPratyush Yadav 413f453f293SPratyush Yadav switch (op->data.buswidth) { 414f453f293SPratyush Yadav case 0: 415f453f293SPratyush Yadav case 8: 416f453f293SPratyush Yadav break; 417f453f293SPratyush Yadav default: 418f453f293SPratyush Yadav return -EINVAL; 419f453f293SPratyush Yadav } 420f453f293SPratyush Yadav } 421f453f293SPratyush Yadav 422f453f293SPratyush Yadav return 0; 423f453f293SPratyush Yadav } 424f453f293SPratyush Yadav 42531fb632bSRamuthevar Vadivel Murugan static int cqspi_wait_idle(struct cqspi_st *cqspi) 42631fb632bSRamuthevar Vadivel Murugan { 42731fb632bSRamuthevar Vadivel Murugan const unsigned int poll_idle_retry = 3; 42831fb632bSRamuthevar Vadivel Murugan unsigned int count = 0; 42931fb632bSRamuthevar Vadivel Murugan unsigned long timeout; 43031fb632bSRamuthevar Vadivel Murugan 43131fb632bSRamuthevar Vadivel Murugan timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS); 43231fb632bSRamuthevar Vadivel Murugan while (1) { 43331fb632bSRamuthevar Vadivel Murugan /* 43431fb632bSRamuthevar Vadivel Murugan * Read few times in succession to ensure the controller 43531fb632bSRamuthevar Vadivel Murugan * is indeed idle, that is, the bit does not transition 43631fb632bSRamuthevar Vadivel Murugan * low again. 43731fb632bSRamuthevar Vadivel Murugan */ 43831fb632bSRamuthevar Vadivel Murugan if (cqspi_is_idle(cqspi)) 43931fb632bSRamuthevar Vadivel Murugan count++; 44031fb632bSRamuthevar Vadivel Murugan else 44131fb632bSRamuthevar Vadivel Murugan count = 0; 44231fb632bSRamuthevar Vadivel Murugan 44331fb632bSRamuthevar Vadivel Murugan if (count >= poll_idle_retry) 44431fb632bSRamuthevar Vadivel Murugan return 0; 44531fb632bSRamuthevar Vadivel Murugan 44631fb632bSRamuthevar Vadivel Murugan if (time_after(jiffies, timeout)) { 44731fb632bSRamuthevar Vadivel Murugan /* Timeout, in busy mode. */ 44831fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 44931fb632bSRamuthevar Vadivel Murugan "QSPI is still busy after %dms timeout.\n", 45031fb632bSRamuthevar Vadivel Murugan CQSPI_TIMEOUT_MS); 45131fb632bSRamuthevar Vadivel Murugan return -ETIMEDOUT; 45231fb632bSRamuthevar Vadivel Murugan } 45331fb632bSRamuthevar Vadivel Murugan 45431fb632bSRamuthevar Vadivel Murugan cpu_relax(); 45531fb632bSRamuthevar Vadivel Murugan } 45631fb632bSRamuthevar Vadivel Murugan } 45731fb632bSRamuthevar Vadivel Murugan 45831fb632bSRamuthevar Vadivel Murugan static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg) 45931fb632bSRamuthevar Vadivel Murugan { 46031fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 46131fb632bSRamuthevar Vadivel Murugan int ret; 46231fb632bSRamuthevar Vadivel Murugan 46331fb632bSRamuthevar Vadivel Murugan /* Write the CMDCTRL without start execution. */ 46431fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CMDCTRL); 46531fb632bSRamuthevar Vadivel Murugan /* Start execute */ 46631fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK; 46731fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CMDCTRL); 46831fb632bSRamuthevar Vadivel Murugan 46931fb632bSRamuthevar Vadivel Murugan /* Polling for completion. */ 47031fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL, 47131fb632bSRamuthevar Vadivel Murugan CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1); 47231fb632bSRamuthevar Vadivel Murugan if (ret) { 47331fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 47431fb632bSRamuthevar Vadivel Murugan "Flash command execution timed out.\n"); 47531fb632bSRamuthevar Vadivel Murugan return ret; 47631fb632bSRamuthevar Vadivel Murugan } 47731fb632bSRamuthevar Vadivel Murugan 47831fb632bSRamuthevar Vadivel Murugan /* Polling QSPI idle status. */ 47931fb632bSRamuthevar Vadivel Murugan return cqspi_wait_idle(cqspi); 48031fb632bSRamuthevar Vadivel Murugan } 48131fb632bSRamuthevar Vadivel Murugan 482f453f293SPratyush Yadav static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata, 483f453f293SPratyush Yadav const struct spi_mem_op *op, 484f453f293SPratyush Yadav unsigned int shift) 485f453f293SPratyush Yadav { 486f453f293SPratyush Yadav struct cqspi_st *cqspi = f_pdata->cqspi; 487f453f293SPratyush Yadav void __iomem *reg_base = cqspi->iobase; 488f453f293SPratyush Yadav unsigned int reg; 489f453f293SPratyush Yadav u8 ext; 490f453f293SPratyush Yadav 491f453f293SPratyush Yadav if (op->cmd.nbytes != 2) 492f453f293SPratyush Yadav return -EINVAL; 493f453f293SPratyush Yadav 494f453f293SPratyush Yadav /* Opcode extension is the LSB. */ 495f453f293SPratyush Yadav ext = op->cmd.opcode & 0xff; 496f453f293SPratyush Yadav 497f453f293SPratyush Yadav reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER); 498f453f293SPratyush Yadav reg &= ~(0xff << shift); 499f453f293SPratyush Yadav reg |= ext << shift; 500f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER); 501f453f293SPratyush Yadav 502f453f293SPratyush Yadav return 0; 503f453f293SPratyush Yadav } 504f453f293SPratyush Yadav 505f453f293SPratyush Yadav static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata, 506f453f293SPratyush Yadav const struct spi_mem_op *op, unsigned int shift, 507f453f293SPratyush Yadav bool enable) 508f453f293SPratyush Yadav { 509f453f293SPratyush Yadav struct cqspi_st *cqspi = f_pdata->cqspi; 510f453f293SPratyush Yadav void __iomem *reg_base = cqspi->iobase; 511f453f293SPratyush Yadav unsigned int reg; 512f453f293SPratyush Yadav int ret; 513f453f293SPratyush Yadav 514f453f293SPratyush Yadav reg = readl(reg_base + CQSPI_REG_CONFIG); 515f453f293SPratyush Yadav 516f453f293SPratyush Yadav /* 517f453f293SPratyush Yadav * We enable dual byte opcode here. The callers have to set up the 518f453f293SPratyush Yadav * extension opcode based on which type of operation it is. 519f453f293SPratyush Yadav */ 520f453f293SPratyush Yadav if (enable) { 521f453f293SPratyush Yadav reg |= CQSPI_REG_CONFIG_DTR_PROTO; 522f453f293SPratyush Yadav reg |= CQSPI_REG_CONFIG_DUAL_OPCODE; 523f453f293SPratyush Yadav 524f453f293SPratyush Yadav /* Set up command opcode extension. */ 525f453f293SPratyush Yadav ret = cqspi_setup_opcode_ext(f_pdata, op, shift); 526f453f293SPratyush Yadav if (ret) 527f453f293SPratyush Yadav return ret; 528f453f293SPratyush Yadav } else { 529f453f293SPratyush Yadav reg &= ~CQSPI_REG_CONFIG_DTR_PROTO; 530f453f293SPratyush Yadav reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE; 531f453f293SPratyush Yadav } 532f453f293SPratyush Yadav 533f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_CONFIG); 534f453f293SPratyush Yadav 535f453f293SPratyush Yadav return cqspi_wait_idle(cqspi); 536f453f293SPratyush Yadav } 537f453f293SPratyush Yadav 53831fb632bSRamuthevar Vadivel Murugan static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, 53931fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 54031fb632bSRamuthevar Vadivel Murugan { 54131fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 54231fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 54331fb632bSRamuthevar Vadivel Murugan u8 *rxbuf = op->data.buf.in; 544f453f293SPratyush Yadav u8 opcode; 54531fb632bSRamuthevar Vadivel Murugan size_t n_rx = op->data.nbytes; 54631fb632bSRamuthevar Vadivel Murugan unsigned int rdreg; 54731fb632bSRamuthevar Vadivel Murugan unsigned int reg; 548888d517bSPratyush Yadav unsigned int dummy_clk; 54931fb632bSRamuthevar Vadivel Murugan size_t read_len; 55031fb632bSRamuthevar Vadivel Murugan int status; 55131fb632bSRamuthevar Vadivel Murugan 552f453f293SPratyush Yadav status = cqspi_set_protocol(f_pdata, op); 553f453f293SPratyush Yadav if (status) 554f453f293SPratyush Yadav return status; 555f453f293SPratyush Yadav 556f453f293SPratyush Yadav status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB, 557f453f293SPratyush Yadav f_pdata->dtr); 558f453f293SPratyush Yadav if (status) 559f453f293SPratyush Yadav return status; 560f453f293SPratyush Yadav 56131fb632bSRamuthevar Vadivel Murugan if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) { 56231fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 56331fb632bSRamuthevar Vadivel Murugan "Invalid input argument, len %zu rxbuf 0x%p\n", 56431fb632bSRamuthevar Vadivel Murugan n_rx, rxbuf); 56531fb632bSRamuthevar Vadivel Murugan return -EINVAL; 56631fb632bSRamuthevar Vadivel Murugan } 56731fb632bSRamuthevar Vadivel Murugan 568f453f293SPratyush Yadav if (f_pdata->dtr) 569f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 570f453f293SPratyush Yadav else 571f453f293SPratyush Yadav opcode = op->cmd.opcode; 572f453f293SPratyush Yadav 57331fb632bSRamuthevar Vadivel Murugan reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 57431fb632bSRamuthevar Vadivel Murugan 57531fb632bSRamuthevar Vadivel Murugan rdreg = cqspi_calc_rdreg(f_pdata); 57631fb632bSRamuthevar Vadivel Murugan writel(rdreg, reg_base + CQSPI_REG_RD_INSTR); 57731fb632bSRamuthevar Vadivel Murugan 578f453f293SPratyush Yadav dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr); 579888d517bSPratyush Yadav if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 580888d517bSPratyush Yadav return -EOPNOTSUPP; 581888d517bSPratyush Yadav 582888d517bSPratyush Yadav if (dummy_clk) 583888d517bSPratyush Yadav reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK) 584888d517bSPratyush Yadav << CQSPI_REG_CMDCTRL_DUMMY_LSB; 585888d517bSPratyush Yadav 58631fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); 58731fb632bSRamuthevar Vadivel Murugan 58831fb632bSRamuthevar Vadivel Murugan /* 0 means 1 byte. */ 58931fb632bSRamuthevar Vadivel Murugan reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) 59031fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); 59131fb632bSRamuthevar Vadivel Murugan status = cqspi_exec_flash_cmd(cqspi, reg); 59231fb632bSRamuthevar Vadivel Murugan if (status) 59331fb632bSRamuthevar Vadivel Murugan return status; 59431fb632bSRamuthevar Vadivel Murugan 59531fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER); 59631fb632bSRamuthevar Vadivel Murugan 59731fb632bSRamuthevar Vadivel Murugan /* Put the read value into rx_buf */ 59831fb632bSRamuthevar Vadivel Murugan read_len = (n_rx > 4) ? 4 : n_rx; 59931fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, ®, read_len); 60031fb632bSRamuthevar Vadivel Murugan rxbuf += read_len; 60131fb632bSRamuthevar Vadivel Murugan 60231fb632bSRamuthevar Vadivel Murugan if (n_rx > 4) { 60331fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER); 60431fb632bSRamuthevar Vadivel Murugan 60531fb632bSRamuthevar Vadivel Murugan read_len = n_rx - read_len; 60631fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, ®, read_len); 60731fb632bSRamuthevar Vadivel Murugan } 60831fb632bSRamuthevar Vadivel Murugan 60931fb632bSRamuthevar Vadivel Murugan return 0; 61031fb632bSRamuthevar Vadivel Murugan } 61131fb632bSRamuthevar Vadivel Murugan 61231fb632bSRamuthevar Vadivel Murugan static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata, 61331fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 61431fb632bSRamuthevar Vadivel Murugan { 61531fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 61631fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 617f453f293SPratyush Yadav u8 opcode; 61831fb632bSRamuthevar Vadivel Murugan const u8 *txbuf = op->data.buf.out; 61931fb632bSRamuthevar Vadivel Murugan size_t n_tx = op->data.nbytes; 62031fb632bSRamuthevar Vadivel Murugan unsigned int reg; 62131fb632bSRamuthevar Vadivel Murugan unsigned int data; 62231fb632bSRamuthevar Vadivel Murugan size_t write_len; 623f453f293SPratyush Yadav int ret; 624f453f293SPratyush Yadav 625f453f293SPratyush Yadav ret = cqspi_set_protocol(f_pdata, op); 626f453f293SPratyush Yadav if (ret) 627f453f293SPratyush Yadav return ret; 628f453f293SPratyush Yadav 629f453f293SPratyush Yadav ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB, 630f453f293SPratyush Yadav f_pdata->dtr); 631f453f293SPratyush Yadav if (ret) 632f453f293SPratyush Yadav return ret; 63331fb632bSRamuthevar Vadivel Murugan 63431fb632bSRamuthevar Vadivel Murugan if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) { 63531fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 63631fb632bSRamuthevar Vadivel Murugan "Invalid input argument, cmdlen %zu txbuf 0x%p\n", 63731fb632bSRamuthevar Vadivel Murugan n_tx, txbuf); 63831fb632bSRamuthevar Vadivel Murugan return -EINVAL; 63931fb632bSRamuthevar Vadivel Murugan } 64031fb632bSRamuthevar Vadivel Murugan 641f453f293SPratyush Yadav reg = cqspi_calc_rdreg(f_pdata); 642f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_RD_INSTR); 643f453f293SPratyush Yadav 644f453f293SPratyush Yadav if (f_pdata->dtr) 645f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 646f453f293SPratyush Yadav else 647f453f293SPratyush Yadav opcode = op->cmd.opcode; 648f453f293SPratyush Yadav 64931fb632bSRamuthevar Vadivel Murugan reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 65031fb632bSRamuthevar Vadivel Murugan 65131fb632bSRamuthevar Vadivel Murugan if (op->addr.nbytes) { 65231fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 65331fb632bSRamuthevar Vadivel Murugan reg |= ((op->addr.nbytes - 1) & 65431fb632bSRamuthevar Vadivel Murugan CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) 65531fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; 65631fb632bSRamuthevar Vadivel Murugan 65731fb632bSRamuthevar Vadivel Murugan writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); 65831fb632bSRamuthevar Vadivel Murugan } 65931fb632bSRamuthevar Vadivel Murugan 66031fb632bSRamuthevar Vadivel Murugan if (n_tx) { 66131fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB); 66231fb632bSRamuthevar Vadivel Murugan reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) 66331fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_WR_BYTES_LSB; 66431fb632bSRamuthevar Vadivel Murugan data = 0; 66531fb632bSRamuthevar Vadivel Murugan write_len = (n_tx > 4) ? 4 : n_tx; 66631fb632bSRamuthevar Vadivel Murugan memcpy(&data, txbuf, write_len); 66731fb632bSRamuthevar Vadivel Murugan txbuf += write_len; 66831fb632bSRamuthevar Vadivel Murugan writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER); 66931fb632bSRamuthevar Vadivel Murugan 67031fb632bSRamuthevar Vadivel Murugan if (n_tx > 4) { 67131fb632bSRamuthevar Vadivel Murugan data = 0; 67231fb632bSRamuthevar Vadivel Murugan write_len = n_tx - 4; 67331fb632bSRamuthevar Vadivel Murugan memcpy(&data, txbuf, write_len); 67431fb632bSRamuthevar Vadivel Murugan writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER); 67531fb632bSRamuthevar Vadivel Murugan } 67631fb632bSRamuthevar Vadivel Murugan } 67731fb632bSRamuthevar Vadivel Murugan 67831fb632bSRamuthevar Vadivel Murugan return cqspi_exec_flash_cmd(cqspi, reg); 67931fb632bSRamuthevar Vadivel Murugan } 68031fb632bSRamuthevar Vadivel Murugan 68131fb632bSRamuthevar Vadivel Murugan static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata, 68231fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 68331fb632bSRamuthevar Vadivel Murugan { 68431fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 68531fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 68631fb632bSRamuthevar Vadivel Murugan unsigned int dummy_clk = 0; 68731fb632bSRamuthevar Vadivel Murugan unsigned int reg; 688f453f293SPratyush Yadav int ret; 689f453f293SPratyush Yadav u8 opcode; 69031fb632bSRamuthevar Vadivel Murugan 691f453f293SPratyush Yadav ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB, 692f453f293SPratyush Yadav f_pdata->dtr); 693f453f293SPratyush Yadav if (ret) 694f453f293SPratyush Yadav return ret; 695f453f293SPratyush Yadav 696f453f293SPratyush Yadav if (f_pdata->dtr) 697f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 698f453f293SPratyush Yadav else 699f453f293SPratyush Yadav opcode = op->cmd.opcode; 700f453f293SPratyush Yadav 701f453f293SPratyush Yadav reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB; 70231fb632bSRamuthevar Vadivel Murugan reg |= cqspi_calc_rdreg(f_pdata); 70331fb632bSRamuthevar Vadivel Murugan 70431fb632bSRamuthevar Vadivel Murugan /* Setup dummy clock cycles */ 705f453f293SPratyush Yadav dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr); 706888d517bSPratyush Yadav 70731fb632bSRamuthevar Vadivel Murugan if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 708ceeda328SPratyush Yadav return -EOPNOTSUPP; 70931fb632bSRamuthevar Vadivel Murugan 71031fb632bSRamuthevar Vadivel Murugan if (dummy_clk) 71131fb632bSRamuthevar Vadivel Murugan reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK) 71231fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_RD_INSTR_DUMMY_LSB; 71331fb632bSRamuthevar Vadivel Murugan 71431fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_RD_INSTR); 71531fb632bSRamuthevar Vadivel Murugan 71631fb632bSRamuthevar Vadivel Murugan /* Set address width */ 71731fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_SIZE); 71831fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 71931fb632bSRamuthevar Vadivel Murugan reg |= (op->addr.nbytes - 1); 72031fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_SIZE); 72131fb632bSRamuthevar Vadivel Murugan return 0; 72231fb632bSRamuthevar Vadivel Murugan } 72331fb632bSRamuthevar Vadivel Murugan 72431fb632bSRamuthevar Vadivel Murugan static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, 72531fb632bSRamuthevar Vadivel Murugan u8 *rxbuf, loff_t from_addr, 72631fb632bSRamuthevar Vadivel Murugan const size_t n_rx) 72731fb632bSRamuthevar Vadivel Murugan { 72831fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 72931fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 73031fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 73131fb632bSRamuthevar Vadivel Murugan void __iomem *ahb_base = cqspi->ahb_base; 73231fb632bSRamuthevar Vadivel Murugan unsigned int remaining = n_rx; 73331fb632bSRamuthevar Vadivel Murugan unsigned int mod_bytes = n_rx % 4; 73431fb632bSRamuthevar Vadivel Murugan unsigned int bytes_to_read = 0; 73531fb632bSRamuthevar Vadivel Murugan u8 *rxbuf_end = rxbuf + n_rx; 73631fb632bSRamuthevar Vadivel Murugan int ret = 0; 73731fb632bSRamuthevar Vadivel Murugan 73831fb632bSRamuthevar Vadivel Murugan writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 73931fb632bSRamuthevar Vadivel Murugan writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES); 74031fb632bSRamuthevar Vadivel Murugan 74131fb632bSRamuthevar Vadivel Murugan /* Clear all interrupts. */ 74231fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 74331fb632bSRamuthevar Vadivel Murugan 74431fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK); 74531fb632bSRamuthevar Vadivel Murugan 74631fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 74731fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTRD_START_MASK, 74831fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTRD); 74931fb632bSRamuthevar Vadivel Murugan 75031fb632bSRamuthevar Vadivel Murugan while (remaining > 0) { 75131fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->transfer_complete, 75231fb632bSRamuthevar Vadivel Murugan msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) 75331fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 75431fb632bSRamuthevar Vadivel Murugan 75531fb632bSRamuthevar Vadivel Murugan bytes_to_read = cqspi_get_rd_sram_level(cqspi); 75631fb632bSRamuthevar Vadivel Murugan 75731fb632bSRamuthevar Vadivel Murugan if (ret && bytes_to_read == 0) { 75831fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect read timeout, no bytes\n"); 75931fb632bSRamuthevar Vadivel Murugan goto failrd; 76031fb632bSRamuthevar Vadivel Murugan } 76131fb632bSRamuthevar Vadivel Murugan 76231fb632bSRamuthevar Vadivel Murugan while (bytes_to_read != 0) { 76331fb632bSRamuthevar Vadivel Murugan unsigned int word_remain = round_down(remaining, 4); 76431fb632bSRamuthevar Vadivel Murugan 76531fb632bSRamuthevar Vadivel Murugan bytes_to_read *= cqspi->fifo_width; 76631fb632bSRamuthevar Vadivel Murugan bytes_to_read = bytes_to_read > remaining ? 76731fb632bSRamuthevar Vadivel Murugan remaining : bytes_to_read; 76831fb632bSRamuthevar Vadivel Murugan bytes_to_read = round_down(bytes_to_read, 4); 76931fb632bSRamuthevar Vadivel Murugan /* Read 4 byte word chunks then single bytes */ 77031fb632bSRamuthevar Vadivel Murugan if (bytes_to_read) { 77131fb632bSRamuthevar Vadivel Murugan ioread32_rep(ahb_base, rxbuf, 77231fb632bSRamuthevar Vadivel Murugan (bytes_to_read / 4)); 77331fb632bSRamuthevar Vadivel Murugan } else if (!word_remain && mod_bytes) { 77431fb632bSRamuthevar Vadivel Murugan unsigned int temp = ioread32(ahb_base); 77531fb632bSRamuthevar Vadivel Murugan 77631fb632bSRamuthevar Vadivel Murugan bytes_to_read = mod_bytes; 77731fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, &temp, min((unsigned int) 77831fb632bSRamuthevar Vadivel Murugan (rxbuf_end - rxbuf), 77931fb632bSRamuthevar Vadivel Murugan bytes_to_read)); 78031fb632bSRamuthevar Vadivel Murugan } 78131fb632bSRamuthevar Vadivel Murugan rxbuf += bytes_to_read; 78231fb632bSRamuthevar Vadivel Murugan remaining -= bytes_to_read; 78331fb632bSRamuthevar Vadivel Murugan bytes_to_read = cqspi_get_rd_sram_level(cqspi); 78431fb632bSRamuthevar Vadivel Murugan } 78531fb632bSRamuthevar Vadivel Murugan 78631fb632bSRamuthevar Vadivel Murugan if (remaining > 0) 78731fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 78831fb632bSRamuthevar Vadivel Murugan } 78931fb632bSRamuthevar Vadivel Murugan 79031fb632bSRamuthevar Vadivel Murugan /* Check indirect done status */ 79131fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD, 79231fb632bSRamuthevar Vadivel Murugan CQSPI_REG_INDIRECTRD_DONE_MASK, 0); 79331fb632bSRamuthevar Vadivel Murugan if (ret) { 79431fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect read completion error (%i)\n", ret); 79531fb632bSRamuthevar Vadivel Murugan goto failrd; 79631fb632bSRamuthevar Vadivel Murugan } 79731fb632bSRamuthevar Vadivel Murugan 79831fb632bSRamuthevar Vadivel Murugan /* Disable interrupt */ 79931fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 80031fb632bSRamuthevar Vadivel Murugan 80131fb632bSRamuthevar Vadivel Murugan /* Clear indirect completion status */ 80231fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD); 80331fb632bSRamuthevar Vadivel Murugan 80431fb632bSRamuthevar Vadivel Murugan return 0; 80531fb632bSRamuthevar Vadivel Murugan 80631fb632bSRamuthevar Vadivel Murugan failrd: 80731fb632bSRamuthevar Vadivel Murugan /* Disable interrupt */ 80831fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 80931fb632bSRamuthevar Vadivel Murugan 81031fb632bSRamuthevar Vadivel Murugan /* Cancel the indirect read */ 81131fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 81231fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTRD); 81331fb632bSRamuthevar Vadivel Murugan return ret; 81431fb632bSRamuthevar Vadivel Murugan } 81531fb632bSRamuthevar Vadivel Murugan 8161a6f854fSSai Krishna Potthuri static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata, 8171a6f854fSSai Krishna Potthuri u_char *rxbuf, loff_t from_addr, 8181a6f854fSSai Krishna Potthuri size_t n_rx) 8191a6f854fSSai Krishna Potthuri { 8201a6f854fSSai Krishna Potthuri struct cqspi_st *cqspi = f_pdata->cqspi; 8211a6f854fSSai Krishna Potthuri struct device *dev = &cqspi->pdev->dev; 8221a6f854fSSai Krishna Potthuri void __iomem *reg_base = cqspi->iobase; 8231a6f854fSSai Krishna Potthuri u32 reg, bytes_to_dma; 8241a6f854fSSai Krishna Potthuri loff_t addr = from_addr; 8251a6f854fSSai Krishna Potthuri void *buf = rxbuf; 8261a6f854fSSai Krishna Potthuri dma_addr_t dma_addr; 8271a6f854fSSai Krishna Potthuri u8 bytes_rem; 8281a6f854fSSai Krishna Potthuri int ret = 0; 8291a6f854fSSai Krishna Potthuri 8301a6f854fSSai Krishna Potthuri bytes_rem = n_rx % 4; 8311a6f854fSSai Krishna Potthuri bytes_to_dma = (n_rx - bytes_rem); 8321a6f854fSSai Krishna Potthuri 8331a6f854fSSai Krishna Potthuri if (!bytes_to_dma) 8341a6f854fSSai Krishna Potthuri goto nondmard; 8351a6f854fSSai Krishna Potthuri 8361a6f854fSSai Krishna Potthuri ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA); 8371a6f854fSSai Krishna Potthuri if (ret) 8381a6f854fSSai Krishna Potthuri return ret; 8391a6f854fSSai Krishna Potthuri 8401a6f854fSSai Krishna Potthuri reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 8411a6f854fSSai Krishna Potthuri reg |= CQSPI_REG_CONFIG_DMA_MASK; 8421a6f854fSSai Krishna Potthuri writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 8431a6f854fSSai Krishna Potthuri 8441a6f854fSSai Krishna Potthuri dma_addr = dma_map_single(dev, rxbuf, bytes_to_dma, DMA_FROM_DEVICE); 8451a6f854fSSai Krishna Potthuri if (dma_mapping_error(dev, dma_addr)) { 8461a6f854fSSai Krishna Potthuri dev_err(dev, "dma mapping failed\n"); 8471a6f854fSSai Krishna Potthuri return -ENOMEM; 8481a6f854fSSai Krishna Potthuri } 8491a6f854fSSai Krishna Potthuri 8501a6f854fSSai Krishna Potthuri writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 8511a6f854fSSai Krishna Potthuri writel(bytes_to_dma, reg_base + CQSPI_REG_INDIRECTRDBYTES); 8521a6f854fSSai Krishna Potthuri writel(CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL, 8531a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_INDTRIG_ADDRRANGE); 8541a6f854fSSai Krishna Potthuri 8551a6f854fSSai Krishna Potthuri /* Clear all interrupts. */ 8561a6f854fSSai Krishna Potthuri writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 8571a6f854fSSai Krishna Potthuri 8581a6f854fSSai Krishna Potthuri /* Enable DMA done interrupt */ 8591a6f854fSSai Krishna Potthuri writel(CQSPI_REG_VERSAL_DMA_DST_DONE_MASK, 8601a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_VERSAL_DMA_DST_I_EN); 8611a6f854fSSai Krishna Potthuri 8621a6f854fSSai Krishna Potthuri /* Default DMA periph configuration */ 8631a6f854fSSai Krishna Potthuri writel(CQSPI_REG_VERSAL_DMA_VAL, reg_base + CQSPI_REG_DMA); 8641a6f854fSSai Krishna Potthuri 8651a6f854fSSai Krishna Potthuri /* Configure DMA Dst address */ 8661a6f854fSSai Krishna Potthuri writel(lower_32_bits(dma_addr), 8671a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR); 8681a6f854fSSai Krishna Potthuri writel(upper_32_bits(dma_addr), 8691a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB); 8701a6f854fSSai Krishna Potthuri 8711a6f854fSSai Krishna Potthuri /* Configure DMA Src address */ 8721a6f854fSSai Krishna Potthuri writel(cqspi->trigger_address, reg_base + 8731a6f854fSSai Krishna Potthuri CQSPI_REG_VERSAL_DMA_SRC_ADDR); 8741a6f854fSSai Krishna Potthuri 8751a6f854fSSai Krishna Potthuri /* Set DMA destination size */ 8761a6f854fSSai Krishna Potthuri writel(bytes_to_dma, reg_base + CQSPI_REG_VERSAL_DMA_DST_SIZE); 8771a6f854fSSai Krishna Potthuri 8781a6f854fSSai Krishna Potthuri /* Set DMA destination control */ 8791a6f854fSSai Krishna Potthuri writel(CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL, 8801a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_VERSAL_DMA_DST_CTRL); 8811a6f854fSSai Krishna Potthuri 8821a6f854fSSai Krishna Potthuri writel(CQSPI_REG_INDIRECTRD_START_MASK, 8831a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_INDIRECTRD); 8841a6f854fSSai Krishna Potthuri 8851a6f854fSSai Krishna Potthuri reinit_completion(&cqspi->transfer_complete); 8861a6f854fSSai Krishna Potthuri 8871a6f854fSSai Krishna Potthuri if (!wait_for_completion_timeout(&cqspi->transfer_complete, 8881a6f854fSSai Krishna Potthuri msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) { 8891a6f854fSSai Krishna Potthuri ret = -ETIMEDOUT; 8901a6f854fSSai Krishna Potthuri goto failrd; 8911a6f854fSSai Krishna Potthuri } 8921a6f854fSSai Krishna Potthuri 8931a6f854fSSai Krishna Potthuri /* Disable DMA interrupt */ 8941a6f854fSSai Krishna Potthuri writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS); 8951a6f854fSSai Krishna Potthuri 8961a6f854fSSai Krishna Potthuri /* Clear indirect completion status */ 8971a6f854fSSai Krishna Potthuri writel(CQSPI_REG_INDIRECTRD_DONE_MASK, 8981a6f854fSSai Krishna Potthuri cqspi->iobase + CQSPI_REG_INDIRECTRD); 8991a6f854fSSai Krishna Potthuri dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE); 9001a6f854fSSai Krishna Potthuri 9011a6f854fSSai Krishna Potthuri reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 9021a6f854fSSai Krishna Potthuri reg &= ~CQSPI_REG_CONFIG_DMA_MASK; 9031a6f854fSSai Krishna Potthuri writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 9041a6f854fSSai Krishna Potthuri 9051a6f854fSSai Krishna Potthuri ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, 9061a6f854fSSai Krishna Potthuri PM_OSPI_MUX_SEL_LINEAR); 9071a6f854fSSai Krishna Potthuri if (ret) 9081a6f854fSSai Krishna Potthuri return ret; 9091a6f854fSSai Krishna Potthuri 9101a6f854fSSai Krishna Potthuri nondmard: 9111a6f854fSSai Krishna Potthuri if (bytes_rem) { 9121a6f854fSSai Krishna Potthuri addr += bytes_to_dma; 9131a6f854fSSai Krishna Potthuri buf += bytes_to_dma; 9141a6f854fSSai Krishna Potthuri ret = cqspi_indirect_read_execute(f_pdata, buf, addr, 9151a6f854fSSai Krishna Potthuri bytes_rem); 9161a6f854fSSai Krishna Potthuri if (ret) 9171a6f854fSSai Krishna Potthuri return ret; 9181a6f854fSSai Krishna Potthuri } 9191a6f854fSSai Krishna Potthuri 9201a6f854fSSai Krishna Potthuri return 0; 9211a6f854fSSai Krishna Potthuri 9221a6f854fSSai Krishna Potthuri failrd: 9231a6f854fSSai Krishna Potthuri /* Disable DMA interrupt */ 9241a6f854fSSai Krishna Potthuri writel(0x0, reg_base + CQSPI_REG_VERSAL_DMA_DST_I_DIS); 9251a6f854fSSai Krishna Potthuri 9261a6f854fSSai Krishna Potthuri /* Cancel the indirect read */ 9271a6f854fSSai Krishna Potthuri writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 9281a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_INDIRECTRD); 9291a6f854fSSai Krishna Potthuri 930d9c55c95SArnd Bergmann dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE); 9311a6f854fSSai Krishna Potthuri 9321a6f854fSSai Krishna Potthuri reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 9331a6f854fSSai Krishna Potthuri reg &= ~CQSPI_REG_CONFIG_DMA_MASK; 9341a6f854fSSai Krishna Potthuri writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 9351a6f854fSSai Krishna Potthuri 9361a6f854fSSai Krishna Potthuri zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR); 9371a6f854fSSai Krishna Potthuri 9381a6f854fSSai Krishna Potthuri return ret; 9391a6f854fSSai Krishna Potthuri } 9401a6f854fSSai Krishna Potthuri 94131fb632bSRamuthevar Vadivel Murugan static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata, 94231fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 94331fb632bSRamuthevar Vadivel Murugan { 94431fb632bSRamuthevar Vadivel Murugan unsigned int reg; 945f453f293SPratyush Yadav int ret; 94631fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 94731fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 948f453f293SPratyush Yadav u8 opcode; 949f453f293SPratyush Yadav 950f453f293SPratyush Yadav ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB, 951f453f293SPratyush Yadav f_pdata->dtr); 952f453f293SPratyush Yadav if (ret) 953f453f293SPratyush Yadav return ret; 954f453f293SPratyush Yadav 955f453f293SPratyush Yadav if (f_pdata->dtr) 956f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 957f453f293SPratyush Yadav else 958f453f293SPratyush Yadav opcode = op->cmd.opcode; 95931fb632bSRamuthevar Vadivel Murugan 96031fb632bSRamuthevar Vadivel Murugan /* Set opcode. */ 961f453f293SPratyush Yadav reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; 962f453f293SPratyush Yadav reg |= f_pdata->data_width << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; 963f453f293SPratyush Yadav reg |= f_pdata->addr_width << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; 96431fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_WR_INSTR); 96531fb632bSRamuthevar Vadivel Murugan reg = cqspi_calc_rdreg(f_pdata); 96631fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_RD_INSTR); 96731fb632bSRamuthevar Vadivel Murugan 968f453f293SPratyush Yadav /* 9699cb2ff11SApurva Nandan * SPI NAND flashes require the address of the status register to be 9709cb2ff11SApurva Nandan * passed in the Read SR command. Also, some SPI NOR flashes like the 9719cb2ff11SApurva Nandan * cypress Semper flash expect a 4-byte dummy address in the Read SR 9729cb2ff11SApurva Nandan * command in DTR mode. 9739cb2ff11SApurva Nandan * 9749cb2ff11SApurva Nandan * But this controller does not support address phase in the Read SR 9759cb2ff11SApurva Nandan * command when doing auto-HW polling. So, disable write completion 9769cb2ff11SApurva Nandan * polling on the controller's side. spinand and spi-nor will take 9779cb2ff11SApurva Nandan * care of polling the status register. 978f453f293SPratyush Yadav */ 97998d948ebSDinh Nguyen if (cqspi->wr_completion) { 980f453f293SPratyush Yadav reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL); 981f453f293SPratyush Yadav reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL; 982f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL); 98398d948ebSDinh Nguyen } 984f453f293SPratyush Yadav 98531fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_SIZE); 98631fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 98731fb632bSRamuthevar Vadivel Murugan reg |= (op->addr.nbytes - 1); 98831fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_SIZE); 98931fb632bSRamuthevar Vadivel Murugan return 0; 99031fb632bSRamuthevar Vadivel Murugan } 99131fb632bSRamuthevar Vadivel Murugan 99231fb632bSRamuthevar Vadivel Murugan static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, 99331fb632bSRamuthevar Vadivel Murugan loff_t to_addr, const u8 *txbuf, 99431fb632bSRamuthevar Vadivel Murugan const size_t n_tx) 99531fb632bSRamuthevar Vadivel Murugan { 99631fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 99731fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 99831fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 99931fb632bSRamuthevar Vadivel Murugan unsigned int remaining = n_tx; 100031fb632bSRamuthevar Vadivel Murugan unsigned int write_bytes; 100131fb632bSRamuthevar Vadivel Murugan int ret; 100231fb632bSRamuthevar Vadivel Murugan 100331fb632bSRamuthevar Vadivel Murugan writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR); 100431fb632bSRamuthevar Vadivel Murugan writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES); 100531fb632bSRamuthevar Vadivel Murugan 100631fb632bSRamuthevar Vadivel Murugan /* Clear all interrupts. */ 100731fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 100831fb632bSRamuthevar Vadivel Murugan 100931fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK); 101031fb632bSRamuthevar Vadivel Murugan 101131fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 101231fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_START_MASK, 101331fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTWR); 101431fb632bSRamuthevar Vadivel Murugan /* 101531fb632bSRamuthevar Vadivel Murugan * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access 101631fb632bSRamuthevar Vadivel Murugan * Controller programming sequence, couple of cycles of 101731fb632bSRamuthevar Vadivel Murugan * QSPI_REF_CLK delay is required for the above bit to 101831fb632bSRamuthevar Vadivel Murugan * be internally synchronized by the QSPI module. Provide 5 101931fb632bSRamuthevar Vadivel Murugan * cycles of delay. 102031fb632bSRamuthevar Vadivel Murugan */ 102131fb632bSRamuthevar Vadivel Murugan if (cqspi->wr_delay) 102231fb632bSRamuthevar Vadivel Murugan ndelay(cqspi->wr_delay); 102331fb632bSRamuthevar Vadivel Murugan 102431fb632bSRamuthevar Vadivel Murugan while (remaining > 0) { 102531fb632bSRamuthevar Vadivel Murugan size_t write_words, mod_bytes; 102631fb632bSRamuthevar Vadivel Murugan 102731fb632bSRamuthevar Vadivel Murugan write_bytes = remaining; 102831fb632bSRamuthevar Vadivel Murugan write_words = write_bytes / 4; 102931fb632bSRamuthevar Vadivel Murugan mod_bytes = write_bytes % 4; 103031fb632bSRamuthevar Vadivel Murugan /* Write 4 bytes at a time then single bytes. */ 103131fb632bSRamuthevar Vadivel Murugan if (write_words) { 103231fb632bSRamuthevar Vadivel Murugan iowrite32_rep(cqspi->ahb_base, txbuf, write_words); 103331fb632bSRamuthevar Vadivel Murugan txbuf += (write_words * 4); 103431fb632bSRamuthevar Vadivel Murugan } 103531fb632bSRamuthevar Vadivel Murugan if (mod_bytes) { 103631fb632bSRamuthevar Vadivel Murugan unsigned int temp = 0xFFFFFFFF; 103731fb632bSRamuthevar Vadivel Murugan 103831fb632bSRamuthevar Vadivel Murugan memcpy(&temp, txbuf, mod_bytes); 103931fb632bSRamuthevar Vadivel Murugan iowrite32(temp, cqspi->ahb_base); 104031fb632bSRamuthevar Vadivel Murugan txbuf += mod_bytes; 104131fb632bSRamuthevar Vadivel Murugan } 104231fb632bSRamuthevar Vadivel Murugan 104331fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->transfer_complete, 104431fb632bSRamuthevar Vadivel Murugan msecs_to_jiffies(CQSPI_TIMEOUT_MS))) { 104531fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect write timeout\n"); 104631fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 104731fb632bSRamuthevar Vadivel Murugan goto failwr; 104831fb632bSRamuthevar Vadivel Murugan } 104931fb632bSRamuthevar Vadivel Murugan 105031fb632bSRamuthevar Vadivel Murugan remaining -= write_bytes; 105131fb632bSRamuthevar Vadivel Murugan 105231fb632bSRamuthevar Vadivel Murugan if (remaining > 0) 105331fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 105431fb632bSRamuthevar Vadivel Murugan } 105531fb632bSRamuthevar Vadivel Murugan 105631fb632bSRamuthevar Vadivel Murugan /* Check indirect done status */ 105731fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR, 105831fb632bSRamuthevar Vadivel Murugan CQSPI_REG_INDIRECTWR_DONE_MASK, 0); 105931fb632bSRamuthevar Vadivel Murugan if (ret) { 106031fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect write completion error (%i)\n", ret); 106131fb632bSRamuthevar Vadivel Murugan goto failwr; 106231fb632bSRamuthevar Vadivel Murugan } 106331fb632bSRamuthevar Vadivel Murugan 106431fb632bSRamuthevar Vadivel Murugan /* Disable interrupt. */ 106531fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 106631fb632bSRamuthevar Vadivel Murugan 106731fb632bSRamuthevar Vadivel Murugan /* Clear indirect completion status */ 106831fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR); 106931fb632bSRamuthevar Vadivel Murugan 107031fb632bSRamuthevar Vadivel Murugan cqspi_wait_idle(cqspi); 107131fb632bSRamuthevar Vadivel Murugan 107231fb632bSRamuthevar Vadivel Murugan return 0; 107331fb632bSRamuthevar Vadivel Murugan 107431fb632bSRamuthevar Vadivel Murugan failwr: 107531fb632bSRamuthevar Vadivel Murugan /* Disable interrupt. */ 107631fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 107731fb632bSRamuthevar Vadivel Murugan 107831fb632bSRamuthevar Vadivel Murugan /* Cancel the indirect write */ 107931fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 108031fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTWR); 108131fb632bSRamuthevar Vadivel Murugan return ret; 108231fb632bSRamuthevar Vadivel Murugan } 108331fb632bSRamuthevar Vadivel Murugan 108431fb632bSRamuthevar Vadivel Murugan static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata) 108531fb632bSRamuthevar Vadivel Murugan { 108631fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 108731fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 108831fb632bSRamuthevar Vadivel Murugan unsigned int chip_select = f_pdata->cs; 108931fb632bSRamuthevar Vadivel Murugan unsigned int reg; 109031fb632bSRamuthevar Vadivel Murugan 109131fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG); 109231fb632bSRamuthevar Vadivel Murugan if (cqspi->is_decoded_cs) { 109331fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CONFIG_DECODE_MASK; 109431fb632bSRamuthevar Vadivel Murugan } else { 109531fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; 109631fb632bSRamuthevar Vadivel Murugan 109731fb632bSRamuthevar Vadivel Murugan /* Convert CS if without decoder. 109831fb632bSRamuthevar Vadivel Murugan * CS0 to 4b'1110 109931fb632bSRamuthevar Vadivel Murugan * CS1 to 4b'1101 110031fb632bSRamuthevar Vadivel Murugan * CS2 to 4b'1011 110131fb632bSRamuthevar Vadivel Murugan * CS3 to 4b'0111 110231fb632bSRamuthevar Vadivel Murugan */ 110331fb632bSRamuthevar Vadivel Murugan chip_select = 0xF & ~(1 << chip_select); 110431fb632bSRamuthevar Vadivel Murugan } 110531fb632bSRamuthevar Vadivel Murugan 110631fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK 110731fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CONFIG_CHIPSELECT_LSB); 110831fb632bSRamuthevar Vadivel Murugan reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK) 110931fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CONFIG_CHIPSELECT_LSB; 111031fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG); 111131fb632bSRamuthevar Vadivel Murugan } 111231fb632bSRamuthevar Vadivel Murugan 111331fb632bSRamuthevar Vadivel Murugan static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz, 111431fb632bSRamuthevar Vadivel Murugan const unsigned int ns_val) 111531fb632bSRamuthevar Vadivel Murugan { 111631fb632bSRamuthevar Vadivel Murugan unsigned int ticks; 111731fb632bSRamuthevar Vadivel Murugan 111831fb632bSRamuthevar Vadivel Murugan ticks = ref_clk_hz / 1000; /* kHz */ 111931fb632bSRamuthevar Vadivel Murugan ticks = DIV_ROUND_UP(ticks * ns_val, 1000000); 112031fb632bSRamuthevar Vadivel Murugan 112131fb632bSRamuthevar Vadivel Murugan return ticks; 112231fb632bSRamuthevar Vadivel Murugan } 112331fb632bSRamuthevar Vadivel Murugan 112431fb632bSRamuthevar Vadivel Murugan static void cqspi_delay(struct cqspi_flash_pdata *f_pdata) 112531fb632bSRamuthevar Vadivel Murugan { 112631fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 112731fb632bSRamuthevar Vadivel Murugan void __iomem *iobase = cqspi->iobase; 112831fb632bSRamuthevar Vadivel Murugan const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 112931fb632bSRamuthevar Vadivel Murugan unsigned int tshsl, tchsh, tslch, tsd2d; 113031fb632bSRamuthevar Vadivel Murugan unsigned int reg; 113131fb632bSRamuthevar Vadivel Murugan unsigned int tsclk; 113231fb632bSRamuthevar Vadivel Murugan 113331fb632bSRamuthevar Vadivel Murugan /* calculate the number of ref ticks for one sclk tick */ 113431fb632bSRamuthevar Vadivel Murugan tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk); 113531fb632bSRamuthevar Vadivel Murugan 113631fb632bSRamuthevar Vadivel Murugan tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns); 113731fb632bSRamuthevar Vadivel Murugan /* this particular value must be at least one sclk */ 113831fb632bSRamuthevar Vadivel Murugan if (tshsl < tsclk) 113931fb632bSRamuthevar Vadivel Murugan tshsl = tsclk; 114031fb632bSRamuthevar Vadivel Murugan 114131fb632bSRamuthevar Vadivel Murugan tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns); 114231fb632bSRamuthevar Vadivel Murugan tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns); 114331fb632bSRamuthevar Vadivel Murugan tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns); 114431fb632bSRamuthevar Vadivel Murugan 114531fb632bSRamuthevar Vadivel Murugan reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK) 114631fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSHSL_LSB; 114731fb632bSRamuthevar Vadivel Murugan reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK) 114831fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TCHSH_LSB; 114931fb632bSRamuthevar Vadivel Murugan reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK) 115031fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSLCH_LSB; 115131fb632bSRamuthevar Vadivel Murugan reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK) 115231fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSD2D_LSB; 115331fb632bSRamuthevar Vadivel Murugan writel(reg, iobase + CQSPI_REG_DELAY); 115431fb632bSRamuthevar Vadivel Murugan } 115531fb632bSRamuthevar Vadivel Murugan 115631fb632bSRamuthevar Vadivel Murugan static void cqspi_config_baudrate_div(struct cqspi_st *cqspi) 115731fb632bSRamuthevar Vadivel Murugan { 115831fb632bSRamuthevar Vadivel Murugan const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 115931fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 116031fb632bSRamuthevar Vadivel Murugan u32 reg, div; 116131fb632bSRamuthevar Vadivel Murugan 116231fb632bSRamuthevar Vadivel Murugan /* Recalculate the baudrate divisor based on QSPI specification. */ 116331fb632bSRamuthevar Vadivel Murugan div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1; 116431fb632bSRamuthevar Vadivel Murugan 116531fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG); 116631fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); 116731fb632bSRamuthevar Vadivel Murugan reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB; 116831fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG); 116931fb632bSRamuthevar Vadivel Murugan } 117031fb632bSRamuthevar Vadivel Murugan 117131fb632bSRamuthevar Vadivel Murugan static void cqspi_readdata_capture(struct cqspi_st *cqspi, 117231fb632bSRamuthevar Vadivel Murugan const bool bypass, 117331fb632bSRamuthevar Vadivel Murugan const unsigned int delay) 117431fb632bSRamuthevar Vadivel Murugan { 117531fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 117631fb632bSRamuthevar Vadivel Murugan unsigned int reg; 117731fb632bSRamuthevar Vadivel Murugan 117831fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_READCAPTURE); 117931fb632bSRamuthevar Vadivel Murugan 118031fb632bSRamuthevar Vadivel Murugan if (bypass) 118131fb632bSRamuthevar Vadivel Murugan reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 118231fb632bSRamuthevar Vadivel Murugan else 118331fb632bSRamuthevar Vadivel Murugan reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 118431fb632bSRamuthevar Vadivel Murugan 118531fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK 118631fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_READCAPTURE_DELAY_LSB); 118731fb632bSRamuthevar Vadivel Murugan 118831fb632bSRamuthevar Vadivel Murugan reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK) 118931fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_READCAPTURE_DELAY_LSB; 119031fb632bSRamuthevar Vadivel Murugan 119131fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_READCAPTURE); 119231fb632bSRamuthevar Vadivel Murugan } 119331fb632bSRamuthevar Vadivel Murugan 119431fb632bSRamuthevar Vadivel Murugan static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable) 119531fb632bSRamuthevar Vadivel Murugan { 119631fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 119731fb632bSRamuthevar Vadivel Murugan unsigned int reg; 119831fb632bSRamuthevar Vadivel Murugan 119931fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG); 120031fb632bSRamuthevar Vadivel Murugan 120131fb632bSRamuthevar Vadivel Murugan if (enable) 120231fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CONFIG_ENABLE_MASK; 120331fb632bSRamuthevar Vadivel Murugan else 120431fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; 120531fb632bSRamuthevar Vadivel Murugan 120631fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG); 120731fb632bSRamuthevar Vadivel Murugan } 120831fb632bSRamuthevar Vadivel Murugan 120931fb632bSRamuthevar Vadivel Murugan static void cqspi_configure(struct cqspi_flash_pdata *f_pdata, 121031fb632bSRamuthevar Vadivel Murugan unsigned long sclk) 121131fb632bSRamuthevar Vadivel Murugan { 121231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 121331fb632bSRamuthevar Vadivel Murugan int switch_cs = (cqspi->current_cs != f_pdata->cs); 121431fb632bSRamuthevar Vadivel Murugan int switch_ck = (cqspi->sclk != sclk); 121531fb632bSRamuthevar Vadivel Murugan 121631fb632bSRamuthevar Vadivel Murugan if (switch_cs || switch_ck) 121731fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 121831fb632bSRamuthevar Vadivel Murugan 121931fb632bSRamuthevar Vadivel Murugan /* Switch chip select. */ 122031fb632bSRamuthevar Vadivel Murugan if (switch_cs) { 122131fb632bSRamuthevar Vadivel Murugan cqspi->current_cs = f_pdata->cs; 122231fb632bSRamuthevar Vadivel Murugan cqspi_chipselect(f_pdata); 122331fb632bSRamuthevar Vadivel Murugan } 122431fb632bSRamuthevar Vadivel Murugan 122531fb632bSRamuthevar Vadivel Murugan /* Setup baudrate divisor and delays */ 122631fb632bSRamuthevar Vadivel Murugan if (switch_ck) { 122731fb632bSRamuthevar Vadivel Murugan cqspi->sclk = sclk; 122831fb632bSRamuthevar Vadivel Murugan cqspi_config_baudrate_div(cqspi); 122931fb632bSRamuthevar Vadivel Murugan cqspi_delay(f_pdata); 123031fb632bSRamuthevar Vadivel Murugan cqspi_readdata_capture(cqspi, !cqspi->rclk_en, 123131fb632bSRamuthevar Vadivel Murugan f_pdata->read_delay); 123231fb632bSRamuthevar Vadivel Murugan } 123331fb632bSRamuthevar Vadivel Murugan 123431fb632bSRamuthevar Vadivel Murugan if (switch_cs || switch_ck) 123531fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1); 123631fb632bSRamuthevar Vadivel Murugan } 123731fb632bSRamuthevar Vadivel Murugan 123831fb632bSRamuthevar Vadivel Murugan static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata, 123931fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 124031fb632bSRamuthevar Vadivel Murugan { 124131fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 124231fb632bSRamuthevar Vadivel Murugan loff_t to = op->addr.val; 124331fb632bSRamuthevar Vadivel Murugan size_t len = op->data.nbytes; 124431fb632bSRamuthevar Vadivel Murugan const u_char *buf = op->data.buf.out; 124531fb632bSRamuthevar Vadivel Murugan int ret; 124631fb632bSRamuthevar Vadivel Murugan 124731fb632bSRamuthevar Vadivel Murugan ret = cqspi_set_protocol(f_pdata, op); 124831fb632bSRamuthevar Vadivel Murugan if (ret) 124931fb632bSRamuthevar Vadivel Murugan return ret; 125031fb632bSRamuthevar Vadivel Murugan 125131fb632bSRamuthevar Vadivel Murugan ret = cqspi_write_setup(f_pdata, op); 125231fb632bSRamuthevar Vadivel Murugan if (ret) 125331fb632bSRamuthevar Vadivel Murugan return ret; 125431fb632bSRamuthevar Vadivel Murugan 1255f453f293SPratyush Yadav /* 1256f453f293SPratyush Yadav * Some flashes like the Cypress Semper flash expect a dummy 4-byte 1257f453f293SPratyush Yadav * address (all 0s) with the read status register command in DTR mode. 1258f453f293SPratyush Yadav * But this controller does not support sending dummy address bytes to 1259f453f293SPratyush Yadav * the flash when it is polling the write completion register in DTR 1260f453f293SPratyush Yadav * mode. So, we can not use direct mode when in DTR mode for writing 1261f453f293SPratyush Yadav * data. 1262f453f293SPratyush Yadav */ 1263f453f293SPratyush Yadav if (!f_pdata->dtr && cqspi->use_direct_mode && 1264f453f293SPratyush Yadav ((to + len) <= cqspi->ahb_size)) { 126531fb632bSRamuthevar Vadivel Murugan memcpy_toio(cqspi->ahb_base + to, buf, len); 126631fb632bSRamuthevar Vadivel Murugan return cqspi_wait_idle(cqspi); 126731fb632bSRamuthevar Vadivel Murugan } 126831fb632bSRamuthevar Vadivel Murugan 126931fb632bSRamuthevar Vadivel Murugan return cqspi_indirect_write_execute(f_pdata, to, buf, len); 127031fb632bSRamuthevar Vadivel Murugan } 127131fb632bSRamuthevar Vadivel Murugan 127231fb632bSRamuthevar Vadivel Murugan static void cqspi_rx_dma_callback(void *param) 127331fb632bSRamuthevar Vadivel Murugan { 127431fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = param; 127531fb632bSRamuthevar Vadivel Murugan 127631fb632bSRamuthevar Vadivel Murugan complete(&cqspi->rx_dma_complete); 127731fb632bSRamuthevar Vadivel Murugan } 127831fb632bSRamuthevar Vadivel Murugan 127931fb632bSRamuthevar Vadivel Murugan static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata, 128031fb632bSRamuthevar Vadivel Murugan u_char *buf, loff_t from, size_t len) 128131fb632bSRamuthevar Vadivel Murugan { 128231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 128331fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 128431fb632bSRamuthevar Vadivel Murugan enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; 128531fb632bSRamuthevar Vadivel Murugan dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from; 128631fb632bSRamuthevar Vadivel Murugan int ret = 0; 128731fb632bSRamuthevar Vadivel Murugan struct dma_async_tx_descriptor *tx; 128831fb632bSRamuthevar Vadivel Murugan dma_cookie_t cookie; 128931fb632bSRamuthevar Vadivel Murugan dma_addr_t dma_dst; 129083048015SVignesh Raghavendra struct device *ddev; 129131fb632bSRamuthevar Vadivel Murugan 129231fb632bSRamuthevar Vadivel Murugan if (!cqspi->rx_chan || !virt_addr_valid(buf)) { 129331fb632bSRamuthevar Vadivel Murugan memcpy_fromio(buf, cqspi->ahb_base + from, len); 129431fb632bSRamuthevar Vadivel Murugan return 0; 129531fb632bSRamuthevar Vadivel Murugan } 129631fb632bSRamuthevar Vadivel Murugan 129783048015SVignesh Raghavendra ddev = cqspi->rx_chan->device->dev; 129883048015SVignesh Raghavendra dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE); 129983048015SVignesh Raghavendra if (dma_mapping_error(ddev, dma_dst)) { 130031fb632bSRamuthevar Vadivel Murugan dev_err(dev, "dma mapping failed\n"); 130131fb632bSRamuthevar Vadivel Murugan return -ENOMEM; 130231fb632bSRamuthevar Vadivel Murugan } 130331fb632bSRamuthevar Vadivel Murugan tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src, 130431fb632bSRamuthevar Vadivel Murugan len, flags); 130531fb632bSRamuthevar Vadivel Murugan if (!tx) { 130631fb632bSRamuthevar Vadivel Murugan dev_err(dev, "device_prep_dma_memcpy error\n"); 130731fb632bSRamuthevar Vadivel Murugan ret = -EIO; 130831fb632bSRamuthevar Vadivel Murugan goto err_unmap; 130931fb632bSRamuthevar Vadivel Murugan } 131031fb632bSRamuthevar Vadivel Murugan 131131fb632bSRamuthevar Vadivel Murugan tx->callback = cqspi_rx_dma_callback; 131231fb632bSRamuthevar Vadivel Murugan tx->callback_param = cqspi; 131331fb632bSRamuthevar Vadivel Murugan cookie = tx->tx_submit(tx); 131431fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->rx_dma_complete); 131531fb632bSRamuthevar Vadivel Murugan 131631fb632bSRamuthevar Vadivel Murugan ret = dma_submit_error(cookie); 131731fb632bSRamuthevar Vadivel Murugan if (ret) { 131831fb632bSRamuthevar Vadivel Murugan dev_err(dev, "dma_submit_error %d\n", cookie); 131931fb632bSRamuthevar Vadivel Murugan ret = -EIO; 132031fb632bSRamuthevar Vadivel Murugan goto err_unmap; 132131fb632bSRamuthevar Vadivel Murugan } 132231fb632bSRamuthevar Vadivel Murugan 132331fb632bSRamuthevar Vadivel Murugan dma_async_issue_pending(cqspi->rx_chan); 132431fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->rx_dma_complete, 13252ef0170eSPratyush Yadav msecs_to_jiffies(max_t(size_t, len, 500)))) { 132631fb632bSRamuthevar Vadivel Murugan dmaengine_terminate_sync(cqspi->rx_chan); 132731fb632bSRamuthevar Vadivel Murugan dev_err(dev, "DMA wait_for_completion_timeout\n"); 132831fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 132931fb632bSRamuthevar Vadivel Murugan goto err_unmap; 133031fb632bSRamuthevar Vadivel Murugan } 133131fb632bSRamuthevar Vadivel Murugan 133231fb632bSRamuthevar Vadivel Murugan err_unmap: 133383048015SVignesh Raghavendra dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE); 133431fb632bSRamuthevar Vadivel Murugan 133531fb632bSRamuthevar Vadivel Murugan return ret; 133631fb632bSRamuthevar Vadivel Murugan } 133731fb632bSRamuthevar Vadivel Murugan 133831fb632bSRamuthevar Vadivel Murugan static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata, 133931fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 134031fb632bSRamuthevar Vadivel Murugan { 134131fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 13421a6f854fSSai Krishna Potthuri struct device *dev = &cqspi->pdev->dev; 13431a6f854fSSai Krishna Potthuri const struct cqspi_driver_platdata *ddata; 134431fb632bSRamuthevar Vadivel Murugan loff_t from = op->addr.val; 134531fb632bSRamuthevar Vadivel Murugan size_t len = op->data.nbytes; 134631fb632bSRamuthevar Vadivel Murugan u_char *buf = op->data.buf.in; 13471a6f854fSSai Krishna Potthuri u64 dma_align = (u64)(uintptr_t)buf; 134831fb632bSRamuthevar Vadivel Murugan int ret; 134931fb632bSRamuthevar Vadivel Murugan 13501a6f854fSSai Krishna Potthuri ddata = of_device_get_match_data(dev); 135131fb632bSRamuthevar Vadivel Murugan ret = cqspi_set_protocol(f_pdata, op); 135231fb632bSRamuthevar Vadivel Murugan if (ret) 135331fb632bSRamuthevar Vadivel Murugan return ret; 135431fb632bSRamuthevar Vadivel Murugan 135531fb632bSRamuthevar Vadivel Murugan ret = cqspi_read_setup(f_pdata, op); 135631fb632bSRamuthevar Vadivel Murugan if (ret) 135731fb632bSRamuthevar Vadivel Murugan return ret; 135831fb632bSRamuthevar Vadivel Murugan 135931fb632bSRamuthevar Vadivel Murugan if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) 136031fb632bSRamuthevar Vadivel Murugan return cqspi_direct_read_execute(f_pdata, buf, from, len); 136131fb632bSRamuthevar Vadivel Murugan 13621a6f854fSSai Krishna Potthuri if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma && 13631a6f854fSSai Krishna Potthuri virt_addr_valid(buf) && ((dma_align & CQSPI_DMA_UNALIGN) == 0)) 13641a6f854fSSai Krishna Potthuri return ddata->indirect_read_dma(f_pdata, buf, from, len); 13651a6f854fSSai Krishna Potthuri 136631fb632bSRamuthevar Vadivel Murugan return cqspi_indirect_read_execute(f_pdata, buf, from, len); 136731fb632bSRamuthevar Vadivel Murugan } 136831fb632bSRamuthevar Vadivel Murugan 136931fb632bSRamuthevar Vadivel Murugan static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op) 137031fb632bSRamuthevar Vadivel Murugan { 137131fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); 137231fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata; 137331fb632bSRamuthevar Vadivel Murugan 137431fb632bSRamuthevar Vadivel Murugan f_pdata = &cqspi->f_pdata[mem->spi->chip_select]; 137531fb632bSRamuthevar Vadivel Murugan cqspi_configure(f_pdata, mem->spi->max_speed_hz); 137631fb632bSRamuthevar Vadivel Murugan 137731fb632bSRamuthevar Vadivel Murugan if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { 137831fb632bSRamuthevar Vadivel Murugan if (!op->addr.nbytes) 137931fb632bSRamuthevar Vadivel Murugan return cqspi_command_read(f_pdata, op); 138031fb632bSRamuthevar Vadivel Murugan 138131fb632bSRamuthevar Vadivel Murugan return cqspi_read(f_pdata, op); 138231fb632bSRamuthevar Vadivel Murugan } 138331fb632bSRamuthevar Vadivel Murugan 138431fb632bSRamuthevar Vadivel Murugan if (!op->addr.nbytes || !op->data.buf.out) 138531fb632bSRamuthevar Vadivel Murugan return cqspi_command_write(f_pdata, op); 138631fb632bSRamuthevar Vadivel Murugan 138731fb632bSRamuthevar Vadivel Murugan return cqspi_write(f_pdata, op); 138831fb632bSRamuthevar Vadivel Murugan } 138931fb632bSRamuthevar Vadivel Murugan 139031fb632bSRamuthevar Vadivel Murugan static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) 139131fb632bSRamuthevar Vadivel Murugan { 139231fb632bSRamuthevar Vadivel Murugan int ret; 139331fb632bSRamuthevar Vadivel Murugan 139431fb632bSRamuthevar Vadivel Murugan ret = cqspi_mem_process(mem, op); 139531fb632bSRamuthevar Vadivel Murugan if (ret) 139631fb632bSRamuthevar Vadivel Murugan dev_err(&mem->spi->dev, "operation failed with %d\n", ret); 139731fb632bSRamuthevar Vadivel Murugan 139831fb632bSRamuthevar Vadivel Murugan return ret; 139931fb632bSRamuthevar Vadivel Murugan } 140031fb632bSRamuthevar Vadivel Murugan 1401a273596bSPratyush Yadav static bool cqspi_supports_mem_op(struct spi_mem *mem, 1402a273596bSPratyush Yadav const struct spi_mem_op *op) 1403a273596bSPratyush Yadav { 1404f453f293SPratyush Yadav bool all_true, all_false; 1405f453f293SPratyush Yadav 14060395be96SApurva Nandan /* 14070395be96SApurva Nandan * op->dummy.dtr is required for converting nbytes into ncycles. 14080395be96SApurva Nandan * Also, don't check the dtr field of the op phase having zero nbytes. 14090395be96SApurva Nandan */ 14100395be96SApurva Nandan all_true = op->cmd.dtr && 14110395be96SApurva Nandan (!op->addr.nbytes || op->addr.dtr) && 14120395be96SApurva Nandan (!op->dummy.nbytes || op->dummy.dtr) && 14130395be96SApurva Nandan (!op->data.nbytes || op->data.dtr); 14140395be96SApurva Nandan 1415f453f293SPratyush Yadav all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && 1416f453f293SPratyush Yadav !op->data.dtr; 1417f453f293SPratyush Yadav 1418f453f293SPratyush Yadav /* Mixed DTR modes not supported. */ 1419f453f293SPratyush Yadav if (!(all_true || all_false)) 1420f453f293SPratyush Yadav return false; 1421f453f293SPratyush Yadav 1422d2275139SPratyush Yadav return spi_mem_default_supports_op(mem, op); 1423a273596bSPratyush Yadav } 1424a273596bSPratyush Yadav 142531fb632bSRamuthevar Vadivel Murugan static int cqspi_of_get_flash_pdata(struct platform_device *pdev, 142631fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata, 142731fb632bSRamuthevar Vadivel Murugan struct device_node *np) 142831fb632bSRamuthevar Vadivel Murugan { 142931fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) { 143031fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine read-delay\n"); 143131fb632bSRamuthevar Vadivel Murugan return -ENXIO; 143231fb632bSRamuthevar Vadivel Murugan } 143331fb632bSRamuthevar Vadivel Murugan 143431fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) { 143531fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tshsl-ns\n"); 143631fb632bSRamuthevar Vadivel Murugan return -ENXIO; 143731fb632bSRamuthevar Vadivel Murugan } 143831fb632bSRamuthevar Vadivel Murugan 143931fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) { 144031fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n"); 144131fb632bSRamuthevar Vadivel Murugan return -ENXIO; 144231fb632bSRamuthevar Vadivel Murugan } 144331fb632bSRamuthevar Vadivel Murugan 144431fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) { 144531fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tchsh-ns\n"); 144631fb632bSRamuthevar Vadivel Murugan return -ENXIO; 144731fb632bSRamuthevar Vadivel Murugan } 144831fb632bSRamuthevar Vadivel Murugan 144931fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) { 145031fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tslch-ns\n"); 145131fb632bSRamuthevar Vadivel Murugan return -ENXIO; 145231fb632bSRamuthevar Vadivel Murugan } 145331fb632bSRamuthevar Vadivel Murugan 145431fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) { 145531fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n"); 145631fb632bSRamuthevar Vadivel Murugan return -ENXIO; 145731fb632bSRamuthevar Vadivel Murugan } 145831fb632bSRamuthevar Vadivel Murugan 145931fb632bSRamuthevar Vadivel Murugan return 0; 146031fb632bSRamuthevar Vadivel Murugan } 146131fb632bSRamuthevar Vadivel Murugan 146231fb632bSRamuthevar Vadivel Murugan static int cqspi_of_get_pdata(struct cqspi_st *cqspi) 146331fb632bSRamuthevar Vadivel Murugan { 146431fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 146531fb632bSRamuthevar Vadivel Murugan struct device_node *np = dev->of_node; 146609e393e3SSai Krishna Potthuri u32 id[2]; 146731fb632bSRamuthevar Vadivel Murugan 146831fb632bSRamuthevar Vadivel Murugan cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); 146931fb632bSRamuthevar Vadivel Murugan 147031fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { 147131fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine fifo-depth\n"); 147231fb632bSRamuthevar Vadivel Murugan return -ENXIO; 147331fb632bSRamuthevar Vadivel Murugan } 147431fb632bSRamuthevar Vadivel Murugan 147531fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) { 147631fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine fifo-width\n"); 147731fb632bSRamuthevar Vadivel Murugan return -ENXIO; 147831fb632bSRamuthevar Vadivel Murugan } 147931fb632bSRamuthevar Vadivel Murugan 148031fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,trigger-address", 148131fb632bSRamuthevar Vadivel Murugan &cqspi->trigger_address)) { 148231fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine trigger-address\n"); 148331fb632bSRamuthevar Vadivel Murugan return -ENXIO; 148431fb632bSRamuthevar Vadivel Murugan } 148531fb632bSRamuthevar Vadivel Murugan 1486b436fb7dSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) 1487b436fb7dSRamuthevar Vadivel Murugan cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT; 1488b436fb7dSRamuthevar Vadivel Murugan 148931fb632bSRamuthevar Vadivel Murugan cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); 149031fb632bSRamuthevar Vadivel Murugan 149109e393e3SSai Krishna Potthuri if (!of_property_read_u32_array(np, "power-domains", id, 149209e393e3SSai Krishna Potthuri ARRAY_SIZE(id))) 149309e393e3SSai Krishna Potthuri cqspi->pd_dev_id = id[1]; 149409e393e3SSai Krishna Potthuri 149531fb632bSRamuthevar Vadivel Murugan return 0; 149631fb632bSRamuthevar Vadivel Murugan } 149731fb632bSRamuthevar Vadivel Murugan 149831fb632bSRamuthevar Vadivel Murugan static void cqspi_controller_init(struct cqspi_st *cqspi) 149931fb632bSRamuthevar Vadivel Murugan { 150031fb632bSRamuthevar Vadivel Murugan u32 reg; 150131fb632bSRamuthevar Vadivel Murugan 150231fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 150331fb632bSRamuthevar Vadivel Murugan 150431fb632bSRamuthevar Vadivel Murugan /* Configure the remap address register, no remap */ 150531fb632bSRamuthevar Vadivel Murugan writel(0, cqspi->iobase + CQSPI_REG_REMAP); 150631fb632bSRamuthevar Vadivel Murugan 150731fb632bSRamuthevar Vadivel Murugan /* Disable all interrupts. */ 150831fb632bSRamuthevar Vadivel Murugan writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); 150931fb632bSRamuthevar Vadivel Murugan 151031fb632bSRamuthevar Vadivel Murugan /* Configure the SRAM split to 1:1 . */ 151131fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); 151231fb632bSRamuthevar Vadivel Murugan 151331fb632bSRamuthevar Vadivel Murugan /* Load indirect trigger address. */ 151431fb632bSRamuthevar Vadivel Murugan writel(cqspi->trigger_address, 151531fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); 151631fb632bSRamuthevar Vadivel Murugan 151731fb632bSRamuthevar Vadivel Murugan /* Program read watermark -- 1/2 of the FIFO. */ 151831fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth * cqspi->fifo_width / 2, 151931fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); 152031fb632bSRamuthevar Vadivel Murugan /* Program write watermark -- 1/8 of the FIFO. */ 152131fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth * cqspi->fifo_width / 8, 152231fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); 152331fb632bSRamuthevar Vadivel Murugan 1524ad2775dcSRamuthevar Vadivel Murugan /* Disable direct access controller */ 1525ad2775dcSRamuthevar Vadivel Murugan if (!cqspi->use_direct_mode) { 152631fb632bSRamuthevar Vadivel Murugan reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 1527ad2775dcSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL; 152831fb632bSRamuthevar Vadivel Murugan writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 1529ad2775dcSRamuthevar Vadivel Murugan } 153031fb632bSRamuthevar Vadivel Murugan 15311a6f854fSSai Krishna Potthuri /* Enable DMA interface */ 15321a6f854fSSai Krishna Potthuri if (cqspi->use_dma_read) { 15331a6f854fSSai Krishna Potthuri reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 15341a6f854fSSai Krishna Potthuri reg |= CQSPI_REG_CONFIG_DMA_MASK; 15351a6f854fSSai Krishna Potthuri writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 15361a6f854fSSai Krishna Potthuri } 15371a6f854fSSai Krishna Potthuri 153831fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1); 153931fb632bSRamuthevar Vadivel Murugan } 154031fb632bSRamuthevar Vadivel Murugan 154131fb632bSRamuthevar Vadivel Murugan static int cqspi_request_mmap_dma(struct cqspi_st *cqspi) 154231fb632bSRamuthevar Vadivel Murugan { 154331fb632bSRamuthevar Vadivel Murugan dma_cap_mask_t mask; 154431fb632bSRamuthevar Vadivel Murugan 154531fb632bSRamuthevar Vadivel Murugan dma_cap_zero(mask); 154631fb632bSRamuthevar Vadivel Murugan dma_cap_set(DMA_MEMCPY, mask); 154731fb632bSRamuthevar Vadivel Murugan 154831fb632bSRamuthevar Vadivel Murugan cqspi->rx_chan = dma_request_chan_by_mask(&mask); 154931fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->rx_chan)) { 155031fb632bSRamuthevar Vadivel Murugan int ret = PTR_ERR(cqspi->rx_chan); 155131fb632bSRamuthevar Vadivel Murugan cqspi->rx_chan = NULL; 1552436a5c20SKrzysztof Kozlowski return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n"); 155331fb632bSRamuthevar Vadivel Murugan } 155431fb632bSRamuthevar Vadivel Murugan init_completion(&cqspi->rx_dma_complete); 155531fb632bSRamuthevar Vadivel Murugan 155631fb632bSRamuthevar Vadivel Murugan return 0; 155731fb632bSRamuthevar Vadivel Murugan } 155831fb632bSRamuthevar Vadivel Murugan 15592ea370a9SVignesh Raghavendra static const char *cqspi_get_name(struct spi_mem *mem) 15602ea370a9SVignesh Raghavendra { 15612ea370a9SVignesh Raghavendra struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); 15622ea370a9SVignesh Raghavendra struct device *dev = &cqspi->pdev->dev; 15632ea370a9SVignesh Raghavendra 15642ea370a9SVignesh Raghavendra return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select); 15652ea370a9SVignesh Raghavendra } 15662ea370a9SVignesh Raghavendra 156731fb632bSRamuthevar Vadivel Murugan static const struct spi_controller_mem_ops cqspi_mem_ops = { 156831fb632bSRamuthevar Vadivel Murugan .exec_op = cqspi_exec_mem_op, 15692ea370a9SVignesh Raghavendra .get_name = cqspi_get_name, 1570a273596bSPratyush Yadav .supports_op = cqspi_supports_mem_op, 157131fb632bSRamuthevar Vadivel Murugan }; 157231fb632bSRamuthevar Vadivel Murugan 1573a9be4549SMiquel Raynal static const struct spi_controller_mem_caps cqspi_mem_caps = { 1574a9be4549SMiquel Raynal .dtr = true, 1575a9be4549SMiquel Raynal }; 1576a9be4549SMiquel Raynal 157731fb632bSRamuthevar Vadivel Murugan static int cqspi_setup_flash(struct cqspi_st *cqspi) 157831fb632bSRamuthevar Vadivel Murugan { 157931fb632bSRamuthevar Vadivel Murugan struct platform_device *pdev = cqspi->pdev; 158031fb632bSRamuthevar Vadivel Murugan struct device *dev = &pdev->dev; 158131fb632bSRamuthevar Vadivel Murugan struct device_node *np = dev->of_node; 158231fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata; 158331fb632bSRamuthevar Vadivel Murugan unsigned int cs; 158431fb632bSRamuthevar Vadivel Murugan int ret; 158531fb632bSRamuthevar Vadivel Murugan 158631fb632bSRamuthevar Vadivel Murugan /* Get flash device data */ 158731fb632bSRamuthevar Vadivel Murugan for_each_available_child_of_node(dev->of_node, np) { 158831fb632bSRamuthevar Vadivel Murugan ret = of_property_read_u32(np, "reg", &cs); 158931fb632bSRamuthevar Vadivel Murugan if (ret) { 159031fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Couldn't determine chip select.\n"); 159187d62d8fSJunlin Yang of_node_put(np); 159231fb632bSRamuthevar Vadivel Murugan return ret; 159331fb632bSRamuthevar Vadivel Murugan } 159431fb632bSRamuthevar Vadivel Murugan 159531fb632bSRamuthevar Vadivel Murugan if (cs >= CQSPI_MAX_CHIPSELECT) { 159631fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Chip select %d out of range.\n", cs); 159787d62d8fSJunlin Yang of_node_put(np); 159831fb632bSRamuthevar Vadivel Murugan return -EINVAL; 159931fb632bSRamuthevar Vadivel Murugan } 160031fb632bSRamuthevar Vadivel Murugan 160131fb632bSRamuthevar Vadivel Murugan f_pdata = &cqspi->f_pdata[cs]; 160231fb632bSRamuthevar Vadivel Murugan f_pdata->cqspi = cqspi; 160331fb632bSRamuthevar Vadivel Murugan f_pdata->cs = cs; 160431fb632bSRamuthevar Vadivel Murugan 160531fb632bSRamuthevar Vadivel Murugan ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np); 160687d62d8fSJunlin Yang if (ret) { 160787d62d8fSJunlin Yang of_node_put(np); 160831fb632bSRamuthevar Vadivel Murugan return ret; 160931fb632bSRamuthevar Vadivel Murugan } 161087d62d8fSJunlin Yang } 161131fb632bSRamuthevar Vadivel Murugan 161231fb632bSRamuthevar Vadivel Murugan return 0; 161331fb632bSRamuthevar Vadivel Murugan } 161431fb632bSRamuthevar Vadivel Murugan 161531fb632bSRamuthevar Vadivel Murugan static int cqspi_probe(struct platform_device *pdev) 161631fb632bSRamuthevar Vadivel Murugan { 161731fb632bSRamuthevar Vadivel Murugan const struct cqspi_driver_platdata *ddata; 161831fb632bSRamuthevar Vadivel Murugan struct reset_control *rstc, *rstc_ocp; 161931fb632bSRamuthevar Vadivel Murugan struct device *dev = &pdev->dev; 162031fb632bSRamuthevar Vadivel Murugan struct spi_master *master; 162131fb632bSRamuthevar Vadivel Murugan struct resource *res_ahb; 162231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi; 162331fb632bSRamuthevar Vadivel Murugan struct resource *res; 162431fb632bSRamuthevar Vadivel Murugan int ret; 162531fb632bSRamuthevar Vadivel Murugan int irq; 162631fb632bSRamuthevar Vadivel Murugan 162731fb632bSRamuthevar Vadivel Murugan master = spi_alloc_master(&pdev->dev, sizeof(*cqspi)); 162831fb632bSRamuthevar Vadivel Murugan if (!master) { 162931fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "spi_alloc_master failed\n"); 163031fb632bSRamuthevar Vadivel Murugan return -ENOMEM; 163131fb632bSRamuthevar Vadivel Murugan } 163231fb632bSRamuthevar Vadivel Murugan master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; 163331fb632bSRamuthevar Vadivel Murugan master->mem_ops = &cqspi_mem_ops; 1634a9be4549SMiquel Raynal master->mem_caps = &cqspi_mem_caps; 163531fb632bSRamuthevar Vadivel Murugan master->dev.of_node = pdev->dev.of_node; 163631fb632bSRamuthevar Vadivel Murugan 163731fb632bSRamuthevar Vadivel Murugan cqspi = spi_master_get_devdata(master); 163831fb632bSRamuthevar Vadivel Murugan 163931fb632bSRamuthevar Vadivel Murugan cqspi->pdev = pdev; 1640ea94191eSMeng Li platform_set_drvdata(pdev, cqspi); 164131fb632bSRamuthevar Vadivel Murugan 164231fb632bSRamuthevar Vadivel Murugan /* Obtain configuration from OF. */ 164331fb632bSRamuthevar Vadivel Murugan ret = cqspi_of_get_pdata(cqspi); 164431fb632bSRamuthevar Vadivel Murugan if (ret) { 164531fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get mandatory OF data.\n"); 164631fb632bSRamuthevar Vadivel Murugan ret = -ENODEV; 164731fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 164831fb632bSRamuthevar Vadivel Murugan } 164931fb632bSRamuthevar Vadivel Murugan 165031fb632bSRamuthevar Vadivel Murugan /* Obtain QSPI clock. */ 165131fb632bSRamuthevar Vadivel Murugan cqspi->clk = devm_clk_get(dev, NULL); 165231fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->clk)) { 165331fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot claim QSPI clock.\n"); 165431fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->clk); 165531fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 165631fb632bSRamuthevar Vadivel Murugan } 165731fb632bSRamuthevar Vadivel Murugan 165831fb632bSRamuthevar Vadivel Murugan /* Obtain and remap controller address. */ 165931fb632bSRamuthevar Vadivel Murugan res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 166031fb632bSRamuthevar Vadivel Murugan cqspi->iobase = devm_ioremap_resource(dev, res); 166131fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->iobase)) { 166231fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot remap controller address.\n"); 166331fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->iobase); 166431fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 166531fb632bSRamuthevar Vadivel Murugan } 166631fb632bSRamuthevar Vadivel Murugan 166731fb632bSRamuthevar Vadivel Murugan /* Obtain and remap AHB address. */ 166831fb632bSRamuthevar Vadivel Murugan res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1); 166931fb632bSRamuthevar Vadivel Murugan cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb); 167031fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->ahb_base)) { 167131fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot remap AHB address.\n"); 167231fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->ahb_base); 167331fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 167431fb632bSRamuthevar Vadivel Murugan } 167531fb632bSRamuthevar Vadivel Murugan cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start; 167631fb632bSRamuthevar Vadivel Murugan cqspi->ahb_size = resource_size(res_ahb); 167731fb632bSRamuthevar Vadivel Murugan 167831fb632bSRamuthevar Vadivel Murugan init_completion(&cqspi->transfer_complete); 167931fb632bSRamuthevar Vadivel Murugan 168031fb632bSRamuthevar Vadivel Murugan /* Obtain IRQ line. */ 168131fb632bSRamuthevar Vadivel Murugan irq = platform_get_irq(pdev, 0); 168231fb632bSRamuthevar Vadivel Murugan if (irq < 0) { 168331fb632bSRamuthevar Vadivel Murugan ret = -ENXIO; 168431fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 168531fb632bSRamuthevar Vadivel Murugan } 168631fb632bSRamuthevar Vadivel Murugan 168731fb632bSRamuthevar Vadivel Murugan pm_runtime_enable(dev); 168831fb632bSRamuthevar Vadivel Murugan ret = pm_runtime_get_sync(dev); 168931fb632bSRamuthevar Vadivel Murugan if (ret < 0) { 169031fb632bSRamuthevar Vadivel Murugan pm_runtime_put_noidle(dev); 169131fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 169231fb632bSRamuthevar Vadivel Murugan } 169331fb632bSRamuthevar Vadivel Murugan 169431fb632bSRamuthevar Vadivel Murugan ret = clk_prepare_enable(cqspi->clk); 169531fb632bSRamuthevar Vadivel Murugan if (ret) { 169631fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot enable QSPI clock.\n"); 169731fb632bSRamuthevar Vadivel Murugan goto probe_clk_failed; 169831fb632bSRamuthevar Vadivel Murugan } 169931fb632bSRamuthevar Vadivel Murugan 170031fb632bSRamuthevar Vadivel Murugan /* Obtain QSPI reset control */ 170131fb632bSRamuthevar Vadivel Murugan rstc = devm_reset_control_get_optional_exclusive(dev, "qspi"); 170231fb632bSRamuthevar Vadivel Murugan if (IS_ERR(rstc)) { 1703ac9978fcSZhihao Cheng ret = PTR_ERR(rstc); 170431fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get QSPI reset.\n"); 170531fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 170631fb632bSRamuthevar Vadivel Murugan } 170731fb632bSRamuthevar Vadivel Murugan 170831fb632bSRamuthevar Vadivel Murugan rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); 170931fb632bSRamuthevar Vadivel Murugan if (IS_ERR(rstc_ocp)) { 1710ac9978fcSZhihao Cheng ret = PTR_ERR(rstc_ocp); 171131fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get QSPI OCP reset.\n"); 171231fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 171331fb632bSRamuthevar Vadivel Murugan } 171431fb632bSRamuthevar Vadivel Murugan 171531fb632bSRamuthevar Vadivel Murugan reset_control_assert(rstc); 171631fb632bSRamuthevar Vadivel Murugan reset_control_deassert(rstc); 171731fb632bSRamuthevar Vadivel Murugan 171831fb632bSRamuthevar Vadivel Murugan reset_control_assert(rstc_ocp); 171931fb632bSRamuthevar Vadivel Murugan reset_control_deassert(rstc_ocp); 172031fb632bSRamuthevar Vadivel Murugan 172131fb632bSRamuthevar Vadivel Murugan cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); 17223a5c09c8SPratyush Yadav master->max_speed_hz = cqspi->master_ref_clk_hz; 172398d948ebSDinh Nguyen 172498d948ebSDinh Nguyen /* write completion is supported by default */ 172598d948ebSDinh Nguyen cqspi->wr_completion = true; 172698d948ebSDinh Nguyen 172731fb632bSRamuthevar Vadivel Murugan ddata = of_device_get_match_data(dev); 172831fb632bSRamuthevar Vadivel Murugan if (ddata) { 172931fb632bSRamuthevar Vadivel Murugan if (ddata->quirks & CQSPI_NEEDS_WR_DELAY) 1730f453f293SPratyush Yadav cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, 173131fb632bSRamuthevar Vadivel Murugan cqspi->master_ref_clk_hz); 173231fb632bSRamuthevar Vadivel Murugan if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL) 1733f453f293SPratyush Yadav master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; 173431fb632bSRamuthevar Vadivel Murugan if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) 173531fb632bSRamuthevar Vadivel Murugan cqspi->use_direct_mode = true; 17361a6f854fSSai Krishna Potthuri if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA) 17371a6f854fSSai Krishna Potthuri cqspi->use_dma_read = true; 173898d948ebSDinh Nguyen if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION) 173998d948ebSDinh Nguyen cqspi->wr_completion = false; 17401a6f854fSSai Krishna Potthuri 174109e393e3SSai Krishna Potthuri if (of_device_is_compatible(pdev->dev.of_node, 17421a6f854fSSai Krishna Potthuri "xlnx,versal-ospi-1.0")) 17431a6f854fSSai Krishna Potthuri dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); 174431fb632bSRamuthevar Vadivel Murugan } 174531fb632bSRamuthevar Vadivel Murugan 174631fb632bSRamuthevar Vadivel Murugan ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0, 174731fb632bSRamuthevar Vadivel Murugan pdev->name, cqspi); 174831fb632bSRamuthevar Vadivel Murugan if (ret) { 174931fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot request IRQ.\n"); 175031fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 175131fb632bSRamuthevar Vadivel Murugan } 175231fb632bSRamuthevar Vadivel Murugan 175331fb632bSRamuthevar Vadivel Murugan cqspi_wait_idle(cqspi); 175431fb632bSRamuthevar Vadivel Murugan cqspi_controller_init(cqspi); 175531fb632bSRamuthevar Vadivel Murugan cqspi->current_cs = -1; 175631fb632bSRamuthevar Vadivel Murugan cqspi->sclk = 0; 175731fb632bSRamuthevar Vadivel Murugan 1758b436fb7dSRamuthevar Vadivel Murugan master->num_chipselect = cqspi->num_chipselect; 1759b436fb7dSRamuthevar Vadivel Murugan 176031fb632bSRamuthevar Vadivel Murugan ret = cqspi_setup_flash(cqspi); 176131fb632bSRamuthevar Vadivel Murugan if (ret) { 176231fb632bSRamuthevar Vadivel Murugan dev_err(dev, "failed to setup flash parameters %d\n", ret); 176331fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 176431fb632bSRamuthevar Vadivel Murugan } 176531fb632bSRamuthevar Vadivel Murugan 176631fb632bSRamuthevar Vadivel Murugan if (cqspi->use_direct_mode) { 176731fb632bSRamuthevar Vadivel Murugan ret = cqspi_request_mmap_dma(cqspi); 176831fb632bSRamuthevar Vadivel Murugan if (ret == -EPROBE_DEFER) 176931fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 177031fb632bSRamuthevar Vadivel Murugan } 177131fb632bSRamuthevar Vadivel Murugan 177231fb632bSRamuthevar Vadivel Murugan ret = devm_spi_register_master(dev, master); 177331fb632bSRamuthevar Vadivel Murugan if (ret) { 177431fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret); 177531fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 177631fb632bSRamuthevar Vadivel Murugan } 177731fb632bSRamuthevar Vadivel Murugan 177831fb632bSRamuthevar Vadivel Murugan return 0; 177931fb632bSRamuthevar Vadivel Murugan probe_setup_failed: 178031fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 178131fb632bSRamuthevar Vadivel Murugan probe_reset_failed: 178231fb632bSRamuthevar Vadivel Murugan clk_disable_unprepare(cqspi->clk); 178331fb632bSRamuthevar Vadivel Murugan probe_clk_failed: 178431fb632bSRamuthevar Vadivel Murugan pm_runtime_put_sync(dev); 178531fb632bSRamuthevar Vadivel Murugan pm_runtime_disable(dev); 178631fb632bSRamuthevar Vadivel Murugan probe_master_put: 178731fb632bSRamuthevar Vadivel Murugan spi_master_put(master); 178831fb632bSRamuthevar Vadivel Murugan return ret; 178931fb632bSRamuthevar Vadivel Murugan } 179031fb632bSRamuthevar Vadivel Murugan 179131fb632bSRamuthevar Vadivel Murugan static int cqspi_remove(struct platform_device *pdev) 179231fb632bSRamuthevar Vadivel Murugan { 179331fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = platform_get_drvdata(pdev); 179431fb632bSRamuthevar Vadivel Murugan 179531fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 179631fb632bSRamuthevar Vadivel Murugan 179731fb632bSRamuthevar Vadivel Murugan if (cqspi->rx_chan) 179831fb632bSRamuthevar Vadivel Murugan dma_release_channel(cqspi->rx_chan); 179931fb632bSRamuthevar Vadivel Murugan 180031fb632bSRamuthevar Vadivel Murugan clk_disable_unprepare(cqspi->clk); 180131fb632bSRamuthevar Vadivel Murugan 180231fb632bSRamuthevar Vadivel Murugan pm_runtime_put_sync(&pdev->dev); 180331fb632bSRamuthevar Vadivel Murugan pm_runtime_disable(&pdev->dev); 180431fb632bSRamuthevar Vadivel Murugan 180531fb632bSRamuthevar Vadivel Murugan return 0; 180631fb632bSRamuthevar Vadivel Murugan } 180731fb632bSRamuthevar Vadivel Murugan 180831fb632bSRamuthevar Vadivel Murugan #ifdef CONFIG_PM_SLEEP 180931fb632bSRamuthevar Vadivel Murugan static int cqspi_suspend(struct device *dev) 181031fb632bSRamuthevar Vadivel Murugan { 181131fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev_get_drvdata(dev); 181231fb632bSRamuthevar Vadivel Murugan 181331fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 181431fb632bSRamuthevar Vadivel Murugan return 0; 181531fb632bSRamuthevar Vadivel Murugan } 181631fb632bSRamuthevar Vadivel Murugan 181731fb632bSRamuthevar Vadivel Murugan static int cqspi_resume(struct device *dev) 181831fb632bSRamuthevar Vadivel Murugan { 181931fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev_get_drvdata(dev); 182031fb632bSRamuthevar Vadivel Murugan 182131fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1); 182231fb632bSRamuthevar Vadivel Murugan return 0; 182331fb632bSRamuthevar Vadivel Murugan } 182431fb632bSRamuthevar Vadivel Murugan 182531fb632bSRamuthevar Vadivel Murugan static const struct dev_pm_ops cqspi__dev_pm_ops = { 182631fb632bSRamuthevar Vadivel Murugan .suspend = cqspi_suspend, 182731fb632bSRamuthevar Vadivel Murugan .resume = cqspi_resume, 182831fb632bSRamuthevar Vadivel Murugan }; 182931fb632bSRamuthevar Vadivel Murugan 183031fb632bSRamuthevar Vadivel Murugan #define CQSPI_DEV_PM_OPS (&cqspi__dev_pm_ops) 183131fb632bSRamuthevar Vadivel Murugan #else 183231fb632bSRamuthevar Vadivel Murugan #define CQSPI_DEV_PM_OPS NULL 183331fb632bSRamuthevar Vadivel Murugan #endif 183431fb632bSRamuthevar Vadivel Murugan 183531fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata cdns_qspi = { 183631fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_DISABLE_DAC_MODE, 183731fb632bSRamuthevar Vadivel Murugan }; 183831fb632bSRamuthevar Vadivel Murugan 183931fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata k2g_qspi = { 184031fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_NEEDS_WR_DELAY, 184131fb632bSRamuthevar Vadivel Murugan }; 184231fb632bSRamuthevar Vadivel Murugan 184331fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata am654_ospi = { 184431fb632bSRamuthevar Vadivel Murugan .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 184531fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_NEEDS_WR_DELAY, 184631fb632bSRamuthevar Vadivel Murugan }; 184731fb632bSRamuthevar Vadivel Murugan 1848ad2775dcSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata intel_lgm_qspi = { 1849ad2775dcSRamuthevar Vadivel Murugan .quirks = CQSPI_DISABLE_DAC_MODE, 1850ad2775dcSRamuthevar Vadivel Murugan }; 1851ad2775dcSRamuthevar Vadivel Murugan 185298d948ebSDinh Nguyen static const struct cqspi_driver_platdata socfpga_qspi = { 185398d948ebSDinh Nguyen .quirks = CQSPI_NO_SUPPORT_WR_COMPLETION, 185498d948ebSDinh Nguyen }; 185598d948ebSDinh Nguyen 185609e393e3SSai Krishna Potthuri static const struct cqspi_driver_platdata versal_ospi = { 185709e393e3SSai Krishna Potthuri .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 18581a6f854fSSai Krishna Potthuri .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA, 18591a6f854fSSai Krishna Potthuri .indirect_read_dma = cqspi_versal_indirect_read_dma, 18601a6f854fSSai Krishna Potthuri .get_dma_status = cqspi_get_versal_dma_status, 186109e393e3SSai Krishna Potthuri }; 186209e393e3SSai Krishna Potthuri 186331fb632bSRamuthevar Vadivel Murugan static const struct of_device_id cqspi_dt_ids[] = { 186431fb632bSRamuthevar Vadivel Murugan { 186531fb632bSRamuthevar Vadivel Murugan .compatible = "cdns,qspi-nor", 186631fb632bSRamuthevar Vadivel Murugan .data = &cdns_qspi, 186731fb632bSRamuthevar Vadivel Murugan }, 186831fb632bSRamuthevar Vadivel Murugan { 186931fb632bSRamuthevar Vadivel Murugan .compatible = "ti,k2g-qspi", 187031fb632bSRamuthevar Vadivel Murugan .data = &k2g_qspi, 187131fb632bSRamuthevar Vadivel Murugan }, 187231fb632bSRamuthevar Vadivel Murugan { 187331fb632bSRamuthevar Vadivel Murugan .compatible = "ti,am654-ospi", 187431fb632bSRamuthevar Vadivel Murugan .data = &am654_ospi, 187531fb632bSRamuthevar Vadivel Murugan }, 1876ab2d2875SRamuthevar Vadivel Murugan { 1877ab2d2875SRamuthevar Vadivel Murugan .compatible = "intel,lgm-qspi", 1878ad2775dcSRamuthevar Vadivel Murugan .data = &intel_lgm_qspi, 1879ab2d2875SRamuthevar Vadivel Murugan }, 188009e393e3SSai Krishna Potthuri { 188109e393e3SSai Krishna Potthuri .compatible = "xlnx,versal-ospi-1.0", 188209e393e3SSai Krishna Potthuri .data = (void *)&versal_ospi, 188309e393e3SSai Krishna Potthuri }, 188498d948ebSDinh Nguyen { 188598d948ebSDinh Nguyen .compatible = "intel,socfpga-qspi", 188698d948ebSDinh Nguyen .data = (void *)&socfpga_qspi, 188798d948ebSDinh Nguyen }, 188831fb632bSRamuthevar Vadivel Murugan { /* end of table */ } 188931fb632bSRamuthevar Vadivel Murugan }; 189031fb632bSRamuthevar Vadivel Murugan 189131fb632bSRamuthevar Vadivel Murugan MODULE_DEVICE_TABLE(of, cqspi_dt_ids); 189231fb632bSRamuthevar Vadivel Murugan 189331fb632bSRamuthevar Vadivel Murugan static struct platform_driver cqspi_platform_driver = { 189431fb632bSRamuthevar Vadivel Murugan .probe = cqspi_probe, 189531fb632bSRamuthevar Vadivel Murugan .remove = cqspi_remove, 189631fb632bSRamuthevar Vadivel Murugan .driver = { 189731fb632bSRamuthevar Vadivel Murugan .name = CQSPI_NAME, 189831fb632bSRamuthevar Vadivel Murugan .pm = CQSPI_DEV_PM_OPS, 189931fb632bSRamuthevar Vadivel Murugan .of_match_table = cqspi_dt_ids, 190031fb632bSRamuthevar Vadivel Murugan }, 190131fb632bSRamuthevar Vadivel Murugan }; 190231fb632bSRamuthevar Vadivel Murugan 190331fb632bSRamuthevar Vadivel Murugan module_platform_driver(cqspi_platform_driver); 190431fb632bSRamuthevar Vadivel Murugan 190531fb632bSRamuthevar Vadivel Murugan MODULE_DESCRIPTION("Cadence QSPI Controller Driver"); 190631fb632bSRamuthevar Vadivel Murugan MODULE_LICENSE("GPL v2"); 190731fb632bSRamuthevar Vadivel Murugan MODULE_ALIAS("platform:" CQSPI_NAME); 190831fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>"); 190931fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>"); 191031fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>"); 191131fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>"); 1912f453f293SPratyush Yadav MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>"); 1913