131fb632bSRamuthevar Vadivel Murugan // SPDX-License-Identifier: GPL-2.0-only 231fb632bSRamuthevar Vadivel Murugan // 331fb632bSRamuthevar Vadivel Murugan // Driver for Cadence QSPI Controller 431fb632bSRamuthevar Vadivel Murugan // 531fb632bSRamuthevar Vadivel Murugan // Copyright Altera Corporation (C) 2012-2014. All rights reserved. 631fb632bSRamuthevar Vadivel Murugan // Copyright Intel Corporation (C) 2019-2020. All rights reserved. 731fb632bSRamuthevar Vadivel Murugan // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 831fb632bSRamuthevar Vadivel Murugan 931fb632bSRamuthevar Vadivel Murugan #include <linux/clk.h> 1031fb632bSRamuthevar Vadivel Murugan #include <linux/completion.h> 1131fb632bSRamuthevar Vadivel Murugan #include <linux/delay.h> 1231fb632bSRamuthevar Vadivel Murugan #include <linux/dma-mapping.h> 1331fb632bSRamuthevar Vadivel Murugan #include <linux/dmaengine.h> 1431fb632bSRamuthevar Vadivel Murugan #include <linux/err.h> 1531fb632bSRamuthevar Vadivel Murugan #include <linux/errno.h> 1609e393e3SSai Krishna Potthuri #include <linux/firmware/xlnx-zynqmp.h> 1731fb632bSRamuthevar Vadivel Murugan #include <linux/interrupt.h> 1831fb632bSRamuthevar Vadivel Murugan #include <linux/io.h> 1931fb632bSRamuthevar Vadivel Murugan #include <linux/iopoll.h> 2031fb632bSRamuthevar Vadivel Murugan #include <linux/jiffies.h> 2131fb632bSRamuthevar Vadivel Murugan #include <linux/kernel.h> 2297e4827dSMatthias Schiffer #include <linux/log2.h> 2331fb632bSRamuthevar Vadivel Murugan #include <linux/module.h> 2431fb632bSRamuthevar Vadivel Murugan #include <linux/of_device.h> 2531fb632bSRamuthevar Vadivel Murugan #include <linux/of.h> 2631fb632bSRamuthevar Vadivel Murugan #include <linux/platform_device.h> 2731fb632bSRamuthevar Vadivel Murugan #include <linux/pm_runtime.h> 2831fb632bSRamuthevar Vadivel Murugan #include <linux/reset.h> 2931fb632bSRamuthevar Vadivel Murugan #include <linux/sched.h> 3031fb632bSRamuthevar Vadivel Murugan #include <linux/spi/spi.h> 3131fb632bSRamuthevar Vadivel Murugan #include <linux/spi/spi-mem.h> 3231fb632bSRamuthevar Vadivel Murugan #include <linux/timer.h> 3331fb632bSRamuthevar Vadivel Murugan 3431fb632bSRamuthevar Vadivel Murugan #define CQSPI_NAME "cadence-qspi" 3531fb632bSRamuthevar Vadivel Murugan #define CQSPI_MAX_CHIPSELECT 16 3631fb632bSRamuthevar Vadivel Murugan 3731fb632bSRamuthevar Vadivel Murugan /* Quirks */ 3831fb632bSRamuthevar Vadivel Murugan #define CQSPI_NEEDS_WR_DELAY BIT(0) 3931fb632bSRamuthevar Vadivel Murugan #define CQSPI_DISABLE_DAC_MODE BIT(1) 401a6f854fSSai Krishna Potthuri #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) 4198d948ebSDinh Nguyen #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) 429ee5b6d5SNiravkumar L Rabara #define CQSPI_SLOW_SRAM BIT(4) 4331fb632bSRamuthevar Vadivel Murugan 4431fb632bSRamuthevar Vadivel Murugan /* Capabilities */ 4531fb632bSRamuthevar Vadivel Murugan #define CQSPI_SUPPORTS_OCTAL BIT(0) 4631fb632bSRamuthevar Vadivel Murugan 4728ac902aSMatthias Schiffer #define CQSPI_OP_WIDTH(part) ((part).nbytes ? ilog2((part).buswidth) : 0) 4828ac902aSMatthias Schiffer 4931fb632bSRamuthevar Vadivel Murugan struct cqspi_st; 5031fb632bSRamuthevar Vadivel Murugan 5131fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata { 5231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi; 5331fb632bSRamuthevar Vadivel Murugan u32 clk_rate; 5431fb632bSRamuthevar Vadivel Murugan u32 read_delay; 5531fb632bSRamuthevar Vadivel Murugan u32 tshsl_ns; 5631fb632bSRamuthevar Vadivel Murugan u32 tsd2d_ns; 5731fb632bSRamuthevar Vadivel Murugan u32 tchsh_ns; 5831fb632bSRamuthevar Vadivel Murugan u32 tslch_ns; 5931fb632bSRamuthevar Vadivel Murugan u8 cs; 6031fb632bSRamuthevar Vadivel Murugan }; 6131fb632bSRamuthevar Vadivel Murugan 6231fb632bSRamuthevar Vadivel Murugan struct cqspi_st { 6331fb632bSRamuthevar Vadivel Murugan struct platform_device *pdev; 64606e5d40SVaishnav Achath struct spi_master *master; 6531fb632bSRamuthevar Vadivel Murugan struct clk *clk; 6631fb632bSRamuthevar Vadivel Murugan unsigned int sclk; 6731fb632bSRamuthevar Vadivel Murugan 6831fb632bSRamuthevar Vadivel Murugan void __iomem *iobase; 6931fb632bSRamuthevar Vadivel Murugan void __iomem *ahb_base; 7031fb632bSRamuthevar Vadivel Murugan resource_size_t ahb_size; 7131fb632bSRamuthevar Vadivel Murugan struct completion transfer_complete; 7231fb632bSRamuthevar Vadivel Murugan 7331fb632bSRamuthevar Vadivel Murugan struct dma_chan *rx_chan; 7431fb632bSRamuthevar Vadivel Murugan struct completion rx_dma_complete; 7531fb632bSRamuthevar Vadivel Murugan dma_addr_t mmap_phys_base; 7631fb632bSRamuthevar Vadivel Murugan 7731fb632bSRamuthevar Vadivel Murugan int current_cs; 7831fb632bSRamuthevar Vadivel Murugan unsigned long master_ref_clk_hz; 7931fb632bSRamuthevar Vadivel Murugan bool is_decoded_cs; 8031fb632bSRamuthevar Vadivel Murugan u32 fifo_depth; 8131fb632bSRamuthevar Vadivel Murugan u32 fifo_width; 82b436fb7dSRamuthevar Vadivel Murugan u32 num_chipselect; 8331fb632bSRamuthevar Vadivel Murugan bool rclk_en; 8431fb632bSRamuthevar Vadivel Murugan u32 trigger_address; 8531fb632bSRamuthevar Vadivel Murugan u32 wr_delay; 8631fb632bSRamuthevar Vadivel Murugan bool use_direct_mode; 87e8c51b16SDhruva Gole bool use_direct_mode_wr; 8831fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; 891a6f854fSSai Krishna Potthuri bool use_dma_read; 9009e393e3SSai Krishna Potthuri u32 pd_dev_id; 9198d948ebSDinh Nguyen bool wr_completion; 929ee5b6d5SNiravkumar L Rabara bool slow_sram; 9331fb632bSRamuthevar Vadivel Murugan }; 9431fb632bSRamuthevar Vadivel Murugan 9531fb632bSRamuthevar Vadivel Murugan struct cqspi_driver_platdata { 9631fb632bSRamuthevar Vadivel Murugan u32 hwcaps_mask; 9731fb632bSRamuthevar Vadivel Murugan u8 quirks; 981a6f854fSSai Krishna Potthuri int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata, 991a6f854fSSai Krishna Potthuri u_char *rxbuf, loff_t from_addr, size_t n_rx); 1001a6f854fSSai Krishna Potthuri u32 (*get_dma_status)(struct cqspi_st *cqspi); 10131fb632bSRamuthevar Vadivel Murugan }; 10231fb632bSRamuthevar Vadivel Murugan 10331fb632bSRamuthevar Vadivel Murugan /* Operation timeout value */ 10431fb632bSRamuthevar Vadivel Murugan #define CQSPI_TIMEOUT_MS 500 10531fb632bSRamuthevar Vadivel Murugan #define CQSPI_READ_TIMEOUT_MS 10 10631fb632bSRamuthevar Vadivel Murugan 10731fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_CLKS_PER_BYTE 8 10831fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_BYTES_MAX 4 10931fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_CLKS_MAX 31 11031fb632bSRamuthevar Vadivel Murugan 11131fb632bSRamuthevar Vadivel Murugan #define CQSPI_STIG_DATA_LEN_MAX 8 11231fb632bSRamuthevar Vadivel Murugan 11331fb632bSRamuthevar Vadivel Murugan /* Register map */ 11431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG 0x00 11531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0) 11631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7) 11731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9) 11831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 11931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_DMA_MASK BIT(15) 12031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_BAUD_LSB 19 121f453f293SPratyush Yadav #define CQSPI_REG_CONFIG_DTR_PROTO BIT(24) 122f453f293SPratyush Yadav #define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30) 12331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_IDLE_LSB 31 12431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF 12531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_BAUD_MASK 0xF 12631fb632bSRamuthevar Vadivel Murugan 12731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR 0x04 12831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 12931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 13031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 13131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 13231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 13331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 13431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 13531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 13631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 13731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F 13831fb632bSRamuthevar Vadivel Murugan 13931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR 0x08 14031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 14131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12 14231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16 14331fb632bSRamuthevar Vadivel Murugan 14431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY 0x0C 14531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSLCH_LSB 0 14631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TCHSH_LSB 8 14731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSD2D_LSB 16 14831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSHSL_LSB 24 14931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF 15031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF 15131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF 15231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF 15331fb632bSRamuthevar Vadivel Murugan 15431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE 0x10 15531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0 15631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_DELAY_LSB 1 15731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF 15831fb632bSRamuthevar Vadivel Murugan 15931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE 0x14 16031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_ADDRESS_LSB 0 16131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_PAGE_LSB 4 16231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_BLOCK_LSB 16 16331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF 16431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF 16531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F 16631fb632bSRamuthevar Vadivel Murugan 16731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SRAMPARTITION 0x18 16831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTTRIGGER 0x1C 16931fb632bSRamuthevar Vadivel Murugan 17031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA 0x20 17131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_SINGLE_LSB 0 17231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_BURST_LSB 8 17331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_SINGLE_MASK 0xFF 17431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_BURST_MASK 0xFF 17531fb632bSRamuthevar Vadivel Murugan 17631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_REMAP 0x24 17731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_MODE_BIT 0x28 17831fb632bSRamuthevar Vadivel Murugan 17931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL 0x2C 18031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 18131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 18231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF 18331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF 18431fb632bSRamuthevar Vadivel Murugan 185f453f293SPratyush Yadav #define CQSPI_REG_WR_COMPLETION_CTRL 0x38 186f453f293SPratyush Yadav #define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14) 187f453f293SPratyush Yadav 18831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQSTATUS 0x40 18931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQMASK 0x44 19031fb632bSRamuthevar Vadivel Murugan 19131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD 0x60 19231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0) 19331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1) 19431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5) 19531fb632bSRamuthevar Vadivel Murugan 19631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDWATERMARK 0x64 19731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 19831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDBYTES 0x6C 19931fb632bSRamuthevar Vadivel Murugan 20031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL 0x90 20131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0) 20231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1) 203888d517bSPratyush Yadav #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 20431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 20531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 20631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 20731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 20831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 20931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 21031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 21131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 21231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 21331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 214888d517bSPratyush Yadav #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F 21531fb632bSRamuthevar Vadivel Murugan 21631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR 0x70 21731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0) 21831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1) 21931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5) 22031fb632bSRamuthevar Vadivel Murugan 22131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRWATERMARK 0x74 22231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 22331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRBYTES 0x7C 22431fb632bSRamuthevar Vadivel Murugan 2251a6f854fSSai Krishna Potthuri #define CQSPI_REG_INDTRIG_ADDRRANGE 0x80 2261a6f854fSSai Krishna Potthuri 22731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDADDRESS 0x94 22831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDREADDATALOWER 0xA0 22931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDREADDATAUPPER 0xA4 23031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDWRITEDATALOWER 0xA8 23131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC 23231fb632bSRamuthevar Vadivel Murugan 233f453f293SPratyush Yadav #define CQSPI_REG_POLLING_STATUS 0xB0 234f453f293SPratyush Yadav #define CQSPI_REG_POLLING_STATUS_DUMMY_LSB 16 235f453f293SPratyush Yadav 236f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_LOWER 0xE0 237f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_READ_LSB 24 238f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_WRITE_LSB 16 239f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_STIG_LSB 0 240f453f293SPratyush Yadav 2411a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_SRC_ADDR 0x1000 2421a6f854fSSai Krishna Potthuri 2431a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_ADDR 0x1800 2441a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_SIZE 0x1804 2451a6f854fSSai Krishna Potthuri 2461a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_CTRL 0x180C 2471a6f854fSSai Krishna Potthuri 2481a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_I_STS 0x1814 2491a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_I_EN 0x1818 2501a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_I_DIS 0x181C 2511a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_DONE_MASK BIT(1) 2521a6f854fSSai Krishna Potthuri 2531a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB 0x1828 2541a6f854fSSai Krishna Potthuri 2551a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL 0xF43FFA00 2561a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL 0x6 2571a6f854fSSai Krishna Potthuri 25831fb632bSRamuthevar Vadivel Murugan /* Interrupt status bits */ 25931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_MODE_ERR BIT(0) 26031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_UNDERFLOW BIT(1) 26131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_COMP BIT(2) 26231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3) 26331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4) 26431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5) 26531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_WATERMARK BIT(6) 26631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12) 26731fb632bSRamuthevar Vadivel Murugan 26831fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \ 26931fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_IND_SRAM_FULL | \ 27031fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_IND_COMP) 27131fb632bSRamuthevar Vadivel Murugan 27231fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \ 27331fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_WATERMARK | \ 27431fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_UNDERFLOW) 27531fb632bSRamuthevar Vadivel Murugan 27631fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_STATUS_MASK 0x1FFFF 2771a6f854fSSai Krishna Potthuri #define CQSPI_DMA_UNALIGN 0x3 2781a6f854fSSai Krishna Potthuri 2791a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_VAL 0x602 28031fb632bSRamuthevar Vadivel Murugan 28131fb632bSRamuthevar Vadivel Murugan static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr) 28231fb632bSRamuthevar Vadivel Murugan { 28331fb632bSRamuthevar Vadivel Murugan u32 val; 28431fb632bSRamuthevar Vadivel Murugan 28531fb632bSRamuthevar Vadivel Murugan return readl_relaxed_poll_timeout(reg, val, 28631fb632bSRamuthevar Vadivel Murugan (((clr ? ~val : val) & mask) == mask), 28731fb632bSRamuthevar Vadivel Murugan 10, CQSPI_TIMEOUT_MS * 1000); 28831fb632bSRamuthevar Vadivel Murugan } 28931fb632bSRamuthevar Vadivel Murugan 29031fb632bSRamuthevar Vadivel Murugan static bool cqspi_is_idle(struct cqspi_st *cqspi) 29131fb632bSRamuthevar Vadivel Murugan { 29231fb632bSRamuthevar Vadivel Murugan u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 29331fb632bSRamuthevar Vadivel Murugan 29431890269SJay Fang return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB); 29531fb632bSRamuthevar Vadivel Murugan } 29631fb632bSRamuthevar Vadivel Murugan 29731fb632bSRamuthevar Vadivel Murugan static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi) 29831fb632bSRamuthevar Vadivel Murugan { 29931fb632bSRamuthevar Vadivel Murugan u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL); 30031fb632bSRamuthevar Vadivel Murugan 30131fb632bSRamuthevar Vadivel Murugan reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB; 30231fb632bSRamuthevar Vadivel Murugan return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK; 30331fb632bSRamuthevar Vadivel Murugan } 30431fb632bSRamuthevar Vadivel Murugan 3051a6f854fSSai Krishna Potthuri static u32 cqspi_get_versal_dma_status(struct cqspi_st *cqspi) 3061a6f854fSSai Krishna Potthuri { 3071a6f854fSSai Krishna Potthuri u32 dma_status; 3081a6f854fSSai Krishna Potthuri 3091a6f854fSSai Krishna Potthuri dma_status = readl(cqspi->iobase + 3101a6f854fSSai Krishna Potthuri CQSPI_REG_VERSAL_DMA_DST_I_STS); 3111a6f854fSSai Krishna Potthuri writel(dma_status, cqspi->iobase + 3121a6f854fSSai Krishna Potthuri CQSPI_REG_VERSAL_DMA_DST_I_STS); 3131a6f854fSSai Krishna Potthuri 3141a6f854fSSai Krishna Potthuri return dma_status & CQSPI_REG_VERSAL_DMA_DST_DONE_MASK; 3151a6f854fSSai Krishna Potthuri } 3161a6f854fSSai Krishna Potthuri 31731fb632bSRamuthevar Vadivel Murugan static irqreturn_t cqspi_irq_handler(int this_irq, void *dev) 31831fb632bSRamuthevar Vadivel Murugan { 31931fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev; 32031fb632bSRamuthevar Vadivel Murugan unsigned int irq_status; 3211a6f854fSSai Krishna Potthuri struct device *device = &cqspi->pdev->dev; 3221a6f854fSSai Krishna Potthuri const struct cqspi_driver_platdata *ddata; 3231a6f854fSSai Krishna Potthuri 3241a6f854fSSai Krishna Potthuri ddata = of_device_get_match_data(device); 32531fb632bSRamuthevar Vadivel Murugan 32631fb632bSRamuthevar Vadivel Murugan /* Read interrupt status */ 32731fb632bSRamuthevar Vadivel Murugan irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS); 32831fb632bSRamuthevar Vadivel Murugan 32931fb632bSRamuthevar Vadivel Murugan /* Clear interrupt */ 33031fb632bSRamuthevar Vadivel Murugan writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS); 33131fb632bSRamuthevar Vadivel Murugan 3321a6f854fSSai Krishna Potthuri if (cqspi->use_dma_read && ddata && ddata->get_dma_status) { 3331a6f854fSSai Krishna Potthuri if (ddata->get_dma_status(cqspi)) { 3341a6f854fSSai Krishna Potthuri complete(&cqspi->transfer_complete); 3351a6f854fSSai Krishna Potthuri return IRQ_HANDLED; 3361a6f854fSSai Krishna Potthuri } 3371a6f854fSSai Krishna Potthuri } 3381a6f854fSSai Krishna Potthuri 3399ee5b6d5SNiravkumar L Rabara else if (!cqspi->slow_sram) 34031fb632bSRamuthevar Vadivel Murugan irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR; 3419ee5b6d5SNiravkumar L Rabara else 3429ee5b6d5SNiravkumar L Rabara irq_status &= CQSPI_REG_IRQ_WATERMARK | CQSPI_IRQ_MASK_WR; 34331fb632bSRamuthevar Vadivel Murugan 34431fb632bSRamuthevar Vadivel Murugan if (irq_status) 34531fb632bSRamuthevar Vadivel Murugan complete(&cqspi->transfer_complete); 34631fb632bSRamuthevar Vadivel Murugan 34731fb632bSRamuthevar Vadivel Murugan return IRQ_HANDLED; 34831fb632bSRamuthevar Vadivel Murugan } 34931fb632bSRamuthevar Vadivel Murugan 35028ac902aSMatthias Schiffer static unsigned int cqspi_calc_rdreg(const struct spi_mem_op *op) 35131fb632bSRamuthevar Vadivel Murugan { 35231fb632bSRamuthevar Vadivel Murugan u32 rdreg = 0; 35331fb632bSRamuthevar Vadivel Murugan 35428ac902aSMatthias Schiffer rdreg |= CQSPI_OP_WIDTH(op->cmd) << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; 35528ac902aSMatthias Schiffer rdreg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; 35628ac902aSMatthias Schiffer rdreg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; 35731fb632bSRamuthevar Vadivel Murugan 35831fb632bSRamuthevar Vadivel Murugan return rdreg; 35931fb632bSRamuthevar Vadivel Murugan } 36031fb632bSRamuthevar Vadivel Murugan 36128ac902aSMatthias Schiffer static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op) 362888d517bSPratyush Yadav { 3630ccfd1baSYoshitaka Ikeda unsigned int dummy_clk; 364888d517bSPratyush Yadav 3650e85ee89SYoshitaka Ikeda if (!op->dummy.nbytes) 3660e85ee89SYoshitaka Ikeda return 0; 3670e85ee89SYoshitaka Ikeda 3687512eaf5SPratyush Yadav dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth); 36928ac902aSMatthias Schiffer if (op->cmd.dtr) 370f453f293SPratyush Yadav dummy_clk /= 2; 371888d517bSPratyush Yadav 372888d517bSPratyush Yadav return dummy_clk; 373888d517bSPratyush Yadav } 374888d517bSPratyush Yadav 37531fb632bSRamuthevar Vadivel Murugan static int cqspi_wait_idle(struct cqspi_st *cqspi) 37631fb632bSRamuthevar Vadivel Murugan { 37731fb632bSRamuthevar Vadivel Murugan const unsigned int poll_idle_retry = 3; 37831fb632bSRamuthevar Vadivel Murugan unsigned int count = 0; 37931fb632bSRamuthevar Vadivel Murugan unsigned long timeout; 38031fb632bSRamuthevar Vadivel Murugan 38131fb632bSRamuthevar Vadivel Murugan timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS); 38231fb632bSRamuthevar Vadivel Murugan while (1) { 38331fb632bSRamuthevar Vadivel Murugan /* 38431fb632bSRamuthevar Vadivel Murugan * Read few times in succession to ensure the controller 38531fb632bSRamuthevar Vadivel Murugan * is indeed idle, that is, the bit does not transition 38631fb632bSRamuthevar Vadivel Murugan * low again. 38731fb632bSRamuthevar Vadivel Murugan */ 38831fb632bSRamuthevar Vadivel Murugan if (cqspi_is_idle(cqspi)) 38931fb632bSRamuthevar Vadivel Murugan count++; 39031fb632bSRamuthevar Vadivel Murugan else 39131fb632bSRamuthevar Vadivel Murugan count = 0; 39231fb632bSRamuthevar Vadivel Murugan 39331fb632bSRamuthevar Vadivel Murugan if (count >= poll_idle_retry) 39431fb632bSRamuthevar Vadivel Murugan return 0; 39531fb632bSRamuthevar Vadivel Murugan 39631fb632bSRamuthevar Vadivel Murugan if (time_after(jiffies, timeout)) { 39731fb632bSRamuthevar Vadivel Murugan /* Timeout, in busy mode. */ 39831fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 39931fb632bSRamuthevar Vadivel Murugan "QSPI is still busy after %dms timeout.\n", 40031fb632bSRamuthevar Vadivel Murugan CQSPI_TIMEOUT_MS); 40131fb632bSRamuthevar Vadivel Murugan return -ETIMEDOUT; 40231fb632bSRamuthevar Vadivel Murugan } 40331fb632bSRamuthevar Vadivel Murugan 40431fb632bSRamuthevar Vadivel Murugan cpu_relax(); 40531fb632bSRamuthevar Vadivel Murugan } 40631fb632bSRamuthevar Vadivel Murugan } 40731fb632bSRamuthevar Vadivel Murugan 40831fb632bSRamuthevar Vadivel Murugan static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg) 40931fb632bSRamuthevar Vadivel Murugan { 41031fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 41131fb632bSRamuthevar Vadivel Murugan int ret; 41231fb632bSRamuthevar Vadivel Murugan 41331fb632bSRamuthevar Vadivel Murugan /* Write the CMDCTRL without start execution. */ 41431fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CMDCTRL); 41531fb632bSRamuthevar Vadivel Murugan /* Start execute */ 41631fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK; 41731fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CMDCTRL); 41831fb632bSRamuthevar Vadivel Murugan 41931fb632bSRamuthevar Vadivel Murugan /* Polling for completion. */ 42031fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL, 42131fb632bSRamuthevar Vadivel Murugan CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1); 42231fb632bSRamuthevar Vadivel Murugan if (ret) { 42331fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 42431fb632bSRamuthevar Vadivel Murugan "Flash command execution timed out.\n"); 42531fb632bSRamuthevar Vadivel Murugan return ret; 42631fb632bSRamuthevar Vadivel Murugan } 42731fb632bSRamuthevar Vadivel Murugan 42831fb632bSRamuthevar Vadivel Murugan /* Polling QSPI idle status. */ 42931fb632bSRamuthevar Vadivel Murugan return cqspi_wait_idle(cqspi); 43031fb632bSRamuthevar Vadivel Murugan } 43131fb632bSRamuthevar Vadivel Murugan 432f453f293SPratyush Yadav static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata, 433f453f293SPratyush Yadav const struct spi_mem_op *op, 434f453f293SPratyush Yadav unsigned int shift) 435f453f293SPratyush Yadav { 436f453f293SPratyush Yadav struct cqspi_st *cqspi = f_pdata->cqspi; 437f453f293SPratyush Yadav void __iomem *reg_base = cqspi->iobase; 438f453f293SPratyush Yadav unsigned int reg; 439f453f293SPratyush Yadav u8 ext; 440f453f293SPratyush Yadav 441f453f293SPratyush Yadav if (op->cmd.nbytes != 2) 442f453f293SPratyush Yadav return -EINVAL; 443f453f293SPratyush Yadav 444f453f293SPratyush Yadav /* Opcode extension is the LSB. */ 445f453f293SPratyush Yadav ext = op->cmd.opcode & 0xff; 446f453f293SPratyush Yadav 447f453f293SPratyush Yadav reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER); 448f453f293SPratyush Yadav reg &= ~(0xff << shift); 449f453f293SPratyush Yadav reg |= ext << shift; 450f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER); 451f453f293SPratyush Yadav 452f453f293SPratyush Yadav return 0; 453f453f293SPratyush Yadav } 454f453f293SPratyush Yadav 455f453f293SPratyush Yadav static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata, 45628ac902aSMatthias Schiffer const struct spi_mem_op *op, unsigned int shift) 457f453f293SPratyush Yadav { 458f453f293SPratyush Yadav struct cqspi_st *cqspi = f_pdata->cqspi; 459f453f293SPratyush Yadav void __iomem *reg_base = cqspi->iobase; 460f453f293SPratyush Yadav unsigned int reg; 461f453f293SPratyush Yadav int ret; 462f453f293SPratyush Yadav 463f453f293SPratyush Yadav reg = readl(reg_base + CQSPI_REG_CONFIG); 464f453f293SPratyush Yadav 465f453f293SPratyush Yadav /* 466f453f293SPratyush Yadav * We enable dual byte opcode here. The callers have to set up the 467f453f293SPratyush Yadav * extension opcode based on which type of operation it is. 468f453f293SPratyush Yadav */ 46928ac902aSMatthias Schiffer if (op->cmd.dtr) { 470f453f293SPratyush Yadav reg |= CQSPI_REG_CONFIG_DTR_PROTO; 471f453f293SPratyush Yadav reg |= CQSPI_REG_CONFIG_DUAL_OPCODE; 472f453f293SPratyush Yadav 473f453f293SPratyush Yadav /* Set up command opcode extension. */ 474f453f293SPratyush Yadav ret = cqspi_setup_opcode_ext(f_pdata, op, shift); 475f453f293SPratyush Yadav if (ret) 476f453f293SPratyush Yadav return ret; 477f453f293SPratyush Yadav } else { 478f453f293SPratyush Yadav reg &= ~CQSPI_REG_CONFIG_DTR_PROTO; 479f453f293SPratyush Yadav reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE; 480f453f293SPratyush Yadav } 481f453f293SPratyush Yadav 482f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_CONFIG); 483f453f293SPratyush Yadav 484f453f293SPratyush Yadav return cqspi_wait_idle(cqspi); 485f453f293SPratyush Yadav } 486f453f293SPratyush Yadav 48731fb632bSRamuthevar Vadivel Murugan static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, 48831fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 48931fb632bSRamuthevar Vadivel Murugan { 49031fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 49131fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 49231fb632bSRamuthevar Vadivel Murugan u8 *rxbuf = op->data.buf.in; 493f453f293SPratyush Yadav u8 opcode; 49431fb632bSRamuthevar Vadivel Murugan size_t n_rx = op->data.nbytes; 49531fb632bSRamuthevar Vadivel Murugan unsigned int rdreg; 49631fb632bSRamuthevar Vadivel Murugan unsigned int reg; 497888d517bSPratyush Yadav unsigned int dummy_clk; 49831fb632bSRamuthevar Vadivel Murugan size_t read_len; 49931fb632bSRamuthevar Vadivel Murugan int status; 50031fb632bSRamuthevar Vadivel Murugan 50128ac902aSMatthias Schiffer status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB); 502f453f293SPratyush Yadav if (status) 503f453f293SPratyush Yadav return status; 504f453f293SPratyush Yadav 50531fb632bSRamuthevar Vadivel Murugan if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) { 50631fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 50731fb632bSRamuthevar Vadivel Murugan "Invalid input argument, len %zu rxbuf 0x%p\n", 50831fb632bSRamuthevar Vadivel Murugan n_rx, rxbuf); 50931fb632bSRamuthevar Vadivel Murugan return -EINVAL; 51031fb632bSRamuthevar Vadivel Murugan } 51131fb632bSRamuthevar Vadivel Murugan 51228ac902aSMatthias Schiffer if (op->cmd.dtr) 513f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 514f453f293SPratyush Yadav else 515f453f293SPratyush Yadav opcode = op->cmd.opcode; 516f453f293SPratyush Yadav 51731fb632bSRamuthevar Vadivel Murugan reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 51831fb632bSRamuthevar Vadivel Murugan 51928ac902aSMatthias Schiffer rdreg = cqspi_calc_rdreg(op); 52031fb632bSRamuthevar Vadivel Murugan writel(rdreg, reg_base + CQSPI_REG_RD_INSTR); 52131fb632bSRamuthevar Vadivel Murugan 52228ac902aSMatthias Schiffer dummy_clk = cqspi_calc_dummy(op); 523888d517bSPratyush Yadav if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 524888d517bSPratyush Yadav return -EOPNOTSUPP; 525888d517bSPratyush Yadav 526888d517bSPratyush Yadav if (dummy_clk) 527888d517bSPratyush Yadav reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK) 528888d517bSPratyush Yadav << CQSPI_REG_CMDCTRL_DUMMY_LSB; 529888d517bSPratyush Yadav 53031fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); 53131fb632bSRamuthevar Vadivel Murugan 53231fb632bSRamuthevar Vadivel Murugan /* 0 means 1 byte. */ 53331fb632bSRamuthevar Vadivel Murugan reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) 53431fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); 535a8674ae0SDhruva Gole 536a8674ae0SDhruva Gole /* setup ADDR BIT field */ 537a8674ae0SDhruva Gole if (op->addr.nbytes) { 538a8674ae0SDhruva Gole reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 539a8674ae0SDhruva Gole reg |= ((op->addr.nbytes - 1) & 540a8674ae0SDhruva Gole CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) 541a8674ae0SDhruva Gole << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; 542a8674ae0SDhruva Gole 543a8674ae0SDhruva Gole writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); 544a8674ae0SDhruva Gole } 545a8674ae0SDhruva Gole 54631fb632bSRamuthevar Vadivel Murugan status = cqspi_exec_flash_cmd(cqspi, reg); 54731fb632bSRamuthevar Vadivel Murugan if (status) 54831fb632bSRamuthevar Vadivel Murugan return status; 54931fb632bSRamuthevar Vadivel Murugan 55031fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER); 55131fb632bSRamuthevar Vadivel Murugan 55231fb632bSRamuthevar Vadivel Murugan /* Put the read value into rx_buf */ 55331fb632bSRamuthevar Vadivel Murugan read_len = (n_rx > 4) ? 4 : n_rx; 55431fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, ®, read_len); 55531fb632bSRamuthevar Vadivel Murugan rxbuf += read_len; 55631fb632bSRamuthevar Vadivel Murugan 55731fb632bSRamuthevar Vadivel Murugan if (n_rx > 4) { 55831fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER); 55931fb632bSRamuthevar Vadivel Murugan 56031fb632bSRamuthevar Vadivel Murugan read_len = n_rx - read_len; 56131fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, ®, read_len); 56231fb632bSRamuthevar Vadivel Murugan } 56331fb632bSRamuthevar Vadivel Murugan 564d4f43a2dSDhruva Gole /* Reset CMD_CTRL Reg once command read completes */ 565d4f43a2dSDhruva Gole writel(0, reg_base + CQSPI_REG_CMDCTRL); 566d4f43a2dSDhruva Gole 56731fb632bSRamuthevar Vadivel Murugan return 0; 56831fb632bSRamuthevar Vadivel Murugan } 56931fb632bSRamuthevar Vadivel Murugan 57031fb632bSRamuthevar Vadivel Murugan static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata, 57131fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 57231fb632bSRamuthevar Vadivel Murugan { 57331fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 57431fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 575f453f293SPratyush Yadav u8 opcode; 57631fb632bSRamuthevar Vadivel Murugan const u8 *txbuf = op->data.buf.out; 57731fb632bSRamuthevar Vadivel Murugan size_t n_tx = op->data.nbytes; 57831fb632bSRamuthevar Vadivel Murugan unsigned int reg; 57931fb632bSRamuthevar Vadivel Murugan unsigned int data; 58031fb632bSRamuthevar Vadivel Murugan size_t write_len; 581f453f293SPratyush Yadav int ret; 582f453f293SPratyush Yadav 58328ac902aSMatthias Schiffer ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB); 584f453f293SPratyush Yadav if (ret) 585f453f293SPratyush Yadav return ret; 58631fb632bSRamuthevar Vadivel Murugan 58731fb632bSRamuthevar Vadivel Murugan if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) { 58831fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 58931fb632bSRamuthevar Vadivel Murugan "Invalid input argument, cmdlen %zu txbuf 0x%p\n", 59031fb632bSRamuthevar Vadivel Murugan n_tx, txbuf); 59131fb632bSRamuthevar Vadivel Murugan return -EINVAL; 59231fb632bSRamuthevar Vadivel Murugan } 59331fb632bSRamuthevar Vadivel Murugan 59428ac902aSMatthias Schiffer reg = cqspi_calc_rdreg(op); 595f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_RD_INSTR); 596f453f293SPratyush Yadav 59728ac902aSMatthias Schiffer if (op->cmd.dtr) 598f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 599f453f293SPratyush Yadav else 600f453f293SPratyush Yadav opcode = op->cmd.opcode; 601f453f293SPratyush Yadav 60231fb632bSRamuthevar Vadivel Murugan reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 60331fb632bSRamuthevar Vadivel Murugan 60431fb632bSRamuthevar Vadivel Murugan if (op->addr.nbytes) { 60531fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 60631fb632bSRamuthevar Vadivel Murugan reg |= ((op->addr.nbytes - 1) & 60731fb632bSRamuthevar Vadivel Murugan CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) 60831fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; 60931fb632bSRamuthevar Vadivel Murugan 61031fb632bSRamuthevar Vadivel Murugan writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); 61131fb632bSRamuthevar Vadivel Murugan } 61231fb632bSRamuthevar Vadivel Murugan 61331fb632bSRamuthevar Vadivel Murugan if (n_tx) { 61431fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB); 61531fb632bSRamuthevar Vadivel Murugan reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) 61631fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_WR_BYTES_LSB; 61731fb632bSRamuthevar Vadivel Murugan data = 0; 61831fb632bSRamuthevar Vadivel Murugan write_len = (n_tx > 4) ? 4 : n_tx; 61931fb632bSRamuthevar Vadivel Murugan memcpy(&data, txbuf, write_len); 62031fb632bSRamuthevar Vadivel Murugan txbuf += write_len; 62131fb632bSRamuthevar Vadivel Murugan writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER); 62231fb632bSRamuthevar Vadivel Murugan 62331fb632bSRamuthevar Vadivel Murugan if (n_tx > 4) { 62431fb632bSRamuthevar Vadivel Murugan data = 0; 62531fb632bSRamuthevar Vadivel Murugan write_len = n_tx - 4; 62631fb632bSRamuthevar Vadivel Murugan memcpy(&data, txbuf, write_len); 62731fb632bSRamuthevar Vadivel Murugan writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER); 62831fb632bSRamuthevar Vadivel Murugan } 62931fb632bSRamuthevar Vadivel Murugan } 63031fb632bSRamuthevar Vadivel Murugan 631d4f43a2dSDhruva Gole ret = cqspi_exec_flash_cmd(cqspi, reg); 632d4f43a2dSDhruva Gole 633d4f43a2dSDhruva Gole /* Reset CMD_CTRL Reg once command write completes */ 634d4f43a2dSDhruva Gole writel(0, reg_base + CQSPI_REG_CMDCTRL); 635d4f43a2dSDhruva Gole 636d4f43a2dSDhruva Gole return ret; 63731fb632bSRamuthevar Vadivel Murugan } 63831fb632bSRamuthevar Vadivel Murugan 63931fb632bSRamuthevar Vadivel Murugan static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata, 64031fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 64131fb632bSRamuthevar Vadivel Murugan { 64231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 64331fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 64431fb632bSRamuthevar Vadivel Murugan unsigned int dummy_clk = 0; 64531fb632bSRamuthevar Vadivel Murugan unsigned int reg; 646f453f293SPratyush Yadav int ret; 647f453f293SPratyush Yadav u8 opcode; 64831fb632bSRamuthevar Vadivel Murugan 64928ac902aSMatthias Schiffer ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB); 650f453f293SPratyush Yadav if (ret) 651f453f293SPratyush Yadav return ret; 652f453f293SPratyush Yadav 65328ac902aSMatthias Schiffer if (op->cmd.dtr) 654f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 655f453f293SPratyush Yadav else 656f453f293SPratyush Yadav opcode = op->cmd.opcode; 657f453f293SPratyush Yadav 658f453f293SPratyush Yadav reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB; 65928ac902aSMatthias Schiffer reg |= cqspi_calc_rdreg(op); 66031fb632bSRamuthevar Vadivel Murugan 66131fb632bSRamuthevar Vadivel Murugan /* Setup dummy clock cycles */ 66228ac902aSMatthias Schiffer dummy_clk = cqspi_calc_dummy(op); 663888d517bSPratyush Yadav 66431fb632bSRamuthevar Vadivel Murugan if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 665ceeda328SPratyush Yadav return -EOPNOTSUPP; 66631fb632bSRamuthevar Vadivel Murugan 66731fb632bSRamuthevar Vadivel Murugan if (dummy_clk) 66831fb632bSRamuthevar Vadivel Murugan reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK) 66931fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_RD_INSTR_DUMMY_LSB; 67031fb632bSRamuthevar Vadivel Murugan 67131fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_RD_INSTR); 67231fb632bSRamuthevar Vadivel Murugan 67331fb632bSRamuthevar Vadivel Murugan /* Set address width */ 67431fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_SIZE); 67531fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 67631fb632bSRamuthevar Vadivel Murugan reg |= (op->addr.nbytes - 1); 67731fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_SIZE); 67831fb632bSRamuthevar Vadivel Murugan return 0; 67931fb632bSRamuthevar Vadivel Murugan } 68031fb632bSRamuthevar Vadivel Murugan 68131fb632bSRamuthevar Vadivel Murugan static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, 68231fb632bSRamuthevar Vadivel Murugan u8 *rxbuf, loff_t from_addr, 68331fb632bSRamuthevar Vadivel Murugan const size_t n_rx) 68431fb632bSRamuthevar Vadivel Murugan { 68531fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 68631fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 68731fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 68831fb632bSRamuthevar Vadivel Murugan void __iomem *ahb_base = cqspi->ahb_base; 68931fb632bSRamuthevar Vadivel Murugan unsigned int remaining = n_rx; 69031fb632bSRamuthevar Vadivel Murugan unsigned int mod_bytes = n_rx % 4; 69131fb632bSRamuthevar Vadivel Murugan unsigned int bytes_to_read = 0; 69231fb632bSRamuthevar Vadivel Murugan u8 *rxbuf_end = rxbuf + n_rx; 69331fb632bSRamuthevar Vadivel Murugan int ret = 0; 69431fb632bSRamuthevar Vadivel Murugan 69531fb632bSRamuthevar Vadivel Murugan writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 69631fb632bSRamuthevar Vadivel Murugan writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES); 69731fb632bSRamuthevar Vadivel Murugan 69831fb632bSRamuthevar Vadivel Murugan /* Clear all interrupts. */ 69931fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 70031fb632bSRamuthevar Vadivel Murugan 7019ee5b6d5SNiravkumar L Rabara /* 7029ee5b6d5SNiravkumar L Rabara * On SoCFPGA platform reading the SRAM is slow due to 7039ee5b6d5SNiravkumar L Rabara * hardware limitation and causing read interrupt storm to CPU, 7049ee5b6d5SNiravkumar L Rabara * so enabling only watermark interrupt to disable all read 7059ee5b6d5SNiravkumar L Rabara * interrupts later as we want to run "bytes to read" loop with 7069ee5b6d5SNiravkumar L Rabara * all the read interrupts disabled for max performance. 7079ee5b6d5SNiravkumar L Rabara */ 7089ee5b6d5SNiravkumar L Rabara 7099ee5b6d5SNiravkumar L Rabara if (!cqspi->slow_sram) 71031fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK); 7119ee5b6d5SNiravkumar L Rabara else 7129ee5b6d5SNiravkumar L Rabara writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK); 71331fb632bSRamuthevar Vadivel Murugan 71431fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 71531fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTRD_START_MASK, 71631fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTRD); 71731fb632bSRamuthevar Vadivel Murugan 71831fb632bSRamuthevar Vadivel Murugan while (remaining > 0) { 71931fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->transfer_complete, 72031fb632bSRamuthevar Vadivel Murugan msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) 72131fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 72231fb632bSRamuthevar Vadivel Murugan 7239ee5b6d5SNiravkumar L Rabara /* 7249ee5b6d5SNiravkumar L Rabara * Disable all read interrupts until 7259ee5b6d5SNiravkumar L Rabara * we are out of "bytes to read" 7269ee5b6d5SNiravkumar L Rabara */ 7279ee5b6d5SNiravkumar L Rabara if (cqspi->slow_sram) 7289ee5b6d5SNiravkumar L Rabara writel(0x0, reg_base + CQSPI_REG_IRQMASK); 7299ee5b6d5SNiravkumar L Rabara 73031fb632bSRamuthevar Vadivel Murugan bytes_to_read = cqspi_get_rd_sram_level(cqspi); 73131fb632bSRamuthevar Vadivel Murugan 73231fb632bSRamuthevar Vadivel Murugan if (ret && bytes_to_read == 0) { 73331fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect read timeout, no bytes\n"); 73431fb632bSRamuthevar Vadivel Murugan goto failrd; 73531fb632bSRamuthevar Vadivel Murugan } 73631fb632bSRamuthevar Vadivel Murugan 73731fb632bSRamuthevar Vadivel Murugan while (bytes_to_read != 0) { 73831fb632bSRamuthevar Vadivel Murugan unsigned int word_remain = round_down(remaining, 4); 73931fb632bSRamuthevar Vadivel Murugan 74031fb632bSRamuthevar Vadivel Murugan bytes_to_read *= cqspi->fifo_width; 74131fb632bSRamuthevar Vadivel Murugan bytes_to_read = bytes_to_read > remaining ? 74231fb632bSRamuthevar Vadivel Murugan remaining : bytes_to_read; 74331fb632bSRamuthevar Vadivel Murugan bytes_to_read = round_down(bytes_to_read, 4); 74431fb632bSRamuthevar Vadivel Murugan /* Read 4 byte word chunks then single bytes */ 74531fb632bSRamuthevar Vadivel Murugan if (bytes_to_read) { 74631fb632bSRamuthevar Vadivel Murugan ioread32_rep(ahb_base, rxbuf, 74731fb632bSRamuthevar Vadivel Murugan (bytes_to_read / 4)); 74831fb632bSRamuthevar Vadivel Murugan } else if (!word_remain && mod_bytes) { 74931fb632bSRamuthevar Vadivel Murugan unsigned int temp = ioread32(ahb_base); 75031fb632bSRamuthevar Vadivel Murugan 75131fb632bSRamuthevar Vadivel Murugan bytes_to_read = mod_bytes; 75231fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, &temp, min((unsigned int) 75331fb632bSRamuthevar Vadivel Murugan (rxbuf_end - rxbuf), 75431fb632bSRamuthevar Vadivel Murugan bytes_to_read)); 75531fb632bSRamuthevar Vadivel Murugan } 75631fb632bSRamuthevar Vadivel Murugan rxbuf += bytes_to_read; 75731fb632bSRamuthevar Vadivel Murugan remaining -= bytes_to_read; 75831fb632bSRamuthevar Vadivel Murugan bytes_to_read = cqspi_get_rd_sram_level(cqspi); 75931fb632bSRamuthevar Vadivel Murugan } 76031fb632bSRamuthevar Vadivel Murugan 7619ee5b6d5SNiravkumar L Rabara if (remaining > 0) { 76231fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 7639ee5b6d5SNiravkumar L Rabara if (cqspi->slow_sram) 7649ee5b6d5SNiravkumar L Rabara writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK); 7659ee5b6d5SNiravkumar L Rabara } 76631fb632bSRamuthevar Vadivel Murugan } 76731fb632bSRamuthevar Vadivel Murugan 76831fb632bSRamuthevar Vadivel Murugan /* Check indirect done status */ 76931fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD, 77031fb632bSRamuthevar Vadivel Murugan CQSPI_REG_INDIRECTRD_DONE_MASK, 0); 77131fb632bSRamuthevar Vadivel Murugan if (ret) { 77231fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect read completion error (%i)\n", ret); 77331fb632bSRamuthevar Vadivel Murugan goto failrd; 77431fb632bSRamuthevar Vadivel Murugan } 77531fb632bSRamuthevar Vadivel Murugan 77631fb632bSRamuthevar Vadivel Murugan /* Disable interrupt */ 77731fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 77831fb632bSRamuthevar Vadivel Murugan 77931fb632bSRamuthevar Vadivel Murugan /* Clear indirect completion status */ 78031fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD); 78131fb632bSRamuthevar Vadivel Murugan 78231fb632bSRamuthevar Vadivel Murugan return 0; 78331fb632bSRamuthevar Vadivel Murugan 78431fb632bSRamuthevar Vadivel Murugan failrd: 78531fb632bSRamuthevar Vadivel Murugan /* Disable interrupt */ 78631fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 78731fb632bSRamuthevar Vadivel Murugan 78831fb632bSRamuthevar Vadivel Murugan /* Cancel the indirect read */ 789152ac606SHongbin Ji writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK, 79031fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTRD); 79131fb632bSRamuthevar Vadivel Murugan return ret; 79231fb632bSRamuthevar Vadivel Murugan } 79331fb632bSRamuthevar Vadivel Murugan 794c0b53f4eSSai Krishna Potthuri static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable) 795c0b53f4eSSai Krishna Potthuri { 796c0b53f4eSSai Krishna Potthuri void __iomem *reg_base = cqspi->iobase; 797c0b53f4eSSai Krishna Potthuri unsigned int reg; 798c0b53f4eSSai Krishna Potthuri 799c0b53f4eSSai Krishna Potthuri reg = readl(reg_base + CQSPI_REG_CONFIG); 800c0b53f4eSSai Krishna Potthuri 801c0b53f4eSSai Krishna Potthuri if (enable) 802c0b53f4eSSai Krishna Potthuri reg |= CQSPI_REG_CONFIG_ENABLE_MASK; 803c0b53f4eSSai Krishna Potthuri else 804c0b53f4eSSai Krishna Potthuri reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; 805c0b53f4eSSai Krishna Potthuri 806c0b53f4eSSai Krishna Potthuri writel(reg, reg_base + CQSPI_REG_CONFIG); 807c0b53f4eSSai Krishna Potthuri } 808c0b53f4eSSai Krishna Potthuri 8091a6f854fSSai Krishna Potthuri static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata, 8101a6f854fSSai Krishna Potthuri u_char *rxbuf, loff_t from_addr, 8111a6f854fSSai Krishna Potthuri size_t n_rx) 8121a6f854fSSai Krishna Potthuri { 8131a6f854fSSai Krishna Potthuri struct cqspi_st *cqspi = f_pdata->cqspi; 8141a6f854fSSai Krishna Potthuri struct device *dev = &cqspi->pdev->dev; 8151a6f854fSSai Krishna Potthuri void __iomem *reg_base = cqspi->iobase; 8161a6f854fSSai Krishna Potthuri u32 reg, bytes_to_dma; 8171a6f854fSSai Krishna Potthuri loff_t addr = from_addr; 8181a6f854fSSai Krishna Potthuri void *buf = rxbuf; 8191a6f854fSSai Krishna Potthuri dma_addr_t dma_addr; 8201a6f854fSSai Krishna Potthuri u8 bytes_rem; 8211a6f854fSSai Krishna Potthuri int ret = 0; 8221a6f854fSSai Krishna Potthuri 8231a6f854fSSai Krishna Potthuri bytes_rem = n_rx % 4; 8241a6f854fSSai Krishna Potthuri bytes_to_dma = (n_rx - bytes_rem); 8251a6f854fSSai Krishna Potthuri 8261a6f854fSSai Krishna Potthuri if (!bytes_to_dma) 8271a6f854fSSai Krishna Potthuri goto nondmard; 8281a6f854fSSai Krishna Potthuri 8291a6f854fSSai Krishna Potthuri ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA); 8301a6f854fSSai Krishna Potthuri if (ret) 8311a6f854fSSai Krishna Potthuri return ret; 8321a6f854fSSai Krishna Potthuri 833c0b53f4eSSai Krishna Potthuri cqspi_controller_enable(cqspi, 0); 834c0b53f4eSSai Krishna Potthuri 8351a6f854fSSai Krishna Potthuri reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 8361a6f854fSSai Krishna Potthuri reg |= CQSPI_REG_CONFIG_DMA_MASK; 8371a6f854fSSai Krishna Potthuri writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 8381a6f854fSSai Krishna Potthuri 839c0b53f4eSSai Krishna Potthuri cqspi_controller_enable(cqspi, 1); 840c0b53f4eSSai Krishna Potthuri 8411a6f854fSSai Krishna Potthuri dma_addr = dma_map_single(dev, rxbuf, bytes_to_dma, DMA_FROM_DEVICE); 8421a6f854fSSai Krishna Potthuri if (dma_mapping_error(dev, dma_addr)) { 8431a6f854fSSai Krishna Potthuri dev_err(dev, "dma mapping failed\n"); 8441a6f854fSSai Krishna Potthuri return -ENOMEM; 8451a6f854fSSai Krishna Potthuri } 8461a6f854fSSai Krishna Potthuri 8471a6f854fSSai Krishna Potthuri writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 8481a6f854fSSai Krishna Potthuri writel(bytes_to_dma, reg_base + CQSPI_REG_INDIRECTRDBYTES); 8491a6f854fSSai Krishna Potthuri writel(CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL, 8501a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_INDTRIG_ADDRRANGE); 8511a6f854fSSai Krishna Potthuri 8521a6f854fSSai Krishna Potthuri /* Clear all interrupts. */ 8531a6f854fSSai Krishna Potthuri writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 8541a6f854fSSai Krishna Potthuri 8551a6f854fSSai Krishna Potthuri /* Enable DMA done interrupt */ 8561a6f854fSSai Krishna Potthuri writel(CQSPI_REG_VERSAL_DMA_DST_DONE_MASK, 8571a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_VERSAL_DMA_DST_I_EN); 8581a6f854fSSai Krishna Potthuri 8591a6f854fSSai Krishna Potthuri /* Default DMA periph configuration */ 8601a6f854fSSai Krishna Potthuri writel(CQSPI_REG_VERSAL_DMA_VAL, reg_base + CQSPI_REG_DMA); 8611a6f854fSSai Krishna Potthuri 8621a6f854fSSai Krishna Potthuri /* Configure DMA Dst address */ 8631a6f854fSSai Krishna Potthuri writel(lower_32_bits(dma_addr), 8641a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR); 8651a6f854fSSai Krishna Potthuri writel(upper_32_bits(dma_addr), 8661a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB); 8671a6f854fSSai Krishna Potthuri 8681a6f854fSSai Krishna Potthuri /* Configure DMA Src address */ 8691a6f854fSSai Krishna Potthuri writel(cqspi->trigger_address, reg_base + 8701a6f854fSSai Krishna Potthuri CQSPI_REG_VERSAL_DMA_SRC_ADDR); 8711a6f854fSSai Krishna Potthuri 8721a6f854fSSai Krishna Potthuri /* Set DMA destination size */ 8731a6f854fSSai Krishna Potthuri writel(bytes_to_dma, reg_base + CQSPI_REG_VERSAL_DMA_DST_SIZE); 8741a6f854fSSai Krishna Potthuri 8751a6f854fSSai Krishna Potthuri /* Set DMA destination control */ 8761a6f854fSSai Krishna Potthuri writel(CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL, 8771a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_VERSAL_DMA_DST_CTRL); 8781a6f854fSSai Krishna Potthuri 8791a6f854fSSai Krishna Potthuri writel(CQSPI_REG_INDIRECTRD_START_MASK, 8801a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_INDIRECTRD); 8811a6f854fSSai Krishna Potthuri 8821a6f854fSSai Krishna Potthuri reinit_completion(&cqspi->transfer_complete); 8831a6f854fSSai Krishna Potthuri 8841a6f854fSSai Krishna Potthuri if (!wait_for_completion_timeout(&cqspi->transfer_complete, 88522c8ce0aSSai Krishna Potthuri msecs_to_jiffies(max_t(size_t, bytes_to_dma, 500)))) { 8861a6f854fSSai Krishna Potthuri ret = -ETIMEDOUT; 8871a6f854fSSai Krishna Potthuri goto failrd; 8881a6f854fSSai Krishna Potthuri } 8891a6f854fSSai Krishna Potthuri 8901a6f854fSSai Krishna Potthuri /* Disable DMA interrupt */ 8911a6f854fSSai Krishna Potthuri writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS); 8921a6f854fSSai Krishna Potthuri 8931a6f854fSSai Krishna Potthuri /* Clear indirect completion status */ 8941a6f854fSSai Krishna Potthuri writel(CQSPI_REG_INDIRECTRD_DONE_MASK, 8951a6f854fSSai Krishna Potthuri cqspi->iobase + CQSPI_REG_INDIRECTRD); 8961a6f854fSSai Krishna Potthuri dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE); 8971a6f854fSSai Krishna Potthuri 898c0b53f4eSSai Krishna Potthuri cqspi_controller_enable(cqspi, 0); 899c0b53f4eSSai Krishna Potthuri 9001a6f854fSSai Krishna Potthuri reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 9011a6f854fSSai Krishna Potthuri reg &= ~CQSPI_REG_CONFIG_DMA_MASK; 9021a6f854fSSai Krishna Potthuri writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 9031a6f854fSSai Krishna Potthuri 904c0b53f4eSSai Krishna Potthuri cqspi_controller_enable(cqspi, 1); 905c0b53f4eSSai Krishna Potthuri 9061a6f854fSSai Krishna Potthuri ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, 9071a6f854fSSai Krishna Potthuri PM_OSPI_MUX_SEL_LINEAR); 9081a6f854fSSai Krishna Potthuri if (ret) 9091a6f854fSSai Krishna Potthuri return ret; 9101a6f854fSSai Krishna Potthuri 9111a6f854fSSai Krishna Potthuri nondmard: 9121a6f854fSSai Krishna Potthuri if (bytes_rem) { 9131a6f854fSSai Krishna Potthuri addr += bytes_to_dma; 9141a6f854fSSai Krishna Potthuri buf += bytes_to_dma; 9151a6f854fSSai Krishna Potthuri ret = cqspi_indirect_read_execute(f_pdata, buf, addr, 9161a6f854fSSai Krishna Potthuri bytes_rem); 9171a6f854fSSai Krishna Potthuri if (ret) 9181a6f854fSSai Krishna Potthuri return ret; 9191a6f854fSSai Krishna Potthuri } 9201a6f854fSSai Krishna Potthuri 9211a6f854fSSai Krishna Potthuri return 0; 9221a6f854fSSai Krishna Potthuri 9231a6f854fSSai Krishna Potthuri failrd: 9241a6f854fSSai Krishna Potthuri /* Disable DMA interrupt */ 9251a6f854fSSai Krishna Potthuri writel(0x0, reg_base + CQSPI_REG_VERSAL_DMA_DST_I_DIS); 9261a6f854fSSai Krishna Potthuri 9271a6f854fSSai Krishna Potthuri /* Cancel the indirect read */ 9281a6f854fSSai Krishna Potthuri writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 9291a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_INDIRECTRD); 9301a6f854fSSai Krishna Potthuri 931d9c55c95SArnd Bergmann dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE); 9321a6f854fSSai Krishna Potthuri 9331a6f854fSSai Krishna Potthuri reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 9341a6f854fSSai Krishna Potthuri reg &= ~CQSPI_REG_CONFIG_DMA_MASK; 9351a6f854fSSai Krishna Potthuri writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 9361a6f854fSSai Krishna Potthuri 9371a6f854fSSai Krishna Potthuri zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR); 9381a6f854fSSai Krishna Potthuri 9391a6f854fSSai Krishna Potthuri return ret; 9401a6f854fSSai Krishna Potthuri } 9411a6f854fSSai Krishna Potthuri 94231fb632bSRamuthevar Vadivel Murugan static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata, 94331fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 94431fb632bSRamuthevar Vadivel Murugan { 94531fb632bSRamuthevar Vadivel Murugan unsigned int reg; 946f453f293SPratyush Yadav int ret; 94731fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 94831fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 949f453f293SPratyush Yadav u8 opcode; 950f453f293SPratyush Yadav 95128ac902aSMatthias Schiffer ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB); 952f453f293SPratyush Yadav if (ret) 953f453f293SPratyush Yadav return ret; 954f453f293SPratyush Yadav 95528ac902aSMatthias Schiffer if (op->cmd.dtr) 956f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 957f453f293SPratyush Yadav else 958f453f293SPratyush Yadav opcode = op->cmd.opcode; 95931fb632bSRamuthevar Vadivel Murugan 96031fb632bSRamuthevar Vadivel Murugan /* Set opcode. */ 961f453f293SPratyush Yadav reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; 96228ac902aSMatthias Schiffer reg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; 96328ac902aSMatthias Schiffer reg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; 96431fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_WR_INSTR); 96528ac902aSMatthias Schiffer reg = cqspi_calc_rdreg(op); 96631fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_RD_INSTR); 96731fb632bSRamuthevar Vadivel Murugan 968f453f293SPratyush Yadav /* 9699cb2ff11SApurva Nandan * SPI NAND flashes require the address of the status register to be 9709cb2ff11SApurva Nandan * passed in the Read SR command. Also, some SPI NOR flashes like the 9719cb2ff11SApurva Nandan * cypress Semper flash expect a 4-byte dummy address in the Read SR 9729cb2ff11SApurva Nandan * command in DTR mode. 9739cb2ff11SApurva Nandan * 9749cb2ff11SApurva Nandan * But this controller does not support address phase in the Read SR 9759cb2ff11SApurva Nandan * command when doing auto-HW polling. So, disable write completion 9769cb2ff11SApurva Nandan * polling on the controller's side. spinand and spi-nor will take 9779cb2ff11SApurva Nandan * care of polling the status register. 978f453f293SPratyush Yadav */ 97998d948ebSDinh Nguyen if (cqspi->wr_completion) { 980f453f293SPratyush Yadav reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL); 981f453f293SPratyush Yadav reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL; 982f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL); 983e8c51b16SDhruva Gole /* 984e8c51b16SDhruva Gole * DAC mode require auto polling as flash needs to be polled 985e8c51b16SDhruva Gole * for write completion in case of bubble in SPI transaction 986e8c51b16SDhruva Gole * due to slow CPU/DMA master. 987e8c51b16SDhruva Gole */ 988e8c51b16SDhruva Gole cqspi->use_direct_mode_wr = false; 98998d948ebSDinh Nguyen } 990f453f293SPratyush Yadav 99131fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_SIZE); 99231fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 99331fb632bSRamuthevar Vadivel Murugan reg |= (op->addr.nbytes - 1); 99431fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_SIZE); 99531fb632bSRamuthevar Vadivel Murugan return 0; 99631fb632bSRamuthevar Vadivel Murugan } 99731fb632bSRamuthevar Vadivel Murugan 99831fb632bSRamuthevar Vadivel Murugan static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, 99931fb632bSRamuthevar Vadivel Murugan loff_t to_addr, const u8 *txbuf, 100031fb632bSRamuthevar Vadivel Murugan const size_t n_tx) 100131fb632bSRamuthevar Vadivel Murugan { 100231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 100331fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 100431fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 100531fb632bSRamuthevar Vadivel Murugan unsigned int remaining = n_tx; 100631fb632bSRamuthevar Vadivel Murugan unsigned int write_bytes; 100731fb632bSRamuthevar Vadivel Murugan int ret; 100831fb632bSRamuthevar Vadivel Murugan 100931fb632bSRamuthevar Vadivel Murugan writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR); 101031fb632bSRamuthevar Vadivel Murugan writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES); 101131fb632bSRamuthevar Vadivel Murugan 101231fb632bSRamuthevar Vadivel Murugan /* Clear all interrupts. */ 101331fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 101431fb632bSRamuthevar Vadivel Murugan 101531fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK); 101631fb632bSRamuthevar Vadivel Murugan 101731fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 101831fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_START_MASK, 101931fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTWR); 102031fb632bSRamuthevar Vadivel Murugan /* 102131fb632bSRamuthevar Vadivel Murugan * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access 102231fb632bSRamuthevar Vadivel Murugan * Controller programming sequence, couple of cycles of 102331fb632bSRamuthevar Vadivel Murugan * QSPI_REF_CLK delay is required for the above bit to 102431fb632bSRamuthevar Vadivel Murugan * be internally synchronized by the QSPI module. Provide 5 102531fb632bSRamuthevar Vadivel Murugan * cycles of delay. 102631fb632bSRamuthevar Vadivel Murugan */ 102731fb632bSRamuthevar Vadivel Murugan if (cqspi->wr_delay) 102831fb632bSRamuthevar Vadivel Murugan ndelay(cqspi->wr_delay); 102931fb632bSRamuthevar Vadivel Murugan 103031fb632bSRamuthevar Vadivel Murugan while (remaining > 0) { 103131fb632bSRamuthevar Vadivel Murugan size_t write_words, mod_bytes; 103231fb632bSRamuthevar Vadivel Murugan 103331fb632bSRamuthevar Vadivel Murugan write_bytes = remaining; 103431fb632bSRamuthevar Vadivel Murugan write_words = write_bytes / 4; 103531fb632bSRamuthevar Vadivel Murugan mod_bytes = write_bytes % 4; 103631fb632bSRamuthevar Vadivel Murugan /* Write 4 bytes at a time then single bytes. */ 103731fb632bSRamuthevar Vadivel Murugan if (write_words) { 103831fb632bSRamuthevar Vadivel Murugan iowrite32_rep(cqspi->ahb_base, txbuf, write_words); 103931fb632bSRamuthevar Vadivel Murugan txbuf += (write_words * 4); 104031fb632bSRamuthevar Vadivel Murugan } 104131fb632bSRamuthevar Vadivel Murugan if (mod_bytes) { 104231fb632bSRamuthevar Vadivel Murugan unsigned int temp = 0xFFFFFFFF; 104331fb632bSRamuthevar Vadivel Murugan 104431fb632bSRamuthevar Vadivel Murugan memcpy(&temp, txbuf, mod_bytes); 104531fb632bSRamuthevar Vadivel Murugan iowrite32(temp, cqspi->ahb_base); 104631fb632bSRamuthevar Vadivel Murugan txbuf += mod_bytes; 104731fb632bSRamuthevar Vadivel Murugan } 104831fb632bSRamuthevar Vadivel Murugan 104931fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->transfer_complete, 105031fb632bSRamuthevar Vadivel Murugan msecs_to_jiffies(CQSPI_TIMEOUT_MS))) { 105131fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect write timeout\n"); 105231fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 105331fb632bSRamuthevar Vadivel Murugan goto failwr; 105431fb632bSRamuthevar Vadivel Murugan } 105531fb632bSRamuthevar Vadivel Murugan 105631fb632bSRamuthevar Vadivel Murugan remaining -= write_bytes; 105731fb632bSRamuthevar Vadivel Murugan 105831fb632bSRamuthevar Vadivel Murugan if (remaining > 0) 105931fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 106031fb632bSRamuthevar Vadivel Murugan } 106131fb632bSRamuthevar Vadivel Murugan 106231fb632bSRamuthevar Vadivel Murugan /* Check indirect done status */ 106331fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR, 106431fb632bSRamuthevar Vadivel Murugan CQSPI_REG_INDIRECTWR_DONE_MASK, 0); 106531fb632bSRamuthevar Vadivel Murugan if (ret) { 106631fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect write completion error (%i)\n", ret); 106731fb632bSRamuthevar Vadivel Murugan goto failwr; 106831fb632bSRamuthevar Vadivel Murugan } 106931fb632bSRamuthevar Vadivel Murugan 107031fb632bSRamuthevar Vadivel Murugan /* Disable interrupt. */ 107131fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 107231fb632bSRamuthevar Vadivel Murugan 107331fb632bSRamuthevar Vadivel Murugan /* Clear indirect completion status */ 107431fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR); 107531fb632bSRamuthevar Vadivel Murugan 107631fb632bSRamuthevar Vadivel Murugan cqspi_wait_idle(cqspi); 107731fb632bSRamuthevar Vadivel Murugan 107831fb632bSRamuthevar Vadivel Murugan return 0; 107931fb632bSRamuthevar Vadivel Murugan 108031fb632bSRamuthevar Vadivel Murugan failwr: 108131fb632bSRamuthevar Vadivel Murugan /* Disable interrupt. */ 108231fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 108331fb632bSRamuthevar Vadivel Murugan 108431fb632bSRamuthevar Vadivel Murugan /* Cancel the indirect write */ 108531fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 108631fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTWR); 108731fb632bSRamuthevar Vadivel Murugan return ret; 108831fb632bSRamuthevar Vadivel Murugan } 108931fb632bSRamuthevar Vadivel Murugan 109031fb632bSRamuthevar Vadivel Murugan static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata) 109131fb632bSRamuthevar Vadivel Murugan { 109231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 109331fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 109431fb632bSRamuthevar Vadivel Murugan unsigned int chip_select = f_pdata->cs; 109531fb632bSRamuthevar Vadivel Murugan unsigned int reg; 109631fb632bSRamuthevar Vadivel Murugan 109731fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG); 109831fb632bSRamuthevar Vadivel Murugan if (cqspi->is_decoded_cs) { 109931fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CONFIG_DECODE_MASK; 110031fb632bSRamuthevar Vadivel Murugan } else { 110131fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; 110231fb632bSRamuthevar Vadivel Murugan 110331fb632bSRamuthevar Vadivel Murugan /* Convert CS if without decoder. 110431fb632bSRamuthevar Vadivel Murugan * CS0 to 4b'1110 110531fb632bSRamuthevar Vadivel Murugan * CS1 to 4b'1101 110631fb632bSRamuthevar Vadivel Murugan * CS2 to 4b'1011 110731fb632bSRamuthevar Vadivel Murugan * CS3 to 4b'0111 110831fb632bSRamuthevar Vadivel Murugan */ 110931fb632bSRamuthevar Vadivel Murugan chip_select = 0xF & ~(1 << chip_select); 111031fb632bSRamuthevar Vadivel Murugan } 111131fb632bSRamuthevar Vadivel Murugan 111231fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK 111331fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CONFIG_CHIPSELECT_LSB); 111431fb632bSRamuthevar Vadivel Murugan reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK) 111531fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CONFIG_CHIPSELECT_LSB; 111631fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG); 111731fb632bSRamuthevar Vadivel Murugan } 111831fb632bSRamuthevar Vadivel Murugan 111931fb632bSRamuthevar Vadivel Murugan static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz, 112031fb632bSRamuthevar Vadivel Murugan const unsigned int ns_val) 112131fb632bSRamuthevar Vadivel Murugan { 112231fb632bSRamuthevar Vadivel Murugan unsigned int ticks; 112331fb632bSRamuthevar Vadivel Murugan 112431fb632bSRamuthevar Vadivel Murugan ticks = ref_clk_hz / 1000; /* kHz */ 112531fb632bSRamuthevar Vadivel Murugan ticks = DIV_ROUND_UP(ticks * ns_val, 1000000); 112631fb632bSRamuthevar Vadivel Murugan 112731fb632bSRamuthevar Vadivel Murugan return ticks; 112831fb632bSRamuthevar Vadivel Murugan } 112931fb632bSRamuthevar Vadivel Murugan 113031fb632bSRamuthevar Vadivel Murugan static void cqspi_delay(struct cqspi_flash_pdata *f_pdata) 113131fb632bSRamuthevar Vadivel Murugan { 113231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 113331fb632bSRamuthevar Vadivel Murugan void __iomem *iobase = cqspi->iobase; 113431fb632bSRamuthevar Vadivel Murugan const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 113531fb632bSRamuthevar Vadivel Murugan unsigned int tshsl, tchsh, tslch, tsd2d; 113631fb632bSRamuthevar Vadivel Murugan unsigned int reg; 113731fb632bSRamuthevar Vadivel Murugan unsigned int tsclk; 113831fb632bSRamuthevar Vadivel Murugan 113931fb632bSRamuthevar Vadivel Murugan /* calculate the number of ref ticks for one sclk tick */ 114031fb632bSRamuthevar Vadivel Murugan tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk); 114131fb632bSRamuthevar Vadivel Murugan 114231fb632bSRamuthevar Vadivel Murugan tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns); 114331fb632bSRamuthevar Vadivel Murugan /* this particular value must be at least one sclk */ 114431fb632bSRamuthevar Vadivel Murugan if (tshsl < tsclk) 114531fb632bSRamuthevar Vadivel Murugan tshsl = tsclk; 114631fb632bSRamuthevar Vadivel Murugan 114731fb632bSRamuthevar Vadivel Murugan tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns); 114831fb632bSRamuthevar Vadivel Murugan tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns); 114931fb632bSRamuthevar Vadivel Murugan tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns); 115031fb632bSRamuthevar Vadivel Murugan 115131fb632bSRamuthevar Vadivel Murugan reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK) 115231fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSHSL_LSB; 115331fb632bSRamuthevar Vadivel Murugan reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK) 115431fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TCHSH_LSB; 115531fb632bSRamuthevar Vadivel Murugan reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK) 115631fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSLCH_LSB; 115731fb632bSRamuthevar Vadivel Murugan reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK) 115831fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSD2D_LSB; 115931fb632bSRamuthevar Vadivel Murugan writel(reg, iobase + CQSPI_REG_DELAY); 116031fb632bSRamuthevar Vadivel Murugan } 116131fb632bSRamuthevar Vadivel Murugan 116231fb632bSRamuthevar Vadivel Murugan static void cqspi_config_baudrate_div(struct cqspi_st *cqspi) 116331fb632bSRamuthevar Vadivel Murugan { 116431fb632bSRamuthevar Vadivel Murugan const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 116531fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 116631fb632bSRamuthevar Vadivel Murugan u32 reg, div; 116731fb632bSRamuthevar Vadivel Murugan 116831fb632bSRamuthevar Vadivel Murugan /* Recalculate the baudrate divisor based on QSPI specification. */ 116931fb632bSRamuthevar Vadivel Murugan div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1; 117031fb632bSRamuthevar Vadivel Murugan 1171f8fc65e5SNathan Barrett-Morrison /* Maximum baud divisor */ 1172f8fc65e5SNathan Barrett-Morrison if (div > CQSPI_REG_CONFIG_BAUD_MASK) { 1173f8fc65e5SNathan Barrett-Morrison div = CQSPI_REG_CONFIG_BAUD_MASK; 1174f8fc65e5SNathan Barrett-Morrison dev_warn(&cqspi->pdev->dev, 1175f8fc65e5SNathan Barrett-Morrison "Unable to adjust clock <= %d hz. Reduced to %d hz\n", 1176f8fc65e5SNathan Barrett-Morrison cqspi->sclk, ref_clk_hz/((div+1)*2)); 1177f8fc65e5SNathan Barrett-Morrison } 1178f8fc65e5SNathan Barrett-Morrison 117931fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG); 118031fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); 118131fb632bSRamuthevar Vadivel Murugan reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB; 118231fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG); 118331fb632bSRamuthevar Vadivel Murugan } 118431fb632bSRamuthevar Vadivel Murugan 118531fb632bSRamuthevar Vadivel Murugan static void cqspi_readdata_capture(struct cqspi_st *cqspi, 118631fb632bSRamuthevar Vadivel Murugan const bool bypass, 118731fb632bSRamuthevar Vadivel Murugan const unsigned int delay) 118831fb632bSRamuthevar Vadivel Murugan { 118931fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 119031fb632bSRamuthevar Vadivel Murugan unsigned int reg; 119131fb632bSRamuthevar Vadivel Murugan 119231fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_READCAPTURE); 119331fb632bSRamuthevar Vadivel Murugan 119431fb632bSRamuthevar Vadivel Murugan if (bypass) 119531fb632bSRamuthevar Vadivel Murugan reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 119631fb632bSRamuthevar Vadivel Murugan else 119731fb632bSRamuthevar Vadivel Murugan reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 119831fb632bSRamuthevar Vadivel Murugan 119931fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK 120031fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_READCAPTURE_DELAY_LSB); 120131fb632bSRamuthevar Vadivel Murugan 120231fb632bSRamuthevar Vadivel Murugan reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK) 120331fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_READCAPTURE_DELAY_LSB; 120431fb632bSRamuthevar Vadivel Murugan 120531fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_READCAPTURE); 120631fb632bSRamuthevar Vadivel Murugan } 120731fb632bSRamuthevar Vadivel Murugan 120831fb632bSRamuthevar Vadivel Murugan static void cqspi_configure(struct cqspi_flash_pdata *f_pdata, 120931fb632bSRamuthevar Vadivel Murugan unsigned long sclk) 121031fb632bSRamuthevar Vadivel Murugan { 121131fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 121231fb632bSRamuthevar Vadivel Murugan int switch_cs = (cqspi->current_cs != f_pdata->cs); 121331fb632bSRamuthevar Vadivel Murugan int switch_ck = (cqspi->sclk != sclk); 121431fb632bSRamuthevar Vadivel Murugan 121531fb632bSRamuthevar Vadivel Murugan if (switch_cs || switch_ck) 121631fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 121731fb632bSRamuthevar Vadivel Murugan 121831fb632bSRamuthevar Vadivel Murugan /* Switch chip select. */ 121931fb632bSRamuthevar Vadivel Murugan if (switch_cs) { 122031fb632bSRamuthevar Vadivel Murugan cqspi->current_cs = f_pdata->cs; 122131fb632bSRamuthevar Vadivel Murugan cqspi_chipselect(f_pdata); 122231fb632bSRamuthevar Vadivel Murugan } 122331fb632bSRamuthevar Vadivel Murugan 122431fb632bSRamuthevar Vadivel Murugan /* Setup baudrate divisor and delays */ 122531fb632bSRamuthevar Vadivel Murugan if (switch_ck) { 122631fb632bSRamuthevar Vadivel Murugan cqspi->sclk = sclk; 122731fb632bSRamuthevar Vadivel Murugan cqspi_config_baudrate_div(cqspi); 122831fb632bSRamuthevar Vadivel Murugan cqspi_delay(f_pdata); 122931fb632bSRamuthevar Vadivel Murugan cqspi_readdata_capture(cqspi, !cqspi->rclk_en, 123031fb632bSRamuthevar Vadivel Murugan f_pdata->read_delay); 123131fb632bSRamuthevar Vadivel Murugan } 123231fb632bSRamuthevar Vadivel Murugan 123331fb632bSRamuthevar Vadivel Murugan if (switch_cs || switch_ck) 123431fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1); 123531fb632bSRamuthevar Vadivel Murugan } 123631fb632bSRamuthevar Vadivel Murugan 123731fb632bSRamuthevar Vadivel Murugan static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata, 123831fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 123931fb632bSRamuthevar Vadivel Murugan { 124031fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 124131fb632bSRamuthevar Vadivel Murugan loff_t to = op->addr.val; 124231fb632bSRamuthevar Vadivel Murugan size_t len = op->data.nbytes; 124331fb632bSRamuthevar Vadivel Murugan const u_char *buf = op->data.buf.out; 124431fb632bSRamuthevar Vadivel Murugan int ret; 124531fb632bSRamuthevar Vadivel Murugan 124631fb632bSRamuthevar Vadivel Murugan ret = cqspi_write_setup(f_pdata, op); 124731fb632bSRamuthevar Vadivel Murugan if (ret) 124831fb632bSRamuthevar Vadivel Murugan return ret; 124931fb632bSRamuthevar Vadivel Murugan 1250f453f293SPratyush Yadav /* 1251f453f293SPratyush Yadav * Some flashes like the Cypress Semper flash expect a dummy 4-byte 1252f453f293SPratyush Yadav * address (all 0s) with the read status register command in DTR mode. 1253f453f293SPratyush Yadav * But this controller does not support sending dummy address bytes to 1254f453f293SPratyush Yadav * the flash when it is polling the write completion register in DTR 1255f453f293SPratyush Yadav * mode. So, we can not use direct mode when in DTR mode for writing 1256f453f293SPratyush Yadav * data. 1257f453f293SPratyush Yadav */ 125828ac902aSMatthias Schiffer if (!op->cmd.dtr && cqspi->use_direct_mode && 1259e8c51b16SDhruva Gole cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) { 126031fb632bSRamuthevar Vadivel Murugan memcpy_toio(cqspi->ahb_base + to, buf, len); 126131fb632bSRamuthevar Vadivel Murugan return cqspi_wait_idle(cqspi); 126231fb632bSRamuthevar Vadivel Murugan } 126331fb632bSRamuthevar Vadivel Murugan 126431fb632bSRamuthevar Vadivel Murugan return cqspi_indirect_write_execute(f_pdata, to, buf, len); 126531fb632bSRamuthevar Vadivel Murugan } 126631fb632bSRamuthevar Vadivel Murugan 126731fb632bSRamuthevar Vadivel Murugan static void cqspi_rx_dma_callback(void *param) 126831fb632bSRamuthevar Vadivel Murugan { 126931fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = param; 127031fb632bSRamuthevar Vadivel Murugan 127131fb632bSRamuthevar Vadivel Murugan complete(&cqspi->rx_dma_complete); 127231fb632bSRamuthevar Vadivel Murugan } 127331fb632bSRamuthevar Vadivel Murugan 127431fb632bSRamuthevar Vadivel Murugan static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata, 127531fb632bSRamuthevar Vadivel Murugan u_char *buf, loff_t from, size_t len) 127631fb632bSRamuthevar Vadivel Murugan { 127731fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 127831fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 127931fb632bSRamuthevar Vadivel Murugan enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; 128031fb632bSRamuthevar Vadivel Murugan dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from; 128131fb632bSRamuthevar Vadivel Murugan int ret = 0; 128231fb632bSRamuthevar Vadivel Murugan struct dma_async_tx_descriptor *tx; 128331fb632bSRamuthevar Vadivel Murugan dma_cookie_t cookie; 128431fb632bSRamuthevar Vadivel Murugan dma_addr_t dma_dst; 128583048015SVignesh Raghavendra struct device *ddev; 128631fb632bSRamuthevar Vadivel Murugan 128731fb632bSRamuthevar Vadivel Murugan if (!cqspi->rx_chan || !virt_addr_valid(buf)) { 128831fb632bSRamuthevar Vadivel Murugan memcpy_fromio(buf, cqspi->ahb_base + from, len); 128931fb632bSRamuthevar Vadivel Murugan return 0; 129031fb632bSRamuthevar Vadivel Murugan } 129131fb632bSRamuthevar Vadivel Murugan 129283048015SVignesh Raghavendra ddev = cqspi->rx_chan->device->dev; 129383048015SVignesh Raghavendra dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE); 129483048015SVignesh Raghavendra if (dma_mapping_error(ddev, dma_dst)) { 129531fb632bSRamuthevar Vadivel Murugan dev_err(dev, "dma mapping failed\n"); 129631fb632bSRamuthevar Vadivel Murugan return -ENOMEM; 129731fb632bSRamuthevar Vadivel Murugan } 129831fb632bSRamuthevar Vadivel Murugan tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src, 129931fb632bSRamuthevar Vadivel Murugan len, flags); 130031fb632bSRamuthevar Vadivel Murugan if (!tx) { 130131fb632bSRamuthevar Vadivel Murugan dev_err(dev, "device_prep_dma_memcpy error\n"); 130231fb632bSRamuthevar Vadivel Murugan ret = -EIO; 130331fb632bSRamuthevar Vadivel Murugan goto err_unmap; 130431fb632bSRamuthevar Vadivel Murugan } 130531fb632bSRamuthevar Vadivel Murugan 130631fb632bSRamuthevar Vadivel Murugan tx->callback = cqspi_rx_dma_callback; 130731fb632bSRamuthevar Vadivel Murugan tx->callback_param = cqspi; 130831fb632bSRamuthevar Vadivel Murugan cookie = tx->tx_submit(tx); 130931fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->rx_dma_complete); 131031fb632bSRamuthevar Vadivel Murugan 131131fb632bSRamuthevar Vadivel Murugan ret = dma_submit_error(cookie); 131231fb632bSRamuthevar Vadivel Murugan if (ret) { 131331fb632bSRamuthevar Vadivel Murugan dev_err(dev, "dma_submit_error %d\n", cookie); 131431fb632bSRamuthevar Vadivel Murugan ret = -EIO; 131531fb632bSRamuthevar Vadivel Murugan goto err_unmap; 131631fb632bSRamuthevar Vadivel Murugan } 131731fb632bSRamuthevar Vadivel Murugan 131831fb632bSRamuthevar Vadivel Murugan dma_async_issue_pending(cqspi->rx_chan); 131931fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->rx_dma_complete, 13202ef0170eSPratyush Yadav msecs_to_jiffies(max_t(size_t, len, 500)))) { 132131fb632bSRamuthevar Vadivel Murugan dmaengine_terminate_sync(cqspi->rx_chan); 132231fb632bSRamuthevar Vadivel Murugan dev_err(dev, "DMA wait_for_completion_timeout\n"); 132331fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 132431fb632bSRamuthevar Vadivel Murugan goto err_unmap; 132531fb632bSRamuthevar Vadivel Murugan } 132631fb632bSRamuthevar Vadivel Murugan 132731fb632bSRamuthevar Vadivel Murugan err_unmap: 132883048015SVignesh Raghavendra dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE); 132931fb632bSRamuthevar Vadivel Murugan 133031fb632bSRamuthevar Vadivel Murugan return ret; 133131fb632bSRamuthevar Vadivel Murugan } 133231fb632bSRamuthevar Vadivel Murugan 133331fb632bSRamuthevar Vadivel Murugan static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata, 133431fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 133531fb632bSRamuthevar Vadivel Murugan { 133631fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 13371a6f854fSSai Krishna Potthuri struct device *dev = &cqspi->pdev->dev; 13381a6f854fSSai Krishna Potthuri const struct cqspi_driver_platdata *ddata; 133931fb632bSRamuthevar Vadivel Murugan loff_t from = op->addr.val; 134031fb632bSRamuthevar Vadivel Murugan size_t len = op->data.nbytes; 134131fb632bSRamuthevar Vadivel Murugan u_char *buf = op->data.buf.in; 13421a6f854fSSai Krishna Potthuri u64 dma_align = (u64)(uintptr_t)buf; 134331fb632bSRamuthevar Vadivel Murugan int ret; 134431fb632bSRamuthevar Vadivel Murugan 13451a6f854fSSai Krishna Potthuri ddata = of_device_get_match_data(dev); 134631fb632bSRamuthevar Vadivel Murugan 134731fb632bSRamuthevar Vadivel Murugan ret = cqspi_read_setup(f_pdata, op); 134831fb632bSRamuthevar Vadivel Murugan if (ret) 134931fb632bSRamuthevar Vadivel Murugan return ret; 135031fb632bSRamuthevar Vadivel Murugan 135131fb632bSRamuthevar Vadivel Murugan if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) 135231fb632bSRamuthevar Vadivel Murugan return cqspi_direct_read_execute(f_pdata, buf, from, len); 135331fb632bSRamuthevar Vadivel Murugan 13541a6f854fSSai Krishna Potthuri if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma && 13551a6f854fSSai Krishna Potthuri virt_addr_valid(buf) && ((dma_align & CQSPI_DMA_UNALIGN) == 0)) 13561a6f854fSSai Krishna Potthuri return ddata->indirect_read_dma(f_pdata, buf, from, len); 13571a6f854fSSai Krishna Potthuri 135831fb632bSRamuthevar Vadivel Murugan return cqspi_indirect_read_execute(f_pdata, buf, from, len); 135931fb632bSRamuthevar Vadivel Murugan } 136031fb632bSRamuthevar Vadivel Murugan 136131fb632bSRamuthevar Vadivel Murugan static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op) 136231fb632bSRamuthevar Vadivel Murugan { 136331fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); 136431fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata; 136531fb632bSRamuthevar Vadivel Murugan 13669e264f3fSAmit Kumar Mahapatra via Alsa-devel f_pdata = &cqspi->f_pdata[spi_get_chipselect(mem->spi, 0)]; 136731fb632bSRamuthevar Vadivel Murugan cqspi_configure(f_pdata, mem->spi->max_speed_hz); 136831fb632bSRamuthevar Vadivel Murugan 136931fb632bSRamuthevar Vadivel Murugan if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { 1370d403fb6eSDhruva Gole /* 1371d403fb6eSDhruva Gole * Performing reads in DAC mode forces to read minimum 4 bytes 1372d403fb6eSDhruva Gole * which is unsupported on some flash devices during register 1373d403fb6eSDhruva Gole * reads, prefer STIG mode for such small reads. 1374d403fb6eSDhruva Gole */ 1375d403fb6eSDhruva Gole if (!op->addr.nbytes || 1376d403fb6eSDhruva Gole op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX) 137731fb632bSRamuthevar Vadivel Murugan return cqspi_command_read(f_pdata, op); 137831fb632bSRamuthevar Vadivel Murugan 137931fb632bSRamuthevar Vadivel Murugan return cqspi_read(f_pdata, op); 138031fb632bSRamuthevar Vadivel Murugan } 138131fb632bSRamuthevar Vadivel Murugan 138231fb632bSRamuthevar Vadivel Murugan if (!op->addr.nbytes || !op->data.buf.out) 138331fb632bSRamuthevar Vadivel Murugan return cqspi_command_write(f_pdata, op); 138431fb632bSRamuthevar Vadivel Murugan 138531fb632bSRamuthevar Vadivel Murugan return cqspi_write(f_pdata, op); 138631fb632bSRamuthevar Vadivel Murugan } 138731fb632bSRamuthevar Vadivel Murugan 138831fb632bSRamuthevar Vadivel Murugan static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) 138931fb632bSRamuthevar Vadivel Murugan { 139031fb632bSRamuthevar Vadivel Murugan int ret; 139131fb632bSRamuthevar Vadivel Murugan 139231fb632bSRamuthevar Vadivel Murugan ret = cqspi_mem_process(mem, op); 139331fb632bSRamuthevar Vadivel Murugan if (ret) 139431fb632bSRamuthevar Vadivel Murugan dev_err(&mem->spi->dev, "operation failed with %d\n", ret); 139531fb632bSRamuthevar Vadivel Murugan 139631fb632bSRamuthevar Vadivel Murugan return ret; 139731fb632bSRamuthevar Vadivel Murugan } 139831fb632bSRamuthevar Vadivel Murugan 1399a273596bSPratyush Yadav static bool cqspi_supports_mem_op(struct spi_mem *mem, 1400a273596bSPratyush Yadav const struct spi_mem_op *op) 1401a273596bSPratyush Yadav { 1402f453f293SPratyush Yadav bool all_true, all_false; 1403f453f293SPratyush Yadav 14040395be96SApurva Nandan /* 14050395be96SApurva Nandan * op->dummy.dtr is required for converting nbytes into ncycles. 14060395be96SApurva Nandan * Also, don't check the dtr field of the op phase having zero nbytes. 14070395be96SApurva Nandan */ 14080395be96SApurva Nandan all_true = op->cmd.dtr && 14090395be96SApurva Nandan (!op->addr.nbytes || op->addr.dtr) && 14100395be96SApurva Nandan (!op->dummy.nbytes || op->dummy.dtr) && 14110395be96SApurva Nandan (!op->data.nbytes || op->data.dtr); 14120395be96SApurva Nandan 1413f453f293SPratyush Yadav all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && 1414f453f293SPratyush Yadav !op->data.dtr; 1415f453f293SPratyush Yadav 1416f1d388f2SMatthias Schiffer if (all_true) { 1417f1d388f2SMatthias Schiffer /* Right now we only support 8-8-8 DTR mode. */ 1418f1d388f2SMatthias Schiffer if (op->cmd.nbytes && op->cmd.buswidth != 8) 1419f453f293SPratyush Yadav return false; 1420f1d388f2SMatthias Schiffer if (op->addr.nbytes && op->addr.buswidth != 8) 1421f1d388f2SMatthias Schiffer return false; 1422f1d388f2SMatthias Schiffer if (op->data.nbytes && op->data.buswidth != 8) 1423f1d388f2SMatthias Schiffer return false; 14241aeda096SMatthias Schiffer } else if (!all_false) { 1425f1d388f2SMatthias Schiffer /* Mixed DTR modes are not supported. */ 1426f1d388f2SMatthias Schiffer return false; 1427f1d388f2SMatthias Schiffer } 1428f453f293SPratyush Yadav 1429d2275139SPratyush Yadav return spi_mem_default_supports_op(mem, op); 1430a273596bSPratyush Yadav } 1431a273596bSPratyush Yadav 143231fb632bSRamuthevar Vadivel Murugan static int cqspi_of_get_flash_pdata(struct platform_device *pdev, 143331fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata, 143431fb632bSRamuthevar Vadivel Murugan struct device_node *np) 143531fb632bSRamuthevar Vadivel Murugan { 143631fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) { 143731fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine read-delay\n"); 143831fb632bSRamuthevar Vadivel Murugan return -ENXIO; 143931fb632bSRamuthevar Vadivel Murugan } 144031fb632bSRamuthevar Vadivel Murugan 144131fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) { 144231fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tshsl-ns\n"); 144331fb632bSRamuthevar Vadivel Murugan return -ENXIO; 144431fb632bSRamuthevar Vadivel Murugan } 144531fb632bSRamuthevar Vadivel Murugan 144631fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) { 144731fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n"); 144831fb632bSRamuthevar Vadivel Murugan return -ENXIO; 144931fb632bSRamuthevar Vadivel Murugan } 145031fb632bSRamuthevar Vadivel Murugan 145131fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) { 145231fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tchsh-ns\n"); 145331fb632bSRamuthevar Vadivel Murugan return -ENXIO; 145431fb632bSRamuthevar Vadivel Murugan } 145531fb632bSRamuthevar Vadivel Murugan 145631fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) { 145731fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tslch-ns\n"); 145831fb632bSRamuthevar Vadivel Murugan return -ENXIO; 145931fb632bSRamuthevar Vadivel Murugan } 146031fb632bSRamuthevar Vadivel Murugan 146131fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) { 146231fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n"); 146331fb632bSRamuthevar Vadivel Murugan return -ENXIO; 146431fb632bSRamuthevar Vadivel Murugan } 146531fb632bSRamuthevar Vadivel Murugan 146631fb632bSRamuthevar Vadivel Murugan return 0; 146731fb632bSRamuthevar Vadivel Murugan } 146831fb632bSRamuthevar Vadivel Murugan 146931fb632bSRamuthevar Vadivel Murugan static int cqspi_of_get_pdata(struct cqspi_st *cqspi) 147031fb632bSRamuthevar Vadivel Murugan { 147131fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 147231fb632bSRamuthevar Vadivel Murugan struct device_node *np = dev->of_node; 147309e393e3SSai Krishna Potthuri u32 id[2]; 147431fb632bSRamuthevar Vadivel Murugan 147531fb632bSRamuthevar Vadivel Murugan cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); 147631fb632bSRamuthevar Vadivel Murugan 147731fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { 147831fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine fifo-depth\n"); 147931fb632bSRamuthevar Vadivel Murugan return -ENXIO; 148031fb632bSRamuthevar Vadivel Murugan } 148131fb632bSRamuthevar Vadivel Murugan 148231fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) { 148331fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine fifo-width\n"); 148431fb632bSRamuthevar Vadivel Murugan return -ENXIO; 148531fb632bSRamuthevar Vadivel Murugan } 148631fb632bSRamuthevar Vadivel Murugan 148731fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,trigger-address", 148831fb632bSRamuthevar Vadivel Murugan &cqspi->trigger_address)) { 148931fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine trigger-address\n"); 149031fb632bSRamuthevar Vadivel Murugan return -ENXIO; 149131fb632bSRamuthevar Vadivel Murugan } 149231fb632bSRamuthevar Vadivel Murugan 1493b436fb7dSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) 1494b436fb7dSRamuthevar Vadivel Murugan cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT; 1495b436fb7dSRamuthevar Vadivel Murugan 149631fb632bSRamuthevar Vadivel Murugan cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); 149731fb632bSRamuthevar Vadivel Murugan 149809e393e3SSai Krishna Potthuri if (!of_property_read_u32_array(np, "power-domains", id, 149909e393e3SSai Krishna Potthuri ARRAY_SIZE(id))) 150009e393e3SSai Krishna Potthuri cqspi->pd_dev_id = id[1]; 150109e393e3SSai Krishna Potthuri 150231fb632bSRamuthevar Vadivel Murugan return 0; 150331fb632bSRamuthevar Vadivel Murugan } 150431fb632bSRamuthevar Vadivel Murugan 150531fb632bSRamuthevar Vadivel Murugan static void cqspi_controller_init(struct cqspi_st *cqspi) 150631fb632bSRamuthevar Vadivel Murugan { 150731fb632bSRamuthevar Vadivel Murugan u32 reg; 150831fb632bSRamuthevar Vadivel Murugan 150931fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 151031fb632bSRamuthevar Vadivel Murugan 151131fb632bSRamuthevar Vadivel Murugan /* Configure the remap address register, no remap */ 151231fb632bSRamuthevar Vadivel Murugan writel(0, cqspi->iobase + CQSPI_REG_REMAP); 151331fb632bSRamuthevar Vadivel Murugan 151431fb632bSRamuthevar Vadivel Murugan /* Disable all interrupts. */ 151531fb632bSRamuthevar Vadivel Murugan writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); 151631fb632bSRamuthevar Vadivel Murugan 151731fb632bSRamuthevar Vadivel Murugan /* Configure the SRAM split to 1:1 . */ 151831fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); 151931fb632bSRamuthevar Vadivel Murugan 152031fb632bSRamuthevar Vadivel Murugan /* Load indirect trigger address. */ 152131fb632bSRamuthevar Vadivel Murugan writel(cqspi->trigger_address, 152231fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); 152331fb632bSRamuthevar Vadivel Murugan 152431fb632bSRamuthevar Vadivel Murugan /* Program read watermark -- 1/2 of the FIFO. */ 152531fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth * cqspi->fifo_width / 2, 152631fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); 152731fb632bSRamuthevar Vadivel Murugan /* Program write watermark -- 1/8 of the FIFO. */ 152831fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth * cqspi->fifo_width / 8, 152931fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); 153031fb632bSRamuthevar Vadivel Murugan 1531ad2775dcSRamuthevar Vadivel Murugan /* Disable direct access controller */ 1532ad2775dcSRamuthevar Vadivel Murugan if (!cqspi->use_direct_mode) { 153331fb632bSRamuthevar Vadivel Murugan reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 1534ad2775dcSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL; 153531fb632bSRamuthevar Vadivel Murugan writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 1536ad2775dcSRamuthevar Vadivel Murugan } 153731fb632bSRamuthevar Vadivel Murugan 15381a6f854fSSai Krishna Potthuri /* Enable DMA interface */ 15391a6f854fSSai Krishna Potthuri if (cqspi->use_dma_read) { 15401a6f854fSSai Krishna Potthuri reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 15411a6f854fSSai Krishna Potthuri reg |= CQSPI_REG_CONFIG_DMA_MASK; 15421a6f854fSSai Krishna Potthuri writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 15431a6f854fSSai Krishna Potthuri } 15441a6f854fSSai Krishna Potthuri 154531fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1); 154631fb632bSRamuthevar Vadivel Murugan } 154731fb632bSRamuthevar Vadivel Murugan 154831fb632bSRamuthevar Vadivel Murugan static int cqspi_request_mmap_dma(struct cqspi_st *cqspi) 154931fb632bSRamuthevar Vadivel Murugan { 155031fb632bSRamuthevar Vadivel Murugan dma_cap_mask_t mask; 155131fb632bSRamuthevar Vadivel Murugan 155231fb632bSRamuthevar Vadivel Murugan dma_cap_zero(mask); 155331fb632bSRamuthevar Vadivel Murugan dma_cap_set(DMA_MEMCPY, mask); 155431fb632bSRamuthevar Vadivel Murugan 155531fb632bSRamuthevar Vadivel Murugan cqspi->rx_chan = dma_request_chan_by_mask(&mask); 155631fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->rx_chan)) { 155731fb632bSRamuthevar Vadivel Murugan int ret = PTR_ERR(cqspi->rx_chan); 155876159e2fSIan Abbott 155931fb632bSRamuthevar Vadivel Murugan cqspi->rx_chan = NULL; 1560436a5c20SKrzysztof Kozlowski return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n"); 156131fb632bSRamuthevar Vadivel Murugan } 156231fb632bSRamuthevar Vadivel Murugan init_completion(&cqspi->rx_dma_complete); 156331fb632bSRamuthevar Vadivel Murugan 156431fb632bSRamuthevar Vadivel Murugan return 0; 156531fb632bSRamuthevar Vadivel Murugan } 156631fb632bSRamuthevar Vadivel Murugan 15672ea370a9SVignesh Raghavendra static const char *cqspi_get_name(struct spi_mem *mem) 15682ea370a9SVignesh Raghavendra { 15692ea370a9SVignesh Raghavendra struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); 15702ea370a9SVignesh Raghavendra struct device *dev = &cqspi->pdev->dev; 15712ea370a9SVignesh Raghavendra 15729e264f3fSAmit Kumar Mahapatra via Alsa-devel return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), 15739e264f3fSAmit Kumar Mahapatra via Alsa-devel spi_get_chipselect(mem->spi, 0)); 15742ea370a9SVignesh Raghavendra } 15752ea370a9SVignesh Raghavendra 157631fb632bSRamuthevar Vadivel Murugan static const struct spi_controller_mem_ops cqspi_mem_ops = { 157731fb632bSRamuthevar Vadivel Murugan .exec_op = cqspi_exec_mem_op, 15782ea370a9SVignesh Raghavendra .get_name = cqspi_get_name, 1579a273596bSPratyush Yadav .supports_op = cqspi_supports_mem_op, 158031fb632bSRamuthevar Vadivel Murugan }; 158131fb632bSRamuthevar Vadivel Murugan 1582a9be4549SMiquel Raynal static const struct spi_controller_mem_caps cqspi_mem_caps = { 1583a9be4549SMiquel Raynal .dtr = true, 1584a9be4549SMiquel Raynal }; 1585a9be4549SMiquel Raynal 158631fb632bSRamuthevar Vadivel Murugan static int cqspi_setup_flash(struct cqspi_st *cqspi) 158731fb632bSRamuthevar Vadivel Murugan { 158831fb632bSRamuthevar Vadivel Murugan struct platform_device *pdev = cqspi->pdev; 158931fb632bSRamuthevar Vadivel Murugan struct device *dev = &pdev->dev; 159031fb632bSRamuthevar Vadivel Murugan struct device_node *np = dev->of_node; 159131fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata; 159231fb632bSRamuthevar Vadivel Murugan unsigned int cs; 159331fb632bSRamuthevar Vadivel Murugan int ret; 159431fb632bSRamuthevar Vadivel Murugan 159531fb632bSRamuthevar Vadivel Murugan /* Get flash device data */ 159631fb632bSRamuthevar Vadivel Murugan for_each_available_child_of_node(dev->of_node, np) { 159731fb632bSRamuthevar Vadivel Murugan ret = of_property_read_u32(np, "reg", &cs); 159831fb632bSRamuthevar Vadivel Murugan if (ret) { 159931fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Couldn't determine chip select.\n"); 160087d62d8fSJunlin Yang of_node_put(np); 160131fb632bSRamuthevar Vadivel Murugan return ret; 160231fb632bSRamuthevar Vadivel Murugan } 160331fb632bSRamuthevar Vadivel Murugan 160431fb632bSRamuthevar Vadivel Murugan if (cs >= CQSPI_MAX_CHIPSELECT) { 160531fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Chip select %d out of range.\n", cs); 160687d62d8fSJunlin Yang of_node_put(np); 160731fb632bSRamuthevar Vadivel Murugan return -EINVAL; 160831fb632bSRamuthevar Vadivel Murugan } 160931fb632bSRamuthevar Vadivel Murugan 161031fb632bSRamuthevar Vadivel Murugan f_pdata = &cqspi->f_pdata[cs]; 161131fb632bSRamuthevar Vadivel Murugan f_pdata->cqspi = cqspi; 161231fb632bSRamuthevar Vadivel Murugan f_pdata->cs = cs; 161331fb632bSRamuthevar Vadivel Murugan 161431fb632bSRamuthevar Vadivel Murugan ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np); 161587d62d8fSJunlin Yang if (ret) { 161687d62d8fSJunlin Yang of_node_put(np); 161731fb632bSRamuthevar Vadivel Murugan return ret; 161831fb632bSRamuthevar Vadivel Murugan } 161987d62d8fSJunlin Yang } 162031fb632bSRamuthevar Vadivel Murugan 162131fb632bSRamuthevar Vadivel Murugan return 0; 162231fb632bSRamuthevar Vadivel Murugan } 162331fb632bSRamuthevar Vadivel Murugan 162431fb632bSRamuthevar Vadivel Murugan static int cqspi_probe(struct platform_device *pdev) 162531fb632bSRamuthevar Vadivel Murugan { 162631fb632bSRamuthevar Vadivel Murugan const struct cqspi_driver_platdata *ddata; 162747fef94aSWilliam Qiu struct reset_control *rstc, *rstc_ocp, *rstc_ref; 162831fb632bSRamuthevar Vadivel Murugan struct device *dev = &pdev->dev; 162931fb632bSRamuthevar Vadivel Murugan struct spi_master *master; 163031fb632bSRamuthevar Vadivel Murugan struct resource *res_ahb; 163131fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi; 163231fb632bSRamuthevar Vadivel Murugan int ret; 163331fb632bSRamuthevar Vadivel Murugan int irq; 163431fb632bSRamuthevar Vadivel Murugan 1635606e5d40SVaishnav Achath master = devm_spi_alloc_master(&pdev->dev, sizeof(*cqspi)); 163631fb632bSRamuthevar Vadivel Murugan if (!master) { 163731fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "spi_alloc_master failed\n"); 163831fb632bSRamuthevar Vadivel Murugan return -ENOMEM; 163931fb632bSRamuthevar Vadivel Murugan } 164031fb632bSRamuthevar Vadivel Murugan master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; 164131fb632bSRamuthevar Vadivel Murugan master->mem_ops = &cqspi_mem_ops; 1642a9be4549SMiquel Raynal master->mem_caps = &cqspi_mem_caps; 164331fb632bSRamuthevar Vadivel Murugan master->dev.of_node = pdev->dev.of_node; 164431fb632bSRamuthevar Vadivel Murugan 164531fb632bSRamuthevar Vadivel Murugan cqspi = spi_master_get_devdata(master); 164631fb632bSRamuthevar Vadivel Murugan 164731fb632bSRamuthevar Vadivel Murugan cqspi->pdev = pdev; 1648606e5d40SVaishnav Achath cqspi->master = master; 1649ea94191eSMeng Li platform_set_drvdata(pdev, cqspi); 165031fb632bSRamuthevar Vadivel Murugan 165131fb632bSRamuthevar Vadivel Murugan /* Obtain configuration from OF. */ 165231fb632bSRamuthevar Vadivel Murugan ret = cqspi_of_get_pdata(cqspi); 165331fb632bSRamuthevar Vadivel Murugan if (ret) { 165431fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get mandatory OF data.\n"); 165573d5fe04SVaishnav Achath return -ENODEV; 165631fb632bSRamuthevar Vadivel Murugan } 165731fb632bSRamuthevar Vadivel Murugan 165831fb632bSRamuthevar Vadivel Murugan /* Obtain QSPI clock. */ 165931fb632bSRamuthevar Vadivel Murugan cqspi->clk = devm_clk_get(dev, NULL); 166031fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->clk)) { 166131fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot claim QSPI clock.\n"); 166231fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->clk); 166373d5fe04SVaishnav Achath return ret; 166431fb632bSRamuthevar Vadivel Murugan } 166531fb632bSRamuthevar Vadivel Murugan 166631fb632bSRamuthevar Vadivel Murugan /* Obtain and remap controller address. */ 16674e12ef2bSYang Yingliang cqspi->iobase = devm_platform_ioremap_resource(pdev, 0); 166831fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->iobase)) { 166931fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot remap controller address.\n"); 167031fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->iobase); 167173d5fe04SVaishnav Achath return ret; 167231fb632bSRamuthevar Vadivel Murugan } 167331fb632bSRamuthevar Vadivel Murugan 167431fb632bSRamuthevar Vadivel Murugan /* Obtain and remap AHB address. */ 16754e12ef2bSYang Yingliang cqspi->ahb_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res_ahb); 167631fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->ahb_base)) { 167731fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot remap AHB address.\n"); 167831fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->ahb_base); 167973d5fe04SVaishnav Achath return ret; 168031fb632bSRamuthevar Vadivel Murugan } 168131fb632bSRamuthevar Vadivel Murugan cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start; 168231fb632bSRamuthevar Vadivel Murugan cqspi->ahb_size = resource_size(res_ahb); 168331fb632bSRamuthevar Vadivel Murugan 168431fb632bSRamuthevar Vadivel Murugan init_completion(&cqspi->transfer_complete); 168531fb632bSRamuthevar Vadivel Murugan 168631fb632bSRamuthevar Vadivel Murugan /* Obtain IRQ line. */ 168731fb632bSRamuthevar Vadivel Murugan irq = platform_get_irq(pdev, 0); 168873d5fe04SVaishnav Achath if (irq < 0) 168973d5fe04SVaishnav Achath return -ENXIO; 169031fb632bSRamuthevar Vadivel Murugan 169131fb632bSRamuthevar Vadivel Murugan pm_runtime_enable(dev); 1692b7be05d5SMinghao Chi ret = pm_runtime_resume_and_get(dev); 1693b7be05d5SMinghao Chi if (ret < 0) 16944d0ef0a1SZhang Qilong goto probe_pm_failed; 169531fb632bSRamuthevar Vadivel Murugan 169631fb632bSRamuthevar Vadivel Murugan ret = clk_prepare_enable(cqspi->clk); 169731fb632bSRamuthevar Vadivel Murugan if (ret) { 169831fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot enable QSPI clock.\n"); 169931fb632bSRamuthevar Vadivel Murugan goto probe_clk_failed; 170031fb632bSRamuthevar Vadivel Murugan } 170131fb632bSRamuthevar Vadivel Murugan 170231fb632bSRamuthevar Vadivel Murugan /* Obtain QSPI reset control */ 170331fb632bSRamuthevar Vadivel Murugan rstc = devm_reset_control_get_optional_exclusive(dev, "qspi"); 170431fb632bSRamuthevar Vadivel Murugan if (IS_ERR(rstc)) { 1705ac9978fcSZhihao Cheng ret = PTR_ERR(rstc); 170631fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get QSPI reset.\n"); 170731fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 170831fb632bSRamuthevar Vadivel Murugan } 170931fb632bSRamuthevar Vadivel Murugan 171031fb632bSRamuthevar Vadivel Murugan rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); 171131fb632bSRamuthevar Vadivel Murugan if (IS_ERR(rstc_ocp)) { 1712ac9978fcSZhihao Cheng ret = PTR_ERR(rstc_ocp); 171331fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get QSPI OCP reset.\n"); 171431fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 171531fb632bSRamuthevar Vadivel Murugan } 171631fb632bSRamuthevar Vadivel Murugan 171747fef94aSWilliam Qiu if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) { 171847fef94aSWilliam Qiu rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref"); 171947fef94aSWilliam Qiu if (IS_ERR(rstc_ref)) { 172047fef94aSWilliam Qiu ret = PTR_ERR(rstc_ref); 172147fef94aSWilliam Qiu dev_err(dev, "Cannot get QSPI REF reset.\n"); 172247fef94aSWilliam Qiu goto probe_reset_failed; 172347fef94aSWilliam Qiu } 172447fef94aSWilliam Qiu reset_control_assert(rstc_ref); 172547fef94aSWilliam Qiu reset_control_deassert(rstc_ref); 172647fef94aSWilliam Qiu } 172747fef94aSWilliam Qiu 172831fb632bSRamuthevar Vadivel Murugan reset_control_assert(rstc); 172931fb632bSRamuthevar Vadivel Murugan reset_control_deassert(rstc); 173031fb632bSRamuthevar Vadivel Murugan 173131fb632bSRamuthevar Vadivel Murugan reset_control_assert(rstc_ocp); 173231fb632bSRamuthevar Vadivel Murugan reset_control_deassert(rstc_ocp); 173331fb632bSRamuthevar Vadivel Murugan 173431fb632bSRamuthevar Vadivel Murugan cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); 17353a5c09c8SPratyush Yadav master->max_speed_hz = cqspi->master_ref_clk_hz; 173698d948ebSDinh Nguyen 173798d948ebSDinh Nguyen /* write completion is supported by default */ 173898d948ebSDinh Nguyen cqspi->wr_completion = true; 173998d948ebSDinh Nguyen 174031fb632bSRamuthevar Vadivel Murugan ddata = of_device_get_match_data(dev); 174131fb632bSRamuthevar Vadivel Murugan if (ddata) { 174231fb632bSRamuthevar Vadivel Murugan if (ddata->quirks & CQSPI_NEEDS_WR_DELAY) 1743f453f293SPratyush Yadav cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, 174431fb632bSRamuthevar Vadivel Murugan cqspi->master_ref_clk_hz); 174531fb632bSRamuthevar Vadivel Murugan if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL) 1746f453f293SPratyush Yadav master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; 1747e8c51b16SDhruva Gole if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) { 174831fb632bSRamuthevar Vadivel Murugan cqspi->use_direct_mode = true; 1749e8c51b16SDhruva Gole cqspi->use_direct_mode_wr = true; 1750e8c51b16SDhruva Gole } 17511a6f854fSSai Krishna Potthuri if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA) 17521a6f854fSSai Krishna Potthuri cqspi->use_dma_read = true; 175398d948ebSDinh Nguyen if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION) 175498d948ebSDinh Nguyen cqspi->wr_completion = false; 17559ee5b6d5SNiravkumar L Rabara if (ddata->quirks & CQSPI_SLOW_SRAM) 17569ee5b6d5SNiravkumar L Rabara cqspi->slow_sram = true; 17571a6f854fSSai Krishna Potthuri 175809e393e3SSai Krishna Potthuri if (of_device_is_compatible(pdev->dev.of_node, 1759*947c70a2SJiasheng Jiang "xlnx,versal-ospi-1.0")) { 1760*947c70a2SJiasheng Jiang ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); 1761*947c70a2SJiasheng Jiang if (ret) 1762*947c70a2SJiasheng Jiang goto probe_reset_failed; 1763*947c70a2SJiasheng Jiang } 176431fb632bSRamuthevar Vadivel Murugan } 176531fb632bSRamuthevar Vadivel Murugan 176631fb632bSRamuthevar Vadivel Murugan ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0, 176731fb632bSRamuthevar Vadivel Murugan pdev->name, cqspi); 176831fb632bSRamuthevar Vadivel Murugan if (ret) { 176931fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot request IRQ.\n"); 177031fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 177131fb632bSRamuthevar Vadivel Murugan } 177231fb632bSRamuthevar Vadivel Murugan 177331fb632bSRamuthevar Vadivel Murugan cqspi_wait_idle(cqspi); 177431fb632bSRamuthevar Vadivel Murugan cqspi_controller_init(cqspi); 177531fb632bSRamuthevar Vadivel Murugan cqspi->current_cs = -1; 177631fb632bSRamuthevar Vadivel Murugan cqspi->sclk = 0; 177731fb632bSRamuthevar Vadivel Murugan 1778b436fb7dSRamuthevar Vadivel Murugan master->num_chipselect = cqspi->num_chipselect; 1779b436fb7dSRamuthevar Vadivel Murugan 178031fb632bSRamuthevar Vadivel Murugan ret = cqspi_setup_flash(cqspi); 178131fb632bSRamuthevar Vadivel Murugan if (ret) { 178231fb632bSRamuthevar Vadivel Murugan dev_err(dev, "failed to setup flash parameters %d\n", ret); 178331fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 178431fb632bSRamuthevar Vadivel Murugan } 178531fb632bSRamuthevar Vadivel Murugan 178631fb632bSRamuthevar Vadivel Murugan if (cqspi->use_direct_mode) { 178731fb632bSRamuthevar Vadivel Murugan ret = cqspi_request_mmap_dma(cqspi); 178831fb632bSRamuthevar Vadivel Murugan if (ret == -EPROBE_DEFER) 178931fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 179031fb632bSRamuthevar Vadivel Murugan } 179131fb632bSRamuthevar Vadivel Murugan 1792606e5d40SVaishnav Achath ret = spi_register_master(master); 179331fb632bSRamuthevar Vadivel Murugan if (ret) { 179431fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret); 179531fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 179631fb632bSRamuthevar Vadivel Murugan } 179731fb632bSRamuthevar Vadivel Murugan 179831fb632bSRamuthevar Vadivel Murugan return 0; 179931fb632bSRamuthevar Vadivel Murugan probe_setup_failed: 180031fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 180131fb632bSRamuthevar Vadivel Murugan probe_reset_failed: 180231fb632bSRamuthevar Vadivel Murugan clk_disable_unprepare(cqspi->clk); 180331fb632bSRamuthevar Vadivel Murugan probe_clk_failed: 180431fb632bSRamuthevar Vadivel Murugan pm_runtime_put_sync(dev); 18054d0ef0a1SZhang Qilong probe_pm_failed: 180631fb632bSRamuthevar Vadivel Murugan pm_runtime_disable(dev); 180731fb632bSRamuthevar Vadivel Murugan return ret; 180831fb632bSRamuthevar Vadivel Murugan } 180931fb632bSRamuthevar Vadivel Murugan 18106fe41879SUwe Kleine-König static void cqspi_remove(struct platform_device *pdev) 181131fb632bSRamuthevar Vadivel Murugan { 181231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = platform_get_drvdata(pdev); 181331fb632bSRamuthevar Vadivel Murugan 1814606e5d40SVaishnav Achath spi_unregister_master(cqspi->master); 181531fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 181631fb632bSRamuthevar Vadivel Murugan 181731fb632bSRamuthevar Vadivel Murugan if (cqspi->rx_chan) 181831fb632bSRamuthevar Vadivel Murugan dma_release_channel(cqspi->rx_chan); 181931fb632bSRamuthevar Vadivel Murugan 182031fb632bSRamuthevar Vadivel Murugan clk_disable_unprepare(cqspi->clk); 182131fb632bSRamuthevar Vadivel Murugan 182231fb632bSRamuthevar Vadivel Murugan pm_runtime_put_sync(&pdev->dev); 182331fb632bSRamuthevar Vadivel Murugan pm_runtime_disable(&pdev->dev); 182431fb632bSRamuthevar Vadivel Murugan } 182531fb632bSRamuthevar Vadivel Murugan 182631fb632bSRamuthevar Vadivel Murugan static int cqspi_suspend(struct device *dev) 182731fb632bSRamuthevar Vadivel Murugan { 182831fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev_get_drvdata(dev); 18292087e85bSDhruva Gole struct spi_master *master = dev_get_drvdata(dev); 18302087e85bSDhruva Gole int ret; 183131fb632bSRamuthevar Vadivel Murugan 18322087e85bSDhruva Gole ret = spi_master_suspend(master); 183331fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 18342087e85bSDhruva Gole 18352087e85bSDhruva Gole clk_disable_unprepare(cqspi->clk); 18362087e85bSDhruva Gole 18372087e85bSDhruva Gole return ret; 183831fb632bSRamuthevar Vadivel Murugan } 183931fb632bSRamuthevar Vadivel Murugan 184031fb632bSRamuthevar Vadivel Murugan static int cqspi_resume(struct device *dev) 184131fb632bSRamuthevar Vadivel Murugan { 184231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev_get_drvdata(dev); 18432087e85bSDhruva Gole struct spi_master *master = dev_get_drvdata(dev); 184431fb632bSRamuthevar Vadivel Murugan 18452087e85bSDhruva Gole clk_prepare_enable(cqspi->clk); 18462087e85bSDhruva Gole cqspi_wait_idle(cqspi); 18472087e85bSDhruva Gole cqspi_controller_init(cqspi); 18482087e85bSDhruva Gole 18492087e85bSDhruva Gole cqspi->current_cs = -1; 18502087e85bSDhruva Gole cqspi->sclk = 0; 18512087e85bSDhruva Gole 18522087e85bSDhruva Gole return spi_master_resume(master); 185331fb632bSRamuthevar Vadivel Murugan } 185431fb632bSRamuthevar Vadivel Murugan 1855be3206e8SDhruva Gole static DEFINE_SIMPLE_DEV_PM_OPS(cqspi_dev_pm_ops, cqspi_suspend, cqspi_resume); 185631fb632bSRamuthevar Vadivel Murugan 185731fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata cdns_qspi = { 185831fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_DISABLE_DAC_MODE, 185931fb632bSRamuthevar Vadivel Murugan }; 186031fb632bSRamuthevar Vadivel Murugan 186131fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata k2g_qspi = { 186231fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_NEEDS_WR_DELAY, 186331fb632bSRamuthevar Vadivel Murugan }; 186431fb632bSRamuthevar Vadivel Murugan 186531fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata am654_ospi = { 186631fb632bSRamuthevar Vadivel Murugan .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 186731fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_NEEDS_WR_DELAY, 186831fb632bSRamuthevar Vadivel Murugan }; 186931fb632bSRamuthevar Vadivel Murugan 1870ad2775dcSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata intel_lgm_qspi = { 1871ad2775dcSRamuthevar Vadivel Murugan .quirks = CQSPI_DISABLE_DAC_MODE, 1872ad2775dcSRamuthevar Vadivel Murugan }; 1873ad2775dcSRamuthevar Vadivel Murugan 187498d948ebSDinh Nguyen static const struct cqspi_driver_platdata socfpga_qspi = { 18759ee5b6d5SNiravkumar L Rabara .quirks = CQSPI_DISABLE_DAC_MODE 18769ee5b6d5SNiravkumar L Rabara | CQSPI_NO_SUPPORT_WR_COMPLETION 18779ee5b6d5SNiravkumar L Rabara | CQSPI_SLOW_SRAM, 187898d948ebSDinh Nguyen }; 187998d948ebSDinh Nguyen 188009e393e3SSai Krishna Potthuri static const struct cqspi_driver_platdata versal_ospi = { 188109e393e3SSai Krishna Potthuri .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 18821a6f854fSSai Krishna Potthuri .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA, 18831a6f854fSSai Krishna Potthuri .indirect_read_dma = cqspi_versal_indirect_read_dma, 18841a6f854fSSai Krishna Potthuri .get_dma_status = cqspi_get_versal_dma_status, 188509e393e3SSai Krishna Potthuri }; 188609e393e3SSai Krishna Potthuri 188747fef94aSWilliam Qiu static const struct cqspi_driver_platdata jh7110_qspi = { 188847fef94aSWilliam Qiu .quirks = CQSPI_DISABLE_DAC_MODE, 188947fef94aSWilliam Qiu }; 189047fef94aSWilliam Qiu 189131fb632bSRamuthevar Vadivel Murugan static const struct of_device_id cqspi_dt_ids[] = { 189231fb632bSRamuthevar Vadivel Murugan { 189331fb632bSRamuthevar Vadivel Murugan .compatible = "cdns,qspi-nor", 189431fb632bSRamuthevar Vadivel Murugan .data = &cdns_qspi, 189531fb632bSRamuthevar Vadivel Murugan }, 189631fb632bSRamuthevar Vadivel Murugan { 189731fb632bSRamuthevar Vadivel Murugan .compatible = "ti,k2g-qspi", 189831fb632bSRamuthevar Vadivel Murugan .data = &k2g_qspi, 189931fb632bSRamuthevar Vadivel Murugan }, 190031fb632bSRamuthevar Vadivel Murugan { 190131fb632bSRamuthevar Vadivel Murugan .compatible = "ti,am654-ospi", 190231fb632bSRamuthevar Vadivel Murugan .data = &am654_ospi, 190331fb632bSRamuthevar Vadivel Murugan }, 1904ab2d2875SRamuthevar Vadivel Murugan { 1905ab2d2875SRamuthevar Vadivel Murugan .compatible = "intel,lgm-qspi", 1906ad2775dcSRamuthevar Vadivel Murugan .data = &intel_lgm_qspi, 1907ab2d2875SRamuthevar Vadivel Murugan }, 190809e393e3SSai Krishna Potthuri { 190909e393e3SSai Krishna Potthuri .compatible = "xlnx,versal-ospi-1.0", 19100d868829SIan Abbott .data = &versal_ospi, 191109e393e3SSai Krishna Potthuri }, 191298d948ebSDinh Nguyen { 191398d948ebSDinh Nguyen .compatible = "intel,socfpga-qspi", 19140d868829SIan Abbott .data = &socfpga_qspi, 191598d948ebSDinh Nguyen }, 191647fef94aSWilliam Qiu { 191747fef94aSWilliam Qiu .compatible = "starfive,jh7110-qspi", 191847fef94aSWilliam Qiu .data = &jh7110_qspi, 191947fef94aSWilliam Qiu }, 192031fb632bSRamuthevar Vadivel Murugan { /* end of table */ } 192131fb632bSRamuthevar Vadivel Murugan }; 192231fb632bSRamuthevar Vadivel Murugan 192331fb632bSRamuthevar Vadivel Murugan MODULE_DEVICE_TABLE(of, cqspi_dt_ids); 192431fb632bSRamuthevar Vadivel Murugan 192531fb632bSRamuthevar Vadivel Murugan static struct platform_driver cqspi_platform_driver = { 192631fb632bSRamuthevar Vadivel Murugan .probe = cqspi_probe, 19276fe41879SUwe Kleine-König .remove_new = cqspi_remove, 192831fb632bSRamuthevar Vadivel Murugan .driver = { 192931fb632bSRamuthevar Vadivel Murugan .name = CQSPI_NAME, 1930be3206e8SDhruva Gole .pm = &cqspi_dev_pm_ops, 193131fb632bSRamuthevar Vadivel Murugan .of_match_table = cqspi_dt_ids, 193231fb632bSRamuthevar Vadivel Murugan }, 193331fb632bSRamuthevar Vadivel Murugan }; 193431fb632bSRamuthevar Vadivel Murugan 193531fb632bSRamuthevar Vadivel Murugan module_platform_driver(cqspi_platform_driver); 193631fb632bSRamuthevar Vadivel Murugan 193731fb632bSRamuthevar Vadivel Murugan MODULE_DESCRIPTION("Cadence QSPI Controller Driver"); 193831fb632bSRamuthevar Vadivel Murugan MODULE_LICENSE("GPL v2"); 193931fb632bSRamuthevar Vadivel Murugan MODULE_ALIAS("platform:" CQSPI_NAME); 194031fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>"); 194131fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>"); 194231fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>"); 194331fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>"); 1944f453f293SPratyush Yadav MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>"); 1945