131fb632bSRamuthevar Vadivel Murugan // SPDX-License-Identifier: GPL-2.0-only 231fb632bSRamuthevar Vadivel Murugan // 331fb632bSRamuthevar Vadivel Murugan // Driver for Cadence QSPI Controller 431fb632bSRamuthevar Vadivel Murugan // 531fb632bSRamuthevar Vadivel Murugan // Copyright Altera Corporation (C) 2012-2014. All rights reserved. 631fb632bSRamuthevar Vadivel Murugan // Copyright Intel Corporation (C) 2019-2020. All rights reserved. 731fb632bSRamuthevar Vadivel Murugan // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 831fb632bSRamuthevar Vadivel Murugan 931fb632bSRamuthevar Vadivel Murugan #include <linux/clk.h> 1031fb632bSRamuthevar Vadivel Murugan #include <linux/completion.h> 1131fb632bSRamuthevar Vadivel Murugan #include <linux/delay.h> 1231fb632bSRamuthevar Vadivel Murugan #include <linux/dma-mapping.h> 1331fb632bSRamuthevar Vadivel Murugan #include <linux/dmaengine.h> 1431fb632bSRamuthevar Vadivel Murugan #include <linux/err.h> 1531fb632bSRamuthevar Vadivel Murugan #include <linux/errno.h> 1631fb632bSRamuthevar Vadivel Murugan #include <linux/interrupt.h> 1731fb632bSRamuthevar Vadivel Murugan #include <linux/io.h> 1831fb632bSRamuthevar Vadivel Murugan #include <linux/iopoll.h> 1931fb632bSRamuthevar Vadivel Murugan #include <linux/jiffies.h> 2031fb632bSRamuthevar Vadivel Murugan #include <linux/kernel.h> 2131fb632bSRamuthevar Vadivel Murugan #include <linux/module.h> 2231fb632bSRamuthevar Vadivel Murugan #include <linux/of_device.h> 2331fb632bSRamuthevar Vadivel Murugan #include <linux/of.h> 2431fb632bSRamuthevar Vadivel Murugan #include <linux/platform_device.h> 2531fb632bSRamuthevar Vadivel Murugan #include <linux/pm_runtime.h> 2631fb632bSRamuthevar Vadivel Murugan #include <linux/reset.h> 2731fb632bSRamuthevar Vadivel Murugan #include <linux/sched.h> 2831fb632bSRamuthevar Vadivel Murugan #include <linux/spi/spi.h> 2931fb632bSRamuthevar Vadivel Murugan #include <linux/spi/spi-mem.h> 3031fb632bSRamuthevar Vadivel Murugan #include <linux/timer.h> 3131fb632bSRamuthevar Vadivel Murugan 3231fb632bSRamuthevar Vadivel Murugan #define CQSPI_NAME "cadence-qspi" 3331fb632bSRamuthevar Vadivel Murugan #define CQSPI_MAX_CHIPSELECT 16 3431fb632bSRamuthevar Vadivel Murugan 3531fb632bSRamuthevar Vadivel Murugan /* Quirks */ 3631fb632bSRamuthevar Vadivel Murugan #define CQSPI_NEEDS_WR_DELAY BIT(0) 3731fb632bSRamuthevar Vadivel Murugan #define CQSPI_DISABLE_DAC_MODE BIT(1) 3831fb632bSRamuthevar Vadivel Murugan 3931fb632bSRamuthevar Vadivel Murugan /* Capabilities */ 4031fb632bSRamuthevar Vadivel Murugan #define CQSPI_SUPPORTS_OCTAL BIT(0) 4131fb632bSRamuthevar Vadivel Murugan 4231fb632bSRamuthevar Vadivel Murugan struct cqspi_st; 4331fb632bSRamuthevar Vadivel Murugan 4431fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata { 4531fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi; 4631fb632bSRamuthevar Vadivel Murugan u32 clk_rate; 4731fb632bSRamuthevar Vadivel Murugan u32 read_delay; 4831fb632bSRamuthevar Vadivel Murugan u32 tshsl_ns; 4931fb632bSRamuthevar Vadivel Murugan u32 tsd2d_ns; 5031fb632bSRamuthevar Vadivel Murugan u32 tchsh_ns; 5131fb632bSRamuthevar Vadivel Murugan u32 tslch_ns; 5231fb632bSRamuthevar Vadivel Murugan u8 inst_width; 5331fb632bSRamuthevar Vadivel Murugan u8 addr_width; 5431fb632bSRamuthevar Vadivel Murugan u8 data_width; 55f453f293SPratyush Yadav bool dtr; 5631fb632bSRamuthevar Vadivel Murugan u8 cs; 5731fb632bSRamuthevar Vadivel Murugan }; 5831fb632bSRamuthevar Vadivel Murugan 5931fb632bSRamuthevar Vadivel Murugan struct cqspi_st { 6031fb632bSRamuthevar Vadivel Murugan struct platform_device *pdev; 6131fb632bSRamuthevar Vadivel Murugan 6231fb632bSRamuthevar Vadivel Murugan struct clk *clk; 6331fb632bSRamuthevar Vadivel Murugan unsigned int sclk; 6431fb632bSRamuthevar Vadivel Murugan 6531fb632bSRamuthevar Vadivel Murugan void __iomem *iobase; 6631fb632bSRamuthevar Vadivel Murugan void __iomem *ahb_base; 6731fb632bSRamuthevar Vadivel Murugan resource_size_t ahb_size; 6831fb632bSRamuthevar Vadivel Murugan struct completion transfer_complete; 6931fb632bSRamuthevar Vadivel Murugan 7031fb632bSRamuthevar Vadivel Murugan struct dma_chan *rx_chan; 7131fb632bSRamuthevar Vadivel Murugan struct completion rx_dma_complete; 7231fb632bSRamuthevar Vadivel Murugan dma_addr_t mmap_phys_base; 7331fb632bSRamuthevar Vadivel Murugan 7431fb632bSRamuthevar Vadivel Murugan int current_cs; 7531fb632bSRamuthevar Vadivel Murugan unsigned long master_ref_clk_hz; 7631fb632bSRamuthevar Vadivel Murugan bool is_decoded_cs; 7731fb632bSRamuthevar Vadivel Murugan u32 fifo_depth; 7831fb632bSRamuthevar Vadivel Murugan u32 fifo_width; 79b436fb7dSRamuthevar Vadivel Murugan u32 num_chipselect; 8031fb632bSRamuthevar Vadivel Murugan bool rclk_en; 8131fb632bSRamuthevar Vadivel Murugan u32 trigger_address; 8231fb632bSRamuthevar Vadivel Murugan u32 wr_delay; 8331fb632bSRamuthevar Vadivel Murugan bool use_direct_mode; 8431fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; 8531fb632bSRamuthevar Vadivel Murugan }; 8631fb632bSRamuthevar Vadivel Murugan 8731fb632bSRamuthevar Vadivel Murugan struct cqspi_driver_platdata { 8831fb632bSRamuthevar Vadivel Murugan u32 hwcaps_mask; 8931fb632bSRamuthevar Vadivel Murugan u8 quirks; 9031fb632bSRamuthevar Vadivel Murugan }; 9131fb632bSRamuthevar Vadivel Murugan 9231fb632bSRamuthevar Vadivel Murugan /* Operation timeout value */ 9331fb632bSRamuthevar Vadivel Murugan #define CQSPI_TIMEOUT_MS 500 9431fb632bSRamuthevar Vadivel Murugan #define CQSPI_READ_TIMEOUT_MS 10 9531fb632bSRamuthevar Vadivel Murugan 9631fb632bSRamuthevar Vadivel Murugan /* Instruction type */ 9731fb632bSRamuthevar Vadivel Murugan #define CQSPI_INST_TYPE_SINGLE 0 9831fb632bSRamuthevar Vadivel Murugan #define CQSPI_INST_TYPE_DUAL 1 9931fb632bSRamuthevar Vadivel Murugan #define CQSPI_INST_TYPE_QUAD 2 10031fb632bSRamuthevar Vadivel Murugan #define CQSPI_INST_TYPE_OCTAL 3 10131fb632bSRamuthevar Vadivel Murugan 10231fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_CLKS_PER_BYTE 8 10331fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_BYTES_MAX 4 10431fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_CLKS_MAX 31 10531fb632bSRamuthevar Vadivel Murugan 10631fb632bSRamuthevar Vadivel Murugan #define CQSPI_STIG_DATA_LEN_MAX 8 10731fb632bSRamuthevar Vadivel Murugan 10831fb632bSRamuthevar Vadivel Murugan /* Register map */ 10931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG 0x00 11031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0) 11131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7) 11231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9) 11331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 11431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_DMA_MASK BIT(15) 11531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_BAUD_LSB 19 116f453f293SPratyush Yadav #define CQSPI_REG_CONFIG_DTR_PROTO BIT(24) 117f453f293SPratyush Yadav #define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30) 11831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_IDLE_LSB 31 11931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF 12031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_BAUD_MASK 0xF 12131fb632bSRamuthevar Vadivel Murugan 12231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR 0x04 12331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 12431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 12531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 12631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 12731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 12831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 12931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 13031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 13131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 13231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F 13331fb632bSRamuthevar Vadivel Murugan 13431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR 0x08 13531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 13631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12 13731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16 13831fb632bSRamuthevar Vadivel Murugan 13931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY 0x0C 14031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSLCH_LSB 0 14131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TCHSH_LSB 8 14231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSD2D_LSB 16 14331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSHSL_LSB 24 14431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF 14531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF 14631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF 14731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF 14831fb632bSRamuthevar Vadivel Murugan 14931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE 0x10 15031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0 15131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_DELAY_LSB 1 15231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF 15331fb632bSRamuthevar Vadivel Murugan 15431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE 0x14 15531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_ADDRESS_LSB 0 15631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_PAGE_LSB 4 15731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_BLOCK_LSB 16 15831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF 15931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF 16031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F 16131fb632bSRamuthevar Vadivel Murugan 16231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SRAMPARTITION 0x18 16331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTTRIGGER 0x1C 16431fb632bSRamuthevar Vadivel Murugan 16531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA 0x20 16631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_SINGLE_LSB 0 16731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_BURST_LSB 8 16831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_SINGLE_MASK 0xFF 16931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_BURST_MASK 0xFF 17031fb632bSRamuthevar Vadivel Murugan 17131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_REMAP 0x24 17231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_MODE_BIT 0x28 17331fb632bSRamuthevar Vadivel Murugan 17431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL 0x2C 17531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 17631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 17731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF 17831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF 17931fb632bSRamuthevar Vadivel Murugan 180f453f293SPratyush Yadav #define CQSPI_REG_WR_COMPLETION_CTRL 0x38 181f453f293SPratyush Yadav #define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14) 182f453f293SPratyush Yadav 18331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQSTATUS 0x40 18431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQMASK 0x44 18531fb632bSRamuthevar Vadivel Murugan 18631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD 0x60 18731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0) 18831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1) 18931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5) 19031fb632bSRamuthevar Vadivel Murugan 19131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDWATERMARK 0x64 19231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 19331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDBYTES 0x6C 19431fb632bSRamuthevar Vadivel Murugan 19531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL 0x90 19631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0) 19731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1) 198888d517bSPratyush Yadav #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 19931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 20031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 20131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 20231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 20331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 20431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 20531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 20631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 20731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 20831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 209888d517bSPratyush Yadav #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F 21031fb632bSRamuthevar Vadivel Murugan 21131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR 0x70 21231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0) 21331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1) 21431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5) 21531fb632bSRamuthevar Vadivel Murugan 21631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRWATERMARK 0x74 21731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 21831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRBYTES 0x7C 21931fb632bSRamuthevar Vadivel Murugan 22031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDADDRESS 0x94 22131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDREADDATALOWER 0xA0 22231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDREADDATAUPPER 0xA4 22331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDWRITEDATALOWER 0xA8 22431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC 22531fb632bSRamuthevar Vadivel Murugan 226f453f293SPratyush Yadav #define CQSPI_REG_POLLING_STATUS 0xB0 227f453f293SPratyush Yadav #define CQSPI_REG_POLLING_STATUS_DUMMY_LSB 16 228f453f293SPratyush Yadav 229f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_LOWER 0xE0 230f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_READ_LSB 24 231f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_WRITE_LSB 16 232f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_STIG_LSB 0 233f453f293SPratyush Yadav 23431fb632bSRamuthevar Vadivel Murugan /* Interrupt status bits */ 23531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_MODE_ERR BIT(0) 23631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_UNDERFLOW BIT(1) 23731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_COMP BIT(2) 23831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3) 23931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4) 24031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5) 24131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_WATERMARK BIT(6) 24231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12) 24331fb632bSRamuthevar Vadivel Murugan 24431fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \ 24531fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_IND_SRAM_FULL | \ 24631fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_IND_COMP) 24731fb632bSRamuthevar Vadivel Murugan 24831fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \ 24931fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_WATERMARK | \ 25031fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_UNDERFLOW) 25131fb632bSRamuthevar Vadivel Murugan 25231fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_STATUS_MASK 0x1FFFF 25331fb632bSRamuthevar Vadivel Murugan 25431fb632bSRamuthevar Vadivel Murugan static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr) 25531fb632bSRamuthevar Vadivel Murugan { 25631fb632bSRamuthevar Vadivel Murugan u32 val; 25731fb632bSRamuthevar Vadivel Murugan 25831fb632bSRamuthevar Vadivel Murugan return readl_relaxed_poll_timeout(reg, val, 25931fb632bSRamuthevar Vadivel Murugan (((clr ? ~val : val) & mask) == mask), 26031fb632bSRamuthevar Vadivel Murugan 10, CQSPI_TIMEOUT_MS * 1000); 26131fb632bSRamuthevar Vadivel Murugan } 26231fb632bSRamuthevar Vadivel Murugan 26331fb632bSRamuthevar Vadivel Murugan static bool cqspi_is_idle(struct cqspi_st *cqspi) 26431fb632bSRamuthevar Vadivel Murugan { 26531fb632bSRamuthevar Vadivel Murugan u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 26631fb632bSRamuthevar Vadivel Murugan 26731fb632bSRamuthevar Vadivel Murugan return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB); 26831fb632bSRamuthevar Vadivel Murugan } 26931fb632bSRamuthevar Vadivel Murugan 27031fb632bSRamuthevar Vadivel Murugan static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi) 27131fb632bSRamuthevar Vadivel Murugan { 27231fb632bSRamuthevar Vadivel Murugan u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL); 27331fb632bSRamuthevar Vadivel Murugan 27431fb632bSRamuthevar Vadivel Murugan reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB; 27531fb632bSRamuthevar Vadivel Murugan return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK; 27631fb632bSRamuthevar Vadivel Murugan } 27731fb632bSRamuthevar Vadivel Murugan 27831fb632bSRamuthevar Vadivel Murugan static irqreturn_t cqspi_irq_handler(int this_irq, void *dev) 27931fb632bSRamuthevar Vadivel Murugan { 28031fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev; 28131fb632bSRamuthevar Vadivel Murugan unsigned int irq_status; 28231fb632bSRamuthevar Vadivel Murugan 28331fb632bSRamuthevar Vadivel Murugan /* Read interrupt status */ 28431fb632bSRamuthevar Vadivel Murugan irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS); 28531fb632bSRamuthevar Vadivel Murugan 28631fb632bSRamuthevar Vadivel Murugan /* Clear interrupt */ 28731fb632bSRamuthevar Vadivel Murugan writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS); 28831fb632bSRamuthevar Vadivel Murugan 28931fb632bSRamuthevar Vadivel Murugan irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR; 29031fb632bSRamuthevar Vadivel Murugan 29131fb632bSRamuthevar Vadivel Murugan if (irq_status) 29231fb632bSRamuthevar Vadivel Murugan complete(&cqspi->transfer_complete); 29331fb632bSRamuthevar Vadivel Murugan 29431fb632bSRamuthevar Vadivel Murugan return IRQ_HANDLED; 29531fb632bSRamuthevar Vadivel Murugan } 29631fb632bSRamuthevar Vadivel Murugan 29731fb632bSRamuthevar Vadivel Murugan static unsigned int cqspi_calc_rdreg(struct cqspi_flash_pdata *f_pdata) 29831fb632bSRamuthevar Vadivel Murugan { 29931fb632bSRamuthevar Vadivel Murugan u32 rdreg = 0; 30031fb632bSRamuthevar Vadivel Murugan 30131fb632bSRamuthevar Vadivel Murugan rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; 30231fb632bSRamuthevar Vadivel Murugan rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; 30331fb632bSRamuthevar Vadivel Murugan rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; 30431fb632bSRamuthevar Vadivel Murugan 30531fb632bSRamuthevar Vadivel Murugan return rdreg; 30631fb632bSRamuthevar Vadivel Murugan } 30731fb632bSRamuthevar Vadivel Murugan 308f453f293SPratyush Yadav static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op, bool dtr) 309888d517bSPratyush Yadav { 310888d517bSPratyush Yadav unsigned int dummy_clk; 311888d517bSPratyush Yadav 3127512eaf5SPratyush Yadav dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth); 313f453f293SPratyush Yadav if (dtr) 314f453f293SPratyush Yadav dummy_clk /= 2; 315888d517bSPratyush Yadav 316888d517bSPratyush Yadav return dummy_clk; 317888d517bSPratyush Yadav } 318888d517bSPratyush Yadav 319f453f293SPratyush Yadav static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata, 320f453f293SPratyush Yadav const struct spi_mem_op *op) 321f453f293SPratyush Yadav { 322f453f293SPratyush Yadav f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE; 323f453f293SPratyush Yadav f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE; 324f453f293SPratyush Yadav f_pdata->data_width = CQSPI_INST_TYPE_SINGLE; 325f453f293SPratyush Yadav f_pdata->dtr = op->data.dtr && op->cmd.dtr && op->addr.dtr; 326f453f293SPratyush Yadav 327f453f293SPratyush Yadav switch (op->data.buswidth) { 328f453f293SPratyush Yadav case 0: 329f453f293SPratyush Yadav break; 330f453f293SPratyush Yadav case 1: 331f453f293SPratyush Yadav f_pdata->data_width = CQSPI_INST_TYPE_SINGLE; 332f453f293SPratyush Yadav break; 333f453f293SPratyush Yadav case 2: 334f453f293SPratyush Yadav f_pdata->data_width = CQSPI_INST_TYPE_DUAL; 335f453f293SPratyush Yadav break; 336f453f293SPratyush Yadav case 4: 337f453f293SPratyush Yadav f_pdata->data_width = CQSPI_INST_TYPE_QUAD; 338f453f293SPratyush Yadav break; 339f453f293SPratyush Yadav case 8: 340f453f293SPratyush Yadav f_pdata->data_width = CQSPI_INST_TYPE_OCTAL; 341f453f293SPratyush Yadav break; 342f453f293SPratyush Yadav default: 343f453f293SPratyush Yadav return -EINVAL; 344f453f293SPratyush Yadav } 345f453f293SPratyush Yadav 346f453f293SPratyush Yadav /* Right now we only support 8-8-8 DTR mode. */ 347f453f293SPratyush Yadav if (f_pdata->dtr) { 348f453f293SPratyush Yadav switch (op->cmd.buswidth) { 349f453f293SPratyush Yadav case 0: 350f453f293SPratyush Yadav break; 351f453f293SPratyush Yadav case 8: 352f453f293SPratyush Yadav f_pdata->inst_width = CQSPI_INST_TYPE_OCTAL; 353f453f293SPratyush Yadav break; 354f453f293SPratyush Yadav default: 355f453f293SPratyush Yadav return -EINVAL; 356f453f293SPratyush Yadav } 357f453f293SPratyush Yadav 358f453f293SPratyush Yadav switch (op->addr.buswidth) { 359f453f293SPratyush Yadav case 0: 360f453f293SPratyush Yadav break; 361f453f293SPratyush Yadav case 8: 362f453f293SPratyush Yadav f_pdata->addr_width = CQSPI_INST_TYPE_OCTAL; 363f453f293SPratyush Yadav break; 364f453f293SPratyush Yadav default: 365f453f293SPratyush Yadav return -EINVAL; 366f453f293SPratyush Yadav } 367f453f293SPratyush Yadav 368f453f293SPratyush Yadav switch (op->data.buswidth) { 369f453f293SPratyush Yadav case 0: 370f453f293SPratyush Yadav break; 371f453f293SPratyush Yadav case 8: 372f453f293SPratyush Yadav f_pdata->data_width = CQSPI_INST_TYPE_OCTAL; 373f453f293SPratyush Yadav break; 374f453f293SPratyush Yadav default: 375f453f293SPratyush Yadav return -EINVAL; 376f453f293SPratyush Yadav } 377f453f293SPratyush Yadav } 378f453f293SPratyush Yadav 379f453f293SPratyush Yadav return 0; 380f453f293SPratyush Yadav } 381f453f293SPratyush Yadav 38231fb632bSRamuthevar Vadivel Murugan static int cqspi_wait_idle(struct cqspi_st *cqspi) 38331fb632bSRamuthevar Vadivel Murugan { 38431fb632bSRamuthevar Vadivel Murugan const unsigned int poll_idle_retry = 3; 38531fb632bSRamuthevar Vadivel Murugan unsigned int count = 0; 38631fb632bSRamuthevar Vadivel Murugan unsigned long timeout; 38731fb632bSRamuthevar Vadivel Murugan 38831fb632bSRamuthevar Vadivel Murugan timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS); 38931fb632bSRamuthevar Vadivel Murugan while (1) { 39031fb632bSRamuthevar Vadivel Murugan /* 39131fb632bSRamuthevar Vadivel Murugan * Read few times in succession to ensure the controller 39231fb632bSRamuthevar Vadivel Murugan * is indeed idle, that is, the bit does not transition 39331fb632bSRamuthevar Vadivel Murugan * low again. 39431fb632bSRamuthevar Vadivel Murugan */ 39531fb632bSRamuthevar Vadivel Murugan if (cqspi_is_idle(cqspi)) 39631fb632bSRamuthevar Vadivel Murugan count++; 39731fb632bSRamuthevar Vadivel Murugan else 39831fb632bSRamuthevar Vadivel Murugan count = 0; 39931fb632bSRamuthevar Vadivel Murugan 40031fb632bSRamuthevar Vadivel Murugan if (count >= poll_idle_retry) 40131fb632bSRamuthevar Vadivel Murugan return 0; 40231fb632bSRamuthevar Vadivel Murugan 40331fb632bSRamuthevar Vadivel Murugan if (time_after(jiffies, timeout)) { 40431fb632bSRamuthevar Vadivel Murugan /* Timeout, in busy mode. */ 40531fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 40631fb632bSRamuthevar Vadivel Murugan "QSPI is still busy after %dms timeout.\n", 40731fb632bSRamuthevar Vadivel Murugan CQSPI_TIMEOUT_MS); 40831fb632bSRamuthevar Vadivel Murugan return -ETIMEDOUT; 40931fb632bSRamuthevar Vadivel Murugan } 41031fb632bSRamuthevar Vadivel Murugan 41131fb632bSRamuthevar Vadivel Murugan cpu_relax(); 41231fb632bSRamuthevar Vadivel Murugan } 41331fb632bSRamuthevar Vadivel Murugan } 41431fb632bSRamuthevar Vadivel Murugan 41531fb632bSRamuthevar Vadivel Murugan static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg) 41631fb632bSRamuthevar Vadivel Murugan { 41731fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 41831fb632bSRamuthevar Vadivel Murugan int ret; 41931fb632bSRamuthevar Vadivel Murugan 42031fb632bSRamuthevar Vadivel Murugan /* Write the CMDCTRL without start execution. */ 42131fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CMDCTRL); 42231fb632bSRamuthevar Vadivel Murugan /* Start execute */ 42331fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK; 42431fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CMDCTRL); 42531fb632bSRamuthevar Vadivel Murugan 42631fb632bSRamuthevar Vadivel Murugan /* Polling for completion. */ 42731fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL, 42831fb632bSRamuthevar Vadivel Murugan CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1); 42931fb632bSRamuthevar Vadivel Murugan if (ret) { 43031fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 43131fb632bSRamuthevar Vadivel Murugan "Flash command execution timed out.\n"); 43231fb632bSRamuthevar Vadivel Murugan return ret; 43331fb632bSRamuthevar Vadivel Murugan } 43431fb632bSRamuthevar Vadivel Murugan 43531fb632bSRamuthevar Vadivel Murugan /* Polling QSPI idle status. */ 43631fb632bSRamuthevar Vadivel Murugan return cqspi_wait_idle(cqspi); 43731fb632bSRamuthevar Vadivel Murugan } 43831fb632bSRamuthevar Vadivel Murugan 439f453f293SPratyush Yadav static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata, 440f453f293SPratyush Yadav const struct spi_mem_op *op, 441f453f293SPratyush Yadav unsigned int shift) 442f453f293SPratyush Yadav { 443f453f293SPratyush Yadav struct cqspi_st *cqspi = f_pdata->cqspi; 444f453f293SPratyush Yadav void __iomem *reg_base = cqspi->iobase; 445f453f293SPratyush Yadav unsigned int reg; 446f453f293SPratyush Yadav u8 ext; 447f453f293SPratyush Yadav 448f453f293SPratyush Yadav if (op->cmd.nbytes != 2) 449f453f293SPratyush Yadav return -EINVAL; 450f453f293SPratyush Yadav 451f453f293SPratyush Yadav /* Opcode extension is the LSB. */ 452f453f293SPratyush Yadav ext = op->cmd.opcode & 0xff; 453f453f293SPratyush Yadav 454f453f293SPratyush Yadav reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER); 455f453f293SPratyush Yadav reg &= ~(0xff << shift); 456f453f293SPratyush Yadav reg |= ext << shift; 457f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER); 458f453f293SPratyush Yadav 459f453f293SPratyush Yadav return 0; 460f453f293SPratyush Yadav } 461f453f293SPratyush Yadav 462f453f293SPratyush Yadav static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata, 463f453f293SPratyush Yadav const struct spi_mem_op *op, unsigned int shift, 464f453f293SPratyush Yadav bool enable) 465f453f293SPratyush Yadav { 466f453f293SPratyush Yadav struct cqspi_st *cqspi = f_pdata->cqspi; 467f453f293SPratyush Yadav void __iomem *reg_base = cqspi->iobase; 468f453f293SPratyush Yadav unsigned int reg; 469f453f293SPratyush Yadav int ret; 470f453f293SPratyush Yadav 471f453f293SPratyush Yadav reg = readl(reg_base + CQSPI_REG_CONFIG); 472f453f293SPratyush Yadav 473f453f293SPratyush Yadav /* 474f453f293SPratyush Yadav * We enable dual byte opcode here. The callers have to set up the 475f453f293SPratyush Yadav * extension opcode based on which type of operation it is. 476f453f293SPratyush Yadav */ 477f453f293SPratyush Yadav if (enable) { 478f453f293SPratyush Yadav reg |= CQSPI_REG_CONFIG_DTR_PROTO; 479f453f293SPratyush Yadav reg |= CQSPI_REG_CONFIG_DUAL_OPCODE; 480f453f293SPratyush Yadav 481f453f293SPratyush Yadav /* Set up command opcode extension. */ 482f453f293SPratyush Yadav ret = cqspi_setup_opcode_ext(f_pdata, op, shift); 483f453f293SPratyush Yadav if (ret) 484f453f293SPratyush Yadav return ret; 485f453f293SPratyush Yadav } else { 486f453f293SPratyush Yadav reg &= ~CQSPI_REG_CONFIG_DTR_PROTO; 487f453f293SPratyush Yadav reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE; 488f453f293SPratyush Yadav } 489f453f293SPratyush Yadav 490f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_CONFIG); 491f453f293SPratyush Yadav 492f453f293SPratyush Yadav return cqspi_wait_idle(cqspi); 493f453f293SPratyush Yadav } 494f453f293SPratyush Yadav 49531fb632bSRamuthevar Vadivel Murugan static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, 49631fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 49731fb632bSRamuthevar Vadivel Murugan { 49831fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 49931fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 50031fb632bSRamuthevar Vadivel Murugan u8 *rxbuf = op->data.buf.in; 501f453f293SPratyush Yadav u8 opcode; 50231fb632bSRamuthevar Vadivel Murugan size_t n_rx = op->data.nbytes; 50331fb632bSRamuthevar Vadivel Murugan unsigned int rdreg; 50431fb632bSRamuthevar Vadivel Murugan unsigned int reg; 505888d517bSPratyush Yadav unsigned int dummy_clk; 50631fb632bSRamuthevar Vadivel Murugan size_t read_len; 50731fb632bSRamuthevar Vadivel Murugan int status; 50831fb632bSRamuthevar Vadivel Murugan 509f453f293SPratyush Yadav status = cqspi_set_protocol(f_pdata, op); 510f453f293SPratyush Yadav if (status) 511f453f293SPratyush Yadav return status; 512f453f293SPratyush Yadav 513f453f293SPratyush Yadav status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB, 514f453f293SPratyush Yadav f_pdata->dtr); 515f453f293SPratyush Yadav if (status) 516f453f293SPratyush Yadav return status; 517f453f293SPratyush Yadav 51831fb632bSRamuthevar Vadivel Murugan if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) { 51931fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 52031fb632bSRamuthevar Vadivel Murugan "Invalid input argument, len %zu rxbuf 0x%p\n", 52131fb632bSRamuthevar Vadivel Murugan n_rx, rxbuf); 52231fb632bSRamuthevar Vadivel Murugan return -EINVAL; 52331fb632bSRamuthevar Vadivel Murugan } 52431fb632bSRamuthevar Vadivel Murugan 525f453f293SPratyush Yadav if (f_pdata->dtr) 526f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 527f453f293SPratyush Yadav else 528f453f293SPratyush Yadav opcode = op->cmd.opcode; 529f453f293SPratyush Yadav 53031fb632bSRamuthevar Vadivel Murugan reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 53131fb632bSRamuthevar Vadivel Murugan 53231fb632bSRamuthevar Vadivel Murugan rdreg = cqspi_calc_rdreg(f_pdata); 53331fb632bSRamuthevar Vadivel Murugan writel(rdreg, reg_base + CQSPI_REG_RD_INSTR); 53431fb632bSRamuthevar Vadivel Murugan 535f453f293SPratyush Yadav dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr); 536888d517bSPratyush Yadav if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 537888d517bSPratyush Yadav return -EOPNOTSUPP; 538888d517bSPratyush Yadav 539888d517bSPratyush Yadav if (dummy_clk) 540888d517bSPratyush Yadav reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK) 541888d517bSPratyush Yadav << CQSPI_REG_CMDCTRL_DUMMY_LSB; 542888d517bSPratyush Yadav 54331fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); 54431fb632bSRamuthevar Vadivel Murugan 54531fb632bSRamuthevar Vadivel Murugan /* 0 means 1 byte. */ 54631fb632bSRamuthevar Vadivel Murugan reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) 54731fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); 54831fb632bSRamuthevar Vadivel Murugan status = cqspi_exec_flash_cmd(cqspi, reg); 54931fb632bSRamuthevar Vadivel Murugan if (status) 55031fb632bSRamuthevar Vadivel Murugan return status; 55131fb632bSRamuthevar Vadivel Murugan 55231fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER); 55331fb632bSRamuthevar Vadivel Murugan 55431fb632bSRamuthevar Vadivel Murugan /* Put the read value into rx_buf */ 55531fb632bSRamuthevar Vadivel Murugan read_len = (n_rx > 4) ? 4 : n_rx; 55631fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, ®, read_len); 55731fb632bSRamuthevar Vadivel Murugan rxbuf += read_len; 55831fb632bSRamuthevar Vadivel Murugan 55931fb632bSRamuthevar Vadivel Murugan if (n_rx > 4) { 56031fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER); 56131fb632bSRamuthevar Vadivel Murugan 56231fb632bSRamuthevar Vadivel Murugan read_len = n_rx - read_len; 56331fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, ®, read_len); 56431fb632bSRamuthevar Vadivel Murugan } 56531fb632bSRamuthevar Vadivel Murugan 56631fb632bSRamuthevar Vadivel Murugan return 0; 56731fb632bSRamuthevar Vadivel Murugan } 56831fb632bSRamuthevar Vadivel Murugan 56931fb632bSRamuthevar Vadivel Murugan static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata, 57031fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 57131fb632bSRamuthevar Vadivel Murugan { 57231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 57331fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 574f453f293SPratyush Yadav u8 opcode; 57531fb632bSRamuthevar Vadivel Murugan const u8 *txbuf = op->data.buf.out; 57631fb632bSRamuthevar Vadivel Murugan size_t n_tx = op->data.nbytes; 57731fb632bSRamuthevar Vadivel Murugan unsigned int reg; 57831fb632bSRamuthevar Vadivel Murugan unsigned int data; 57931fb632bSRamuthevar Vadivel Murugan size_t write_len; 580f453f293SPratyush Yadav int ret; 581f453f293SPratyush Yadav 582f453f293SPratyush Yadav ret = cqspi_set_protocol(f_pdata, op); 583f453f293SPratyush Yadav if (ret) 584f453f293SPratyush Yadav return ret; 585f453f293SPratyush Yadav 586f453f293SPratyush Yadav ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB, 587f453f293SPratyush Yadav f_pdata->dtr); 588f453f293SPratyush Yadav if (ret) 589f453f293SPratyush Yadav return ret; 59031fb632bSRamuthevar Vadivel Murugan 59131fb632bSRamuthevar Vadivel Murugan if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) { 59231fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 59331fb632bSRamuthevar Vadivel Murugan "Invalid input argument, cmdlen %zu txbuf 0x%p\n", 59431fb632bSRamuthevar Vadivel Murugan n_tx, txbuf); 59531fb632bSRamuthevar Vadivel Murugan return -EINVAL; 59631fb632bSRamuthevar Vadivel Murugan } 59731fb632bSRamuthevar Vadivel Murugan 598f453f293SPratyush Yadav reg = cqspi_calc_rdreg(f_pdata); 599f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_RD_INSTR); 600f453f293SPratyush Yadav 601f453f293SPratyush Yadav if (f_pdata->dtr) 602f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 603f453f293SPratyush Yadav else 604f453f293SPratyush Yadav opcode = op->cmd.opcode; 605f453f293SPratyush Yadav 60631fb632bSRamuthevar Vadivel Murugan reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 60731fb632bSRamuthevar Vadivel Murugan 60831fb632bSRamuthevar Vadivel Murugan if (op->addr.nbytes) { 60931fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 61031fb632bSRamuthevar Vadivel Murugan reg |= ((op->addr.nbytes - 1) & 61131fb632bSRamuthevar Vadivel Murugan CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) 61231fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; 61331fb632bSRamuthevar Vadivel Murugan 61431fb632bSRamuthevar Vadivel Murugan writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); 61531fb632bSRamuthevar Vadivel Murugan } 61631fb632bSRamuthevar Vadivel Murugan 61731fb632bSRamuthevar Vadivel Murugan if (n_tx) { 61831fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB); 61931fb632bSRamuthevar Vadivel Murugan reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) 62031fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_WR_BYTES_LSB; 62131fb632bSRamuthevar Vadivel Murugan data = 0; 62231fb632bSRamuthevar Vadivel Murugan write_len = (n_tx > 4) ? 4 : n_tx; 62331fb632bSRamuthevar Vadivel Murugan memcpy(&data, txbuf, write_len); 62431fb632bSRamuthevar Vadivel Murugan txbuf += write_len; 62531fb632bSRamuthevar Vadivel Murugan writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER); 62631fb632bSRamuthevar Vadivel Murugan 62731fb632bSRamuthevar Vadivel Murugan if (n_tx > 4) { 62831fb632bSRamuthevar Vadivel Murugan data = 0; 62931fb632bSRamuthevar Vadivel Murugan write_len = n_tx - 4; 63031fb632bSRamuthevar Vadivel Murugan memcpy(&data, txbuf, write_len); 63131fb632bSRamuthevar Vadivel Murugan writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER); 63231fb632bSRamuthevar Vadivel Murugan } 63331fb632bSRamuthevar Vadivel Murugan } 63431fb632bSRamuthevar Vadivel Murugan 63531fb632bSRamuthevar Vadivel Murugan return cqspi_exec_flash_cmd(cqspi, reg); 63631fb632bSRamuthevar Vadivel Murugan } 63731fb632bSRamuthevar Vadivel Murugan 63831fb632bSRamuthevar Vadivel Murugan static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata, 63931fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 64031fb632bSRamuthevar Vadivel Murugan { 64131fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 64231fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 64331fb632bSRamuthevar Vadivel Murugan unsigned int dummy_clk = 0; 64431fb632bSRamuthevar Vadivel Murugan unsigned int reg; 645f453f293SPratyush Yadav int ret; 646f453f293SPratyush Yadav u8 opcode; 64731fb632bSRamuthevar Vadivel Murugan 648f453f293SPratyush Yadav ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB, 649f453f293SPratyush Yadav f_pdata->dtr); 650f453f293SPratyush Yadav if (ret) 651f453f293SPratyush Yadav return ret; 652f453f293SPratyush Yadav 653f453f293SPratyush Yadav if (f_pdata->dtr) 654f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 655f453f293SPratyush Yadav else 656f453f293SPratyush Yadav opcode = op->cmd.opcode; 657f453f293SPratyush Yadav 658f453f293SPratyush Yadav reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB; 65931fb632bSRamuthevar Vadivel Murugan reg |= cqspi_calc_rdreg(f_pdata); 66031fb632bSRamuthevar Vadivel Murugan 66131fb632bSRamuthevar Vadivel Murugan /* Setup dummy clock cycles */ 662f453f293SPratyush Yadav dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr); 663888d517bSPratyush Yadav 66431fb632bSRamuthevar Vadivel Murugan if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 665ceeda328SPratyush Yadav return -EOPNOTSUPP; 66631fb632bSRamuthevar Vadivel Murugan 66731fb632bSRamuthevar Vadivel Murugan if (dummy_clk) 66831fb632bSRamuthevar Vadivel Murugan reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK) 66931fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_RD_INSTR_DUMMY_LSB; 67031fb632bSRamuthevar Vadivel Murugan 67131fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_RD_INSTR); 67231fb632bSRamuthevar Vadivel Murugan 67331fb632bSRamuthevar Vadivel Murugan /* Set address width */ 67431fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_SIZE); 67531fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 67631fb632bSRamuthevar Vadivel Murugan reg |= (op->addr.nbytes - 1); 67731fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_SIZE); 67831fb632bSRamuthevar Vadivel Murugan return 0; 67931fb632bSRamuthevar Vadivel Murugan } 68031fb632bSRamuthevar Vadivel Murugan 68131fb632bSRamuthevar Vadivel Murugan static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, 68231fb632bSRamuthevar Vadivel Murugan u8 *rxbuf, loff_t from_addr, 68331fb632bSRamuthevar Vadivel Murugan const size_t n_rx) 68431fb632bSRamuthevar Vadivel Murugan { 68531fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 68631fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 68731fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 68831fb632bSRamuthevar Vadivel Murugan void __iomem *ahb_base = cqspi->ahb_base; 68931fb632bSRamuthevar Vadivel Murugan unsigned int remaining = n_rx; 69031fb632bSRamuthevar Vadivel Murugan unsigned int mod_bytes = n_rx % 4; 69131fb632bSRamuthevar Vadivel Murugan unsigned int bytes_to_read = 0; 69231fb632bSRamuthevar Vadivel Murugan u8 *rxbuf_end = rxbuf + n_rx; 69331fb632bSRamuthevar Vadivel Murugan int ret = 0; 69431fb632bSRamuthevar Vadivel Murugan 69531fb632bSRamuthevar Vadivel Murugan writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 69631fb632bSRamuthevar Vadivel Murugan writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES); 69731fb632bSRamuthevar Vadivel Murugan 69831fb632bSRamuthevar Vadivel Murugan /* Clear all interrupts. */ 69931fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 70031fb632bSRamuthevar Vadivel Murugan 70131fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK); 70231fb632bSRamuthevar Vadivel Murugan 70331fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 70431fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTRD_START_MASK, 70531fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTRD); 70631fb632bSRamuthevar Vadivel Murugan 70731fb632bSRamuthevar Vadivel Murugan while (remaining > 0) { 70831fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->transfer_complete, 70931fb632bSRamuthevar Vadivel Murugan msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) 71031fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 71131fb632bSRamuthevar Vadivel Murugan 71231fb632bSRamuthevar Vadivel Murugan bytes_to_read = cqspi_get_rd_sram_level(cqspi); 71331fb632bSRamuthevar Vadivel Murugan 71431fb632bSRamuthevar Vadivel Murugan if (ret && bytes_to_read == 0) { 71531fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect read timeout, no bytes\n"); 71631fb632bSRamuthevar Vadivel Murugan goto failrd; 71731fb632bSRamuthevar Vadivel Murugan } 71831fb632bSRamuthevar Vadivel Murugan 71931fb632bSRamuthevar Vadivel Murugan while (bytes_to_read != 0) { 72031fb632bSRamuthevar Vadivel Murugan unsigned int word_remain = round_down(remaining, 4); 72131fb632bSRamuthevar Vadivel Murugan 72231fb632bSRamuthevar Vadivel Murugan bytes_to_read *= cqspi->fifo_width; 72331fb632bSRamuthevar Vadivel Murugan bytes_to_read = bytes_to_read > remaining ? 72431fb632bSRamuthevar Vadivel Murugan remaining : bytes_to_read; 72531fb632bSRamuthevar Vadivel Murugan bytes_to_read = round_down(bytes_to_read, 4); 72631fb632bSRamuthevar Vadivel Murugan /* Read 4 byte word chunks then single bytes */ 72731fb632bSRamuthevar Vadivel Murugan if (bytes_to_read) { 72831fb632bSRamuthevar Vadivel Murugan ioread32_rep(ahb_base, rxbuf, 72931fb632bSRamuthevar Vadivel Murugan (bytes_to_read / 4)); 73031fb632bSRamuthevar Vadivel Murugan } else if (!word_remain && mod_bytes) { 73131fb632bSRamuthevar Vadivel Murugan unsigned int temp = ioread32(ahb_base); 73231fb632bSRamuthevar Vadivel Murugan 73331fb632bSRamuthevar Vadivel Murugan bytes_to_read = mod_bytes; 73431fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, &temp, min((unsigned int) 73531fb632bSRamuthevar Vadivel Murugan (rxbuf_end - rxbuf), 73631fb632bSRamuthevar Vadivel Murugan bytes_to_read)); 73731fb632bSRamuthevar Vadivel Murugan } 73831fb632bSRamuthevar Vadivel Murugan rxbuf += bytes_to_read; 73931fb632bSRamuthevar Vadivel Murugan remaining -= bytes_to_read; 74031fb632bSRamuthevar Vadivel Murugan bytes_to_read = cqspi_get_rd_sram_level(cqspi); 74131fb632bSRamuthevar Vadivel Murugan } 74231fb632bSRamuthevar Vadivel Murugan 74331fb632bSRamuthevar Vadivel Murugan if (remaining > 0) 74431fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 74531fb632bSRamuthevar Vadivel Murugan } 74631fb632bSRamuthevar Vadivel Murugan 74731fb632bSRamuthevar Vadivel Murugan /* Check indirect done status */ 74831fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD, 74931fb632bSRamuthevar Vadivel Murugan CQSPI_REG_INDIRECTRD_DONE_MASK, 0); 75031fb632bSRamuthevar Vadivel Murugan if (ret) { 75131fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect read completion error (%i)\n", ret); 75231fb632bSRamuthevar Vadivel Murugan goto failrd; 75331fb632bSRamuthevar Vadivel Murugan } 75431fb632bSRamuthevar Vadivel Murugan 75531fb632bSRamuthevar Vadivel Murugan /* Disable interrupt */ 75631fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 75731fb632bSRamuthevar Vadivel Murugan 75831fb632bSRamuthevar Vadivel Murugan /* Clear indirect completion status */ 75931fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD); 76031fb632bSRamuthevar Vadivel Murugan 76131fb632bSRamuthevar Vadivel Murugan return 0; 76231fb632bSRamuthevar Vadivel Murugan 76331fb632bSRamuthevar Vadivel Murugan failrd: 76431fb632bSRamuthevar Vadivel Murugan /* Disable interrupt */ 76531fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 76631fb632bSRamuthevar Vadivel Murugan 76731fb632bSRamuthevar Vadivel Murugan /* Cancel the indirect read */ 76831fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 76931fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTRD); 77031fb632bSRamuthevar Vadivel Murugan return ret; 77131fb632bSRamuthevar Vadivel Murugan } 77231fb632bSRamuthevar Vadivel Murugan 77331fb632bSRamuthevar Vadivel Murugan static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata, 77431fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 77531fb632bSRamuthevar Vadivel Murugan { 77631fb632bSRamuthevar Vadivel Murugan unsigned int reg; 777f453f293SPratyush Yadav int ret; 77831fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 77931fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 780f453f293SPratyush Yadav u8 opcode; 781f453f293SPratyush Yadav 782f453f293SPratyush Yadav ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB, 783f453f293SPratyush Yadav f_pdata->dtr); 784f453f293SPratyush Yadav if (ret) 785f453f293SPratyush Yadav return ret; 786f453f293SPratyush Yadav 787f453f293SPratyush Yadav if (f_pdata->dtr) 788f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 789f453f293SPratyush Yadav else 790f453f293SPratyush Yadav opcode = op->cmd.opcode; 79131fb632bSRamuthevar Vadivel Murugan 79231fb632bSRamuthevar Vadivel Murugan /* Set opcode. */ 793f453f293SPratyush Yadav reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; 794f453f293SPratyush Yadav reg |= f_pdata->data_width << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; 795f453f293SPratyush Yadav reg |= f_pdata->addr_width << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; 79631fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_WR_INSTR); 79731fb632bSRamuthevar Vadivel Murugan reg = cqspi_calc_rdreg(f_pdata); 79831fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_RD_INSTR); 79931fb632bSRamuthevar Vadivel Murugan 800f453f293SPratyush Yadav if (f_pdata->dtr) { 801f453f293SPratyush Yadav /* 802f453f293SPratyush Yadav * Some flashes like the cypress Semper flash expect a 4-byte 803f453f293SPratyush Yadav * dummy address with the Read SR command in DTR mode, but this 804f453f293SPratyush Yadav * controller does not support sending address with the Read SR 805f453f293SPratyush Yadav * command. So, disable write completion polling on the 806f453f293SPratyush Yadav * controller's side. spi-nor will take care of polling the 807f453f293SPratyush Yadav * status register. 808f453f293SPratyush Yadav */ 809f453f293SPratyush Yadav reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL); 810f453f293SPratyush Yadav reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL; 811f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL); 812f453f293SPratyush Yadav } 813f453f293SPratyush Yadav 81431fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_SIZE); 81531fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 81631fb632bSRamuthevar Vadivel Murugan reg |= (op->addr.nbytes - 1); 81731fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_SIZE); 81831fb632bSRamuthevar Vadivel Murugan return 0; 81931fb632bSRamuthevar Vadivel Murugan } 82031fb632bSRamuthevar Vadivel Murugan 82131fb632bSRamuthevar Vadivel Murugan static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, 82231fb632bSRamuthevar Vadivel Murugan loff_t to_addr, const u8 *txbuf, 82331fb632bSRamuthevar Vadivel Murugan const size_t n_tx) 82431fb632bSRamuthevar Vadivel Murugan { 82531fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 82631fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 82731fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 82831fb632bSRamuthevar Vadivel Murugan unsigned int remaining = n_tx; 82931fb632bSRamuthevar Vadivel Murugan unsigned int write_bytes; 83031fb632bSRamuthevar Vadivel Murugan int ret; 83131fb632bSRamuthevar Vadivel Murugan 83231fb632bSRamuthevar Vadivel Murugan writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR); 83331fb632bSRamuthevar Vadivel Murugan writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES); 83431fb632bSRamuthevar Vadivel Murugan 83531fb632bSRamuthevar Vadivel Murugan /* Clear all interrupts. */ 83631fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 83731fb632bSRamuthevar Vadivel Murugan 83831fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK); 83931fb632bSRamuthevar Vadivel Murugan 84031fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 84131fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_START_MASK, 84231fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTWR); 84331fb632bSRamuthevar Vadivel Murugan /* 84431fb632bSRamuthevar Vadivel Murugan * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access 84531fb632bSRamuthevar Vadivel Murugan * Controller programming sequence, couple of cycles of 84631fb632bSRamuthevar Vadivel Murugan * QSPI_REF_CLK delay is required for the above bit to 84731fb632bSRamuthevar Vadivel Murugan * be internally synchronized by the QSPI module. Provide 5 84831fb632bSRamuthevar Vadivel Murugan * cycles of delay. 84931fb632bSRamuthevar Vadivel Murugan */ 85031fb632bSRamuthevar Vadivel Murugan if (cqspi->wr_delay) 85131fb632bSRamuthevar Vadivel Murugan ndelay(cqspi->wr_delay); 85231fb632bSRamuthevar Vadivel Murugan 85331fb632bSRamuthevar Vadivel Murugan while (remaining > 0) { 85431fb632bSRamuthevar Vadivel Murugan size_t write_words, mod_bytes; 85531fb632bSRamuthevar Vadivel Murugan 85631fb632bSRamuthevar Vadivel Murugan write_bytes = remaining; 85731fb632bSRamuthevar Vadivel Murugan write_words = write_bytes / 4; 85831fb632bSRamuthevar Vadivel Murugan mod_bytes = write_bytes % 4; 85931fb632bSRamuthevar Vadivel Murugan /* Write 4 bytes at a time then single bytes. */ 86031fb632bSRamuthevar Vadivel Murugan if (write_words) { 86131fb632bSRamuthevar Vadivel Murugan iowrite32_rep(cqspi->ahb_base, txbuf, write_words); 86231fb632bSRamuthevar Vadivel Murugan txbuf += (write_words * 4); 86331fb632bSRamuthevar Vadivel Murugan } 86431fb632bSRamuthevar Vadivel Murugan if (mod_bytes) { 86531fb632bSRamuthevar Vadivel Murugan unsigned int temp = 0xFFFFFFFF; 86631fb632bSRamuthevar Vadivel Murugan 86731fb632bSRamuthevar Vadivel Murugan memcpy(&temp, txbuf, mod_bytes); 86831fb632bSRamuthevar Vadivel Murugan iowrite32(temp, cqspi->ahb_base); 86931fb632bSRamuthevar Vadivel Murugan txbuf += mod_bytes; 87031fb632bSRamuthevar Vadivel Murugan } 87131fb632bSRamuthevar Vadivel Murugan 87231fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->transfer_complete, 87331fb632bSRamuthevar Vadivel Murugan msecs_to_jiffies(CQSPI_TIMEOUT_MS))) { 87431fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect write timeout\n"); 87531fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 87631fb632bSRamuthevar Vadivel Murugan goto failwr; 87731fb632bSRamuthevar Vadivel Murugan } 87831fb632bSRamuthevar Vadivel Murugan 87931fb632bSRamuthevar Vadivel Murugan remaining -= write_bytes; 88031fb632bSRamuthevar Vadivel Murugan 88131fb632bSRamuthevar Vadivel Murugan if (remaining > 0) 88231fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 88331fb632bSRamuthevar Vadivel Murugan } 88431fb632bSRamuthevar Vadivel Murugan 88531fb632bSRamuthevar Vadivel Murugan /* Check indirect done status */ 88631fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR, 88731fb632bSRamuthevar Vadivel Murugan CQSPI_REG_INDIRECTWR_DONE_MASK, 0); 88831fb632bSRamuthevar Vadivel Murugan if (ret) { 88931fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect write completion error (%i)\n", ret); 89031fb632bSRamuthevar Vadivel Murugan goto failwr; 89131fb632bSRamuthevar Vadivel Murugan } 89231fb632bSRamuthevar Vadivel Murugan 89331fb632bSRamuthevar Vadivel Murugan /* Disable interrupt. */ 89431fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 89531fb632bSRamuthevar Vadivel Murugan 89631fb632bSRamuthevar Vadivel Murugan /* Clear indirect completion status */ 89731fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR); 89831fb632bSRamuthevar Vadivel Murugan 89931fb632bSRamuthevar Vadivel Murugan cqspi_wait_idle(cqspi); 90031fb632bSRamuthevar Vadivel Murugan 90131fb632bSRamuthevar Vadivel Murugan return 0; 90231fb632bSRamuthevar Vadivel Murugan 90331fb632bSRamuthevar Vadivel Murugan failwr: 90431fb632bSRamuthevar Vadivel Murugan /* Disable interrupt. */ 90531fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 90631fb632bSRamuthevar Vadivel Murugan 90731fb632bSRamuthevar Vadivel Murugan /* Cancel the indirect write */ 90831fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 90931fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTWR); 91031fb632bSRamuthevar Vadivel Murugan return ret; 91131fb632bSRamuthevar Vadivel Murugan } 91231fb632bSRamuthevar Vadivel Murugan 91331fb632bSRamuthevar Vadivel Murugan static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata) 91431fb632bSRamuthevar Vadivel Murugan { 91531fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 91631fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 91731fb632bSRamuthevar Vadivel Murugan unsigned int chip_select = f_pdata->cs; 91831fb632bSRamuthevar Vadivel Murugan unsigned int reg; 91931fb632bSRamuthevar Vadivel Murugan 92031fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG); 92131fb632bSRamuthevar Vadivel Murugan if (cqspi->is_decoded_cs) { 92231fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CONFIG_DECODE_MASK; 92331fb632bSRamuthevar Vadivel Murugan } else { 92431fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; 92531fb632bSRamuthevar Vadivel Murugan 92631fb632bSRamuthevar Vadivel Murugan /* Convert CS if without decoder. 92731fb632bSRamuthevar Vadivel Murugan * CS0 to 4b'1110 92831fb632bSRamuthevar Vadivel Murugan * CS1 to 4b'1101 92931fb632bSRamuthevar Vadivel Murugan * CS2 to 4b'1011 93031fb632bSRamuthevar Vadivel Murugan * CS3 to 4b'0111 93131fb632bSRamuthevar Vadivel Murugan */ 93231fb632bSRamuthevar Vadivel Murugan chip_select = 0xF & ~(1 << chip_select); 93331fb632bSRamuthevar Vadivel Murugan } 93431fb632bSRamuthevar Vadivel Murugan 93531fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK 93631fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CONFIG_CHIPSELECT_LSB); 93731fb632bSRamuthevar Vadivel Murugan reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK) 93831fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CONFIG_CHIPSELECT_LSB; 93931fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG); 94031fb632bSRamuthevar Vadivel Murugan } 94131fb632bSRamuthevar Vadivel Murugan 94231fb632bSRamuthevar Vadivel Murugan static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz, 94331fb632bSRamuthevar Vadivel Murugan const unsigned int ns_val) 94431fb632bSRamuthevar Vadivel Murugan { 94531fb632bSRamuthevar Vadivel Murugan unsigned int ticks; 94631fb632bSRamuthevar Vadivel Murugan 94731fb632bSRamuthevar Vadivel Murugan ticks = ref_clk_hz / 1000; /* kHz */ 94831fb632bSRamuthevar Vadivel Murugan ticks = DIV_ROUND_UP(ticks * ns_val, 1000000); 94931fb632bSRamuthevar Vadivel Murugan 95031fb632bSRamuthevar Vadivel Murugan return ticks; 95131fb632bSRamuthevar Vadivel Murugan } 95231fb632bSRamuthevar Vadivel Murugan 95331fb632bSRamuthevar Vadivel Murugan static void cqspi_delay(struct cqspi_flash_pdata *f_pdata) 95431fb632bSRamuthevar Vadivel Murugan { 95531fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 95631fb632bSRamuthevar Vadivel Murugan void __iomem *iobase = cqspi->iobase; 95731fb632bSRamuthevar Vadivel Murugan const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 95831fb632bSRamuthevar Vadivel Murugan unsigned int tshsl, tchsh, tslch, tsd2d; 95931fb632bSRamuthevar Vadivel Murugan unsigned int reg; 96031fb632bSRamuthevar Vadivel Murugan unsigned int tsclk; 96131fb632bSRamuthevar Vadivel Murugan 96231fb632bSRamuthevar Vadivel Murugan /* calculate the number of ref ticks for one sclk tick */ 96331fb632bSRamuthevar Vadivel Murugan tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk); 96431fb632bSRamuthevar Vadivel Murugan 96531fb632bSRamuthevar Vadivel Murugan tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns); 96631fb632bSRamuthevar Vadivel Murugan /* this particular value must be at least one sclk */ 96731fb632bSRamuthevar Vadivel Murugan if (tshsl < tsclk) 96831fb632bSRamuthevar Vadivel Murugan tshsl = tsclk; 96931fb632bSRamuthevar Vadivel Murugan 97031fb632bSRamuthevar Vadivel Murugan tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns); 97131fb632bSRamuthevar Vadivel Murugan tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns); 97231fb632bSRamuthevar Vadivel Murugan tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns); 97331fb632bSRamuthevar Vadivel Murugan 97431fb632bSRamuthevar Vadivel Murugan reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK) 97531fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSHSL_LSB; 97631fb632bSRamuthevar Vadivel Murugan reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK) 97731fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TCHSH_LSB; 97831fb632bSRamuthevar Vadivel Murugan reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK) 97931fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSLCH_LSB; 98031fb632bSRamuthevar Vadivel Murugan reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK) 98131fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSD2D_LSB; 98231fb632bSRamuthevar Vadivel Murugan writel(reg, iobase + CQSPI_REG_DELAY); 98331fb632bSRamuthevar Vadivel Murugan } 98431fb632bSRamuthevar Vadivel Murugan 98531fb632bSRamuthevar Vadivel Murugan static void cqspi_config_baudrate_div(struct cqspi_st *cqspi) 98631fb632bSRamuthevar Vadivel Murugan { 98731fb632bSRamuthevar Vadivel Murugan const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 98831fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 98931fb632bSRamuthevar Vadivel Murugan u32 reg, div; 99031fb632bSRamuthevar Vadivel Murugan 99131fb632bSRamuthevar Vadivel Murugan /* Recalculate the baudrate divisor based on QSPI specification. */ 99231fb632bSRamuthevar Vadivel Murugan div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1; 99331fb632bSRamuthevar Vadivel Murugan 99431fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG); 99531fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); 99631fb632bSRamuthevar Vadivel Murugan reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB; 99731fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG); 99831fb632bSRamuthevar Vadivel Murugan } 99931fb632bSRamuthevar Vadivel Murugan 100031fb632bSRamuthevar Vadivel Murugan static void cqspi_readdata_capture(struct cqspi_st *cqspi, 100131fb632bSRamuthevar Vadivel Murugan const bool bypass, 100231fb632bSRamuthevar Vadivel Murugan const unsigned int delay) 100331fb632bSRamuthevar Vadivel Murugan { 100431fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 100531fb632bSRamuthevar Vadivel Murugan unsigned int reg; 100631fb632bSRamuthevar Vadivel Murugan 100731fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_READCAPTURE); 100831fb632bSRamuthevar Vadivel Murugan 100931fb632bSRamuthevar Vadivel Murugan if (bypass) 101031fb632bSRamuthevar Vadivel Murugan reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 101131fb632bSRamuthevar Vadivel Murugan else 101231fb632bSRamuthevar Vadivel Murugan reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 101331fb632bSRamuthevar Vadivel Murugan 101431fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK 101531fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_READCAPTURE_DELAY_LSB); 101631fb632bSRamuthevar Vadivel Murugan 101731fb632bSRamuthevar Vadivel Murugan reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK) 101831fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_READCAPTURE_DELAY_LSB; 101931fb632bSRamuthevar Vadivel Murugan 102031fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_READCAPTURE); 102131fb632bSRamuthevar Vadivel Murugan } 102231fb632bSRamuthevar Vadivel Murugan 102331fb632bSRamuthevar Vadivel Murugan static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable) 102431fb632bSRamuthevar Vadivel Murugan { 102531fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 102631fb632bSRamuthevar Vadivel Murugan unsigned int reg; 102731fb632bSRamuthevar Vadivel Murugan 102831fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG); 102931fb632bSRamuthevar Vadivel Murugan 103031fb632bSRamuthevar Vadivel Murugan if (enable) 103131fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CONFIG_ENABLE_MASK; 103231fb632bSRamuthevar Vadivel Murugan else 103331fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; 103431fb632bSRamuthevar Vadivel Murugan 103531fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG); 103631fb632bSRamuthevar Vadivel Murugan } 103731fb632bSRamuthevar Vadivel Murugan 103831fb632bSRamuthevar Vadivel Murugan static void cqspi_configure(struct cqspi_flash_pdata *f_pdata, 103931fb632bSRamuthevar Vadivel Murugan unsigned long sclk) 104031fb632bSRamuthevar Vadivel Murugan { 104131fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 104231fb632bSRamuthevar Vadivel Murugan int switch_cs = (cqspi->current_cs != f_pdata->cs); 104331fb632bSRamuthevar Vadivel Murugan int switch_ck = (cqspi->sclk != sclk); 104431fb632bSRamuthevar Vadivel Murugan 104531fb632bSRamuthevar Vadivel Murugan if (switch_cs || switch_ck) 104631fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 104731fb632bSRamuthevar Vadivel Murugan 104831fb632bSRamuthevar Vadivel Murugan /* Switch chip select. */ 104931fb632bSRamuthevar Vadivel Murugan if (switch_cs) { 105031fb632bSRamuthevar Vadivel Murugan cqspi->current_cs = f_pdata->cs; 105131fb632bSRamuthevar Vadivel Murugan cqspi_chipselect(f_pdata); 105231fb632bSRamuthevar Vadivel Murugan } 105331fb632bSRamuthevar Vadivel Murugan 105431fb632bSRamuthevar Vadivel Murugan /* Setup baudrate divisor and delays */ 105531fb632bSRamuthevar Vadivel Murugan if (switch_ck) { 105631fb632bSRamuthevar Vadivel Murugan cqspi->sclk = sclk; 105731fb632bSRamuthevar Vadivel Murugan cqspi_config_baudrate_div(cqspi); 105831fb632bSRamuthevar Vadivel Murugan cqspi_delay(f_pdata); 105931fb632bSRamuthevar Vadivel Murugan cqspi_readdata_capture(cqspi, !cqspi->rclk_en, 106031fb632bSRamuthevar Vadivel Murugan f_pdata->read_delay); 106131fb632bSRamuthevar Vadivel Murugan } 106231fb632bSRamuthevar Vadivel Murugan 106331fb632bSRamuthevar Vadivel Murugan if (switch_cs || switch_ck) 106431fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1); 106531fb632bSRamuthevar Vadivel Murugan } 106631fb632bSRamuthevar Vadivel Murugan 106731fb632bSRamuthevar Vadivel Murugan static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata, 106831fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 106931fb632bSRamuthevar Vadivel Murugan { 107031fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 107131fb632bSRamuthevar Vadivel Murugan loff_t to = op->addr.val; 107231fb632bSRamuthevar Vadivel Murugan size_t len = op->data.nbytes; 107331fb632bSRamuthevar Vadivel Murugan const u_char *buf = op->data.buf.out; 107431fb632bSRamuthevar Vadivel Murugan int ret; 107531fb632bSRamuthevar Vadivel Murugan 107631fb632bSRamuthevar Vadivel Murugan ret = cqspi_set_protocol(f_pdata, op); 107731fb632bSRamuthevar Vadivel Murugan if (ret) 107831fb632bSRamuthevar Vadivel Murugan return ret; 107931fb632bSRamuthevar Vadivel Murugan 108031fb632bSRamuthevar Vadivel Murugan ret = cqspi_write_setup(f_pdata, op); 108131fb632bSRamuthevar Vadivel Murugan if (ret) 108231fb632bSRamuthevar Vadivel Murugan return ret; 108331fb632bSRamuthevar Vadivel Murugan 1084f453f293SPratyush Yadav /* 1085f453f293SPratyush Yadav * Some flashes like the Cypress Semper flash expect a dummy 4-byte 1086f453f293SPratyush Yadav * address (all 0s) with the read status register command in DTR mode. 1087f453f293SPratyush Yadav * But this controller does not support sending dummy address bytes to 1088f453f293SPratyush Yadav * the flash when it is polling the write completion register in DTR 1089f453f293SPratyush Yadav * mode. So, we can not use direct mode when in DTR mode for writing 1090f453f293SPratyush Yadav * data. 1091f453f293SPratyush Yadav */ 1092f453f293SPratyush Yadav if (!f_pdata->dtr && cqspi->use_direct_mode && 1093f453f293SPratyush Yadav ((to + len) <= cqspi->ahb_size)) { 109431fb632bSRamuthevar Vadivel Murugan memcpy_toio(cqspi->ahb_base + to, buf, len); 109531fb632bSRamuthevar Vadivel Murugan return cqspi_wait_idle(cqspi); 109631fb632bSRamuthevar Vadivel Murugan } 109731fb632bSRamuthevar Vadivel Murugan 109831fb632bSRamuthevar Vadivel Murugan return cqspi_indirect_write_execute(f_pdata, to, buf, len); 109931fb632bSRamuthevar Vadivel Murugan } 110031fb632bSRamuthevar Vadivel Murugan 110131fb632bSRamuthevar Vadivel Murugan static void cqspi_rx_dma_callback(void *param) 110231fb632bSRamuthevar Vadivel Murugan { 110331fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = param; 110431fb632bSRamuthevar Vadivel Murugan 110531fb632bSRamuthevar Vadivel Murugan complete(&cqspi->rx_dma_complete); 110631fb632bSRamuthevar Vadivel Murugan } 110731fb632bSRamuthevar Vadivel Murugan 110831fb632bSRamuthevar Vadivel Murugan static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata, 110931fb632bSRamuthevar Vadivel Murugan u_char *buf, loff_t from, size_t len) 111031fb632bSRamuthevar Vadivel Murugan { 111131fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 111231fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 111331fb632bSRamuthevar Vadivel Murugan enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; 111431fb632bSRamuthevar Vadivel Murugan dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from; 111531fb632bSRamuthevar Vadivel Murugan int ret = 0; 111631fb632bSRamuthevar Vadivel Murugan struct dma_async_tx_descriptor *tx; 111731fb632bSRamuthevar Vadivel Murugan dma_cookie_t cookie; 111831fb632bSRamuthevar Vadivel Murugan dma_addr_t dma_dst; 111983048015SVignesh Raghavendra struct device *ddev; 112031fb632bSRamuthevar Vadivel Murugan 112131fb632bSRamuthevar Vadivel Murugan if (!cqspi->rx_chan || !virt_addr_valid(buf)) { 112231fb632bSRamuthevar Vadivel Murugan memcpy_fromio(buf, cqspi->ahb_base + from, len); 112331fb632bSRamuthevar Vadivel Murugan return 0; 112431fb632bSRamuthevar Vadivel Murugan } 112531fb632bSRamuthevar Vadivel Murugan 112683048015SVignesh Raghavendra ddev = cqspi->rx_chan->device->dev; 112783048015SVignesh Raghavendra dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE); 112883048015SVignesh Raghavendra if (dma_mapping_error(ddev, dma_dst)) { 112931fb632bSRamuthevar Vadivel Murugan dev_err(dev, "dma mapping failed\n"); 113031fb632bSRamuthevar Vadivel Murugan return -ENOMEM; 113131fb632bSRamuthevar Vadivel Murugan } 113231fb632bSRamuthevar Vadivel Murugan tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src, 113331fb632bSRamuthevar Vadivel Murugan len, flags); 113431fb632bSRamuthevar Vadivel Murugan if (!tx) { 113531fb632bSRamuthevar Vadivel Murugan dev_err(dev, "device_prep_dma_memcpy error\n"); 113631fb632bSRamuthevar Vadivel Murugan ret = -EIO; 113731fb632bSRamuthevar Vadivel Murugan goto err_unmap; 113831fb632bSRamuthevar Vadivel Murugan } 113931fb632bSRamuthevar Vadivel Murugan 114031fb632bSRamuthevar Vadivel Murugan tx->callback = cqspi_rx_dma_callback; 114131fb632bSRamuthevar Vadivel Murugan tx->callback_param = cqspi; 114231fb632bSRamuthevar Vadivel Murugan cookie = tx->tx_submit(tx); 114331fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->rx_dma_complete); 114431fb632bSRamuthevar Vadivel Murugan 114531fb632bSRamuthevar Vadivel Murugan ret = dma_submit_error(cookie); 114631fb632bSRamuthevar Vadivel Murugan if (ret) { 114731fb632bSRamuthevar Vadivel Murugan dev_err(dev, "dma_submit_error %d\n", cookie); 114831fb632bSRamuthevar Vadivel Murugan ret = -EIO; 114931fb632bSRamuthevar Vadivel Murugan goto err_unmap; 115031fb632bSRamuthevar Vadivel Murugan } 115131fb632bSRamuthevar Vadivel Murugan 115231fb632bSRamuthevar Vadivel Murugan dma_async_issue_pending(cqspi->rx_chan); 115331fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->rx_dma_complete, 11542ef0170eSPratyush Yadav msecs_to_jiffies(max_t(size_t, len, 500)))) { 115531fb632bSRamuthevar Vadivel Murugan dmaengine_terminate_sync(cqspi->rx_chan); 115631fb632bSRamuthevar Vadivel Murugan dev_err(dev, "DMA wait_for_completion_timeout\n"); 115731fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 115831fb632bSRamuthevar Vadivel Murugan goto err_unmap; 115931fb632bSRamuthevar Vadivel Murugan } 116031fb632bSRamuthevar Vadivel Murugan 116131fb632bSRamuthevar Vadivel Murugan err_unmap: 116283048015SVignesh Raghavendra dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE); 116331fb632bSRamuthevar Vadivel Murugan 116431fb632bSRamuthevar Vadivel Murugan return ret; 116531fb632bSRamuthevar Vadivel Murugan } 116631fb632bSRamuthevar Vadivel Murugan 116731fb632bSRamuthevar Vadivel Murugan static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata, 116831fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 116931fb632bSRamuthevar Vadivel Murugan { 117031fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 117131fb632bSRamuthevar Vadivel Murugan loff_t from = op->addr.val; 117231fb632bSRamuthevar Vadivel Murugan size_t len = op->data.nbytes; 117331fb632bSRamuthevar Vadivel Murugan u_char *buf = op->data.buf.in; 117431fb632bSRamuthevar Vadivel Murugan int ret; 117531fb632bSRamuthevar Vadivel Murugan 117631fb632bSRamuthevar Vadivel Murugan ret = cqspi_set_protocol(f_pdata, op); 117731fb632bSRamuthevar Vadivel Murugan if (ret) 117831fb632bSRamuthevar Vadivel Murugan return ret; 117931fb632bSRamuthevar Vadivel Murugan 118031fb632bSRamuthevar Vadivel Murugan ret = cqspi_read_setup(f_pdata, op); 118131fb632bSRamuthevar Vadivel Murugan if (ret) 118231fb632bSRamuthevar Vadivel Murugan return ret; 118331fb632bSRamuthevar Vadivel Murugan 118431fb632bSRamuthevar Vadivel Murugan if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) 118531fb632bSRamuthevar Vadivel Murugan return cqspi_direct_read_execute(f_pdata, buf, from, len); 118631fb632bSRamuthevar Vadivel Murugan 118731fb632bSRamuthevar Vadivel Murugan return cqspi_indirect_read_execute(f_pdata, buf, from, len); 118831fb632bSRamuthevar Vadivel Murugan } 118931fb632bSRamuthevar Vadivel Murugan 119031fb632bSRamuthevar Vadivel Murugan static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op) 119131fb632bSRamuthevar Vadivel Murugan { 119231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); 119331fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata; 119431fb632bSRamuthevar Vadivel Murugan 119531fb632bSRamuthevar Vadivel Murugan f_pdata = &cqspi->f_pdata[mem->spi->chip_select]; 119631fb632bSRamuthevar Vadivel Murugan cqspi_configure(f_pdata, mem->spi->max_speed_hz); 119731fb632bSRamuthevar Vadivel Murugan 119831fb632bSRamuthevar Vadivel Murugan if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { 119931fb632bSRamuthevar Vadivel Murugan if (!op->addr.nbytes) 120031fb632bSRamuthevar Vadivel Murugan return cqspi_command_read(f_pdata, op); 120131fb632bSRamuthevar Vadivel Murugan 120231fb632bSRamuthevar Vadivel Murugan return cqspi_read(f_pdata, op); 120331fb632bSRamuthevar Vadivel Murugan } 120431fb632bSRamuthevar Vadivel Murugan 120531fb632bSRamuthevar Vadivel Murugan if (!op->addr.nbytes || !op->data.buf.out) 120631fb632bSRamuthevar Vadivel Murugan return cqspi_command_write(f_pdata, op); 120731fb632bSRamuthevar Vadivel Murugan 120831fb632bSRamuthevar Vadivel Murugan return cqspi_write(f_pdata, op); 120931fb632bSRamuthevar Vadivel Murugan } 121031fb632bSRamuthevar Vadivel Murugan 121131fb632bSRamuthevar Vadivel Murugan static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) 121231fb632bSRamuthevar Vadivel Murugan { 121331fb632bSRamuthevar Vadivel Murugan int ret; 121431fb632bSRamuthevar Vadivel Murugan 121531fb632bSRamuthevar Vadivel Murugan ret = cqspi_mem_process(mem, op); 121631fb632bSRamuthevar Vadivel Murugan if (ret) 121731fb632bSRamuthevar Vadivel Murugan dev_err(&mem->spi->dev, "operation failed with %d\n", ret); 121831fb632bSRamuthevar Vadivel Murugan 121931fb632bSRamuthevar Vadivel Murugan return ret; 122031fb632bSRamuthevar Vadivel Murugan } 122131fb632bSRamuthevar Vadivel Murugan 1222a273596bSPratyush Yadav static bool cqspi_supports_mem_op(struct spi_mem *mem, 1223a273596bSPratyush Yadav const struct spi_mem_op *op) 1224a273596bSPratyush Yadav { 1225f453f293SPratyush Yadav bool all_true, all_false; 1226f453f293SPratyush Yadav 1227f453f293SPratyush Yadav all_true = op->cmd.dtr && op->addr.dtr && op->dummy.dtr && 1228f453f293SPratyush Yadav op->data.dtr; 1229f453f293SPratyush Yadav all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && 1230f453f293SPratyush Yadav !op->data.dtr; 1231f453f293SPratyush Yadav 1232f453f293SPratyush Yadav /* Mixed DTR modes not supported. */ 1233f453f293SPratyush Yadav if (!(all_true || all_false)) 1234f453f293SPratyush Yadav return false; 1235f453f293SPratyush Yadav 1236d2275139SPratyush Yadav if (all_true) 1237d2275139SPratyush Yadav return spi_mem_dtr_supports_op(mem, op); 1238d2275139SPratyush Yadav else 1239d2275139SPratyush Yadav return spi_mem_default_supports_op(mem, op); 1240a273596bSPratyush Yadav } 1241a273596bSPratyush Yadav 124231fb632bSRamuthevar Vadivel Murugan static int cqspi_of_get_flash_pdata(struct platform_device *pdev, 124331fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata, 124431fb632bSRamuthevar Vadivel Murugan struct device_node *np) 124531fb632bSRamuthevar Vadivel Murugan { 124631fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) { 124731fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine read-delay\n"); 124831fb632bSRamuthevar Vadivel Murugan return -ENXIO; 124931fb632bSRamuthevar Vadivel Murugan } 125031fb632bSRamuthevar Vadivel Murugan 125131fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) { 125231fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tshsl-ns\n"); 125331fb632bSRamuthevar Vadivel Murugan return -ENXIO; 125431fb632bSRamuthevar Vadivel Murugan } 125531fb632bSRamuthevar Vadivel Murugan 125631fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) { 125731fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n"); 125831fb632bSRamuthevar Vadivel Murugan return -ENXIO; 125931fb632bSRamuthevar Vadivel Murugan } 126031fb632bSRamuthevar Vadivel Murugan 126131fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) { 126231fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tchsh-ns\n"); 126331fb632bSRamuthevar Vadivel Murugan return -ENXIO; 126431fb632bSRamuthevar Vadivel Murugan } 126531fb632bSRamuthevar Vadivel Murugan 126631fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) { 126731fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tslch-ns\n"); 126831fb632bSRamuthevar Vadivel Murugan return -ENXIO; 126931fb632bSRamuthevar Vadivel Murugan } 127031fb632bSRamuthevar Vadivel Murugan 127131fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) { 127231fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n"); 127331fb632bSRamuthevar Vadivel Murugan return -ENXIO; 127431fb632bSRamuthevar Vadivel Murugan } 127531fb632bSRamuthevar Vadivel Murugan 127631fb632bSRamuthevar Vadivel Murugan return 0; 127731fb632bSRamuthevar Vadivel Murugan } 127831fb632bSRamuthevar Vadivel Murugan 127931fb632bSRamuthevar Vadivel Murugan static int cqspi_of_get_pdata(struct cqspi_st *cqspi) 128031fb632bSRamuthevar Vadivel Murugan { 128131fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 128231fb632bSRamuthevar Vadivel Murugan struct device_node *np = dev->of_node; 128331fb632bSRamuthevar Vadivel Murugan 128431fb632bSRamuthevar Vadivel Murugan cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); 128531fb632bSRamuthevar Vadivel Murugan 128631fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { 128731fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine fifo-depth\n"); 128831fb632bSRamuthevar Vadivel Murugan return -ENXIO; 128931fb632bSRamuthevar Vadivel Murugan } 129031fb632bSRamuthevar Vadivel Murugan 129131fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) { 129231fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine fifo-width\n"); 129331fb632bSRamuthevar Vadivel Murugan return -ENXIO; 129431fb632bSRamuthevar Vadivel Murugan } 129531fb632bSRamuthevar Vadivel Murugan 129631fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,trigger-address", 129731fb632bSRamuthevar Vadivel Murugan &cqspi->trigger_address)) { 129831fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine trigger-address\n"); 129931fb632bSRamuthevar Vadivel Murugan return -ENXIO; 130031fb632bSRamuthevar Vadivel Murugan } 130131fb632bSRamuthevar Vadivel Murugan 1302b436fb7dSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) 1303b436fb7dSRamuthevar Vadivel Murugan cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT; 1304b436fb7dSRamuthevar Vadivel Murugan 130531fb632bSRamuthevar Vadivel Murugan cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); 130631fb632bSRamuthevar Vadivel Murugan 130731fb632bSRamuthevar Vadivel Murugan return 0; 130831fb632bSRamuthevar Vadivel Murugan } 130931fb632bSRamuthevar Vadivel Murugan 131031fb632bSRamuthevar Vadivel Murugan static void cqspi_controller_init(struct cqspi_st *cqspi) 131131fb632bSRamuthevar Vadivel Murugan { 131231fb632bSRamuthevar Vadivel Murugan u32 reg; 131331fb632bSRamuthevar Vadivel Murugan 131431fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 131531fb632bSRamuthevar Vadivel Murugan 131631fb632bSRamuthevar Vadivel Murugan /* Configure the remap address register, no remap */ 131731fb632bSRamuthevar Vadivel Murugan writel(0, cqspi->iobase + CQSPI_REG_REMAP); 131831fb632bSRamuthevar Vadivel Murugan 131931fb632bSRamuthevar Vadivel Murugan /* Disable all interrupts. */ 132031fb632bSRamuthevar Vadivel Murugan writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); 132131fb632bSRamuthevar Vadivel Murugan 132231fb632bSRamuthevar Vadivel Murugan /* Configure the SRAM split to 1:1 . */ 132331fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); 132431fb632bSRamuthevar Vadivel Murugan 132531fb632bSRamuthevar Vadivel Murugan /* Load indirect trigger address. */ 132631fb632bSRamuthevar Vadivel Murugan writel(cqspi->trigger_address, 132731fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); 132831fb632bSRamuthevar Vadivel Murugan 132931fb632bSRamuthevar Vadivel Murugan /* Program read watermark -- 1/2 of the FIFO. */ 133031fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth * cqspi->fifo_width / 2, 133131fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); 133231fb632bSRamuthevar Vadivel Murugan /* Program write watermark -- 1/8 of the FIFO. */ 133331fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth * cqspi->fifo_width / 8, 133431fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); 133531fb632bSRamuthevar Vadivel Murugan 1336ad2775dcSRamuthevar Vadivel Murugan /* Disable direct access controller */ 1337ad2775dcSRamuthevar Vadivel Murugan if (!cqspi->use_direct_mode) { 133831fb632bSRamuthevar Vadivel Murugan reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 1339ad2775dcSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL; 134031fb632bSRamuthevar Vadivel Murugan writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 1341ad2775dcSRamuthevar Vadivel Murugan } 134231fb632bSRamuthevar Vadivel Murugan 134331fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1); 134431fb632bSRamuthevar Vadivel Murugan } 134531fb632bSRamuthevar Vadivel Murugan 134631fb632bSRamuthevar Vadivel Murugan static int cqspi_request_mmap_dma(struct cqspi_st *cqspi) 134731fb632bSRamuthevar Vadivel Murugan { 134831fb632bSRamuthevar Vadivel Murugan dma_cap_mask_t mask; 134931fb632bSRamuthevar Vadivel Murugan 135031fb632bSRamuthevar Vadivel Murugan dma_cap_zero(mask); 135131fb632bSRamuthevar Vadivel Murugan dma_cap_set(DMA_MEMCPY, mask); 135231fb632bSRamuthevar Vadivel Murugan 135331fb632bSRamuthevar Vadivel Murugan cqspi->rx_chan = dma_request_chan_by_mask(&mask); 135431fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->rx_chan)) { 135531fb632bSRamuthevar Vadivel Murugan int ret = PTR_ERR(cqspi->rx_chan); 135631fb632bSRamuthevar Vadivel Murugan cqspi->rx_chan = NULL; 1357436a5c20SKrzysztof Kozlowski return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n"); 135831fb632bSRamuthevar Vadivel Murugan } 135931fb632bSRamuthevar Vadivel Murugan init_completion(&cqspi->rx_dma_complete); 136031fb632bSRamuthevar Vadivel Murugan 136131fb632bSRamuthevar Vadivel Murugan return 0; 136231fb632bSRamuthevar Vadivel Murugan } 136331fb632bSRamuthevar Vadivel Murugan 13642ea370a9SVignesh Raghavendra static const char *cqspi_get_name(struct spi_mem *mem) 13652ea370a9SVignesh Raghavendra { 13662ea370a9SVignesh Raghavendra struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); 13672ea370a9SVignesh Raghavendra struct device *dev = &cqspi->pdev->dev; 13682ea370a9SVignesh Raghavendra 13692ea370a9SVignesh Raghavendra return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select); 13702ea370a9SVignesh Raghavendra } 13712ea370a9SVignesh Raghavendra 137231fb632bSRamuthevar Vadivel Murugan static const struct spi_controller_mem_ops cqspi_mem_ops = { 137331fb632bSRamuthevar Vadivel Murugan .exec_op = cqspi_exec_mem_op, 13742ea370a9SVignesh Raghavendra .get_name = cqspi_get_name, 1375a273596bSPratyush Yadav .supports_op = cqspi_supports_mem_op, 137631fb632bSRamuthevar Vadivel Murugan }; 137731fb632bSRamuthevar Vadivel Murugan 137831fb632bSRamuthevar Vadivel Murugan static int cqspi_setup_flash(struct cqspi_st *cqspi) 137931fb632bSRamuthevar Vadivel Murugan { 138031fb632bSRamuthevar Vadivel Murugan struct platform_device *pdev = cqspi->pdev; 138131fb632bSRamuthevar Vadivel Murugan struct device *dev = &pdev->dev; 138231fb632bSRamuthevar Vadivel Murugan struct device_node *np = dev->of_node; 138331fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata; 138431fb632bSRamuthevar Vadivel Murugan unsigned int cs; 138531fb632bSRamuthevar Vadivel Murugan int ret; 138631fb632bSRamuthevar Vadivel Murugan 138731fb632bSRamuthevar Vadivel Murugan /* Get flash device data */ 138831fb632bSRamuthevar Vadivel Murugan for_each_available_child_of_node(dev->of_node, np) { 138931fb632bSRamuthevar Vadivel Murugan ret = of_property_read_u32(np, "reg", &cs); 139031fb632bSRamuthevar Vadivel Murugan if (ret) { 139131fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Couldn't determine chip select.\n"); 1392*87d62d8fSJunlin Yang of_node_put(np); 139331fb632bSRamuthevar Vadivel Murugan return ret; 139431fb632bSRamuthevar Vadivel Murugan } 139531fb632bSRamuthevar Vadivel Murugan 139631fb632bSRamuthevar Vadivel Murugan if (cs >= CQSPI_MAX_CHIPSELECT) { 139731fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Chip select %d out of range.\n", cs); 1398*87d62d8fSJunlin Yang of_node_put(np); 139931fb632bSRamuthevar Vadivel Murugan return -EINVAL; 140031fb632bSRamuthevar Vadivel Murugan } 140131fb632bSRamuthevar Vadivel Murugan 140231fb632bSRamuthevar Vadivel Murugan f_pdata = &cqspi->f_pdata[cs]; 140331fb632bSRamuthevar Vadivel Murugan f_pdata->cqspi = cqspi; 140431fb632bSRamuthevar Vadivel Murugan f_pdata->cs = cs; 140531fb632bSRamuthevar Vadivel Murugan 140631fb632bSRamuthevar Vadivel Murugan ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np); 1407*87d62d8fSJunlin Yang if (ret) { 1408*87d62d8fSJunlin Yang of_node_put(np); 140931fb632bSRamuthevar Vadivel Murugan return ret; 141031fb632bSRamuthevar Vadivel Murugan } 1411*87d62d8fSJunlin Yang } 141231fb632bSRamuthevar Vadivel Murugan 141331fb632bSRamuthevar Vadivel Murugan return 0; 141431fb632bSRamuthevar Vadivel Murugan } 141531fb632bSRamuthevar Vadivel Murugan 141631fb632bSRamuthevar Vadivel Murugan static int cqspi_probe(struct platform_device *pdev) 141731fb632bSRamuthevar Vadivel Murugan { 141831fb632bSRamuthevar Vadivel Murugan const struct cqspi_driver_platdata *ddata; 141931fb632bSRamuthevar Vadivel Murugan struct reset_control *rstc, *rstc_ocp; 142031fb632bSRamuthevar Vadivel Murugan struct device *dev = &pdev->dev; 142131fb632bSRamuthevar Vadivel Murugan struct spi_master *master; 142231fb632bSRamuthevar Vadivel Murugan struct resource *res_ahb; 142331fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi; 142431fb632bSRamuthevar Vadivel Murugan struct resource *res; 142531fb632bSRamuthevar Vadivel Murugan int ret; 142631fb632bSRamuthevar Vadivel Murugan int irq; 142731fb632bSRamuthevar Vadivel Murugan 142831fb632bSRamuthevar Vadivel Murugan master = spi_alloc_master(&pdev->dev, sizeof(*cqspi)); 142931fb632bSRamuthevar Vadivel Murugan if (!master) { 143031fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "spi_alloc_master failed\n"); 143131fb632bSRamuthevar Vadivel Murugan return -ENOMEM; 143231fb632bSRamuthevar Vadivel Murugan } 143331fb632bSRamuthevar Vadivel Murugan master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; 143431fb632bSRamuthevar Vadivel Murugan master->mem_ops = &cqspi_mem_ops; 143531fb632bSRamuthevar Vadivel Murugan master->dev.of_node = pdev->dev.of_node; 143631fb632bSRamuthevar Vadivel Murugan 143731fb632bSRamuthevar Vadivel Murugan cqspi = spi_master_get_devdata(master); 143831fb632bSRamuthevar Vadivel Murugan 143931fb632bSRamuthevar Vadivel Murugan cqspi->pdev = pdev; 144031fb632bSRamuthevar Vadivel Murugan 144131fb632bSRamuthevar Vadivel Murugan /* Obtain configuration from OF. */ 144231fb632bSRamuthevar Vadivel Murugan ret = cqspi_of_get_pdata(cqspi); 144331fb632bSRamuthevar Vadivel Murugan if (ret) { 144431fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get mandatory OF data.\n"); 144531fb632bSRamuthevar Vadivel Murugan ret = -ENODEV; 144631fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 144731fb632bSRamuthevar Vadivel Murugan } 144831fb632bSRamuthevar Vadivel Murugan 144931fb632bSRamuthevar Vadivel Murugan /* Obtain QSPI clock. */ 145031fb632bSRamuthevar Vadivel Murugan cqspi->clk = devm_clk_get(dev, NULL); 145131fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->clk)) { 145231fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot claim QSPI clock.\n"); 145331fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->clk); 145431fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 145531fb632bSRamuthevar Vadivel Murugan } 145631fb632bSRamuthevar Vadivel Murugan 145731fb632bSRamuthevar Vadivel Murugan /* Obtain and remap controller address. */ 145831fb632bSRamuthevar Vadivel Murugan res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 145931fb632bSRamuthevar Vadivel Murugan cqspi->iobase = devm_ioremap_resource(dev, res); 146031fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->iobase)) { 146131fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot remap controller address.\n"); 146231fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->iobase); 146331fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 146431fb632bSRamuthevar Vadivel Murugan } 146531fb632bSRamuthevar Vadivel Murugan 146631fb632bSRamuthevar Vadivel Murugan /* Obtain and remap AHB address. */ 146731fb632bSRamuthevar Vadivel Murugan res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1); 146831fb632bSRamuthevar Vadivel Murugan cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb); 146931fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->ahb_base)) { 147031fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot remap AHB address.\n"); 147131fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->ahb_base); 147231fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 147331fb632bSRamuthevar Vadivel Murugan } 147431fb632bSRamuthevar Vadivel Murugan cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start; 147531fb632bSRamuthevar Vadivel Murugan cqspi->ahb_size = resource_size(res_ahb); 147631fb632bSRamuthevar Vadivel Murugan 147731fb632bSRamuthevar Vadivel Murugan init_completion(&cqspi->transfer_complete); 147831fb632bSRamuthevar Vadivel Murugan 147931fb632bSRamuthevar Vadivel Murugan /* Obtain IRQ line. */ 148031fb632bSRamuthevar Vadivel Murugan irq = platform_get_irq(pdev, 0); 148131fb632bSRamuthevar Vadivel Murugan if (irq < 0) { 148231fb632bSRamuthevar Vadivel Murugan ret = -ENXIO; 148331fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 148431fb632bSRamuthevar Vadivel Murugan } 148531fb632bSRamuthevar Vadivel Murugan 148631fb632bSRamuthevar Vadivel Murugan pm_runtime_enable(dev); 148731fb632bSRamuthevar Vadivel Murugan ret = pm_runtime_get_sync(dev); 148831fb632bSRamuthevar Vadivel Murugan if (ret < 0) { 148931fb632bSRamuthevar Vadivel Murugan pm_runtime_put_noidle(dev); 149031fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 149131fb632bSRamuthevar Vadivel Murugan } 149231fb632bSRamuthevar Vadivel Murugan 149331fb632bSRamuthevar Vadivel Murugan ret = clk_prepare_enable(cqspi->clk); 149431fb632bSRamuthevar Vadivel Murugan if (ret) { 149531fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot enable QSPI clock.\n"); 149631fb632bSRamuthevar Vadivel Murugan goto probe_clk_failed; 149731fb632bSRamuthevar Vadivel Murugan } 149831fb632bSRamuthevar Vadivel Murugan 149931fb632bSRamuthevar Vadivel Murugan /* Obtain QSPI reset control */ 150031fb632bSRamuthevar Vadivel Murugan rstc = devm_reset_control_get_optional_exclusive(dev, "qspi"); 150131fb632bSRamuthevar Vadivel Murugan if (IS_ERR(rstc)) { 1502ac9978fcSZhihao Cheng ret = PTR_ERR(rstc); 150331fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get QSPI reset.\n"); 150431fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 150531fb632bSRamuthevar Vadivel Murugan } 150631fb632bSRamuthevar Vadivel Murugan 150731fb632bSRamuthevar Vadivel Murugan rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); 150831fb632bSRamuthevar Vadivel Murugan if (IS_ERR(rstc_ocp)) { 1509ac9978fcSZhihao Cheng ret = PTR_ERR(rstc_ocp); 151031fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get QSPI OCP reset.\n"); 151131fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 151231fb632bSRamuthevar Vadivel Murugan } 151331fb632bSRamuthevar Vadivel Murugan 151431fb632bSRamuthevar Vadivel Murugan reset_control_assert(rstc); 151531fb632bSRamuthevar Vadivel Murugan reset_control_deassert(rstc); 151631fb632bSRamuthevar Vadivel Murugan 151731fb632bSRamuthevar Vadivel Murugan reset_control_assert(rstc_ocp); 151831fb632bSRamuthevar Vadivel Murugan reset_control_deassert(rstc_ocp); 151931fb632bSRamuthevar Vadivel Murugan 152031fb632bSRamuthevar Vadivel Murugan cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); 15213a5c09c8SPratyush Yadav master->max_speed_hz = cqspi->master_ref_clk_hz; 152231fb632bSRamuthevar Vadivel Murugan ddata = of_device_get_match_data(dev); 152331fb632bSRamuthevar Vadivel Murugan if (ddata) { 152431fb632bSRamuthevar Vadivel Murugan if (ddata->quirks & CQSPI_NEEDS_WR_DELAY) 1525f453f293SPratyush Yadav cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, 152631fb632bSRamuthevar Vadivel Murugan cqspi->master_ref_clk_hz); 152731fb632bSRamuthevar Vadivel Murugan if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL) 1528f453f293SPratyush Yadav master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; 152931fb632bSRamuthevar Vadivel Murugan if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) 153031fb632bSRamuthevar Vadivel Murugan cqspi->use_direct_mode = true; 153131fb632bSRamuthevar Vadivel Murugan } 153231fb632bSRamuthevar Vadivel Murugan 153331fb632bSRamuthevar Vadivel Murugan ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0, 153431fb632bSRamuthevar Vadivel Murugan pdev->name, cqspi); 153531fb632bSRamuthevar Vadivel Murugan if (ret) { 153631fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot request IRQ.\n"); 153731fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 153831fb632bSRamuthevar Vadivel Murugan } 153931fb632bSRamuthevar Vadivel Murugan 154031fb632bSRamuthevar Vadivel Murugan cqspi_wait_idle(cqspi); 154131fb632bSRamuthevar Vadivel Murugan cqspi_controller_init(cqspi); 154231fb632bSRamuthevar Vadivel Murugan cqspi->current_cs = -1; 154331fb632bSRamuthevar Vadivel Murugan cqspi->sclk = 0; 154431fb632bSRamuthevar Vadivel Murugan 1545b436fb7dSRamuthevar Vadivel Murugan master->num_chipselect = cqspi->num_chipselect; 1546b436fb7dSRamuthevar Vadivel Murugan 154731fb632bSRamuthevar Vadivel Murugan ret = cqspi_setup_flash(cqspi); 154831fb632bSRamuthevar Vadivel Murugan if (ret) { 154931fb632bSRamuthevar Vadivel Murugan dev_err(dev, "failed to setup flash parameters %d\n", ret); 155031fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 155131fb632bSRamuthevar Vadivel Murugan } 155231fb632bSRamuthevar Vadivel Murugan 155331fb632bSRamuthevar Vadivel Murugan if (cqspi->use_direct_mode) { 155431fb632bSRamuthevar Vadivel Murugan ret = cqspi_request_mmap_dma(cqspi); 155531fb632bSRamuthevar Vadivel Murugan if (ret == -EPROBE_DEFER) 155631fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 155731fb632bSRamuthevar Vadivel Murugan } 155831fb632bSRamuthevar Vadivel Murugan 155931fb632bSRamuthevar Vadivel Murugan ret = devm_spi_register_master(dev, master); 156031fb632bSRamuthevar Vadivel Murugan if (ret) { 156131fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret); 156231fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 156331fb632bSRamuthevar Vadivel Murugan } 156431fb632bSRamuthevar Vadivel Murugan 156531fb632bSRamuthevar Vadivel Murugan return 0; 156631fb632bSRamuthevar Vadivel Murugan probe_setup_failed: 156731fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 156831fb632bSRamuthevar Vadivel Murugan probe_reset_failed: 156931fb632bSRamuthevar Vadivel Murugan clk_disable_unprepare(cqspi->clk); 157031fb632bSRamuthevar Vadivel Murugan probe_clk_failed: 157131fb632bSRamuthevar Vadivel Murugan pm_runtime_put_sync(dev); 157231fb632bSRamuthevar Vadivel Murugan pm_runtime_disable(dev); 157331fb632bSRamuthevar Vadivel Murugan probe_master_put: 157431fb632bSRamuthevar Vadivel Murugan spi_master_put(master); 157531fb632bSRamuthevar Vadivel Murugan return ret; 157631fb632bSRamuthevar Vadivel Murugan } 157731fb632bSRamuthevar Vadivel Murugan 157831fb632bSRamuthevar Vadivel Murugan static int cqspi_remove(struct platform_device *pdev) 157931fb632bSRamuthevar Vadivel Murugan { 158031fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = platform_get_drvdata(pdev); 158131fb632bSRamuthevar Vadivel Murugan 158231fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 158331fb632bSRamuthevar Vadivel Murugan 158431fb632bSRamuthevar Vadivel Murugan if (cqspi->rx_chan) 158531fb632bSRamuthevar Vadivel Murugan dma_release_channel(cqspi->rx_chan); 158631fb632bSRamuthevar Vadivel Murugan 158731fb632bSRamuthevar Vadivel Murugan clk_disable_unprepare(cqspi->clk); 158831fb632bSRamuthevar Vadivel Murugan 158931fb632bSRamuthevar Vadivel Murugan pm_runtime_put_sync(&pdev->dev); 159031fb632bSRamuthevar Vadivel Murugan pm_runtime_disable(&pdev->dev); 159131fb632bSRamuthevar Vadivel Murugan 159231fb632bSRamuthevar Vadivel Murugan return 0; 159331fb632bSRamuthevar Vadivel Murugan } 159431fb632bSRamuthevar Vadivel Murugan 159531fb632bSRamuthevar Vadivel Murugan #ifdef CONFIG_PM_SLEEP 159631fb632bSRamuthevar Vadivel Murugan static int cqspi_suspend(struct device *dev) 159731fb632bSRamuthevar Vadivel Murugan { 159831fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev_get_drvdata(dev); 159931fb632bSRamuthevar Vadivel Murugan 160031fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 160131fb632bSRamuthevar Vadivel Murugan return 0; 160231fb632bSRamuthevar Vadivel Murugan } 160331fb632bSRamuthevar Vadivel Murugan 160431fb632bSRamuthevar Vadivel Murugan static int cqspi_resume(struct device *dev) 160531fb632bSRamuthevar Vadivel Murugan { 160631fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev_get_drvdata(dev); 160731fb632bSRamuthevar Vadivel Murugan 160831fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1); 160931fb632bSRamuthevar Vadivel Murugan return 0; 161031fb632bSRamuthevar Vadivel Murugan } 161131fb632bSRamuthevar Vadivel Murugan 161231fb632bSRamuthevar Vadivel Murugan static const struct dev_pm_ops cqspi__dev_pm_ops = { 161331fb632bSRamuthevar Vadivel Murugan .suspend = cqspi_suspend, 161431fb632bSRamuthevar Vadivel Murugan .resume = cqspi_resume, 161531fb632bSRamuthevar Vadivel Murugan }; 161631fb632bSRamuthevar Vadivel Murugan 161731fb632bSRamuthevar Vadivel Murugan #define CQSPI_DEV_PM_OPS (&cqspi__dev_pm_ops) 161831fb632bSRamuthevar Vadivel Murugan #else 161931fb632bSRamuthevar Vadivel Murugan #define CQSPI_DEV_PM_OPS NULL 162031fb632bSRamuthevar Vadivel Murugan #endif 162131fb632bSRamuthevar Vadivel Murugan 162231fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata cdns_qspi = { 162331fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_DISABLE_DAC_MODE, 162431fb632bSRamuthevar Vadivel Murugan }; 162531fb632bSRamuthevar Vadivel Murugan 162631fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata k2g_qspi = { 162731fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_NEEDS_WR_DELAY, 162831fb632bSRamuthevar Vadivel Murugan }; 162931fb632bSRamuthevar Vadivel Murugan 163031fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata am654_ospi = { 163131fb632bSRamuthevar Vadivel Murugan .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 163231fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_NEEDS_WR_DELAY, 163331fb632bSRamuthevar Vadivel Murugan }; 163431fb632bSRamuthevar Vadivel Murugan 1635ad2775dcSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata intel_lgm_qspi = { 1636ad2775dcSRamuthevar Vadivel Murugan .quirks = CQSPI_DISABLE_DAC_MODE, 1637ad2775dcSRamuthevar Vadivel Murugan }; 1638ad2775dcSRamuthevar Vadivel Murugan 163931fb632bSRamuthevar Vadivel Murugan static const struct of_device_id cqspi_dt_ids[] = { 164031fb632bSRamuthevar Vadivel Murugan { 164131fb632bSRamuthevar Vadivel Murugan .compatible = "cdns,qspi-nor", 164231fb632bSRamuthevar Vadivel Murugan .data = &cdns_qspi, 164331fb632bSRamuthevar Vadivel Murugan }, 164431fb632bSRamuthevar Vadivel Murugan { 164531fb632bSRamuthevar Vadivel Murugan .compatible = "ti,k2g-qspi", 164631fb632bSRamuthevar Vadivel Murugan .data = &k2g_qspi, 164731fb632bSRamuthevar Vadivel Murugan }, 164831fb632bSRamuthevar Vadivel Murugan { 164931fb632bSRamuthevar Vadivel Murugan .compatible = "ti,am654-ospi", 165031fb632bSRamuthevar Vadivel Murugan .data = &am654_ospi, 165131fb632bSRamuthevar Vadivel Murugan }, 1652ab2d2875SRamuthevar Vadivel Murugan { 1653ab2d2875SRamuthevar Vadivel Murugan .compatible = "intel,lgm-qspi", 1654ad2775dcSRamuthevar Vadivel Murugan .data = &intel_lgm_qspi, 1655ab2d2875SRamuthevar Vadivel Murugan }, 165631fb632bSRamuthevar Vadivel Murugan { /* end of table */ } 165731fb632bSRamuthevar Vadivel Murugan }; 165831fb632bSRamuthevar Vadivel Murugan 165931fb632bSRamuthevar Vadivel Murugan MODULE_DEVICE_TABLE(of, cqspi_dt_ids); 166031fb632bSRamuthevar Vadivel Murugan 166131fb632bSRamuthevar Vadivel Murugan static struct platform_driver cqspi_platform_driver = { 166231fb632bSRamuthevar Vadivel Murugan .probe = cqspi_probe, 166331fb632bSRamuthevar Vadivel Murugan .remove = cqspi_remove, 166431fb632bSRamuthevar Vadivel Murugan .driver = { 166531fb632bSRamuthevar Vadivel Murugan .name = CQSPI_NAME, 166631fb632bSRamuthevar Vadivel Murugan .pm = CQSPI_DEV_PM_OPS, 166731fb632bSRamuthevar Vadivel Murugan .of_match_table = cqspi_dt_ids, 166831fb632bSRamuthevar Vadivel Murugan }, 166931fb632bSRamuthevar Vadivel Murugan }; 167031fb632bSRamuthevar Vadivel Murugan 167131fb632bSRamuthevar Vadivel Murugan module_platform_driver(cqspi_platform_driver); 167231fb632bSRamuthevar Vadivel Murugan 167331fb632bSRamuthevar Vadivel Murugan MODULE_DESCRIPTION("Cadence QSPI Controller Driver"); 167431fb632bSRamuthevar Vadivel Murugan MODULE_LICENSE("GPL v2"); 167531fb632bSRamuthevar Vadivel Murugan MODULE_ALIAS("platform:" CQSPI_NAME); 167631fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>"); 167731fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>"); 167831fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>"); 167931fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>"); 1680f453f293SPratyush Yadav MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>"); 1681