131fb632bSRamuthevar Vadivel Murugan // SPDX-License-Identifier: GPL-2.0-only 231fb632bSRamuthevar Vadivel Murugan // 331fb632bSRamuthevar Vadivel Murugan // Driver for Cadence QSPI Controller 431fb632bSRamuthevar Vadivel Murugan // 531fb632bSRamuthevar Vadivel Murugan // Copyright Altera Corporation (C) 2012-2014. All rights reserved. 631fb632bSRamuthevar Vadivel Murugan // Copyright Intel Corporation (C) 2019-2020. All rights reserved. 731fb632bSRamuthevar Vadivel Murugan // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 831fb632bSRamuthevar Vadivel Murugan 931fb632bSRamuthevar Vadivel Murugan #include <linux/clk.h> 1031fb632bSRamuthevar Vadivel Murugan #include <linux/completion.h> 1131fb632bSRamuthevar Vadivel Murugan #include <linux/delay.h> 1231fb632bSRamuthevar Vadivel Murugan #include <linux/dma-mapping.h> 1331fb632bSRamuthevar Vadivel Murugan #include <linux/dmaengine.h> 1431fb632bSRamuthevar Vadivel Murugan #include <linux/err.h> 1531fb632bSRamuthevar Vadivel Murugan #include <linux/errno.h> 1609e393e3SSai Krishna Potthuri #include <linux/firmware/xlnx-zynqmp.h> 1731fb632bSRamuthevar Vadivel Murugan #include <linux/interrupt.h> 1831fb632bSRamuthevar Vadivel Murugan #include <linux/io.h> 1931fb632bSRamuthevar Vadivel Murugan #include <linux/iopoll.h> 2031fb632bSRamuthevar Vadivel Murugan #include <linux/jiffies.h> 2131fb632bSRamuthevar Vadivel Murugan #include <linux/kernel.h> 2297e4827dSMatthias Schiffer #include <linux/log2.h> 2331fb632bSRamuthevar Vadivel Murugan #include <linux/module.h> 2431fb632bSRamuthevar Vadivel Murugan #include <linux/of_device.h> 2531fb632bSRamuthevar Vadivel Murugan #include <linux/of.h> 2631fb632bSRamuthevar Vadivel Murugan #include <linux/platform_device.h> 2731fb632bSRamuthevar Vadivel Murugan #include <linux/pm_runtime.h> 2831fb632bSRamuthevar Vadivel Murugan #include <linux/reset.h> 2931fb632bSRamuthevar Vadivel Murugan #include <linux/sched.h> 3031fb632bSRamuthevar Vadivel Murugan #include <linux/spi/spi.h> 3131fb632bSRamuthevar Vadivel Murugan #include <linux/spi/spi-mem.h> 3231fb632bSRamuthevar Vadivel Murugan #include <linux/timer.h> 3331fb632bSRamuthevar Vadivel Murugan 3431fb632bSRamuthevar Vadivel Murugan #define CQSPI_NAME "cadence-qspi" 3531fb632bSRamuthevar Vadivel Murugan #define CQSPI_MAX_CHIPSELECT 16 3631fb632bSRamuthevar Vadivel Murugan 3731fb632bSRamuthevar Vadivel Murugan /* Quirks */ 3831fb632bSRamuthevar Vadivel Murugan #define CQSPI_NEEDS_WR_DELAY BIT(0) 3931fb632bSRamuthevar Vadivel Murugan #define CQSPI_DISABLE_DAC_MODE BIT(1) 401a6f854fSSai Krishna Potthuri #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) 4198d948ebSDinh Nguyen #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) 4231fb632bSRamuthevar Vadivel Murugan 4331fb632bSRamuthevar Vadivel Murugan /* Capabilities */ 4431fb632bSRamuthevar Vadivel Murugan #define CQSPI_SUPPORTS_OCTAL BIT(0) 4531fb632bSRamuthevar Vadivel Murugan 4628ac902aSMatthias Schiffer #define CQSPI_OP_WIDTH(part) ((part).nbytes ? ilog2((part).buswidth) : 0) 4728ac902aSMatthias Schiffer 4831fb632bSRamuthevar Vadivel Murugan struct cqspi_st; 4931fb632bSRamuthevar Vadivel Murugan 5031fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata { 5131fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi; 5231fb632bSRamuthevar Vadivel Murugan u32 clk_rate; 5331fb632bSRamuthevar Vadivel Murugan u32 read_delay; 5431fb632bSRamuthevar Vadivel Murugan u32 tshsl_ns; 5531fb632bSRamuthevar Vadivel Murugan u32 tsd2d_ns; 5631fb632bSRamuthevar Vadivel Murugan u32 tchsh_ns; 5731fb632bSRamuthevar Vadivel Murugan u32 tslch_ns; 5831fb632bSRamuthevar Vadivel Murugan u8 cs; 5931fb632bSRamuthevar Vadivel Murugan }; 6031fb632bSRamuthevar Vadivel Murugan 6131fb632bSRamuthevar Vadivel Murugan struct cqspi_st { 6231fb632bSRamuthevar Vadivel Murugan struct platform_device *pdev; 63*606e5d40SVaishnav Achath struct spi_master *master; 6431fb632bSRamuthevar Vadivel Murugan struct clk *clk; 6531fb632bSRamuthevar Vadivel Murugan unsigned int sclk; 6631fb632bSRamuthevar Vadivel Murugan 6731fb632bSRamuthevar Vadivel Murugan void __iomem *iobase; 6831fb632bSRamuthevar Vadivel Murugan void __iomem *ahb_base; 6931fb632bSRamuthevar Vadivel Murugan resource_size_t ahb_size; 7031fb632bSRamuthevar Vadivel Murugan struct completion transfer_complete; 7131fb632bSRamuthevar Vadivel Murugan 7231fb632bSRamuthevar Vadivel Murugan struct dma_chan *rx_chan; 7331fb632bSRamuthevar Vadivel Murugan struct completion rx_dma_complete; 7431fb632bSRamuthevar Vadivel Murugan dma_addr_t mmap_phys_base; 7531fb632bSRamuthevar Vadivel Murugan 7631fb632bSRamuthevar Vadivel Murugan int current_cs; 7731fb632bSRamuthevar Vadivel Murugan unsigned long master_ref_clk_hz; 7831fb632bSRamuthevar Vadivel Murugan bool is_decoded_cs; 7931fb632bSRamuthevar Vadivel Murugan u32 fifo_depth; 8031fb632bSRamuthevar Vadivel Murugan u32 fifo_width; 81b436fb7dSRamuthevar Vadivel Murugan u32 num_chipselect; 8231fb632bSRamuthevar Vadivel Murugan bool rclk_en; 8331fb632bSRamuthevar Vadivel Murugan u32 trigger_address; 8431fb632bSRamuthevar Vadivel Murugan u32 wr_delay; 8531fb632bSRamuthevar Vadivel Murugan bool use_direct_mode; 8631fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; 871a6f854fSSai Krishna Potthuri bool use_dma_read; 8809e393e3SSai Krishna Potthuri u32 pd_dev_id; 8998d948ebSDinh Nguyen bool wr_completion; 9031fb632bSRamuthevar Vadivel Murugan }; 9131fb632bSRamuthevar Vadivel Murugan 9231fb632bSRamuthevar Vadivel Murugan struct cqspi_driver_platdata { 9331fb632bSRamuthevar Vadivel Murugan u32 hwcaps_mask; 9431fb632bSRamuthevar Vadivel Murugan u8 quirks; 951a6f854fSSai Krishna Potthuri int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata, 961a6f854fSSai Krishna Potthuri u_char *rxbuf, loff_t from_addr, size_t n_rx); 971a6f854fSSai Krishna Potthuri u32 (*get_dma_status)(struct cqspi_st *cqspi); 9831fb632bSRamuthevar Vadivel Murugan }; 9931fb632bSRamuthevar Vadivel Murugan 10031fb632bSRamuthevar Vadivel Murugan /* Operation timeout value */ 10131fb632bSRamuthevar Vadivel Murugan #define CQSPI_TIMEOUT_MS 500 10231fb632bSRamuthevar Vadivel Murugan #define CQSPI_READ_TIMEOUT_MS 10 10331fb632bSRamuthevar Vadivel Murugan 10431fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_CLKS_PER_BYTE 8 10531fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_BYTES_MAX 4 10631fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_CLKS_MAX 31 10731fb632bSRamuthevar Vadivel Murugan 10831fb632bSRamuthevar Vadivel Murugan #define CQSPI_STIG_DATA_LEN_MAX 8 10931fb632bSRamuthevar Vadivel Murugan 11031fb632bSRamuthevar Vadivel Murugan /* Register map */ 11131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG 0x00 11231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0) 11331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7) 11431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9) 11531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 11631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_DMA_MASK BIT(15) 11731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_BAUD_LSB 19 118f453f293SPratyush Yadav #define CQSPI_REG_CONFIG_DTR_PROTO BIT(24) 119f453f293SPratyush Yadav #define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30) 12031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_IDLE_LSB 31 12131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF 12231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_BAUD_MASK 0xF 12331fb632bSRamuthevar Vadivel Murugan 12431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR 0x04 12531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 12631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 12731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 12831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 12931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 13031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 13131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 13231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 13331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 13431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F 13531fb632bSRamuthevar Vadivel Murugan 13631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR 0x08 13731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 13831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12 13931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16 14031fb632bSRamuthevar Vadivel Murugan 14131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY 0x0C 14231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSLCH_LSB 0 14331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TCHSH_LSB 8 14431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSD2D_LSB 16 14531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSHSL_LSB 24 14631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF 14731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF 14831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF 14931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF 15031fb632bSRamuthevar Vadivel Murugan 15131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE 0x10 15231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0 15331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_DELAY_LSB 1 15431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF 15531fb632bSRamuthevar Vadivel Murugan 15631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE 0x14 15731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_ADDRESS_LSB 0 15831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_PAGE_LSB 4 15931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_BLOCK_LSB 16 16031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF 16131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF 16231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F 16331fb632bSRamuthevar Vadivel Murugan 16431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SRAMPARTITION 0x18 16531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTTRIGGER 0x1C 16631fb632bSRamuthevar Vadivel Murugan 16731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA 0x20 16831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_SINGLE_LSB 0 16931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_BURST_LSB 8 17031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_SINGLE_MASK 0xFF 17131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_BURST_MASK 0xFF 17231fb632bSRamuthevar Vadivel Murugan 17331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_REMAP 0x24 17431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_MODE_BIT 0x28 17531fb632bSRamuthevar Vadivel Murugan 17631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL 0x2C 17731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 17831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 17931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF 18031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF 18131fb632bSRamuthevar Vadivel Murugan 182f453f293SPratyush Yadav #define CQSPI_REG_WR_COMPLETION_CTRL 0x38 183f453f293SPratyush Yadav #define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14) 184f453f293SPratyush Yadav 18531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQSTATUS 0x40 18631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQMASK 0x44 18731fb632bSRamuthevar Vadivel Murugan 18831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD 0x60 18931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0) 19031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1) 19131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5) 19231fb632bSRamuthevar Vadivel Murugan 19331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDWATERMARK 0x64 19431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 19531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDBYTES 0x6C 19631fb632bSRamuthevar Vadivel Murugan 19731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL 0x90 19831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0) 19931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1) 200888d517bSPratyush Yadav #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 20131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 20231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 20331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 20431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 20531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 20631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 20731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 20831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 20931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 21031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 211888d517bSPratyush Yadav #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F 21231fb632bSRamuthevar Vadivel Murugan 21331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR 0x70 21431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0) 21531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1) 21631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5) 21731fb632bSRamuthevar Vadivel Murugan 21831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRWATERMARK 0x74 21931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 22031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRBYTES 0x7C 22131fb632bSRamuthevar Vadivel Murugan 2221a6f854fSSai Krishna Potthuri #define CQSPI_REG_INDTRIG_ADDRRANGE 0x80 2231a6f854fSSai Krishna Potthuri 22431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDADDRESS 0x94 22531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDREADDATALOWER 0xA0 22631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDREADDATAUPPER 0xA4 22731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDWRITEDATALOWER 0xA8 22831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC 22931fb632bSRamuthevar Vadivel Murugan 230f453f293SPratyush Yadav #define CQSPI_REG_POLLING_STATUS 0xB0 231f453f293SPratyush Yadav #define CQSPI_REG_POLLING_STATUS_DUMMY_LSB 16 232f453f293SPratyush Yadav 233f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_LOWER 0xE0 234f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_READ_LSB 24 235f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_WRITE_LSB 16 236f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_STIG_LSB 0 237f453f293SPratyush Yadav 2381a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_SRC_ADDR 0x1000 2391a6f854fSSai Krishna Potthuri 2401a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_ADDR 0x1800 2411a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_SIZE 0x1804 2421a6f854fSSai Krishna Potthuri 2431a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_CTRL 0x180C 2441a6f854fSSai Krishna Potthuri 2451a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_I_STS 0x1814 2461a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_I_EN 0x1818 2471a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_I_DIS 0x181C 2481a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_DONE_MASK BIT(1) 2491a6f854fSSai Krishna Potthuri 2501a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB 0x1828 2511a6f854fSSai Krishna Potthuri 2521a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL 0xF43FFA00 2531a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL 0x6 2541a6f854fSSai Krishna Potthuri 25531fb632bSRamuthevar Vadivel Murugan /* Interrupt status bits */ 25631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_MODE_ERR BIT(0) 25731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_UNDERFLOW BIT(1) 25831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_COMP BIT(2) 25931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3) 26031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4) 26131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5) 26231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_WATERMARK BIT(6) 26331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12) 26431fb632bSRamuthevar Vadivel Murugan 26531fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \ 26631fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_IND_SRAM_FULL | \ 26731fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_IND_COMP) 26831fb632bSRamuthevar Vadivel Murugan 26931fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \ 27031fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_WATERMARK | \ 27131fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_UNDERFLOW) 27231fb632bSRamuthevar Vadivel Murugan 27331fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_STATUS_MASK 0x1FFFF 2741a6f854fSSai Krishna Potthuri #define CQSPI_DMA_UNALIGN 0x3 2751a6f854fSSai Krishna Potthuri 2761a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_VAL 0x602 27731fb632bSRamuthevar Vadivel Murugan 27831fb632bSRamuthevar Vadivel Murugan static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr) 27931fb632bSRamuthevar Vadivel Murugan { 28031fb632bSRamuthevar Vadivel Murugan u32 val; 28131fb632bSRamuthevar Vadivel Murugan 28231fb632bSRamuthevar Vadivel Murugan return readl_relaxed_poll_timeout(reg, val, 28331fb632bSRamuthevar Vadivel Murugan (((clr ? ~val : val) & mask) == mask), 28431fb632bSRamuthevar Vadivel Murugan 10, CQSPI_TIMEOUT_MS * 1000); 28531fb632bSRamuthevar Vadivel Murugan } 28631fb632bSRamuthevar Vadivel Murugan 28731fb632bSRamuthevar Vadivel Murugan static bool cqspi_is_idle(struct cqspi_st *cqspi) 28831fb632bSRamuthevar Vadivel Murugan { 28931fb632bSRamuthevar Vadivel Murugan u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 29031fb632bSRamuthevar Vadivel Murugan 29131890269SJay Fang return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB); 29231fb632bSRamuthevar Vadivel Murugan } 29331fb632bSRamuthevar Vadivel Murugan 29431fb632bSRamuthevar Vadivel Murugan static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi) 29531fb632bSRamuthevar Vadivel Murugan { 29631fb632bSRamuthevar Vadivel Murugan u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL); 29731fb632bSRamuthevar Vadivel Murugan 29831fb632bSRamuthevar Vadivel Murugan reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB; 29931fb632bSRamuthevar Vadivel Murugan return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK; 30031fb632bSRamuthevar Vadivel Murugan } 30131fb632bSRamuthevar Vadivel Murugan 3021a6f854fSSai Krishna Potthuri static u32 cqspi_get_versal_dma_status(struct cqspi_st *cqspi) 3031a6f854fSSai Krishna Potthuri { 3041a6f854fSSai Krishna Potthuri u32 dma_status; 3051a6f854fSSai Krishna Potthuri 3061a6f854fSSai Krishna Potthuri dma_status = readl(cqspi->iobase + 3071a6f854fSSai Krishna Potthuri CQSPI_REG_VERSAL_DMA_DST_I_STS); 3081a6f854fSSai Krishna Potthuri writel(dma_status, cqspi->iobase + 3091a6f854fSSai Krishna Potthuri CQSPI_REG_VERSAL_DMA_DST_I_STS); 3101a6f854fSSai Krishna Potthuri 3111a6f854fSSai Krishna Potthuri return dma_status & CQSPI_REG_VERSAL_DMA_DST_DONE_MASK; 3121a6f854fSSai Krishna Potthuri } 3131a6f854fSSai Krishna Potthuri 31431fb632bSRamuthevar Vadivel Murugan static irqreturn_t cqspi_irq_handler(int this_irq, void *dev) 31531fb632bSRamuthevar Vadivel Murugan { 31631fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev; 31731fb632bSRamuthevar Vadivel Murugan unsigned int irq_status; 3181a6f854fSSai Krishna Potthuri struct device *device = &cqspi->pdev->dev; 3191a6f854fSSai Krishna Potthuri const struct cqspi_driver_platdata *ddata; 3201a6f854fSSai Krishna Potthuri 3211a6f854fSSai Krishna Potthuri ddata = of_device_get_match_data(device); 32231fb632bSRamuthevar Vadivel Murugan 32331fb632bSRamuthevar Vadivel Murugan /* Read interrupt status */ 32431fb632bSRamuthevar Vadivel Murugan irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS); 32531fb632bSRamuthevar Vadivel Murugan 32631fb632bSRamuthevar Vadivel Murugan /* Clear interrupt */ 32731fb632bSRamuthevar Vadivel Murugan writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS); 32831fb632bSRamuthevar Vadivel Murugan 3291a6f854fSSai Krishna Potthuri if (cqspi->use_dma_read && ddata && ddata->get_dma_status) { 3301a6f854fSSai Krishna Potthuri if (ddata->get_dma_status(cqspi)) { 3311a6f854fSSai Krishna Potthuri complete(&cqspi->transfer_complete); 3321a6f854fSSai Krishna Potthuri return IRQ_HANDLED; 3331a6f854fSSai Krishna Potthuri } 3341a6f854fSSai Krishna Potthuri } 3351a6f854fSSai Krishna Potthuri 33631fb632bSRamuthevar Vadivel Murugan irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR; 33731fb632bSRamuthevar Vadivel Murugan 33831fb632bSRamuthevar Vadivel Murugan if (irq_status) 33931fb632bSRamuthevar Vadivel Murugan complete(&cqspi->transfer_complete); 34031fb632bSRamuthevar Vadivel Murugan 34131fb632bSRamuthevar Vadivel Murugan return IRQ_HANDLED; 34231fb632bSRamuthevar Vadivel Murugan } 34331fb632bSRamuthevar Vadivel Murugan 34428ac902aSMatthias Schiffer static unsigned int cqspi_calc_rdreg(const struct spi_mem_op *op) 34531fb632bSRamuthevar Vadivel Murugan { 34631fb632bSRamuthevar Vadivel Murugan u32 rdreg = 0; 34731fb632bSRamuthevar Vadivel Murugan 34828ac902aSMatthias Schiffer rdreg |= CQSPI_OP_WIDTH(op->cmd) << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; 34928ac902aSMatthias Schiffer rdreg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; 35028ac902aSMatthias Schiffer rdreg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; 35131fb632bSRamuthevar Vadivel Murugan 35231fb632bSRamuthevar Vadivel Murugan return rdreg; 35331fb632bSRamuthevar Vadivel Murugan } 35431fb632bSRamuthevar Vadivel Murugan 35528ac902aSMatthias Schiffer static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op) 356888d517bSPratyush Yadav { 3570ccfd1baSYoshitaka Ikeda unsigned int dummy_clk; 358888d517bSPratyush Yadav 3590e85ee89SYoshitaka Ikeda if (!op->dummy.nbytes) 3600e85ee89SYoshitaka Ikeda return 0; 3610e85ee89SYoshitaka Ikeda 3627512eaf5SPratyush Yadav dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth); 36328ac902aSMatthias Schiffer if (op->cmd.dtr) 364f453f293SPratyush Yadav dummy_clk /= 2; 365888d517bSPratyush Yadav 366888d517bSPratyush Yadav return dummy_clk; 367888d517bSPratyush Yadav } 368888d517bSPratyush Yadav 36931fb632bSRamuthevar Vadivel Murugan static int cqspi_wait_idle(struct cqspi_st *cqspi) 37031fb632bSRamuthevar Vadivel Murugan { 37131fb632bSRamuthevar Vadivel Murugan const unsigned int poll_idle_retry = 3; 37231fb632bSRamuthevar Vadivel Murugan unsigned int count = 0; 37331fb632bSRamuthevar Vadivel Murugan unsigned long timeout; 37431fb632bSRamuthevar Vadivel Murugan 37531fb632bSRamuthevar Vadivel Murugan timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS); 37631fb632bSRamuthevar Vadivel Murugan while (1) { 37731fb632bSRamuthevar Vadivel Murugan /* 37831fb632bSRamuthevar Vadivel Murugan * Read few times in succession to ensure the controller 37931fb632bSRamuthevar Vadivel Murugan * is indeed idle, that is, the bit does not transition 38031fb632bSRamuthevar Vadivel Murugan * low again. 38131fb632bSRamuthevar Vadivel Murugan */ 38231fb632bSRamuthevar Vadivel Murugan if (cqspi_is_idle(cqspi)) 38331fb632bSRamuthevar Vadivel Murugan count++; 38431fb632bSRamuthevar Vadivel Murugan else 38531fb632bSRamuthevar Vadivel Murugan count = 0; 38631fb632bSRamuthevar Vadivel Murugan 38731fb632bSRamuthevar Vadivel Murugan if (count >= poll_idle_retry) 38831fb632bSRamuthevar Vadivel Murugan return 0; 38931fb632bSRamuthevar Vadivel Murugan 39031fb632bSRamuthevar Vadivel Murugan if (time_after(jiffies, timeout)) { 39131fb632bSRamuthevar Vadivel Murugan /* Timeout, in busy mode. */ 39231fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 39331fb632bSRamuthevar Vadivel Murugan "QSPI is still busy after %dms timeout.\n", 39431fb632bSRamuthevar Vadivel Murugan CQSPI_TIMEOUT_MS); 39531fb632bSRamuthevar Vadivel Murugan return -ETIMEDOUT; 39631fb632bSRamuthevar Vadivel Murugan } 39731fb632bSRamuthevar Vadivel Murugan 39831fb632bSRamuthevar Vadivel Murugan cpu_relax(); 39931fb632bSRamuthevar Vadivel Murugan } 40031fb632bSRamuthevar Vadivel Murugan } 40131fb632bSRamuthevar Vadivel Murugan 40231fb632bSRamuthevar Vadivel Murugan static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg) 40331fb632bSRamuthevar Vadivel Murugan { 40431fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 40531fb632bSRamuthevar Vadivel Murugan int ret; 40631fb632bSRamuthevar Vadivel Murugan 40731fb632bSRamuthevar Vadivel Murugan /* Write the CMDCTRL without start execution. */ 40831fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CMDCTRL); 40931fb632bSRamuthevar Vadivel Murugan /* Start execute */ 41031fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK; 41131fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CMDCTRL); 41231fb632bSRamuthevar Vadivel Murugan 41331fb632bSRamuthevar Vadivel Murugan /* Polling for completion. */ 41431fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL, 41531fb632bSRamuthevar Vadivel Murugan CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1); 41631fb632bSRamuthevar Vadivel Murugan if (ret) { 41731fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 41831fb632bSRamuthevar Vadivel Murugan "Flash command execution timed out.\n"); 41931fb632bSRamuthevar Vadivel Murugan return ret; 42031fb632bSRamuthevar Vadivel Murugan } 42131fb632bSRamuthevar Vadivel Murugan 42231fb632bSRamuthevar Vadivel Murugan /* Polling QSPI idle status. */ 42331fb632bSRamuthevar Vadivel Murugan return cqspi_wait_idle(cqspi); 42431fb632bSRamuthevar Vadivel Murugan } 42531fb632bSRamuthevar Vadivel Murugan 426f453f293SPratyush Yadav static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata, 427f453f293SPratyush Yadav const struct spi_mem_op *op, 428f453f293SPratyush Yadav unsigned int shift) 429f453f293SPratyush Yadav { 430f453f293SPratyush Yadav struct cqspi_st *cqspi = f_pdata->cqspi; 431f453f293SPratyush Yadav void __iomem *reg_base = cqspi->iobase; 432f453f293SPratyush Yadav unsigned int reg; 433f453f293SPratyush Yadav u8 ext; 434f453f293SPratyush Yadav 435f453f293SPratyush Yadav if (op->cmd.nbytes != 2) 436f453f293SPratyush Yadav return -EINVAL; 437f453f293SPratyush Yadav 438f453f293SPratyush Yadav /* Opcode extension is the LSB. */ 439f453f293SPratyush Yadav ext = op->cmd.opcode & 0xff; 440f453f293SPratyush Yadav 441f453f293SPratyush Yadav reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER); 442f453f293SPratyush Yadav reg &= ~(0xff << shift); 443f453f293SPratyush Yadav reg |= ext << shift; 444f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER); 445f453f293SPratyush Yadav 446f453f293SPratyush Yadav return 0; 447f453f293SPratyush Yadav } 448f453f293SPratyush Yadav 449f453f293SPratyush Yadav static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata, 45028ac902aSMatthias Schiffer const struct spi_mem_op *op, unsigned int shift) 451f453f293SPratyush Yadav { 452f453f293SPratyush Yadav struct cqspi_st *cqspi = f_pdata->cqspi; 453f453f293SPratyush Yadav void __iomem *reg_base = cqspi->iobase; 454f453f293SPratyush Yadav unsigned int reg; 455f453f293SPratyush Yadav int ret; 456f453f293SPratyush Yadav 457f453f293SPratyush Yadav reg = readl(reg_base + CQSPI_REG_CONFIG); 458f453f293SPratyush Yadav 459f453f293SPratyush Yadav /* 460f453f293SPratyush Yadav * We enable dual byte opcode here. The callers have to set up the 461f453f293SPratyush Yadav * extension opcode based on which type of operation it is. 462f453f293SPratyush Yadav */ 46328ac902aSMatthias Schiffer if (op->cmd.dtr) { 464f453f293SPratyush Yadav reg |= CQSPI_REG_CONFIG_DTR_PROTO; 465f453f293SPratyush Yadav reg |= CQSPI_REG_CONFIG_DUAL_OPCODE; 466f453f293SPratyush Yadav 467f453f293SPratyush Yadav /* Set up command opcode extension. */ 468f453f293SPratyush Yadav ret = cqspi_setup_opcode_ext(f_pdata, op, shift); 469f453f293SPratyush Yadav if (ret) 470f453f293SPratyush Yadav return ret; 471f453f293SPratyush Yadav } else { 472f453f293SPratyush Yadav reg &= ~CQSPI_REG_CONFIG_DTR_PROTO; 473f453f293SPratyush Yadav reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE; 474f453f293SPratyush Yadav } 475f453f293SPratyush Yadav 476f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_CONFIG); 477f453f293SPratyush Yadav 478f453f293SPratyush Yadav return cqspi_wait_idle(cqspi); 479f453f293SPratyush Yadav } 480f453f293SPratyush Yadav 48131fb632bSRamuthevar Vadivel Murugan static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, 48231fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 48331fb632bSRamuthevar Vadivel Murugan { 48431fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 48531fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 48631fb632bSRamuthevar Vadivel Murugan u8 *rxbuf = op->data.buf.in; 487f453f293SPratyush Yadav u8 opcode; 48831fb632bSRamuthevar Vadivel Murugan size_t n_rx = op->data.nbytes; 48931fb632bSRamuthevar Vadivel Murugan unsigned int rdreg; 49031fb632bSRamuthevar Vadivel Murugan unsigned int reg; 491888d517bSPratyush Yadav unsigned int dummy_clk; 49231fb632bSRamuthevar Vadivel Murugan size_t read_len; 49331fb632bSRamuthevar Vadivel Murugan int status; 49431fb632bSRamuthevar Vadivel Murugan 49528ac902aSMatthias Schiffer status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB); 496f453f293SPratyush Yadav if (status) 497f453f293SPratyush Yadav return status; 498f453f293SPratyush Yadav 49931fb632bSRamuthevar Vadivel Murugan if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) { 50031fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 50131fb632bSRamuthevar Vadivel Murugan "Invalid input argument, len %zu rxbuf 0x%p\n", 50231fb632bSRamuthevar Vadivel Murugan n_rx, rxbuf); 50331fb632bSRamuthevar Vadivel Murugan return -EINVAL; 50431fb632bSRamuthevar Vadivel Murugan } 50531fb632bSRamuthevar Vadivel Murugan 50628ac902aSMatthias Schiffer if (op->cmd.dtr) 507f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 508f453f293SPratyush Yadav else 509f453f293SPratyush Yadav opcode = op->cmd.opcode; 510f453f293SPratyush Yadav 51131fb632bSRamuthevar Vadivel Murugan reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 51231fb632bSRamuthevar Vadivel Murugan 51328ac902aSMatthias Schiffer rdreg = cqspi_calc_rdreg(op); 51431fb632bSRamuthevar Vadivel Murugan writel(rdreg, reg_base + CQSPI_REG_RD_INSTR); 51531fb632bSRamuthevar Vadivel Murugan 51628ac902aSMatthias Schiffer dummy_clk = cqspi_calc_dummy(op); 517888d517bSPratyush Yadav if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 518888d517bSPratyush Yadav return -EOPNOTSUPP; 519888d517bSPratyush Yadav 520888d517bSPratyush Yadav if (dummy_clk) 521888d517bSPratyush Yadav reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK) 522888d517bSPratyush Yadav << CQSPI_REG_CMDCTRL_DUMMY_LSB; 523888d517bSPratyush Yadav 52431fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); 52531fb632bSRamuthevar Vadivel Murugan 52631fb632bSRamuthevar Vadivel Murugan /* 0 means 1 byte. */ 52731fb632bSRamuthevar Vadivel Murugan reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) 52831fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); 52931fb632bSRamuthevar Vadivel Murugan status = cqspi_exec_flash_cmd(cqspi, reg); 53031fb632bSRamuthevar Vadivel Murugan if (status) 53131fb632bSRamuthevar Vadivel Murugan return status; 53231fb632bSRamuthevar Vadivel Murugan 53331fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER); 53431fb632bSRamuthevar Vadivel Murugan 53531fb632bSRamuthevar Vadivel Murugan /* Put the read value into rx_buf */ 53631fb632bSRamuthevar Vadivel Murugan read_len = (n_rx > 4) ? 4 : n_rx; 53731fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, ®, read_len); 53831fb632bSRamuthevar Vadivel Murugan rxbuf += read_len; 53931fb632bSRamuthevar Vadivel Murugan 54031fb632bSRamuthevar Vadivel Murugan if (n_rx > 4) { 54131fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER); 54231fb632bSRamuthevar Vadivel Murugan 54331fb632bSRamuthevar Vadivel Murugan read_len = n_rx - read_len; 54431fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, ®, read_len); 54531fb632bSRamuthevar Vadivel Murugan } 54631fb632bSRamuthevar Vadivel Murugan 54731fb632bSRamuthevar Vadivel Murugan return 0; 54831fb632bSRamuthevar Vadivel Murugan } 54931fb632bSRamuthevar Vadivel Murugan 55031fb632bSRamuthevar Vadivel Murugan static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata, 55131fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 55231fb632bSRamuthevar Vadivel Murugan { 55331fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 55431fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 555f453f293SPratyush Yadav u8 opcode; 55631fb632bSRamuthevar Vadivel Murugan const u8 *txbuf = op->data.buf.out; 55731fb632bSRamuthevar Vadivel Murugan size_t n_tx = op->data.nbytes; 55831fb632bSRamuthevar Vadivel Murugan unsigned int reg; 55931fb632bSRamuthevar Vadivel Murugan unsigned int data; 56031fb632bSRamuthevar Vadivel Murugan size_t write_len; 561f453f293SPratyush Yadav int ret; 562f453f293SPratyush Yadav 56328ac902aSMatthias Schiffer ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB); 564f453f293SPratyush Yadav if (ret) 565f453f293SPratyush Yadav return ret; 56631fb632bSRamuthevar Vadivel Murugan 56731fb632bSRamuthevar Vadivel Murugan if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) { 56831fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 56931fb632bSRamuthevar Vadivel Murugan "Invalid input argument, cmdlen %zu txbuf 0x%p\n", 57031fb632bSRamuthevar Vadivel Murugan n_tx, txbuf); 57131fb632bSRamuthevar Vadivel Murugan return -EINVAL; 57231fb632bSRamuthevar Vadivel Murugan } 57331fb632bSRamuthevar Vadivel Murugan 57428ac902aSMatthias Schiffer reg = cqspi_calc_rdreg(op); 575f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_RD_INSTR); 576f453f293SPratyush Yadav 57728ac902aSMatthias Schiffer if (op->cmd.dtr) 578f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 579f453f293SPratyush Yadav else 580f453f293SPratyush Yadav opcode = op->cmd.opcode; 581f453f293SPratyush Yadav 58231fb632bSRamuthevar Vadivel Murugan reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 58331fb632bSRamuthevar Vadivel Murugan 58431fb632bSRamuthevar Vadivel Murugan if (op->addr.nbytes) { 58531fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 58631fb632bSRamuthevar Vadivel Murugan reg |= ((op->addr.nbytes - 1) & 58731fb632bSRamuthevar Vadivel Murugan CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) 58831fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; 58931fb632bSRamuthevar Vadivel Murugan 59031fb632bSRamuthevar Vadivel Murugan writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); 59131fb632bSRamuthevar Vadivel Murugan } 59231fb632bSRamuthevar Vadivel Murugan 59331fb632bSRamuthevar Vadivel Murugan if (n_tx) { 59431fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB); 59531fb632bSRamuthevar Vadivel Murugan reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) 59631fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_WR_BYTES_LSB; 59731fb632bSRamuthevar Vadivel Murugan data = 0; 59831fb632bSRamuthevar Vadivel Murugan write_len = (n_tx > 4) ? 4 : n_tx; 59931fb632bSRamuthevar Vadivel Murugan memcpy(&data, txbuf, write_len); 60031fb632bSRamuthevar Vadivel Murugan txbuf += write_len; 60131fb632bSRamuthevar Vadivel Murugan writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER); 60231fb632bSRamuthevar Vadivel Murugan 60331fb632bSRamuthevar Vadivel Murugan if (n_tx > 4) { 60431fb632bSRamuthevar Vadivel Murugan data = 0; 60531fb632bSRamuthevar Vadivel Murugan write_len = n_tx - 4; 60631fb632bSRamuthevar Vadivel Murugan memcpy(&data, txbuf, write_len); 60731fb632bSRamuthevar Vadivel Murugan writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER); 60831fb632bSRamuthevar Vadivel Murugan } 60931fb632bSRamuthevar Vadivel Murugan } 61031fb632bSRamuthevar Vadivel Murugan 61131fb632bSRamuthevar Vadivel Murugan return cqspi_exec_flash_cmd(cqspi, reg); 61231fb632bSRamuthevar Vadivel Murugan } 61331fb632bSRamuthevar Vadivel Murugan 61431fb632bSRamuthevar Vadivel Murugan static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata, 61531fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 61631fb632bSRamuthevar Vadivel Murugan { 61731fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 61831fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 61931fb632bSRamuthevar Vadivel Murugan unsigned int dummy_clk = 0; 62031fb632bSRamuthevar Vadivel Murugan unsigned int reg; 621f453f293SPratyush Yadav int ret; 622f453f293SPratyush Yadav u8 opcode; 62331fb632bSRamuthevar Vadivel Murugan 62428ac902aSMatthias Schiffer ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB); 625f453f293SPratyush Yadav if (ret) 626f453f293SPratyush Yadav return ret; 627f453f293SPratyush Yadav 62828ac902aSMatthias Schiffer if (op->cmd.dtr) 629f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 630f453f293SPratyush Yadav else 631f453f293SPratyush Yadav opcode = op->cmd.opcode; 632f453f293SPratyush Yadav 633f453f293SPratyush Yadav reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB; 63428ac902aSMatthias Schiffer reg |= cqspi_calc_rdreg(op); 63531fb632bSRamuthevar Vadivel Murugan 63631fb632bSRamuthevar Vadivel Murugan /* Setup dummy clock cycles */ 63728ac902aSMatthias Schiffer dummy_clk = cqspi_calc_dummy(op); 638888d517bSPratyush Yadav 63931fb632bSRamuthevar Vadivel Murugan if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 640ceeda328SPratyush Yadav return -EOPNOTSUPP; 64131fb632bSRamuthevar Vadivel Murugan 64231fb632bSRamuthevar Vadivel Murugan if (dummy_clk) 64331fb632bSRamuthevar Vadivel Murugan reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK) 64431fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_RD_INSTR_DUMMY_LSB; 64531fb632bSRamuthevar Vadivel Murugan 64631fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_RD_INSTR); 64731fb632bSRamuthevar Vadivel Murugan 64831fb632bSRamuthevar Vadivel Murugan /* Set address width */ 64931fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_SIZE); 65031fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 65131fb632bSRamuthevar Vadivel Murugan reg |= (op->addr.nbytes - 1); 65231fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_SIZE); 65331fb632bSRamuthevar Vadivel Murugan return 0; 65431fb632bSRamuthevar Vadivel Murugan } 65531fb632bSRamuthevar Vadivel Murugan 65631fb632bSRamuthevar Vadivel Murugan static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, 65731fb632bSRamuthevar Vadivel Murugan u8 *rxbuf, loff_t from_addr, 65831fb632bSRamuthevar Vadivel Murugan const size_t n_rx) 65931fb632bSRamuthevar Vadivel Murugan { 66031fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 66131fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 66231fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 66331fb632bSRamuthevar Vadivel Murugan void __iomem *ahb_base = cqspi->ahb_base; 66431fb632bSRamuthevar Vadivel Murugan unsigned int remaining = n_rx; 66531fb632bSRamuthevar Vadivel Murugan unsigned int mod_bytes = n_rx % 4; 66631fb632bSRamuthevar Vadivel Murugan unsigned int bytes_to_read = 0; 66731fb632bSRamuthevar Vadivel Murugan u8 *rxbuf_end = rxbuf + n_rx; 66831fb632bSRamuthevar Vadivel Murugan int ret = 0; 66931fb632bSRamuthevar Vadivel Murugan 67031fb632bSRamuthevar Vadivel Murugan writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 67131fb632bSRamuthevar Vadivel Murugan writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES); 67231fb632bSRamuthevar Vadivel Murugan 67331fb632bSRamuthevar Vadivel Murugan /* Clear all interrupts. */ 67431fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 67531fb632bSRamuthevar Vadivel Murugan 67631fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK); 67731fb632bSRamuthevar Vadivel Murugan 67831fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 67931fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTRD_START_MASK, 68031fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTRD); 68131fb632bSRamuthevar Vadivel Murugan 68231fb632bSRamuthevar Vadivel Murugan while (remaining > 0) { 68331fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->transfer_complete, 68431fb632bSRamuthevar Vadivel Murugan msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) 68531fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 68631fb632bSRamuthevar Vadivel Murugan 68731fb632bSRamuthevar Vadivel Murugan bytes_to_read = cqspi_get_rd_sram_level(cqspi); 68831fb632bSRamuthevar Vadivel Murugan 68931fb632bSRamuthevar Vadivel Murugan if (ret && bytes_to_read == 0) { 69031fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect read timeout, no bytes\n"); 69131fb632bSRamuthevar Vadivel Murugan goto failrd; 69231fb632bSRamuthevar Vadivel Murugan } 69331fb632bSRamuthevar Vadivel Murugan 69431fb632bSRamuthevar Vadivel Murugan while (bytes_to_read != 0) { 69531fb632bSRamuthevar Vadivel Murugan unsigned int word_remain = round_down(remaining, 4); 69631fb632bSRamuthevar Vadivel Murugan 69731fb632bSRamuthevar Vadivel Murugan bytes_to_read *= cqspi->fifo_width; 69831fb632bSRamuthevar Vadivel Murugan bytes_to_read = bytes_to_read > remaining ? 69931fb632bSRamuthevar Vadivel Murugan remaining : bytes_to_read; 70031fb632bSRamuthevar Vadivel Murugan bytes_to_read = round_down(bytes_to_read, 4); 70131fb632bSRamuthevar Vadivel Murugan /* Read 4 byte word chunks then single bytes */ 70231fb632bSRamuthevar Vadivel Murugan if (bytes_to_read) { 70331fb632bSRamuthevar Vadivel Murugan ioread32_rep(ahb_base, rxbuf, 70431fb632bSRamuthevar Vadivel Murugan (bytes_to_read / 4)); 70531fb632bSRamuthevar Vadivel Murugan } else if (!word_remain && mod_bytes) { 70631fb632bSRamuthevar Vadivel Murugan unsigned int temp = ioread32(ahb_base); 70731fb632bSRamuthevar Vadivel Murugan 70831fb632bSRamuthevar Vadivel Murugan bytes_to_read = mod_bytes; 70931fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, &temp, min((unsigned int) 71031fb632bSRamuthevar Vadivel Murugan (rxbuf_end - rxbuf), 71131fb632bSRamuthevar Vadivel Murugan bytes_to_read)); 71231fb632bSRamuthevar Vadivel Murugan } 71331fb632bSRamuthevar Vadivel Murugan rxbuf += bytes_to_read; 71431fb632bSRamuthevar Vadivel Murugan remaining -= bytes_to_read; 71531fb632bSRamuthevar Vadivel Murugan bytes_to_read = cqspi_get_rd_sram_level(cqspi); 71631fb632bSRamuthevar Vadivel Murugan } 71731fb632bSRamuthevar Vadivel Murugan 71831fb632bSRamuthevar Vadivel Murugan if (remaining > 0) 71931fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 72031fb632bSRamuthevar Vadivel Murugan } 72131fb632bSRamuthevar Vadivel Murugan 72231fb632bSRamuthevar Vadivel Murugan /* Check indirect done status */ 72331fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD, 72431fb632bSRamuthevar Vadivel Murugan CQSPI_REG_INDIRECTRD_DONE_MASK, 0); 72531fb632bSRamuthevar Vadivel Murugan if (ret) { 72631fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect read completion error (%i)\n", ret); 72731fb632bSRamuthevar Vadivel Murugan goto failrd; 72831fb632bSRamuthevar Vadivel Murugan } 72931fb632bSRamuthevar Vadivel Murugan 73031fb632bSRamuthevar Vadivel Murugan /* Disable interrupt */ 73131fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 73231fb632bSRamuthevar Vadivel Murugan 73331fb632bSRamuthevar Vadivel Murugan /* Clear indirect completion status */ 73431fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD); 73531fb632bSRamuthevar Vadivel Murugan 73631fb632bSRamuthevar Vadivel Murugan return 0; 73731fb632bSRamuthevar Vadivel Murugan 73831fb632bSRamuthevar Vadivel Murugan failrd: 73931fb632bSRamuthevar Vadivel Murugan /* Disable interrupt */ 74031fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 74131fb632bSRamuthevar Vadivel Murugan 74231fb632bSRamuthevar Vadivel Murugan /* Cancel the indirect read */ 74331fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 74431fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTRD); 74531fb632bSRamuthevar Vadivel Murugan return ret; 74631fb632bSRamuthevar Vadivel Murugan } 74731fb632bSRamuthevar Vadivel Murugan 7481a6f854fSSai Krishna Potthuri static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata, 7491a6f854fSSai Krishna Potthuri u_char *rxbuf, loff_t from_addr, 7501a6f854fSSai Krishna Potthuri size_t n_rx) 7511a6f854fSSai Krishna Potthuri { 7521a6f854fSSai Krishna Potthuri struct cqspi_st *cqspi = f_pdata->cqspi; 7531a6f854fSSai Krishna Potthuri struct device *dev = &cqspi->pdev->dev; 7541a6f854fSSai Krishna Potthuri void __iomem *reg_base = cqspi->iobase; 7551a6f854fSSai Krishna Potthuri u32 reg, bytes_to_dma; 7561a6f854fSSai Krishna Potthuri loff_t addr = from_addr; 7571a6f854fSSai Krishna Potthuri void *buf = rxbuf; 7581a6f854fSSai Krishna Potthuri dma_addr_t dma_addr; 7591a6f854fSSai Krishna Potthuri u8 bytes_rem; 7601a6f854fSSai Krishna Potthuri int ret = 0; 7611a6f854fSSai Krishna Potthuri 7621a6f854fSSai Krishna Potthuri bytes_rem = n_rx % 4; 7631a6f854fSSai Krishna Potthuri bytes_to_dma = (n_rx - bytes_rem); 7641a6f854fSSai Krishna Potthuri 7651a6f854fSSai Krishna Potthuri if (!bytes_to_dma) 7661a6f854fSSai Krishna Potthuri goto nondmard; 7671a6f854fSSai Krishna Potthuri 7681a6f854fSSai Krishna Potthuri ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA); 7691a6f854fSSai Krishna Potthuri if (ret) 7701a6f854fSSai Krishna Potthuri return ret; 7711a6f854fSSai Krishna Potthuri 7721a6f854fSSai Krishna Potthuri reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 7731a6f854fSSai Krishna Potthuri reg |= CQSPI_REG_CONFIG_DMA_MASK; 7741a6f854fSSai Krishna Potthuri writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 7751a6f854fSSai Krishna Potthuri 7761a6f854fSSai Krishna Potthuri dma_addr = dma_map_single(dev, rxbuf, bytes_to_dma, DMA_FROM_DEVICE); 7771a6f854fSSai Krishna Potthuri if (dma_mapping_error(dev, dma_addr)) { 7781a6f854fSSai Krishna Potthuri dev_err(dev, "dma mapping failed\n"); 7791a6f854fSSai Krishna Potthuri return -ENOMEM; 7801a6f854fSSai Krishna Potthuri } 7811a6f854fSSai Krishna Potthuri 7821a6f854fSSai Krishna Potthuri writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 7831a6f854fSSai Krishna Potthuri writel(bytes_to_dma, reg_base + CQSPI_REG_INDIRECTRDBYTES); 7841a6f854fSSai Krishna Potthuri writel(CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL, 7851a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_INDTRIG_ADDRRANGE); 7861a6f854fSSai Krishna Potthuri 7871a6f854fSSai Krishna Potthuri /* Clear all interrupts. */ 7881a6f854fSSai Krishna Potthuri writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 7891a6f854fSSai Krishna Potthuri 7901a6f854fSSai Krishna Potthuri /* Enable DMA done interrupt */ 7911a6f854fSSai Krishna Potthuri writel(CQSPI_REG_VERSAL_DMA_DST_DONE_MASK, 7921a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_VERSAL_DMA_DST_I_EN); 7931a6f854fSSai Krishna Potthuri 7941a6f854fSSai Krishna Potthuri /* Default DMA periph configuration */ 7951a6f854fSSai Krishna Potthuri writel(CQSPI_REG_VERSAL_DMA_VAL, reg_base + CQSPI_REG_DMA); 7961a6f854fSSai Krishna Potthuri 7971a6f854fSSai Krishna Potthuri /* Configure DMA Dst address */ 7981a6f854fSSai Krishna Potthuri writel(lower_32_bits(dma_addr), 7991a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR); 8001a6f854fSSai Krishna Potthuri writel(upper_32_bits(dma_addr), 8011a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB); 8021a6f854fSSai Krishna Potthuri 8031a6f854fSSai Krishna Potthuri /* Configure DMA Src address */ 8041a6f854fSSai Krishna Potthuri writel(cqspi->trigger_address, reg_base + 8051a6f854fSSai Krishna Potthuri CQSPI_REG_VERSAL_DMA_SRC_ADDR); 8061a6f854fSSai Krishna Potthuri 8071a6f854fSSai Krishna Potthuri /* Set DMA destination size */ 8081a6f854fSSai Krishna Potthuri writel(bytes_to_dma, reg_base + CQSPI_REG_VERSAL_DMA_DST_SIZE); 8091a6f854fSSai Krishna Potthuri 8101a6f854fSSai Krishna Potthuri /* Set DMA destination control */ 8111a6f854fSSai Krishna Potthuri writel(CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL, 8121a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_VERSAL_DMA_DST_CTRL); 8131a6f854fSSai Krishna Potthuri 8141a6f854fSSai Krishna Potthuri writel(CQSPI_REG_INDIRECTRD_START_MASK, 8151a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_INDIRECTRD); 8161a6f854fSSai Krishna Potthuri 8171a6f854fSSai Krishna Potthuri reinit_completion(&cqspi->transfer_complete); 8181a6f854fSSai Krishna Potthuri 8191a6f854fSSai Krishna Potthuri if (!wait_for_completion_timeout(&cqspi->transfer_complete, 8201a6f854fSSai Krishna Potthuri msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) { 8211a6f854fSSai Krishna Potthuri ret = -ETIMEDOUT; 8221a6f854fSSai Krishna Potthuri goto failrd; 8231a6f854fSSai Krishna Potthuri } 8241a6f854fSSai Krishna Potthuri 8251a6f854fSSai Krishna Potthuri /* Disable DMA interrupt */ 8261a6f854fSSai Krishna Potthuri writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS); 8271a6f854fSSai Krishna Potthuri 8281a6f854fSSai Krishna Potthuri /* Clear indirect completion status */ 8291a6f854fSSai Krishna Potthuri writel(CQSPI_REG_INDIRECTRD_DONE_MASK, 8301a6f854fSSai Krishna Potthuri cqspi->iobase + CQSPI_REG_INDIRECTRD); 8311a6f854fSSai Krishna Potthuri dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE); 8321a6f854fSSai Krishna Potthuri 8331a6f854fSSai Krishna Potthuri reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 8341a6f854fSSai Krishna Potthuri reg &= ~CQSPI_REG_CONFIG_DMA_MASK; 8351a6f854fSSai Krishna Potthuri writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 8361a6f854fSSai Krishna Potthuri 8371a6f854fSSai Krishna Potthuri ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, 8381a6f854fSSai Krishna Potthuri PM_OSPI_MUX_SEL_LINEAR); 8391a6f854fSSai Krishna Potthuri if (ret) 8401a6f854fSSai Krishna Potthuri return ret; 8411a6f854fSSai Krishna Potthuri 8421a6f854fSSai Krishna Potthuri nondmard: 8431a6f854fSSai Krishna Potthuri if (bytes_rem) { 8441a6f854fSSai Krishna Potthuri addr += bytes_to_dma; 8451a6f854fSSai Krishna Potthuri buf += bytes_to_dma; 8461a6f854fSSai Krishna Potthuri ret = cqspi_indirect_read_execute(f_pdata, buf, addr, 8471a6f854fSSai Krishna Potthuri bytes_rem); 8481a6f854fSSai Krishna Potthuri if (ret) 8491a6f854fSSai Krishna Potthuri return ret; 8501a6f854fSSai Krishna Potthuri } 8511a6f854fSSai Krishna Potthuri 8521a6f854fSSai Krishna Potthuri return 0; 8531a6f854fSSai Krishna Potthuri 8541a6f854fSSai Krishna Potthuri failrd: 8551a6f854fSSai Krishna Potthuri /* Disable DMA interrupt */ 8561a6f854fSSai Krishna Potthuri writel(0x0, reg_base + CQSPI_REG_VERSAL_DMA_DST_I_DIS); 8571a6f854fSSai Krishna Potthuri 8581a6f854fSSai Krishna Potthuri /* Cancel the indirect read */ 8591a6f854fSSai Krishna Potthuri writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 8601a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_INDIRECTRD); 8611a6f854fSSai Krishna Potthuri 862d9c55c95SArnd Bergmann dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE); 8631a6f854fSSai Krishna Potthuri 8641a6f854fSSai Krishna Potthuri reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 8651a6f854fSSai Krishna Potthuri reg &= ~CQSPI_REG_CONFIG_DMA_MASK; 8661a6f854fSSai Krishna Potthuri writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 8671a6f854fSSai Krishna Potthuri 8681a6f854fSSai Krishna Potthuri zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR); 8691a6f854fSSai Krishna Potthuri 8701a6f854fSSai Krishna Potthuri return ret; 8711a6f854fSSai Krishna Potthuri } 8721a6f854fSSai Krishna Potthuri 87331fb632bSRamuthevar Vadivel Murugan static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata, 87431fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 87531fb632bSRamuthevar Vadivel Murugan { 87631fb632bSRamuthevar Vadivel Murugan unsigned int reg; 877f453f293SPratyush Yadav int ret; 87831fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 87931fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 880f453f293SPratyush Yadav u8 opcode; 881f453f293SPratyush Yadav 88228ac902aSMatthias Schiffer ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB); 883f453f293SPratyush Yadav if (ret) 884f453f293SPratyush Yadav return ret; 885f453f293SPratyush Yadav 88628ac902aSMatthias Schiffer if (op->cmd.dtr) 887f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 888f453f293SPratyush Yadav else 889f453f293SPratyush Yadav opcode = op->cmd.opcode; 89031fb632bSRamuthevar Vadivel Murugan 89131fb632bSRamuthevar Vadivel Murugan /* Set opcode. */ 892f453f293SPratyush Yadav reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; 89328ac902aSMatthias Schiffer reg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; 89428ac902aSMatthias Schiffer reg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; 89531fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_WR_INSTR); 89628ac902aSMatthias Schiffer reg = cqspi_calc_rdreg(op); 89731fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_RD_INSTR); 89831fb632bSRamuthevar Vadivel Murugan 899f453f293SPratyush Yadav /* 9009cb2ff11SApurva Nandan * SPI NAND flashes require the address of the status register to be 9019cb2ff11SApurva Nandan * passed in the Read SR command. Also, some SPI NOR flashes like the 9029cb2ff11SApurva Nandan * cypress Semper flash expect a 4-byte dummy address in the Read SR 9039cb2ff11SApurva Nandan * command in DTR mode. 9049cb2ff11SApurva Nandan * 9059cb2ff11SApurva Nandan * But this controller does not support address phase in the Read SR 9069cb2ff11SApurva Nandan * command when doing auto-HW polling. So, disable write completion 9079cb2ff11SApurva Nandan * polling on the controller's side. spinand and spi-nor will take 9089cb2ff11SApurva Nandan * care of polling the status register. 909f453f293SPratyush Yadav */ 91098d948ebSDinh Nguyen if (cqspi->wr_completion) { 911f453f293SPratyush Yadav reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL); 912f453f293SPratyush Yadav reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL; 913f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL); 91498d948ebSDinh Nguyen } 915f453f293SPratyush Yadav 91631fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_SIZE); 91731fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 91831fb632bSRamuthevar Vadivel Murugan reg |= (op->addr.nbytes - 1); 91931fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_SIZE); 92031fb632bSRamuthevar Vadivel Murugan return 0; 92131fb632bSRamuthevar Vadivel Murugan } 92231fb632bSRamuthevar Vadivel Murugan 92331fb632bSRamuthevar Vadivel Murugan static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, 92431fb632bSRamuthevar Vadivel Murugan loff_t to_addr, const u8 *txbuf, 92531fb632bSRamuthevar Vadivel Murugan const size_t n_tx) 92631fb632bSRamuthevar Vadivel Murugan { 92731fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 92831fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 92931fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 93031fb632bSRamuthevar Vadivel Murugan unsigned int remaining = n_tx; 93131fb632bSRamuthevar Vadivel Murugan unsigned int write_bytes; 93231fb632bSRamuthevar Vadivel Murugan int ret; 93331fb632bSRamuthevar Vadivel Murugan 93431fb632bSRamuthevar Vadivel Murugan writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR); 93531fb632bSRamuthevar Vadivel Murugan writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES); 93631fb632bSRamuthevar Vadivel Murugan 93731fb632bSRamuthevar Vadivel Murugan /* Clear all interrupts. */ 93831fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 93931fb632bSRamuthevar Vadivel Murugan 94031fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK); 94131fb632bSRamuthevar Vadivel Murugan 94231fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 94331fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_START_MASK, 94431fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTWR); 94531fb632bSRamuthevar Vadivel Murugan /* 94631fb632bSRamuthevar Vadivel Murugan * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access 94731fb632bSRamuthevar Vadivel Murugan * Controller programming sequence, couple of cycles of 94831fb632bSRamuthevar Vadivel Murugan * QSPI_REF_CLK delay is required for the above bit to 94931fb632bSRamuthevar Vadivel Murugan * be internally synchronized by the QSPI module. Provide 5 95031fb632bSRamuthevar Vadivel Murugan * cycles of delay. 95131fb632bSRamuthevar Vadivel Murugan */ 95231fb632bSRamuthevar Vadivel Murugan if (cqspi->wr_delay) 95331fb632bSRamuthevar Vadivel Murugan ndelay(cqspi->wr_delay); 95431fb632bSRamuthevar Vadivel Murugan 95531fb632bSRamuthevar Vadivel Murugan while (remaining > 0) { 95631fb632bSRamuthevar Vadivel Murugan size_t write_words, mod_bytes; 95731fb632bSRamuthevar Vadivel Murugan 95831fb632bSRamuthevar Vadivel Murugan write_bytes = remaining; 95931fb632bSRamuthevar Vadivel Murugan write_words = write_bytes / 4; 96031fb632bSRamuthevar Vadivel Murugan mod_bytes = write_bytes % 4; 96131fb632bSRamuthevar Vadivel Murugan /* Write 4 bytes at a time then single bytes. */ 96231fb632bSRamuthevar Vadivel Murugan if (write_words) { 96331fb632bSRamuthevar Vadivel Murugan iowrite32_rep(cqspi->ahb_base, txbuf, write_words); 96431fb632bSRamuthevar Vadivel Murugan txbuf += (write_words * 4); 96531fb632bSRamuthevar Vadivel Murugan } 96631fb632bSRamuthevar Vadivel Murugan if (mod_bytes) { 96731fb632bSRamuthevar Vadivel Murugan unsigned int temp = 0xFFFFFFFF; 96831fb632bSRamuthevar Vadivel Murugan 96931fb632bSRamuthevar Vadivel Murugan memcpy(&temp, txbuf, mod_bytes); 97031fb632bSRamuthevar Vadivel Murugan iowrite32(temp, cqspi->ahb_base); 97131fb632bSRamuthevar Vadivel Murugan txbuf += mod_bytes; 97231fb632bSRamuthevar Vadivel Murugan } 97331fb632bSRamuthevar Vadivel Murugan 97431fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->transfer_complete, 97531fb632bSRamuthevar Vadivel Murugan msecs_to_jiffies(CQSPI_TIMEOUT_MS))) { 97631fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect write timeout\n"); 97731fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 97831fb632bSRamuthevar Vadivel Murugan goto failwr; 97931fb632bSRamuthevar Vadivel Murugan } 98031fb632bSRamuthevar Vadivel Murugan 98131fb632bSRamuthevar Vadivel Murugan remaining -= write_bytes; 98231fb632bSRamuthevar Vadivel Murugan 98331fb632bSRamuthevar Vadivel Murugan if (remaining > 0) 98431fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 98531fb632bSRamuthevar Vadivel Murugan } 98631fb632bSRamuthevar Vadivel Murugan 98731fb632bSRamuthevar Vadivel Murugan /* Check indirect done status */ 98831fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR, 98931fb632bSRamuthevar Vadivel Murugan CQSPI_REG_INDIRECTWR_DONE_MASK, 0); 99031fb632bSRamuthevar Vadivel Murugan if (ret) { 99131fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect write completion error (%i)\n", ret); 99231fb632bSRamuthevar Vadivel Murugan goto failwr; 99331fb632bSRamuthevar Vadivel Murugan } 99431fb632bSRamuthevar Vadivel Murugan 99531fb632bSRamuthevar Vadivel Murugan /* Disable interrupt. */ 99631fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 99731fb632bSRamuthevar Vadivel Murugan 99831fb632bSRamuthevar Vadivel Murugan /* Clear indirect completion status */ 99931fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR); 100031fb632bSRamuthevar Vadivel Murugan 100131fb632bSRamuthevar Vadivel Murugan cqspi_wait_idle(cqspi); 100231fb632bSRamuthevar Vadivel Murugan 100331fb632bSRamuthevar Vadivel Murugan return 0; 100431fb632bSRamuthevar Vadivel Murugan 100531fb632bSRamuthevar Vadivel Murugan failwr: 100631fb632bSRamuthevar Vadivel Murugan /* Disable interrupt. */ 100731fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 100831fb632bSRamuthevar Vadivel Murugan 100931fb632bSRamuthevar Vadivel Murugan /* Cancel the indirect write */ 101031fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 101131fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTWR); 101231fb632bSRamuthevar Vadivel Murugan return ret; 101331fb632bSRamuthevar Vadivel Murugan } 101431fb632bSRamuthevar Vadivel Murugan 101531fb632bSRamuthevar Vadivel Murugan static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata) 101631fb632bSRamuthevar Vadivel Murugan { 101731fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 101831fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 101931fb632bSRamuthevar Vadivel Murugan unsigned int chip_select = f_pdata->cs; 102031fb632bSRamuthevar Vadivel Murugan unsigned int reg; 102131fb632bSRamuthevar Vadivel Murugan 102231fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG); 102331fb632bSRamuthevar Vadivel Murugan if (cqspi->is_decoded_cs) { 102431fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CONFIG_DECODE_MASK; 102531fb632bSRamuthevar Vadivel Murugan } else { 102631fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; 102731fb632bSRamuthevar Vadivel Murugan 102831fb632bSRamuthevar Vadivel Murugan /* Convert CS if without decoder. 102931fb632bSRamuthevar Vadivel Murugan * CS0 to 4b'1110 103031fb632bSRamuthevar Vadivel Murugan * CS1 to 4b'1101 103131fb632bSRamuthevar Vadivel Murugan * CS2 to 4b'1011 103231fb632bSRamuthevar Vadivel Murugan * CS3 to 4b'0111 103331fb632bSRamuthevar Vadivel Murugan */ 103431fb632bSRamuthevar Vadivel Murugan chip_select = 0xF & ~(1 << chip_select); 103531fb632bSRamuthevar Vadivel Murugan } 103631fb632bSRamuthevar Vadivel Murugan 103731fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK 103831fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CONFIG_CHIPSELECT_LSB); 103931fb632bSRamuthevar Vadivel Murugan reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK) 104031fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CONFIG_CHIPSELECT_LSB; 104131fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG); 104231fb632bSRamuthevar Vadivel Murugan } 104331fb632bSRamuthevar Vadivel Murugan 104431fb632bSRamuthevar Vadivel Murugan static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz, 104531fb632bSRamuthevar Vadivel Murugan const unsigned int ns_val) 104631fb632bSRamuthevar Vadivel Murugan { 104731fb632bSRamuthevar Vadivel Murugan unsigned int ticks; 104831fb632bSRamuthevar Vadivel Murugan 104931fb632bSRamuthevar Vadivel Murugan ticks = ref_clk_hz / 1000; /* kHz */ 105031fb632bSRamuthevar Vadivel Murugan ticks = DIV_ROUND_UP(ticks * ns_val, 1000000); 105131fb632bSRamuthevar Vadivel Murugan 105231fb632bSRamuthevar Vadivel Murugan return ticks; 105331fb632bSRamuthevar Vadivel Murugan } 105431fb632bSRamuthevar Vadivel Murugan 105531fb632bSRamuthevar Vadivel Murugan static void cqspi_delay(struct cqspi_flash_pdata *f_pdata) 105631fb632bSRamuthevar Vadivel Murugan { 105731fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 105831fb632bSRamuthevar Vadivel Murugan void __iomem *iobase = cqspi->iobase; 105931fb632bSRamuthevar Vadivel Murugan const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 106031fb632bSRamuthevar Vadivel Murugan unsigned int tshsl, tchsh, tslch, tsd2d; 106131fb632bSRamuthevar Vadivel Murugan unsigned int reg; 106231fb632bSRamuthevar Vadivel Murugan unsigned int tsclk; 106331fb632bSRamuthevar Vadivel Murugan 106431fb632bSRamuthevar Vadivel Murugan /* calculate the number of ref ticks for one sclk tick */ 106531fb632bSRamuthevar Vadivel Murugan tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk); 106631fb632bSRamuthevar Vadivel Murugan 106731fb632bSRamuthevar Vadivel Murugan tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns); 106831fb632bSRamuthevar Vadivel Murugan /* this particular value must be at least one sclk */ 106931fb632bSRamuthevar Vadivel Murugan if (tshsl < tsclk) 107031fb632bSRamuthevar Vadivel Murugan tshsl = tsclk; 107131fb632bSRamuthevar Vadivel Murugan 107231fb632bSRamuthevar Vadivel Murugan tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns); 107331fb632bSRamuthevar Vadivel Murugan tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns); 107431fb632bSRamuthevar Vadivel Murugan tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns); 107531fb632bSRamuthevar Vadivel Murugan 107631fb632bSRamuthevar Vadivel Murugan reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK) 107731fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSHSL_LSB; 107831fb632bSRamuthevar Vadivel Murugan reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK) 107931fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TCHSH_LSB; 108031fb632bSRamuthevar Vadivel Murugan reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK) 108131fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSLCH_LSB; 108231fb632bSRamuthevar Vadivel Murugan reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK) 108331fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSD2D_LSB; 108431fb632bSRamuthevar Vadivel Murugan writel(reg, iobase + CQSPI_REG_DELAY); 108531fb632bSRamuthevar Vadivel Murugan } 108631fb632bSRamuthevar Vadivel Murugan 108731fb632bSRamuthevar Vadivel Murugan static void cqspi_config_baudrate_div(struct cqspi_st *cqspi) 108831fb632bSRamuthevar Vadivel Murugan { 108931fb632bSRamuthevar Vadivel Murugan const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 109031fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 109131fb632bSRamuthevar Vadivel Murugan u32 reg, div; 109231fb632bSRamuthevar Vadivel Murugan 109331fb632bSRamuthevar Vadivel Murugan /* Recalculate the baudrate divisor based on QSPI specification. */ 109431fb632bSRamuthevar Vadivel Murugan div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1; 109531fb632bSRamuthevar Vadivel Murugan 109631fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG); 109731fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); 109831fb632bSRamuthevar Vadivel Murugan reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB; 109931fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG); 110031fb632bSRamuthevar Vadivel Murugan } 110131fb632bSRamuthevar Vadivel Murugan 110231fb632bSRamuthevar Vadivel Murugan static void cqspi_readdata_capture(struct cqspi_st *cqspi, 110331fb632bSRamuthevar Vadivel Murugan const bool bypass, 110431fb632bSRamuthevar Vadivel Murugan const unsigned int delay) 110531fb632bSRamuthevar Vadivel Murugan { 110631fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 110731fb632bSRamuthevar Vadivel Murugan unsigned int reg; 110831fb632bSRamuthevar Vadivel Murugan 110931fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_READCAPTURE); 111031fb632bSRamuthevar Vadivel Murugan 111131fb632bSRamuthevar Vadivel Murugan if (bypass) 111231fb632bSRamuthevar Vadivel Murugan reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 111331fb632bSRamuthevar Vadivel Murugan else 111431fb632bSRamuthevar Vadivel Murugan reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 111531fb632bSRamuthevar Vadivel Murugan 111631fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK 111731fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_READCAPTURE_DELAY_LSB); 111831fb632bSRamuthevar Vadivel Murugan 111931fb632bSRamuthevar Vadivel Murugan reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK) 112031fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_READCAPTURE_DELAY_LSB; 112131fb632bSRamuthevar Vadivel Murugan 112231fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_READCAPTURE); 112331fb632bSRamuthevar Vadivel Murugan } 112431fb632bSRamuthevar Vadivel Murugan 112531fb632bSRamuthevar Vadivel Murugan static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable) 112631fb632bSRamuthevar Vadivel Murugan { 112731fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 112831fb632bSRamuthevar Vadivel Murugan unsigned int reg; 112931fb632bSRamuthevar Vadivel Murugan 113031fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG); 113131fb632bSRamuthevar Vadivel Murugan 113231fb632bSRamuthevar Vadivel Murugan if (enable) 113331fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CONFIG_ENABLE_MASK; 113431fb632bSRamuthevar Vadivel Murugan else 113531fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; 113631fb632bSRamuthevar Vadivel Murugan 113731fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG); 113831fb632bSRamuthevar Vadivel Murugan } 113931fb632bSRamuthevar Vadivel Murugan 114031fb632bSRamuthevar Vadivel Murugan static void cqspi_configure(struct cqspi_flash_pdata *f_pdata, 114131fb632bSRamuthevar Vadivel Murugan unsigned long sclk) 114231fb632bSRamuthevar Vadivel Murugan { 114331fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 114431fb632bSRamuthevar Vadivel Murugan int switch_cs = (cqspi->current_cs != f_pdata->cs); 114531fb632bSRamuthevar Vadivel Murugan int switch_ck = (cqspi->sclk != sclk); 114631fb632bSRamuthevar Vadivel Murugan 114731fb632bSRamuthevar Vadivel Murugan if (switch_cs || switch_ck) 114831fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 114931fb632bSRamuthevar Vadivel Murugan 115031fb632bSRamuthevar Vadivel Murugan /* Switch chip select. */ 115131fb632bSRamuthevar Vadivel Murugan if (switch_cs) { 115231fb632bSRamuthevar Vadivel Murugan cqspi->current_cs = f_pdata->cs; 115331fb632bSRamuthevar Vadivel Murugan cqspi_chipselect(f_pdata); 115431fb632bSRamuthevar Vadivel Murugan } 115531fb632bSRamuthevar Vadivel Murugan 115631fb632bSRamuthevar Vadivel Murugan /* Setup baudrate divisor and delays */ 115731fb632bSRamuthevar Vadivel Murugan if (switch_ck) { 115831fb632bSRamuthevar Vadivel Murugan cqspi->sclk = sclk; 115931fb632bSRamuthevar Vadivel Murugan cqspi_config_baudrate_div(cqspi); 116031fb632bSRamuthevar Vadivel Murugan cqspi_delay(f_pdata); 116131fb632bSRamuthevar Vadivel Murugan cqspi_readdata_capture(cqspi, !cqspi->rclk_en, 116231fb632bSRamuthevar Vadivel Murugan f_pdata->read_delay); 116331fb632bSRamuthevar Vadivel Murugan } 116431fb632bSRamuthevar Vadivel Murugan 116531fb632bSRamuthevar Vadivel Murugan if (switch_cs || switch_ck) 116631fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1); 116731fb632bSRamuthevar Vadivel Murugan } 116831fb632bSRamuthevar Vadivel Murugan 116931fb632bSRamuthevar Vadivel Murugan static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata, 117031fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 117131fb632bSRamuthevar Vadivel Murugan { 117231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 117331fb632bSRamuthevar Vadivel Murugan loff_t to = op->addr.val; 117431fb632bSRamuthevar Vadivel Murugan size_t len = op->data.nbytes; 117531fb632bSRamuthevar Vadivel Murugan const u_char *buf = op->data.buf.out; 117631fb632bSRamuthevar Vadivel Murugan int ret; 117731fb632bSRamuthevar Vadivel Murugan 117831fb632bSRamuthevar Vadivel Murugan ret = cqspi_write_setup(f_pdata, op); 117931fb632bSRamuthevar Vadivel Murugan if (ret) 118031fb632bSRamuthevar Vadivel Murugan return ret; 118131fb632bSRamuthevar Vadivel Murugan 1182f453f293SPratyush Yadav /* 1183f453f293SPratyush Yadav * Some flashes like the Cypress Semper flash expect a dummy 4-byte 1184f453f293SPratyush Yadav * address (all 0s) with the read status register command in DTR mode. 1185f453f293SPratyush Yadav * But this controller does not support sending dummy address bytes to 1186f453f293SPratyush Yadav * the flash when it is polling the write completion register in DTR 1187f453f293SPratyush Yadav * mode. So, we can not use direct mode when in DTR mode for writing 1188f453f293SPratyush Yadav * data. 1189f453f293SPratyush Yadav */ 119028ac902aSMatthias Schiffer if (!op->cmd.dtr && cqspi->use_direct_mode && 1191f453f293SPratyush Yadav ((to + len) <= cqspi->ahb_size)) { 119231fb632bSRamuthevar Vadivel Murugan memcpy_toio(cqspi->ahb_base + to, buf, len); 119331fb632bSRamuthevar Vadivel Murugan return cqspi_wait_idle(cqspi); 119431fb632bSRamuthevar Vadivel Murugan } 119531fb632bSRamuthevar Vadivel Murugan 119631fb632bSRamuthevar Vadivel Murugan return cqspi_indirect_write_execute(f_pdata, to, buf, len); 119731fb632bSRamuthevar Vadivel Murugan } 119831fb632bSRamuthevar Vadivel Murugan 119931fb632bSRamuthevar Vadivel Murugan static void cqspi_rx_dma_callback(void *param) 120031fb632bSRamuthevar Vadivel Murugan { 120131fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = param; 120231fb632bSRamuthevar Vadivel Murugan 120331fb632bSRamuthevar Vadivel Murugan complete(&cqspi->rx_dma_complete); 120431fb632bSRamuthevar Vadivel Murugan } 120531fb632bSRamuthevar Vadivel Murugan 120631fb632bSRamuthevar Vadivel Murugan static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata, 120731fb632bSRamuthevar Vadivel Murugan u_char *buf, loff_t from, size_t len) 120831fb632bSRamuthevar Vadivel Murugan { 120931fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 121031fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 121131fb632bSRamuthevar Vadivel Murugan enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; 121231fb632bSRamuthevar Vadivel Murugan dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from; 121331fb632bSRamuthevar Vadivel Murugan int ret = 0; 121431fb632bSRamuthevar Vadivel Murugan struct dma_async_tx_descriptor *tx; 121531fb632bSRamuthevar Vadivel Murugan dma_cookie_t cookie; 121631fb632bSRamuthevar Vadivel Murugan dma_addr_t dma_dst; 121783048015SVignesh Raghavendra struct device *ddev; 121831fb632bSRamuthevar Vadivel Murugan 121931fb632bSRamuthevar Vadivel Murugan if (!cqspi->rx_chan || !virt_addr_valid(buf)) { 122031fb632bSRamuthevar Vadivel Murugan memcpy_fromio(buf, cqspi->ahb_base + from, len); 122131fb632bSRamuthevar Vadivel Murugan return 0; 122231fb632bSRamuthevar Vadivel Murugan } 122331fb632bSRamuthevar Vadivel Murugan 122483048015SVignesh Raghavendra ddev = cqspi->rx_chan->device->dev; 122583048015SVignesh Raghavendra dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE); 122683048015SVignesh Raghavendra if (dma_mapping_error(ddev, dma_dst)) { 122731fb632bSRamuthevar Vadivel Murugan dev_err(dev, "dma mapping failed\n"); 122831fb632bSRamuthevar Vadivel Murugan return -ENOMEM; 122931fb632bSRamuthevar Vadivel Murugan } 123031fb632bSRamuthevar Vadivel Murugan tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src, 123131fb632bSRamuthevar Vadivel Murugan len, flags); 123231fb632bSRamuthevar Vadivel Murugan if (!tx) { 123331fb632bSRamuthevar Vadivel Murugan dev_err(dev, "device_prep_dma_memcpy error\n"); 123431fb632bSRamuthevar Vadivel Murugan ret = -EIO; 123531fb632bSRamuthevar Vadivel Murugan goto err_unmap; 123631fb632bSRamuthevar Vadivel Murugan } 123731fb632bSRamuthevar Vadivel Murugan 123831fb632bSRamuthevar Vadivel Murugan tx->callback = cqspi_rx_dma_callback; 123931fb632bSRamuthevar Vadivel Murugan tx->callback_param = cqspi; 124031fb632bSRamuthevar Vadivel Murugan cookie = tx->tx_submit(tx); 124131fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->rx_dma_complete); 124231fb632bSRamuthevar Vadivel Murugan 124331fb632bSRamuthevar Vadivel Murugan ret = dma_submit_error(cookie); 124431fb632bSRamuthevar Vadivel Murugan if (ret) { 124531fb632bSRamuthevar Vadivel Murugan dev_err(dev, "dma_submit_error %d\n", cookie); 124631fb632bSRamuthevar Vadivel Murugan ret = -EIO; 124731fb632bSRamuthevar Vadivel Murugan goto err_unmap; 124831fb632bSRamuthevar Vadivel Murugan } 124931fb632bSRamuthevar Vadivel Murugan 125031fb632bSRamuthevar Vadivel Murugan dma_async_issue_pending(cqspi->rx_chan); 125131fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->rx_dma_complete, 12522ef0170eSPratyush Yadav msecs_to_jiffies(max_t(size_t, len, 500)))) { 125331fb632bSRamuthevar Vadivel Murugan dmaengine_terminate_sync(cqspi->rx_chan); 125431fb632bSRamuthevar Vadivel Murugan dev_err(dev, "DMA wait_for_completion_timeout\n"); 125531fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 125631fb632bSRamuthevar Vadivel Murugan goto err_unmap; 125731fb632bSRamuthevar Vadivel Murugan } 125831fb632bSRamuthevar Vadivel Murugan 125931fb632bSRamuthevar Vadivel Murugan err_unmap: 126083048015SVignesh Raghavendra dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE); 126131fb632bSRamuthevar Vadivel Murugan 126231fb632bSRamuthevar Vadivel Murugan return ret; 126331fb632bSRamuthevar Vadivel Murugan } 126431fb632bSRamuthevar Vadivel Murugan 126531fb632bSRamuthevar Vadivel Murugan static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata, 126631fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 126731fb632bSRamuthevar Vadivel Murugan { 126831fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 12691a6f854fSSai Krishna Potthuri struct device *dev = &cqspi->pdev->dev; 12701a6f854fSSai Krishna Potthuri const struct cqspi_driver_platdata *ddata; 127131fb632bSRamuthevar Vadivel Murugan loff_t from = op->addr.val; 127231fb632bSRamuthevar Vadivel Murugan size_t len = op->data.nbytes; 127331fb632bSRamuthevar Vadivel Murugan u_char *buf = op->data.buf.in; 12741a6f854fSSai Krishna Potthuri u64 dma_align = (u64)(uintptr_t)buf; 127531fb632bSRamuthevar Vadivel Murugan int ret; 127631fb632bSRamuthevar Vadivel Murugan 12771a6f854fSSai Krishna Potthuri ddata = of_device_get_match_data(dev); 127831fb632bSRamuthevar Vadivel Murugan 127931fb632bSRamuthevar Vadivel Murugan ret = cqspi_read_setup(f_pdata, op); 128031fb632bSRamuthevar Vadivel Murugan if (ret) 128131fb632bSRamuthevar Vadivel Murugan return ret; 128231fb632bSRamuthevar Vadivel Murugan 128331fb632bSRamuthevar Vadivel Murugan if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) 128431fb632bSRamuthevar Vadivel Murugan return cqspi_direct_read_execute(f_pdata, buf, from, len); 128531fb632bSRamuthevar Vadivel Murugan 12861a6f854fSSai Krishna Potthuri if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma && 12871a6f854fSSai Krishna Potthuri virt_addr_valid(buf) && ((dma_align & CQSPI_DMA_UNALIGN) == 0)) 12881a6f854fSSai Krishna Potthuri return ddata->indirect_read_dma(f_pdata, buf, from, len); 12891a6f854fSSai Krishna Potthuri 129031fb632bSRamuthevar Vadivel Murugan return cqspi_indirect_read_execute(f_pdata, buf, from, len); 129131fb632bSRamuthevar Vadivel Murugan } 129231fb632bSRamuthevar Vadivel Murugan 129331fb632bSRamuthevar Vadivel Murugan static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op) 129431fb632bSRamuthevar Vadivel Murugan { 129531fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); 129631fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata; 129731fb632bSRamuthevar Vadivel Murugan 129831fb632bSRamuthevar Vadivel Murugan f_pdata = &cqspi->f_pdata[mem->spi->chip_select]; 129931fb632bSRamuthevar Vadivel Murugan cqspi_configure(f_pdata, mem->spi->max_speed_hz); 130031fb632bSRamuthevar Vadivel Murugan 130131fb632bSRamuthevar Vadivel Murugan if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { 130231fb632bSRamuthevar Vadivel Murugan if (!op->addr.nbytes) 130331fb632bSRamuthevar Vadivel Murugan return cqspi_command_read(f_pdata, op); 130431fb632bSRamuthevar Vadivel Murugan 130531fb632bSRamuthevar Vadivel Murugan return cqspi_read(f_pdata, op); 130631fb632bSRamuthevar Vadivel Murugan } 130731fb632bSRamuthevar Vadivel Murugan 130831fb632bSRamuthevar Vadivel Murugan if (!op->addr.nbytes || !op->data.buf.out) 130931fb632bSRamuthevar Vadivel Murugan return cqspi_command_write(f_pdata, op); 131031fb632bSRamuthevar Vadivel Murugan 131131fb632bSRamuthevar Vadivel Murugan return cqspi_write(f_pdata, op); 131231fb632bSRamuthevar Vadivel Murugan } 131331fb632bSRamuthevar Vadivel Murugan 131431fb632bSRamuthevar Vadivel Murugan static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) 131531fb632bSRamuthevar Vadivel Murugan { 131631fb632bSRamuthevar Vadivel Murugan int ret; 131731fb632bSRamuthevar Vadivel Murugan 131831fb632bSRamuthevar Vadivel Murugan ret = cqspi_mem_process(mem, op); 131931fb632bSRamuthevar Vadivel Murugan if (ret) 132031fb632bSRamuthevar Vadivel Murugan dev_err(&mem->spi->dev, "operation failed with %d\n", ret); 132131fb632bSRamuthevar Vadivel Murugan 132231fb632bSRamuthevar Vadivel Murugan return ret; 132331fb632bSRamuthevar Vadivel Murugan } 132431fb632bSRamuthevar Vadivel Murugan 1325a273596bSPratyush Yadav static bool cqspi_supports_mem_op(struct spi_mem *mem, 1326a273596bSPratyush Yadav const struct spi_mem_op *op) 1327a273596bSPratyush Yadav { 1328f453f293SPratyush Yadav bool all_true, all_false; 1329f453f293SPratyush Yadav 13300395be96SApurva Nandan /* 13310395be96SApurva Nandan * op->dummy.dtr is required for converting nbytes into ncycles. 13320395be96SApurva Nandan * Also, don't check the dtr field of the op phase having zero nbytes. 13330395be96SApurva Nandan */ 13340395be96SApurva Nandan all_true = op->cmd.dtr && 13350395be96SApurva Nandan (!op->addr.nbytes || op->addr.dtr) && 13360395be96SApurva Nandan (!op->dummy.nbytes || op->dummy.dtr) && 13370395be96SApurva Nandan (!op->data.nbytes || op->data.dtr); 13380395be96SApurva Nandan 1339f453f293SPratyush Yadav all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && 1340f453f293SPratyush Yadav !op->data.dtr; 1341f453f293SPratyush Yadav 1342f1d388f2SMatthias Schiffer if (all_true) { 1343f1d388f2SMatthias Schiffer /* Right now we only support 8-8-8 DTR mode. */ 1344f1d388f2SMatthias Schiffer if (op->cmd.nbytes && op->cmd.buswidth != 8) 1345f453f293SPratyush Yadav return false; 1346f1d388f2SMatthias Schiffer if (op->addr.nbytes && op->addr.buswidth != 8) 1347f1d388f2SMatthias Schiffer return false; 1348f1d388f2SMatthias Schiffer if (op->data.nbytes && op->data.buswidth != 8) 1349f1d388f2SMatthias Schiffer return false; 13501aeda096SMatthias Schiffer } else if (!all_false) { 1351f1d388f2SMatthias Schiffer /* Mixed DTR modes are not supported. */ 1352f1d388f2SMatthias Schiffer return false; 1353f1d388f2SMatthias Schiffer } 1354f453f293SPratyush Yadav 1355d2275139SPratyush Yadav return spi_mem_default_supports_op(mem, op); 1356a273596bSPratyush Yadav } 1357a273596bSPratyush Yadav 135831fb632bSRamuthevar Vadivel Murugan static int cqspi_of_get_flash_pdata(struct platform_device *pdev, 135931fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata, 136031fb632bSRamuthevar Vadivel Murugan struct device_node *np) 136131fb632bSRamuthevar Vadivel Murugan { 136231fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) { 136331fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine read-delay\n"); 136431fb632bSRamuthevar Vadivel Murugan return -ENXIO; 136531fb632bSRamuthevar Vadivel Murugan } 136631fb632bSRamuthevar Vadivel Murugan 136731fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) { 136831fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tshsl-ns\n"); 136931fb632bSRamuthevar Vadivel Murugan return -ENXIO; 137031fb632bSRamuthevar Vadivel Murugan } 137131fb632bSRamuthevar Vadivel Murugan 137231fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) { 137331fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n"); 137431fb632bSRamuthevar Vadivel Murugan return -ENXIO; 137531fb632bSRamuthevar Vadivel Murugan } 137631fb632bSRamuthevar Vadivel Murugan 137731fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) { 137831fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tchsh-ns\n"); 137931fb632bSRamuthevar Vadivel Murugan return -ENXIO; 138031fb632bSRamuthevar Vadivel Murugan } 138131fb632bSRamuthevar Vadivel Murugan 138231fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) { 138331fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tslch-ns\n"); 138431fb632bSRamuthevar Vadivel Murugan return -ENXIO; 138531fb632bSRamuthevar Vadivel Murugan } 138631fb632bSRamuthevar Vadivel Murugan 138731fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) { 138831fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n"); 138931fb632bSRamuthevar Vadivel Murugan return -ENXIO; 139031fb632bSRamuthevar Vadivel Murugan } 139131fb632bSRamuthevar Vadivel Murugan 139231fb632bSRamuthevar Vadivel Murugan return 0; 139331fb632bSRamuthevar Vadivel Murugan } 139431fb632bSRamuthevar Vadivel Murugan 139531fb632bSRamuthevar Vadivel Murugan static int cqspi_of_get_pdata(struct cqspi_st *cqspi) 139631fb632bSRamuthevar Vadivel Murugan { 139731fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 139831fb632bSRamuthevar Vadivel Murugan struct device_node *np = dev->of_node; 139909e393e3SSai Krishna Potthuri u32 id[2]; 140031fb632bSRamuthevar Vadivel Murugan 140131fb632bSRamuthevar Vadivel Murugan cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); 140231fb632bSRamuthevar Vadivel Murugan 140331fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { 140431fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine fifo-depth\n"); 140531fb632bSRamuthevar Vadivel Murugan return -ENXIO; 140631fb632bSRamuthevar Vadivel Murugan } 140731fb632bSRamuthevar Vadivel Murugan 140831fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) { 140931fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine fifo-width\n"); 141031fb632bSRamuthevar Vadivel Murugan return -ENXIO; 141131fb632bSRamuthevar Vadivel Murugan } 141231fb632bSRamuthevar Vadivel Murugan 141331fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,trigger-address", 141431fb632bSRamuthevar Vadivel Murugan &cqspi->trigger_address)) { 141531fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine trigger-address\n"); 141631fb632bSRamuthevar Vadivel Murugan return -ENXIO; 141731fb632bSRamuthevar Vadivel Murugan } 141831fb632bSRamuthevar Vadivel Murugan 1419b436fb7dSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) 1420b436fb7dSRamuthevar Vadivel Murugan cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT; 1421b436fb7dSRamuthevar Vadivel Murugan 142231fb632bSRamuthevar Vadivel Murugan cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); 142331fb632bSRamuthevar Vadivel Murugan 142409e393e3SSai Krishna Potthuri if (!of_property_read_u32_array(np, "power-domains", id, 142509e393e3SSai Krishna Potthuri ARRAY_SIZE(id))) 142609e393e3SSai Krishna Potthuri cqspi->pd_dev_id = id[1]; 142709e393e3SSai Krishna Potthuri 142831fb632bSRamuthevar Vadivel Murugan return 0; 142931fb632bSRamuthevar Vadivel Murugan } 143031fb632bSRamuthevar Vadivel Murugan 143131fb632bSRamuthevar Vadivel Murugan static void cqspi_controller_init(struct cqspi_st *cqspi) 143231fb632bSRamuthevar Vadivel Murugan { 143331fb632bSRamuthevar Vadivel Murugan u32 reg; 143431fb632bSRamuthevar Vadivel Murugan 143531fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 143631fb632bSRamuthevar Vadivel Murugan 143731fb632bSRamuthevar Vadivel Murugan /* Configure the remap address register, no remap */ 143831fb632bSRamuthevar Vadivel Murugan writel(0, cqspi->iobase + CQSPI_REG_REMAP); 143931fb632bSRamuthevar Vadivel Murugan 144031fb632bSRamuthevar Vadivel Murugan /* Disable all interrupts. */ 144131fb632bSRamuthevar Vadivel Murugan writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); 144231fb632bSRamuthevar Vadivel Murugan 144331fb632bSRamuthevar Vadivel Murugan /* Configure the SRAM split to 1:1 . */ 144431fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); 144531fb632bSRamuthevar Vadivel Murugan 144631fb632bSRamuthevar Vadivel Murugan /* Load indirect trigger address. */ 144731fb632bSRamuthevar Vadivel Murugan writel(cqspi->trigger_address, 144831fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); 144931fb632bSRamuthevar Vadivel Murugan 145031fb632bSRamuthevar Vadivel Murugan /* Program read watermark -- 1/2 of the FIFO. */ 145131fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth * cqspi->fifo_width / 2, 145231fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); 145331fb632bSRamuthevar Vadivel Murugan /* Program write watermark -- 1/8 of the FIFO. */ 145431fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth * cqspi->fifo_width / 8, 145531fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); 145631fb632bSRamuthevar Vadivel Murugan 1457ad2775dcSRamuthevar Vadivel Murugan /* Disable direct access controller */ 1458ad2775dcSRamuthevar Vadivel Murugan if (!cqspi->use_direct_mode) { 145931fb632bSRamuthevar Vadivel Murugan reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 1460ad2775dcSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL; 146131fb632bSRamuthevar Vadivel Murugan writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 1462ad2775dcSRamuthevar Vadivel Murugan } 146331fb632bSRamuthevar Vadivel Murugan 14641a6f854fSSai Krishna Potthuri /* Enable DMA interface */ 14651a6f854fSSai Krishna Potthuri if (cqspi->use_dma_read) { 14661a6f854fSSai Krishna Potthuri reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 14671a6f854fSSai Krishna Potthuri reg |= CQSPI_REG_CONFIG_DMA_MASK; 14681a6f854fSSai Krishna Potthuri writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 14691a6f854fSSai Krishna Potthuri } 14701a6f854fSSai Krishna Potthuri 147131fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1); 147231fb632bSRamuthevar Vadivel Murugan } 147331fb632bSRamuthevar Vadivel Murugan 147431fb632bSRamuthevar Vadivel Murugan static int cqspi_request_mmap_dma(struct cqspi_st *cqspi) 147531fb632bSRamuthevar Vadivel Murugan { 147631fb632bSRamuthevar Vadivel Murugan dma_cap_mask_t mask; 147731fb632bSRamuthevar Vadivel Murugan 147831fb632bSRamuthevar Vadivel Murugan dma_cap_zero(mask); 147931fb632bSRamuthevar Vadivel Murugan dma_cap_set(DMA_MEMCPY, mask); 148031fb632bSRamuthevar Vadivel Murugan 148131fb632bSRamuthevar Vadivel Murugan cqspi->rx_chan = dma_request_chan_by_mask(&mask); 148231fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->rx_chan)) { 148331fb632bSRamuthevar Vadivel Murugan int ret = PTR_ERR(cqspi->rx_chan); 148476159e2fSIan Abbott 148531fb632bSRamuthevar Vadivel Murugan cqspi->rx_chan = NULL; 1486436a5c20SKrzysztof Kozlowski return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n"); 148731fb632bSRamuthevar Vadivel Murugan } 148831fb632bSRamuthevar Vadivel Murugan init_completion(&cqspi->rx_dma_complete); 148931fb632bSRamuthevar Vadivel Murugan 149031fb632bSRamuthevar Vadivel Murugan return 0; 149131fb632bSRamuthevar Vadivel Murugan } 149231fb632bSRamuthevar Vadivel Murugan 14932ea370a9SVignesh Raghavendra static const char *cqspi_get_name(struct spi_mem *mem) 14942ea370a9SVignesh Raghavendra { 14952ea370a9SVignesh Raghavendra struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); 14962ea370a9SVignesh Raghavendra struct device *dev = &cqspi->pdev->dev; 14972ea370a9SVignesh Raghavendra 14982ea370a9SVignesh Raghavendra return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select); 14992ea370a9SVignesh Raghavendra } 15002ea370a9SVignesh Raghavendra 150131fb632bSRamuthevar Vadivel Murugan static const struct spi_controller_mem_ops cqspi_mem_ops = { 150231fb632bSRamuthevar Vadivel Murugan .exec_op = cqspi_exec_mem_op, 15032ea370a9SVignesh Raghavendra .get_name = cqspi_get_name, 1504a273596bSPratyush Yadav .supports_op = cqspi_supports_mem_op, 150531fb632bSRamuthevar Vadivel Murugan }; 150631fb632bSRamuthevar Vadivel Murugan 1507a9be4549SMiquel Raynal static const struct spi_controller_mem_caps cqspi_mem_caps = { 1508a9be4549SMiquel Raynal .dtr = true, 1509a9be4549SMiquel Raynal }; 1510a9be4549SMiquel Raynal 151131fb632bSRamuthevar Vadivel Murugan static int cqspi_setup_flash(struct cqspi_st *cqspi) 151231fb632bSRamuthevar Vadivel Murugan { 151331fb632bSRamuthevar Vadivel Murugan struct platform_device *pdev = cqspi->pdev; 151431fb632bSRamuthevar Vadivel Murugan struct device *dev = &pdev->dev; 151531fb632bSRamuthevar Vadivel Murugan struct device_node *np = dev->of_node; 151631fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata; 151731fb632bSRamuthevar Vadivel Murugan unsigned int cs; 151831fb632bSRamuthevar Vadivel Murugan int ret; 151931fb632bSRamuthevar Vadivel Murugan 152031fb632bSRamuthevar Vadivel Murugan /* Get flash device data */ 152131fb632bSRamuthevar Vadivel Murugan for_each_available_child_of_node(dev->of_node, np) { 152231fb632bSRamuthevar Vadivel Murugan ret = of_property_read_u32(np, "reg", &cs); 152331fb632bSRamuthevar Vadivel Murugan if (ret) { 152431fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Couldn't determine chip select.\n"); 152587d62d8fSJunlin Yang of_node_put(np); 152631fb632bSRamuthevar Vadivel Murugan return ret; 152731fb632bSRamuthevar Vadivel Murugan } 152831fb632bSRamuthevar Vadivel Murugan 152931fb632bSRamuthevar Vadivel Murugan if (cs >= CQSPI_MAX_CHIPSELECT) { 153031fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Chip select %d out of range.\n", cs); 153187d62d8fSJunlin Yang of_node_put(np); 153231fb632bSRamuthevar Vadivel Murugan return -EINVAL; 153331fb632bSRamuthevar Vadivel Murugan } 153431fb632bSRamuthevar Vadivel Murugan 153531fb632bSRamuthevar Vadivel Murugan f_pdata = &cqspi->f_pdata[cs]; 153631fb632bSRamuthevar Vadivel Murugan f_pdata->cqspi = cqspi; 153731fb632bSRamuthevar Vadivel Murugan f_pdata->cs = cs; 153831fb632bSRamuthevar Vadivel Murugan 153931fb632bSRamuthevar Vadivel Murugan ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np); 154087d62d8fSJunlin Yang if (ret) { 154187d62d8fSJunlin Yang of_node_put(np); 154231fb632bSRamuthevar Vadivel Murugan return ret; 154331fb632bSRamuthevar Vadivel Murugan } 154487d62d8fSJunlin Yang } 154531fb632bSRamuthevar Vadivel Murugan 154631fb632bSRamuthevar Vadivel Murugan return 0; 154731fb632bSRamuthevar Vadivel Murugan } 154831fb632bSRamuthevar Vadivel Murugan 154931fb632bSRamuthevar Vadivel Murugan static int cqspi_probe(struct platform_device *pdev) 155031fb632bSRamuthevar Vadivel Murugan { 155131fb632bSRamuthevar Vadivel Murugan const struct cqspi_driver_platdata *ddata; 155231fb632bSRamuthevar Vadivel Murugan struct reset_control *rstc, *rstc_ocp; 155331fb632bSRamuthevar Vadivel Murugan struct device *dev = &pdev->dev; 155431fb632bSRamuthevar Vadivel Murugan struct spi_master *master; 155531fb632bSRamuthevar Vadivel Murugan struct resource *res_ahb; 155631fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi; 155731fb632bSRamuthevar Vadivel Murugan struct resource *res; 155831fb632bSRamuthevar Vadivel Murugan int ret; 155931fb632bSRamuthevar Vadivel Murugan int irq; 156031fb632bSRamuthevar Vadivel Murugan 1561*606e5d40SVaishnav Achath master = devm_spi_alloc_master(&pdev->dev, sizeof(*cqspi)); 156231fb632bSRamuthevar Vadivel Murugan if (!master) { 156331fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "spi_alloc_master failed\n"); 156431fb632bSRamuthevar Vadivel Murugan return -ENOMEM; 156531fb632bSRamuthevar Vadivel Murugan } 156631fb632bSRamuthevar Vadivel Murugan master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; 156731fb632bSRamuthevar Vadivel Murugan master->mem_ops = &cqspi_mem_ops; 1568a9be4549SMiquel Raynal master->mem_caps = &cqspi_mem_caps; 156931fb632bSRamuthevar Vadivel Murugan master->dev.of_node = pdev->dev.of_node; 157031fb632bSRamuthevar Vadivel Murugan 157131fb632bSRamuthevar Vadivel Murugan cqspi = spi_master_get_devdata(master); 157231fb632bSRamuthevar Vadivel Murugan 157331fb632bSRamuthevar Vadivel Murugan cqspi->pdev = pdev; 1574*606e5d40SVaishnav Achath cqspi->master = master; 1575ea94191eSMeng Li platform_set_drvdata(pdev, cqspi); 157631fb632bSRamuthevar Vadivel Murugan 157731fb632bSRamuthevar Vadivel Murugan /* Obtain configuration from OF. */ 157831fb632bSRamuthevar Vadivel Murugan ret = cqspi_of_get_pdata(cqspi); 157931fb632bSRamuthevar Vadivel Murugan if (ret) { 158031fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get mandatory OF data.\n"); 158131fb632bSRamuthevar Vadivel Murugan ret = -ENODEV; 158231fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 158331fb632bSRamuthevar Vadivel Murugan } 158431fb632bSRamuthevar Vadivel Murugan 158531fb632bSRamuthevar Vadivel Murugan /* Obtain QSPI clock. */ 158631fb632bSRamuthevar Vadivel Murugan cqspi->clk = devm_clk_get(dev, NULL); 158731fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->clk)) { 158831fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot claim QSPI clock.\n"); 158931fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->clk); 159031fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 159131fb632bSRamuthevar Vadivel Murugan } 159231fb632bSRamuthevar Vadivel Murugan 159331fb632bSRamuthevar Vadivel Murugan /* Obtain and remap controller address. */ 159431fb632bSRamuthevar Vadivel Murugan res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 159531fb632bSRamuthevar Vadivel Murugan cqspi->iobase = devm_ioremap_resource(dev, res); 159631fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->iobase)) { 159731fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot remap controller address.\n"); 159831fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->iobase); 159931fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 160031fb632bSRamuthevar Vadivel Murugan } 160131fb632bSRamuthevar Vadivel Murugan 160231fb632bSRamuthevar Vadivel Murugan /* Obtain and remap AHB address. */ 160331fb632bSRamuthevar Vadivel Murugan res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1); 160431fb632bSRamuthevar Vadivel Murugan cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb); 160531fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->ahb_base)) { 160631fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot remap AHB address.\n"); 160731fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->ahb_base); 160831fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 160931fb632bSRamuthevar Vadivel Murugan } 161031fb632bSRamuthevar Vadivel Murugan cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start; 161131fb632bSRamuthevar Vadivel Murugan cqspi->ahb_size = resource_size(res_ahb); 161231fb632bSRamuthevar Vadivel Murugan 161331fb632bSRamuthevar Vadivel Murugan init_completion(&cqspi->transfer_complete); 161431fb632bSRamuthevar Vadivel Murugan 161531fb632bSRamuthevar Vadivel Murugan /* Obtain IRQ line. */ 161631fb632bSRamuthevar Vadivel Murugan irq = platform_get_irq(pdev, 0); 161731fb632bSRamuthevar Vadivel Murugan if (irq < 0) { 161831fb632bSRamuthevar Vadivel Murugan ret = -ENXIO; 161931fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 162031fb632bSRamuthevar Vadivel Murugan } 162131fb632bSRamuthevar Vadivel Murugan 162231fb632bSRamuthevar Vadivel Murugan pm_runtime_enable(dev); 1623b7be05d5SMinghao Chi ret = pm_runtime_resume_and_get(dev); 1624b7be05d5SMinghao Chi if (ret < 0) 162531fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 162631fb632bSRamuthevar Vadivel Murugan 162731fb632bSRamuthevar Vadivel Murugan ret = clk_prepare_enable(cqspi->clk); 162831fb632bSRamuthevar Vadivel Murugan if (ret) { 162931fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot enable QSPI clock.\n"); 163031fb632bSRamuthevar Vadivel Murugan goto probe_clk_failed; 163131fb632bSRamuthevar Vadivel Murugan } 163231fb632bSRamuthevar Vadivel Murugan 163331fb632bSRamuthevar Vadivel Murugan /* Obtain QSPI reset control */ 163431fb632bSRamuthevar Vadivel Murugan rstc = devm_reset_control_get_optional_exclusive(dev, "qspi"); 163531fb632bSRamuthevar Vadivel Murugan if (IS_ERR(rstc)) { 1636ac9978fcSZhihao Cheng ret = PTR_ERR(rstc); 163731fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get QSPI reset.\n"); 163831fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 163931fb632bSRamuthevar Vadivel Murugan } 164031fb632bSRamuthevar Vadivel Murugan 164131fb632bSRamuthevar Vadivel Murugan rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); 164231fb632bSRamuthevar Vadivel Murugan if (IS_ERR(rstc_ocp)) { 1643ac9978fcSZhihao Cheng ret = PTR_ERR(rstc_ocp); 164431fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get QSPI OCP reset.\n"); 164531fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 164631fb632bSRamuthevar Vadivel Murugan } 164731fb632bSRamuthevar Vadivel Murugan 164831fb632bSRamuthevar Vadivel Murugan reset_control_assert(rstc); 164931fb632bSRamuthevar Vadivel Murugan reset_control_deassert(rstc); 165031fb632bSRamuthevar Vadivel Murugan 165131fb632bSRamuthevar Vadivel Murugan reset_control_assert(rstc_ocp); 165231fb632bSRamuthevar Vadivel Murugan reset_control_deassert(rstc_ocp); 165331fb632bSRamuthevar Vadivel Murugan 165431fb632bSRamuthevar Vadivel Murugan cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); 16553a5c09c8SPratyush Yadav master->max_speed_hz = cqspi->master_ref_clk_hz; 165698d948ebSDinh Nguyen 165798d948ebSDinh Nguyen /* write completion is supported by default */ 165898d948ebSDinh Nguyen cqspi->wr_completion = true; 165998d948ebSDinh Nguyen 166031fb632bSRamuthevar Vadivel Murugan ddata = of_device_get_match_data(dev); 166131fb632bSRamuthevar Vadivel Murugan if (ddata) { 166231fb632bSRamuthevar Vadivel Murugan if (ddata->quirks & CQSPI_NEEDS_WR_DELAY) 1663f453f293SPratyush Yadav cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, 166431fb632bSRamuthevar Vadivel Murugan cqspi->master_ref_clk_hz); 166531fb632bSRamuthevar Vadivel Murugan if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL) 1666f453f293SPratyush Yadav master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; 166731fb632bSRamuthevar Vadivel Murugan if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) 166831fb632bSRamuthevar Vadivel Murugan cqspi->use_direct_mode = true; 16691a6f854fSSai Krishna Potthuri if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA) 16701a6f854fSSai Krishna Potthuri cqspi->use_dma_read = true; 167198d948ebSDinh Nguyen if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION) 167298d948ebSDinh Nguyen cqspi->wr_completion = false; 16731a6f854fSSai Krishna Potthuri 167409e393e3SSai Krishna Potthuri if (of_device_is_compatible(pdev->dev.of_node, 16751a6f854fSSai Krishna Potthuri "xlnx,versal-ospi-1.0")) 16761a6f854fSSai Krishna Potthuri dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); 167731fb632bSRamuthevar Vadivel Murugan } 167831fb632bSRamuthevar Vadivel Murugan 167931fb632bSRamuthevar Vadivel Murugan ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0, 168031fb632bSRamuthevar Vadivel Murugan pdev->name, cqspi); 168131fb632bSRamuthevar Vadivel Murugan if (ret) { 168231fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot request IRQ.\n"); 168331fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 168431fb632bSRamuthevar Vadivel Murugan } 168531fb632bSRamuthevar Vadivel Murugan 168631fb632bSRamuthevar Vadivel Murugan cqspi_wait_idle(cqspi); 168731fb632bSRamuthevar Vadivel Murugan cqspi_controller_init(cqspi); 168831fb632bSRamuthevar Vadivel Murugan cqspi->current_cs = -1; 168931fb632bSRamuthevar Vadivel Murugan cqspi->sclk = 0; 169031fb632bSRamuthevar Vadivel Murugan 1691b436fb7dSRamuthevar Vadivel Murugan master->num_chipselect = cqspi->num_chipselect; 1692b436fb7dSRamuthevar Vadivel Murugan 169331fb632bSRamuthevar Vadivel Murugan ret = cqspi_setup_flash(cqspi); 169431fb632bSRamuthevar Vadivel Murugan if (ret) { 169531fb632bSRamuthevar Vadivel Murugan dev_err(dev, "failed to setup flash parameters %d\n", ret); 169631fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 169731fb632bSRamuthevar Vadivel Murugan } 169831fb632bSRamuthevar Vadivel Murugan 169931fb632bSRamuthevar Vadivel Murugan if (cqspi->use_direct_mode) { 170031fb632bSRamuthevar Vadivel Murugan ret = cqspi_request_mmap_dma(cqspi); 170131fb632bSRamuthevar Vadivel Murugan if (ret == -EPROBE_DEFER) 170231fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 170331fb632bSRamuthevar Vadivel Murugan } 170431fb632bSRamuthevar Vadivel Murugan 1705*606e5d40SVaishnav Achath ret = spi_register_master(master); 170631fb632bSRamuthevar Vadivel Murugan if (ret) { 170731fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret); 170831fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 170931fb632bSRamuthevar Vadivel Murugan } 171031fb632bSRamuthevar Vadivel Murugan 171131fb632bSRamuthevar Vadivel Murugan return 0; 171231fb632bSRamuthevar Vadivel Murugan probe_setup_failed: 171331fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 171431fb632bSRamuthevar Vadivel Murugan probe_reset_failed: 171531fb632bSRamuthevar Vadivel Murugan clk_disable_unprepare(cqspi->clk); 171631fb632bSRamuthevar Vadivel Murugan probe_clk_failed: 171731fb632bSRamuthevar Vadivel Murugan pm_runtime_put_sync(dev); 171831fb632bSRamuthevar Vadivel Murugan pm_runtime_disable(dev); 171931fb632bSRamuthevar Vadivel Murugan probe_master_put: 172031fb632bSRamuthevar Vadivel Murugan spi_master_put(master); 172131fb632bSRamuthevar Vadivel Murugan return ret; 172231fb632bSRamuthevar Vadivel Murugan } 172331fb632bSRamuthevar Vadivel Murugan 172431fb632bSRamuthevar Vadivel Murugan static int cqspi_remove(struct platform_device *pdev) 172531fb632bSRamuthevar Vadivel Murugan { 172631fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = platform_get_drvdata(pdev); 172731fb632bSRamuthevar Vadivel Murugan 1728*606e5d40SVaishnav Achath spi_unregister_master(cqspi->master); 172931fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 173031fb632bSRamuthevar Vadivel Murugan 173131fb632bSRamuthevar Vadivel Murugan if (cqspi->rx_chan) 173231fb632bSRamuthevar Vadivel Murugan dma_release_channel(cqspi->rx_chan); 173331fb632bSRamuthevar Vadivel Murugan 173431fb632bSRamuthevar Vadivel Murugan clk_disable_unprepare(cqspi->clk); 173531fb632bSRamuthevar Vadivel Murugan 173631fb632bSRamuthevar Vadivel Murugan pm_runtime_put_sync(&pdev->dev); 173731fb632bSRamuthevar Vadivel Murugan pm_runtime_disable(&pdev->dev); 173831fb632bSRamuthevar Vadivel Murugan 173931fb632bSRamuthevar Vadivel Murugan return 0; 174031fb632bSRamuthevar Vadivel Murugan } 174131fb632bSRamuthevar Vadivel Murugan 174231fb632bSRamuthevar Vadivel Murugan #ifdef CONFIG_PM_SLEEP 174331fb632bSRamuthevar Vadivel Murugan static int cqspi_suspend(struct device *dev) 174431fb632bSRamuthevar Vadivel Murugan { 174531fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev_get_drvdata(dev); 174631fb632bSRamuthevar Vadivel Murugan 174731fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 174831fb632bSRamuthevar Vadivel Murugan return 0; 174931fb632bSRamuthevar Vadivel Murugan } 175031fb632bSRamuthevar Vadivel Murugan 175131fb632bSRamuthevar Vadivel Murugan static int cqspi_resume(struct device *dev) 175231fb632bSRamuthevar Vadivel Murugan { 175331fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev_get_drvdata(dev); 175431fb632bSRamuthevar Vadivel Murugan 175531fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1); 175631fb632bSRamuthevar Vadivel Murugan return 0; 175731fb632bSRamuthevar Vadivel Murugan } 175831fb632bSRamuthevar Vadivel Murugan 175931fb632bSRamuthevar Vadivel Murugan static const struct dev_pm_ops cqspi__dev_pm_ops = { 176031fb632bSRamuthevar Vadivel Murugan .suspend = cqspi_suspend, 176131fb632bSRamuthevar Vadivel Murugan .resume = cqspi_resume, 176231fb632bSRamuthevar Vadivel Murugan }; 176331fb632bSRamuthevar Vadivel Murugan 176431fb632bSRamuthevar Vadivel Murugan #define CQSPI_DEV_PM_OPS (&cqspi__dev_pm_ops) 176531fb632bSRamuthevar Vadivel Murugan #else 176631fb632bSRamuthevar Vadivel Murugan #define CQSPI_DEV_PM_OPS NULL 176731fb632bSRamuthevar Vadivel Murugan #endif 176831fb632bSRamuthevar Vadivel Murugan 176931fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata cdns_qspi = { 177031fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_DISABLE_DAC_MODE, 177131fb632bSRamuthevar Vadivel Murugan }; 177231fb632bSRamuthevar Vadivel Murugan 177331fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata k2g_qspi = { 177431fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_NEEDS_WR_DELAY, 177531fb632bSRamuthevar Vadivel Murugan }; 177631fb632bSRamuthevar Vadivel Murugan 177731fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata am654_ospi = { 177831fb632bSRamuthevar Vadivel Murugan .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 177931fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_NEEDS_WR_DELAY, 178031fb632bSRamuthevar Vadivel Murugan }; 178131fb632bSRamuthevar Vadivel Murugan 1782ad2775dcSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata intel_lgm_qspi = { 1783ad2775dcSRamuthevar Vadivel Murugan .quirks = CQSPI_DISABLE_DAC_MODE, 1784ad2775dcSRamuthevar Vadivel Murugan }; 1785ad2775dcSRamuthevar Vadivel Murugan 178698d948ebSDinh Nguyen static const struct cqspi_driver_platdata socfpga_qspi = { 1787f724c296SIan Abbott .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_NO_SUPPORT_WR_COMPLETION, 178898d948ebSDinh Nguyen }; 178998d948ebSDinh Nguyen 179009e393e3SSai Krishna Potthuri static const struct cqspi_driver_platdata versal_ospi = { 179109e393e3SSai Krishna Potthuri .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 17921a6f854fSSai Krishna Potthuri .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA, 17931a6f854fSSai Krishna Potthuri .indirect_read_dma = cqspi_versal_indirect_read_dma, 17941a6f854fSSai Krishna Potthuri .get_dma_status = cqspi_get_versal_dma_status, 179509e393e3SSai Krishna Potthuri }; 179609e393e3SSai Krishna Potthuri 179731fb632bSRamuthevar Vadivel Murugan static const struct of_device_id cqspi_dt_ids[] = { 179831fb632bSRamuthevar Vadivel Murugan { 179931fb632bSRamuthevar Vadivel Murugan .compatible = "cdns,qspi-nor", 180031fb632bSRamuthevar Vadivel Murugan .data = &cdns_qspi, 180131fb632bSRamuthevar Vadivel Murugan }, 180231fb632bSRamuthevar Vadivel Murugan { 180331fb632bSRamuthevar Vadivel Murugan .compatible = "ti,k2g-qspi", 180431fb632bSRamuthevar Vadivel Murugan .data = &k2g_qspi, 180531fb632bSRamuthevar Vadivel Murugan }, 180631fb632bSRamuthevar Vadivel Murugan { 180731fb632bSRamuthevar Vadivel Murugan .compatible = "ti,am654-ospi", 180831fb632bSRamuthevar Vadivel Murugan .data = &am654_ospi, 180931fb632bSRamuthevar Vadivel Murugan }, 1810ab2d2875SRamuthevar Vadivel Murugan { 1811ab2d2875SRamuthevar Vadivel Murugan .compatible = "intel,lgm-qspi", 1812ad2775dcSRamuthevar Vadivel Murugan .data = &intel_lgm_qspi, 1813ab2d2875SRamuthevar Vadivel Murugan }, 181409e393e3SSai Krishna Potthuri { 181509e393e3SSai Krishna Potthuri .compatible = "xlnx,versal-ospi-1.0", 18160d868829SIan Abbott .data = &versal_ospi, 181709e393e3SSai Krishna Potthuri }, 181898d948ebSDinh Nguyen { 181998d948ebSDinh Nguyen .compatible = "intel,socfpga-qspi", 18200d868829SIan Abbott .data = &socfpga_qspi, 182198d948ebSDinh Nguyen }, 182231fb632bSRamuthevar Vadivel Murugan { /* end of table */ } 182331fb632bSRamuthevar Vadivel Murugan }; 182431fb632bSRamuthevar Vadivel Murugan 182531fb632bSRamuthevar Vadivel Murugan MODULE_DEVICE_TABLE(of, cqspi_dt_ids); 182631fb632bSRamuthevar Vadivel Murugan 182731fb632bSRamuthevar Vadivel Murugan static struct platform_driver cqspi_platform_driver = { 182831fb632bSRamuthevar Vadivel Murugan .probe = cqspi_probe, 182931fb632bSRamuthevar Vadivel Murugan .remove = cqspi_remove, 183031fb632bSRamuthevar Vadivel Murugan .driver = { 183131fb632bSRamuthevar Vadivel Murugan .name = CQSPI_NAME, 183231fb632bSRamuthevar Vadivel Murugan .pm = CQSPI_DEV_PM_OPS, 183331fb632bSRamuthevar Vadivel Murugan .of_match_table = cqspi_dt_ids, 183431fb632bSRamuthevar Vadivel Murugan }, 183531fb632bSRamuthevar Vadivel Murugan }; 183631fb632bSRamuthevar Vadivel Murugan 183731fb632bSRamuthevar Vadivel Murugan module_platform_driver(cqspi_platform_driver); 183831fb632bSRamuthevar Vadivel Murugan 183931fb632bSRamuthevar Vadivel Murugan MODULE_DESCRIPTION("Cadence QSPI Controller Driver"); 184031fb632bSRamuthevar Vadivel Murugan MODULE_LICENSE("GPL v2"); 184131fb632bSRamuthevar Vadivel Murugan MODULE_ALIAS("platform:" CQSPI_NAME); 184231fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>"); 184331fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>"); 184431fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>"); 184531fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>"); 1846f453f293SPratyush Yadav MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>"); 1847