131fb632bSRamuthevar Vadivel Murugan // SPDX-License-Identifier: GPL-2.0-only 231fb632bSRamuthevar Vadivel Murugan // 331fb632bSRamuthevar Vadivel Murugan // Driver for Cadence QSPI Controller 431fb632bSRamuthevar Vadivel Murugan // 531fb632bSRamuthevar Vadivel Murugan // Copyright Altera Corporation (C) 2012-2014. All rights reserved. 631fb632bSRamuthevar Vadivel Murugan // Copyright Intel Corporation (C) 2019-2020. All rights reserved. 731fb632bSRamuthevar Vadivel Murugan // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 831fb632bSRamuthevar Vadivel Murugan 931fb632bSRamuthevar Vadivel Murugan #include <linux/clk.h> 1031fb632bSRamuthevar Vadivel Murugan #include <linux/completion.h> 1131fb632bSRamuthevar Vadivel Murugan #include <linux/delay.h> 1231fb632bSRamuthevar Vadivel Murugan #include <linux/dma-mapping.h> 1331fb632bSRamuthevar Vadivel Murugan #include <linux/dmaengine.h> 1431fb632bSRamuthevar Vadivel Murugan #include <linux/err.h> 1531fb632bSRamuthevar Vadivel Murugan #include <linux/errno.h> 1631fb632bSRamuthevar Vadivel Murugan #include <linux/interrupt.h> 1731fb632bSRamuthevar Vadivel Murugan #include <linux/io.h> 1831fb632bSRamuthevar Vadivel Murugan #include <linux/iopoll.h> 1931fb632bSRamuthevar Vadivel Murugan #include <linux/jiffies.h> 2031fb632bSRamuthevar Vadivel Murugan #include <linux/kernel.h> 2131fb632bSRamuthevar Vadivel Murugan #include <linux/module.h> 2231fb632bSRamuthevar Vadivel Murugan #include <linux/of_device.h> 2331fb632bSRamuthevar Vadivel Murugan #include <linux/of.h> 2431fb632bSRamuthevar Vadivel Murugan #include <linux/platform_device.h> 2531fb632bSRamuthevar Vadivel Murugan #include <linux/pm_runtime.h> 2631fb632bSRamuthevar Vadivel Murugan #include <linux/reset.h> 2731fb632bSRamuthevar Vadivel Murugan #include <linux/sched.h> 2831fb632bSRamuthevar Vadivel Murugan #include <linux/spi/spi.h> 2931fb632bSRamuthevar Vadivel Murugan #include <linux/spi/spi-mem.h> 3031fb632bSRamuthevar Vadivel Murugan #include <linux/timer.h> 3131fb632bSRamuthevar Vadivel Murugan 3231fb632bSRamuthevar Vadivel Murugan #define CQSPI_NAME "cadence-qspi" 3331fb632bSRamuthevar Vadivel Murugan #define CQSPI_MAX_CHIPSELECT 16 3431fb632bSRamuthevar Vadivel Murugan 3531fb632bSRamuthevar Vadivel Murugan /* Quirks */ 3631fb632bSRamuthevar Vadivel Murugan #define CQSPI_NEEDS_WR_DELAY BIT(0) 3731fb632bSRamuthevar Vadivel Murugan #define CQSPI_DISABLE_DAC_MODE BIT(1) 3831fb632bSRamuthevar Vadivel Murugan 3931fb632bSRamuthevar Vadivel Murugan /* Capabilities */ 4031fb632bSRamuthevar Vadivel Murugan #define CQSPI_SUPPORTS_OCTAL BIT(0) 4131fb632bSRamuthevar Vadivel Murugan 4231fb632bSRamuthevar Vadivel Murugan struct cqspi_st; 4331fb632bSRamuthevar Vadivel Murugan 4431fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata { 4531fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi; 4631fb632bSRamuthevar Vadivel Murugan u32 clk_rate; 4731fb632bSRamuthevar Vadivel Murugan u32 read_delay; 4831fb632bSRamuthevar Vadivel Murugan u32 tshsl_ns; 4931fb632bSRamuthevar Vadivel Murugan u32 tsd2d_ns; 5031fb632bSRamuthevar Vadivel Murugan u32 tchsh_ns; 5131fb632bSRamuthevar Vadivel Murugan u32 tslch_ns; 5231fb632bSRamuthevar Vadivel Murugan u8 inst_width; 5331fb632bSRamuthevar Vadivel Murugan u8 addr_width; 5431fb632bSRamuthevar Vadivel Murugan u8 data_width; 5531fb632bSRamuthevar Vadivel Murugan u8 cs; 5631fb632bSRamuthevar Vadivel Murugan }; 5731fb632bSRamuthevar Vadivel Murugan 5831fb632bSRamuthevar Vadivel Murugan struct cqspi_st { 5931fb632bSRamuthevar Vadivel Murugan struct platform_device *pdev; 6031fb632bSRamuthevar Vadivel Murugan 6131fb632bSRamuthevar Vadivel Murugan struct clk *clk; 6231fb632bSRamuthevar Vadivel Murugan unsigned int sclk; 6331fb632bSRamuthevar Vadivel Murugan 6431fb632bSRamuthevar Vadivel Murugan void __iomem *iobase; 6531fb632bSRamuthevar Vadivel Murugan void __iomem *ahb_base; 6631fb632bSRamuthevar Vadivel Murugan resource_size_t ahb_size; 6731fb632bSRamuthevar Vadivel Murugan struct completion transfer_complete; 6831fb632bSRamuthevar Vadivel Murugan 6931fb632bSRamuthevar Vadivel Murugan struct dma_chan *rx_chan; 7031fb632bSRamuthevar Vadivel Murugan struct completion rx_dma_complete; 7131fb632bSRamuthevar Vadivel Murugan dma_addr_t mmap_phys_base; 7231fb632bSRamuthevar Vadivel Murugan 7331fb632bSRamuthevar Vadivel Murugan int current_cs; 7431fb632bSRamuthevar Vadivel Murugan unsigned long master_ref_clk_hz; 7531fb632bSRamuthevar Vadivel Murugan bool is_decoded_cs; 7631fb632bSRamuthevar Vadivel Murugan u32 fifo_depth; 7731fb632bSRamuthevar Vadivel Murugan u32 fifo_width; 7831fb632bSRamuthevar Vadivel Murugan bool rclk_en; 7931fb632bSRamuthevar Vadivel Murugan u32 trigger_address; 8031fb632bSRamuthevar Vadivel Murugan u32 wr_delay; 8131fb632bSRamuthevar Vadivel Murugan bool use_direct_mode; 8231fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; 8331fb632bSRamuthevar Vadivel Murugan }; 8431fb632bSRamuthevar Vadivel Murugan 8531fb632bSRamuthevar Vadivel Murugan struct cqspi_driver_platdata { 8631fb632bSRamuthevar Vadivel Murugan u32 hwcaps_mask; 8731fb632bSRamuthevar Vadivel Murugan u8 quirks; 8831fb632bSRamuthevar Vadivel Murugan }; 8931fb632bSRamuthevar Vadivel Murugan 9031fb632bSRamuthevar Vadivel Murugan /* Operation timeout value */ 9131fb632bSRamuthevar Vadivel Murugan #define CQSPI_TIMEOUT_MS 500 9231fb632bSRamuthevar Vadivel Murugan #define CQSPI_READ_TIMEOUT_MS 10 9331fb632bSRamuthevar Vadivel Murugan 9431fb632bSRamuthevar Vadivel Murugan /* Instruction type */ 9531fb632bSRamuthevar Vadivel Murugan #define CQSPI_INST_TYPE_SINGLE 0 9631fb632bSRamuthevar Vadivel Murugan #define CQSPI_INST_TYPE_DUAL 1 9731fb632bSRamuthevar Vadivel Murugan #define CQSPI_INST_TYPE_QUAD 2 9831fb632bSRamuthevar Vadivel Murugan #define CQSPI_INST_TYPE_OCTAL 3 9931fb632bSRamuthevar Vadivel Murugan 10031fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_CLKS_PER_BYTE 8 10131fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_BYTES_MAX 4 10231fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_CLKS_MAX 31 10331fb632bSRamuthevar Vadivel Murugan 10431fb632bSRamuthevar Vadivel Murugan #define CQSPI_STIG_DATA_LEN_MAX 8 10531fb632bSRamuthevar Vadivel Murugan 10631fb632bSRamuthevar Vadivel Murugan /* Register map */ 10731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG 0x00 10831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0) 10931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7) 11031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9) 11131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 11231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_DMA_MASK BIT(15) 11331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_BAUD_LSB 19 11431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_IDLE_LSB 31 11531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF 11631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_BAUD_MASK 0xF 11731fb632bSRamuthevar Vadivel Murugan 11831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR 0x04 11931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 12031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 12131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 12231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 12331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 12431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 12531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 12631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 12731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 12831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F 12931fb632bSRamuthevar Vadivel Murugan 13031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR 0x08 13131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 13231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12 13331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16 13431fb632bSRamuthevar Vadivel Murugan 13531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY 0x0C 13631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSLCH_LSB 0 13731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TCHSH_LSB 8 13831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSD2D_LSB 16 13931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSHSL_LSB 24 14031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF 14131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF 14231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF 14331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF 14431fb632bSRamuthevar Vadivel Murugan 14531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE 0x10 14631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0 14731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_DELAY_LSB 1 14831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF 14931fb632bSRamuthevar Vadivel Murugan 15031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE 0x14 15131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_ADDRESS_LSB 0 15231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_PAGE_LSB 4 15331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_BLOCK_LSB 16 15431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF 15531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF 15631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F 15731fb632bSRamuthevar Vadivel Murugan 15831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SRAMPARTITION 0x18 15931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTTRIGGER 0x1C 16031fb632bSRamuthevar Vadivel Murugan 16131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA 0x20 16231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_SINGLE_LSB 0 16331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_BURST_LSB 8 16431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_SINGLE_MASK 0xFF 16531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_BURST_MASK 0xFF 16631fb632bSRamuthevar Vadivel Murugan 16731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_REMAP 0x24 16831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_MODE_BIT 0x28 16931fb632bSRamuthevar Vadivel Murugan 17031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL 0x2C 17131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 17231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 17331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF 17431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF 17531fb632bSRamuthevar Vadivel Murugan 17631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQSTATUS 0x40 17731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQMASK 0x44 17831fb632bSRamuthevar Vadivel Murugan 17931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD 0x60 18031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0) 18131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1) 18231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5) 18331fb632bSRamuthevar Vadivel Murugan 18431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDWATERMARK 0x64 18531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 18631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDBYTES 0x6C 18731fb632bSRamuthevar Vadivel Murugan 18831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL 0x90 18931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0) 19031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1) 19131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 19231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 19331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 19431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 19531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 19631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 19731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 19831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 19931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 20031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 20131fb632bSRamuthevar Vadivel Murugan 20231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR 0x70 20331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0) 20431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1) 20531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5) 20631fb632bSRamuthevar Vadivel Murugan 20731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRWATERMARK 0x74 20831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 20931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRBYTES 0x7C 21031fb632bSRamuthevar Vadivel Murugan 21131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDADDRESS 0x94 21231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDREADDATALOWER 0xA0 21331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDREADDATAUPPER 0xA4 21431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDWRITEDATALOWER 0xA8 21531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC 21631fb632bSRamuthevar Vadivel Murugan 21731fb632bSRamuthevar Vadivel Murugan /* Interrupt status bits */ 21831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_MODE_ERR BIT(0) 21931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_UNDERFLOW BIT(1) 22031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_COMP BIT(2) 22131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3) 22231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4) 22331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5) 22431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_WATERMARK BIT(6) 22531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12) 22631fb632bSRamuthevar Vadivel Murugan 22731fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \ 22831fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_IND_SRAM_FULL | \ 22931fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_IND_COMP) 23031fb632bSRamuthevar Vadivel Murugan 23131fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \ 23231fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_WATERMARK | \ 23331fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_UNDERFLOW) 23431fb632bSRamuthevar Vadivel Murugan 23531fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_STATUS_MASK 0x1FFFF 23631fb632bSRamuthevar Vadivel Murugan 23731fb632bSRamuthevar Vadivel Murugan static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr) 23831fb632bSRamuthevar Vadivel Murugan { 23931fb632bSRamuthevar Vadivel Murugan u32 val; 24031fb632bSRamuthevar Vadivel Murugan 24131fb632bSRamuthevar Vadivel Murugan return readl_relaxed_poll_timeout(reg, val, 24231fb632bSRamuthevar Vadivel Murugan (((clr ? ~val : val) & mask) == mask), 24331fb632bSRamuthevar Vadivel Murugan 10, CQSPI_TIMEOUT_MS * 1000); 24431fb632bSRamuthevar Vadivel Murugan } 24531fb632bSRamuthevar Vadivel Murugan 24631fb632bSRamuthevar Vadivel Murugan static bool cqspi_is_idle(struct cqspi_st *cqspi) 24731fb632bSRamuthevar Vadivel Murugan { 24831fb632bSRamuthevar Vadivel Murugan u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 24931fb632bSRamuthevar Vadivel Murugan 25031fb632bSRamuthevar Vadivel Murugan return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB); 25131fb632bSRamuthevar Vadivel Murugan } 25231fb632bSRamuthevar Vadivel Murugan 25331fb632bSRamuthevar Vadivel Murugan static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi) 25431fb632bSRamuthevar Vadivel Murugan { 25531fb632bSRamuthevar Vadivel Murugan u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL); 25631fb632bSRamuthevar Vadivel Murugan 25731fb632bSRamuthevar Vadivel Murugan reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB; 25831fb632bSRamuthevar Vadivel Murugan return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK; 25931fb632bSRamuthevar Vadivel Murugan } 26031fb632bSRamuthevar Vadivel Murugan 26131fb632bSRamuthevar Vadivel Murugan static irqreturn_t cqspi_irq_handler(int this_irq, void *dev) 26231fb632bSRamuthevar Vadivel Murugan { 26331fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev; 26431fb632bSRamuthevar Vadivel Murugan unsigned int irq_status; 26531fb632bSRamuthevar Vadivel Murugan 26631fb632bSRamuthevar Vadivel Murugan /* Read interrupt status */ 26731fb632bSRamuthevar Vadivel Murugan irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS); 26831fb632bSRamuthevar Vadivel Murugan 26931fb632bSRamuthevar Vadivel Murugan /* Clear interrupt */ 27031fb632bSRamuthevar Vadivel Murugan writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS); 27131fb632bSRamuthevar Vadivel Murugan 27231fb632bSRamuthevar Vadivel Murugan irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR; 27331fb632bSRamuthevar Vadivel Murugan 27431fb632bSRamuthevar Vadivel Murugan if (irq_status) 27531fb632bSRamuthevar Vadivel Murugan complete(&cqspi->transfer_complete); 27631fb632bSRamuthevar Vadivel Murugan 27731fb632bSRamuthevar Vadivel Murugan return IRQ_HANDLED; 27831fb632bSRamuthevar Vadivel Murugan } 27931fb632bSRamuthevar Vadivel Murugan 28031fb632bSRamuthevar Vadivel Murugan static unsigned int cqspi_calc_rdreg(struct cqspi_flash_pdata *f_pdata) 28131fb632bSRamuthevar Vadivel Murugan { 28231fb632bSRamuthevar Vadivel Murugan u32 rdreg = 0; 28331fb632bSRamuthevar Vadivel Murugan 28431fb632bSRamuthevar Vadivel Murugan rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; 28531fb632bSRamuthevar Vadivel Murugan rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; 28631fb632bSRamuthevar Vadivel Murugan rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; 28731fb632bSRamuthevar Vadivel Murugan 28831fb632bSRamuthevar Vadivel Murugan return rdreg; 28931fb632bSRamuthevar Vadivel Murugan } 29031fb632bSRamuthevar Vadivel Murugan 29131fb632bSRamuthevar Vadivel Murugan static int cqspi_wait_idle(struct cqspi_st *cqspi) 29231fb632bSRamuthevar Vadivel Murugan { 29331fb632bSRamuthevar Vadivel Murugan const unsigned int poll_idle_retry = 3; 29431fb632bSRamuthevar Vadivel Murugan unsigned int count = 0; 29531fb632bSRamuthevar Vadivel Murugan unsigned long timeout; 29631fb632bSRamuthevar Vadivel Murugan 29731fb632bSRamuthevar Vadivel Murugan timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS); 29831fb632bSRamuthevar Vadivel Murugan while (1) { 29931fb632bSRamuthevar Vadivel Murugan /* 30031fb632bSRamuthevar Vadivel Murugan * Read few times in succession to ensure the controller 30131fb632bSRamuthevar Vadivel Murugan * is indeed idle, that is, the bit does not transition 30231fb632bSRamuthevar Vadivel Murugan * low again. 30331fb632bSRamuthevar Vadivel Murugan */ 30431fb632bSRamuthevar Vadivel Murugan if (cqspi_is_idle(cqspi)) 30531fb632bSRamuthevar Vadivel Murugan count++; 30631fb632bSRamuthevar Vadivel Murugan else 30731fb632bSRamuthevar Vadivel Murugan count = 0; 30831fb632bSRamuthevar Vadivel Murugan 30931fb632bSRamuthevar Vadivel Murugan if (count >= poll_idle_retry) 31031fb632bSRamuthevar Vadivel Murugan return 0; 31131fb632bSRamuthevar Vadivel Murugan 31231fb632bSRamuthevar Vadivel Murugan if (time_after(jiffies, timeout)) { 31331fb632bSRamuthevar Vadivel Murugan /* Timeout, in busy mode. */ 31431fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 31531fb632bSRamuthevar Vadivel Murugan "QSPI is still busy after %dms timeout.\n", 31631fb632bSRamuthevar Vadivel Murugan CQSPI_TIMEOUT_MS); 31731fb632bSRamuthevar Vadivel Murugan return -ETIMEDOUT; 31831fb632bSRamuthevar Vadivel Murugan } 31931fb632bSRamuthevar Vadivel Murugan 32031fb632bSRamuthevar Vadivel Murugan cpu_relax(); 32131fb632bSRamuthevar Vadivel Murugan } 32231fb632bSRamuthevar Vadivel Murugan } 32331fb632bSRamuthevar Vadivel Murugan 32431fb632bSRamuthevar Vadivel Murugan static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg) 32531fb632bSRamuthevar Vadivel Murugan { 32631fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 32731fb632bSRamuthevar Vadivel Murugan int ret; 32831fb632bSRamuthevar Vadivel Murugan 32931fb632bSRamuthevar Vadivel Murugan /* Write the CMDCTRL without start execution. */ 33031fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CMDCTRL); 33131fb632bSRamuthevar Vadivel Murugan /* Start execute */ 33231fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK; 33331fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CMDCTRL); 33431fb632bSRamuthevar Vadivel Murugan 33531fb632bSRamuthevar Vadivel Murugan /* Polling for completion. */ 33631fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL, 33731fb632bSRamuthevar Vadivel Murugan CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1); 33831fb632bSRamuthevar Vadivel Murugan if (ret) { 33931fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 34031fb632bSRamuthevar Vadivel Murugan "Flash command execution timed out.\n"); 34131fb632bSRamuthevar Vadivel Murugan return ret; 34231fb632bSRamuthevar Vadivel Murugan } 34331fb632bSRamuthevar Vadivel Murugan 34431fb632bSRamuthevar Vadivel Murugan /* Polling QSPI idle status. */ 34531fb632bSRamuthevar Vadivel Murugan return cqspi_wait_idle(cqspi); 34631fb632bSRamuthevar Vadivel Murugan } 34731fb632bSRamuthevar Vadivel Murugan 34831fb632bSRamuthevar Vadivel Murugan static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, 34931fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 35031fb632bSRamuthevar Vadivel Murugan { 35131fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 35231fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 35331fb632bSRamuthevar Vadivel Murugan u8 *rxbuf = op->data.buf.in; 35431fb632bSRamuthevar Vadivel Murugan u8 opcode = op->cmd.opcode; 35531fb632bSRamuthevar Vadivel Murugan size_t n_rx = op->data.nbytes; 35631fb632bSRamuthevar Vadivel Murugan unsigned int rdreg; 35731fb632bSRamuthevar Vadivel Murugan unsigned int reg; 35831fb632bSRamuthevar Vadivel Murugan size_t read_len; 35931fb632bSRamuthevar Vadivel Murugan int status; 36031fb632bSRamuthevar Vadivel Murugan 36131fb632bSRamuthevar Vadivel Murugan if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) { 36231fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 36331fb632bSRamuthevar Vadivel Murugan "Invalid input argument, len %zu rxbuf 0x%p\n", 36431fb632bSRamuthevar Vadivel Murugan n_rx, rxbuf); 36531fb632bSRamuthevar Vadivel Murugan return -EINVAL; 36631fb632bSRamuthevar Vadivel Murugan } 36731fb632bSRamuthevar Vadivel Murugan 36831fb632bSRamuthevar Vadivel Murugan reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 36931fb632bSRamuthevar Vadivel Murugan 37031fb632bSRamuthevar Vadivel Murugan rdreg = cqspi_calc_rdreg(f_pdata); 37131fb632bSRamuthevar Vadivel Murugan writel(rdreg, reg_base + CQSPI_REG_RD_INSTR); 37231fb632bSRamuthevar Vadivel Murugan 37331fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); 37431fb632bSRamuthevar Vadivel Murugan 37531fb632bSRamuthevar Vadivel Murugan /* 0 means 1 byte. */ 37631fb632bSRamuthevar Vadivel Murugan reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) 37731fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); 37831fb632bSRamuthevar Vadivel Murugan status = cqspi_exec_flash_cmd(cqspi, reg); 37931fb632bSRamuthevar Vadivel Murugan if (status) 38031fb632bSRamuthevar Vadivel Murugan return status; 38131fb632bSRamuthevar Vadivel Murugan 38231fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER); 38331fb632bSRamuthevar Vadivel Murugan 38431fb632bSRamuthevar Vadivel Murugan /* Put the read value into rx_buf */ 38531fb632bSRamuthevar Vadivel Murugan read_len = (n_rx > 4) ? 4 : n_rx; 38631fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, ®, read_len); 38731fb632bSRamuthevar Vadivel Murugan rxbuf += read_len; 38831fb632bSRamuthevar Vadivel Murugan 38931fb632bSRamuthevar Vadivel Murugan if (n_rx > 4) { 39031fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER); 39131fb632bSRamuthevar Vadivel Murugan 39231fb632bSRamuthevar Vadivel Murugan read_len = n_rx - read_len; 39331fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, ®, read_len); 39431fb632bSRamuthevar Vadivel Murugan } 39531fb632bSRamuthevar Vadivel Murugan 39631fb632bSRamuthevar Vadivel Murugan return 0; 39731fb632bSRamuthevar Vadivel Murugan } 39831fb632bSRamuthevar Vadivel Murugan 39931fb632bSRamuthevar Vadivel Murugan static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata, 40031fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 40131fb632bSRamuthevar Vadivel Murugan { 40231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 40331fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 40431fb632bSRamuthevar Vadivel Murugan const u8 opcode = op->cmd.opcode; 40531fb632bSRamuthevar Vadivel Murugan const u8 *txbuf = op->data.buf.out; 40631fb632bSRamuthevar Vadivel Murugan size_t n_tx = op->data.nbytes; 40731fb632bSRamuthevar Vadivel Murugan unsigned int reg; 40831fb632bSRamuthevar Vadivel Murugan unsigned int data; 40931fb632bSRamuthevar Vadivel Murugan size_t write_len; 41031fb632bSRamuthevar Vadivel Murugan 41131fb632bSRamuthevar Vadivel Murugan if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) { 41231fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 41331fb632bSRamuthevar Vadivel Murugan "Invalid input argument, cmdlen %zu txbuf 0x%p\n", 41431fb632bSRamuthevar Vadivel Murugan n_tx, txbuf); 41531fb632bSRamuthevar Vadivel Murugan return -EINVAL; 41631fb632bSRamuthevar Vadivel Murugan } 41731fb632bSRamuthevar Vadivel Murugan 41831fb632bSRamuthevar Vadivel Murugan reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 41931fb632bSRamuthevar Vadivel Murugan 42031fb632bSRamuthevar Vadivel Murugan if (op->addr.nbytes) { 42131fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 42231fb632bSRamuthevar Vadivel Murugan reg |= ((op->addr.nbytes - 1) & 42331fb632bSRamuthevar Vadivel Murugan CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) 42431fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; 42531fb632bSRamuthevar Vadivel Murugan 42631fb632bSRamuthevar Vadivel Murugan writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); 42731fb632bSRamuthevar Vadivel Murugan } 42831fb632bSRamuthevar Vadivel Murugan 42931fb632bSRamuthevar Vadivel Murugan if (n_tx) { 43031fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB); 43131fb632bSRamuthevar Vadivel Murugan reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) 43231fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_WR_BYTES_LSB; 43331fb632bSRamuthevar Vadivel Murugan data = 0; 43431fb632bSRamuthevar Vadivel Murugan write_len = (n_tx > 4) ? 4 : n_tx; 43531fb632bSRamuthevar Vadivel Murugan memcpy(&data, txbuf, write_len); 43631fb632bSRamuthevar Vadivel Murugan txbuf += write_len; 43731fb632bSRamuthevar Vadivel Murugan writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER); 43831fb632bSRamuthevar Vadivel Murugan 43931fb632bSRamuthevar Vadivel Murugan if (n_tx > 4) { 44031fb632bSRamuthevar Vadivel Murugan data = 0; 44131fb632bSRamuthevar Vadivel Murugan write_len = n_tx - 4; 44231fb632bSRamuthevar Vadivel Murugan memcpy(&data, txbuf, write_len); 44331fb632bSRamuthevar Vadivel Murugan writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER); 44431fb632bSRamuthevar Vadivel Murugan } 44531fb632bSRamuthevar Vadivel Murugan } 44631fb632bSRamuthevar Vadivel Murugan 44731fb632bSRamuthevar Vadivel Murugan return cqspi_exec_flash_cmd(cqspi, reg); 44831fb632bSRamuthevar Vadivel Murugan } 44931fb632bSRamuthevar Vadivel Murugan 45031fb632bSRamuthevar Vadivel Murugan static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata, 45131fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 45231fb632bSRamuthevar Vadivel Murugan { 45331fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 45431fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 45531fb632bSRamuthevar Vadivel Murugan unsigned int dummy_clk = 0; 45631fb632bSRamuthevar Vadivel Murugan unsigned int reg; 45731fb632bSRamuthevar Vadivel Murugan 45831fb632bSRamuthevar Vadivel Murugan reg = op->cmd.opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB; 45931fb632bSRamuthevar Vadivel Murugan reg |= cqspi_calc_rdreg(f_pdata); 46031fb632bSRamuthevar Vadivel Murugan 46131fb632bSRamuthevar Vadivel Murugan /* Setup dummy clock cycles */ 46231fb632bSRamuthevar Vadivel Murugan dummy_clk = op->dummy.nbytes * 8; 46331fb632bSRamuthevar Vadivel Murugan if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 46431fb632bSRamuthevar Vadivel Murugan dummy_clk = CQSPI_DUMMY_CLKS_MAX; 46531fb632bSRamuthevar Vadivel Murugan 46631fb632bSRamuthevar Vadivel Murugan if (dummy_clk) 46731fb632bSRamuthevar Vadivel Murugan reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK) 46831fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_RD_INSTR_DUMMY_LSB; 46931fb632bSRamuthevar Vadivel Murugan 47031fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_RD_INSTR); 47131fb632bSRamuthevar Vadivel Murugan 47231fb632bSRamuthevar Vadivel Murugan /* Set address width */ 47331fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_SIZE); 47431fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 47531fb632bSRamuthevar Vadivel Murugan reg |= (op->addr.nbytes - 1); 47631fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_SIZE); 47731fb632bSRamuthevar Vadivel Murugan return 0; 47831fb632bSRamuthevar Vadivel Murugan } 47931fb632bSRamuthevar Vadivel Murugan 48031fb632bSRamuthevar Vadivel Murugan static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, 48131fb632bSRamuthevar Vadivel Murugan u8 *rxbuf, loff_t from_addr, 48231fb632bSRamuthevar Vadivel Murugan const size_t n_rx) 48331fb632bSRamuthevar Vadivel Murugan { 48431fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 48531fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 48631fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 48731fb632bSRamuthevar Vadivel Murugan void __iomem *ahb_base = cqspi->ahb_base; 48831fb632bSRamuthevar Vadivel Murugan unsigned int remaining = n_rx; 48931fb632bSRamuthevar Vadivel Murugan unsigned int mod_bytes = n_rx % 4; 49031fb632bSRamuthevar Vadivel Murugan unsigned int bytes_to_read = 0; 49131fb632bSRamuthevar Vadivel Murugan u8 *rxbuf_end = rxbuf + n_rx; 49231fb632bSRamuthevar Vadivel Murugan int ret = 0; 49331fb632bSRamuthevar Vadivel Murugan 49431fb632bSRamuthevar Vadivel Murugan writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 49531fb632bSRamuthevar Vadivel Murugan writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES); 49631fb632bSRamuthevar Vadivel Murugan 49731fb632bSRamuthevar Vadivel Murugan /* Clear all interrupts. */ 49831fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 49931fb632bSRamuthevar Vadivel Murugan 50031fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK); 50131fb632bSRamuthevar Vadivel Murugan 50231fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 50331fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTRD_START_MASK, 50431fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTRD); 50531fb632bSRamuthevar Vadivel Murugan 50631fb632bSRamuthevar Vadivel Murugan while (remaining > 0) { 50731fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->transfer_complete, 50831fb632bSRamuthevar Vadivel Murugan msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) 50931fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 51031fb632bSRamuthevar Vadivel Murugan 51131fb632bSRamuthevar Vadivel Murugan bytes_to_read = cqspi_get_rd_sram_level(cqspi); 51231fb632bSRamuthevar Vadivel Murugan 51331fb632bSRamuthevar Vadivel Murugan if (ret && bytes_to_read == 0) { 51431fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect read timeout, no bytes\n"); 51531fb632bSRamuthevar Vadivel Murugan goto failrd; 51631fb632bSRamuthevar Vadivel Murugan } 51731fb632bSRamuthevar Vadivel Murugan 51831fb632bSRamuthevar Vadivel Murugan while (bytes_to_read != 0) { 51931fb632bSRamuthevar Vadivel Murugan unsigned int word_remain = round_down(remaining, 4); 52031fb632bSRamuthevar Vadivel Murugan 52131fb632bSRamuthevar Vadivel Murugan bytes_to_read *= cqspi->fifo_width; 52231fb632bSRamuthevar Vadivel Murugan bytes_to_read = bytes_to_read > remaining ? 52331fb632bSRamuthevar Vadivel Murugan remaining : bytes_to_read; 52431fb632bSRamuthevar Vadivel Murugan bytes_to_read = round_down(bytes_to_read, 4); 52531fb632bSRamuthevar Vadivel Murugan /* Read 4 byte word chunks then single bytes */ 52631fb632bSRamuthevar Vadivel Murugan if (bytes_to_read) { 52731fb632bSRamuthevar Vadivel Murugan ioread32_rep(ahb_base, rxbuf, 52831fb632bSRamuthevar Vadivel Murugan (bytes_to_read / 4)); 52931fb632bSRamuthevar Vadivel Murugan } else if (!word_remain && mod_bytes) { 53031fb632bSRamuthevar Vadivel Murugan unsigned int temp = ioread32(ahb_base); 53131fb632bSRamuthevar Vadivel Murugan 53231fb632bSRamuthevar Vadivel Murugan bytes_to_read = mod_bytes; 53331fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, &temp, min((unsigned int) 53431fb632bSRamuthevar Vadivel Murugan (rxbuf_end - rxbuf), 53531fb632bSRamuthevar Vadivel Murugan bytes_to_read)); 53631fb632bSRamuthevar Vadivel Murugan } 53731fb632bSRamuthevar Vadivel Murugan rxbuf += bytes_to_read; 53831fb632bSRamuthevar Vadivel Murugan remaining -= bytes_to_read; 53931fb632bSRamuthevar Vadivel Murugan bytes_to_read = cqspi_get_rd_sram_level(cqspi); 54031fb632bSRamuthevar Vadivel Murugan } 54131fb632bSRamuthevar Vadivel Murugan 54231fb632bSRamuthevar Vadivel Murugan if (remaining > 0) 54331fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 54431fb632bSRamuthevar Vadivel Murugan } 54531fb632bSRamuthevar Vadivel Murugan 54631fb632bSRamuthevar Vadivel Murugan /* Check indirect done status */ 54731fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD, 54831fb632bSRamuthevar Vadivel Murugan CQSPI_REG_INDIRECTRD_DONE_MASK, 0); 54931fb632bSRamuthevar Vadivel Murugan if (ret) { 55031fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect read completion error (%i)\n", ret); 55131fb632bSRamuthevar Vadivel Murugan goto failrd; 55231fb632bSRamuthevar Vadivel Murugan } 55331fb632bSRamuthevar Vadivel Murugan 55431fb632bSRamuthevar Vadivel Murugan /* Disable interrupt */ 55531fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 55631fb632bSRamuthevar Vadivel Murugan 55731fb632bSRamuthevar Vadivel Murugan /* Clear indirect completion status */ 55831fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD); 55931fb632bSRamuthevar Vadivel Murugan 56031fb632bSRamuthevar Vadivel Murugan return 0; 56131fb632bSRamuthevar Vadivel Murugan 56231fb632bSRamuthevar Vadivel Murugan failrd: 56331fb632bSRamuthevar Vadivel Murugan /* Disable interrupt */ 56431fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 56531fb632bSRamuthevar Vadivel Murugan 56631fb632bSRamuthevar Vadivel Murugan /* Cancel the indirect read */ 56731fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 56831fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTRD); 56931fb632bSRamuthevar Vadivel Murugan return ret; 57031fb632bSRamuthevar Vadivel Murugan } 57131fb632bSRamuthevar Vadivel Murugan 57231fb632bSRamuthevar Vadivel Murugan static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata, 57331fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 57431fb632bSRamuthevar Vadivel Murugan { 57531fb632bSRamuthevar Vadivel Murugan unsigned int reg; 57631fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 57731fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 57831fb632bSRamuthevar Vadivel Murugan 57931fb632bSRamuthevar Vadivel Murugan /* Set opcode. */ 58031fb632bSRamuthevar Vadivel Murugan reg = op->cmd.opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; 58131fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_WR_INSTR); 58231fb632bSRamuthevar Vadivel Murugan reg = cqspi_calc_rdreg(f_pdata); 58331fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_RD_INSTR); 58431fb632bSRamuthevar Vadivel Murugan 58531fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_SIZE); 58631fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 58731fb632bSRamuthevar Vadivel Murugan reg |= (op->addr.nbytes - 1); 58831fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_SIZE); 58931fb632bSRamuthevar Vadivel Murugan return 0; 59031fb632bSRamuthevar Vadivel Murugan } 59131fb632bSRamuthevar Vadivel Murugan 59231fb632bSRamuthevar Vadivel Murugan static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, 59331fb632bSRamuthevar Vadivel Murugan loff_t to_addr, const u8 *txbuf, 59431fb632bSRamuthevar Vadivel Murugan const size_t n_tx) 59531fb632bSRamuthevar Vadivel Murugan { 59631fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 59731fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 59831fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 59931fb632bSRamuthevar Vadivel Murugan unsigned int remaining = n_tx; 60031fb632bSRamuthevar Vadivel Murugan unsigned int write_bytes; 60131fb632bSRamuthevar Vadivel Murugan int ret; 60231fb632bSRamuthevar Vadivel Murugan 60331fb632bSRamuthevar Vadivel Murugan writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR); 60431fb632bSRamuthevar Vadivel Murugan writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES); 60531fb632bSRamuthevar Vadivel Murugan 60631fb632bSRamuthevar Vadivel Murugan /* Clear all interrupts. */ 60731fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 60831fb632bSRamuthevar Vadivel Murugan 60931fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK); 61031fb632bSRamuthevar Vadivel Murugan 61131fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 61231fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_START_MASK, 61331fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTWR); 61431fb632bSRamuthevar Vadivel Murugan /* 61531fb632bSRamuthevar Vadivel Murugan * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access 61631fb632bSRamuthevar Vadivel Murugan * Controller programming sequence, couple of cycles of 61731fb632bSRamuthevar Vadivel Murugan * QSPI_REF_CLK delay is required for the above bit to 61831fb632bSRamuthevar Vadivel Murugan * be internally synchronized by the QSPI module. Provide 5 61931fb632bSRamuthevar Vadivel Murugan * cycles of delay. 62031fb632bSRamuthevar Vadivel Murugan */ 62131fb632bSRamuthevar Vadivel Murugan if (cqspi->wr_delay) 62231fb632bSRamuthevar Vadivel Murugan ndelay(cqspi->wr_delay); 62331fb632bSRamuthevar Vadivel Murugan 62431fb632bSRamuthevar Vadivel Murugan while (remaining > 0) { 62531fb632bSRamuthevar Vadivel Murugan size_t write_words, mod_bytes; 62631fb632bSRamuthevar Vadivel Murugan 62731fb632bSRamuthevar Vadivel Murugan write_bytes = remaining; 62831fb632bSRamuthevar Vadivel Murugan write_words = write_bytes / 4; 62931fb632bSRamuthevar Vadivel Murugan mod_bytes = write_bytes % 4; 63031fb632bSRamuthevar Vadivel Murugan /* Write 4 bytes at a time then single bytes. */ 63131fb632bSRamuthevar Vadivel Murugan if (write_words) { 63231fb632bSRamuthevar Vadivel Murugan iowrite32_rep(cqspi->ahb_base, txbuf, write_words); 63331fb632bSRamuthevar Vadivel Murugan txbuf += (write_words * 4); 63431fb632bSRamuthevar Vadivel Murugan } 63531fb632bSRamuthevar Vadivel Murugan if (mod_bytes) { 63631fb632bSRamuthevar Vadivel Murugan unsigned int temp = 0xFFFFFFFF; 63731fb632bSRamuthevar Vadivel Murugan 63831fb632bSRamuthevar Vadivel Murugan memcpy(&temp, txbuf, mod_bytes); 63931fb632bSRamuthevar Vadivel Murugan iowrite32(temp, cqspi->ahb_base); 64031fb632bSRamuthevar Vadivel Murugan txbuf += mod_bytes; 64131fb632bSRamuthevar Vadivel Murugan } 64231fb632bSRamuthevar Vadivel Murugan 64331fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->transfer_complete, 64431fb632bSRamuthevar Vadivel Murugan msecs_to_jiffies(CQSPI_TIMEOUT_MS))) { 64531fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect write timeout\n"); 64631fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 64731fb632bSRamuthevar Vadivel Murugan goto failwr; 64831fb632bSRamuthevar Vadivel Murugan } 64931fb632bSRamuthevar Vadivel Murugan 65031fb632bSRamuthevar Vadivel Murugan remaining -= write_bytes; 65131fb632bSRamuthevar Vadivel Murugan 65231fb632bSRamuthevar Vadivel Murugan if (remaining > 0) 65331fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 65431fb632bSRamuthevar Vadivel Murugan } 65531fb632bSRamuthevar Vadivel Murugan 65631fb632bSRamuthevar Vadivel Murugan /* Check indirect done status */ 65731fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR, 65831fb632bSRamuthevar Vadivel Murugan CQSPI_REG_INDIRECTWR_DONE_MASK, 0); 65931fb632bSRamuthevar Vadivel Murugan if (ret) { 66031fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect write completion error (%i)\n", ret); 66131fb632bSRamuthevar Vadivel Murugan goto failwr; 66231fb632bSRamuthevar Vadivel Murugan } 66331fb632bSRamuthevar Vadivel Murugan 66431fb632bSRamuthevar Vadivel Murugan /* Disable interrupt. */ 66531fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 66631fb632bSRamuthevar Vadivel Murugan 66731fb632bSRamuthevar Vadivel Murugan /* Clear indirect completion status */ 66831fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR); 66931fb632bSRamuthevar Vadivel Murugan 67031fb632bSRamuthevar Vadivel Murugan cqspi_wait_idle(cqspi); 67131fb632bSRamuthevar Vadivel Murugan 67231fb632bSRamuthevar Vadivel Murugan return 0; 67331fb632bSRamuthevar Vadivel Murugan 67431fb632bSRamuthevar Vadivel Murugan failwr: 67531fb632bSRamuthevar Vadivel Murugan /* Disable interrupt. */ 67631fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 67731fb632bSRamuthevar Vadivel Murugan 67831fb632bSRamuthevar Vadivel Murugan /* Cancel the indirect write */ 67931fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 68031fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTWR); 68131fb632bSRamuthevar Vadivel Murugan return ret; 68231fb632bSRamuthevar Vadivel Murugan } 68331fb632bSRamuthevar Vadivel Murugan 68431fb632bSRamuthevar Vadivel Murugan static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata) 68531fb632bSRamuthevar Vadivel Murugan { 68631fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 68731fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 68831fb632bSRamuthevar Vadivel Murugan unsigned int chip_select = f_pdata->cs; 68931fb632bSRamuthevar Vadivel Murugan unsigned int reg; 69031fb632bSRamuthevar Vadivel Murugan 69131fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG); 69231fb632bSRamuthevar Vadivel Murugan if (cqspi->is_decoded_cs) { 69331fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CONFIG_DECODE_MASK; 69431fb632bSRamuthevar Vadivel Murugan } else { 69531fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; 69631fb632bSRamuthevar Vadivel Murugan 69731fb632bSRamuthevar Vadivel Murugan /* Convert CS if without decoder. 69831fb632bSRamuthevar Vadivel Murugan * CS0 to 4b'1110 69931fb632bSRamuthevar Vadivel Murugan * CS1 to 4b'1101 70031fb632bSRamuthevar Vadivel Murugan * CS2 to 4b'1011 70131fb632bSRamuthevar Vadivel Murugan * CS3 to 4b'0111 70231fb632bSRamuthevar Vadivel Murugan */ 70331fb632bSRamuthevar Vadivel Murugan chip_select = 0xF & ~(1 << chip_select); 70431fb632bSRamuthevar Vadivel Murugan } 70531fb632bSRamuthevar Vadivel Murugan 70631fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK 70731fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CONFIG_CHIPSELECT_LSB); 70831fb632bSRamuthevar Vadivel Murugan reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK) 70931fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CONFIG_CHIPSELECT_LSB; 71031fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG); 71131fb632bSRamuthevar Vadivel Murugan } 71231fb632bSRamuthevar Vadivel Murugan 71331fb632bSRamuthevar Vadivel Murugan static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz, 71431fb632bSRamuthevar Vadivel Murugan const unsigned int ns_val) 71531fb632bSRamuthevar Vadivel Murugan { 71631fb632bSRamuthevar Vadivel Murugan unsigned int ticks; 71731fb632bSRamuthevar Vadivel Murugan 71831fb632bSRamuthevar Vadivel Murugan ticks = ref_clk_hz / 1000; /* kHz */ 71931fb632bSRamuthevar Vadivel Murugan ticks = DIV_ROUND_UP(ticks * ns_val, 1000000); 72031fb632bSRamuthevar Vadivel Murugan 72131fb632bSRamuthevar Vadivel Murugan return ticks; 72231fb632bSRamuthevar Vadivel Murugan } 72331fb632bSRamuthevar Vadivel Murugan 72431fb632bSRamuthevar Vadivel Murugan static void cqspi_delay(struct cqspi_flash_pdata *f_pdata) 72531fb632bSRamuthevar Vadivel Murugan { 72631fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 72731fb632bSRamuthevar Vadivel Murugan void __iomem *iobase = cqspi->iobase; 72831fb632bSRamuthevar Vadivel Murugan const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 72931fb632bSRamuthevar Vadivel Murugan unsigned int tshsl, tchsh, tslch, tsd2d; 73031fb632bSRamuthevar Vadivel Murugan unsigned int reg; 73131fb632bSRamuthevar Vadivel Murugan unsigned int tsclk; 73231fb632bSRamuthevar Vadivel Murugan 73331fb632bSRamuthevar Vadivel Murugan /* calculate the number of ref ticks for one sclk tick */ 73431fb632bSRamuthevar Vadivel Murugan tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk); 73531fb632bSRamuthevar Vadivel Murugan 73631fb632bSRamuthevar Vadivel Murugan tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns); 73731fb632bSRamuthevar Vadivel Murugan /* this particular value must be at least one sclk */ 73831fb632bSRamuthevar Vadivel Murugan if (tshsl < tsclk) 73931fb632bSRamuthevar Vadivel Murugan tshsl = tsclk; 74031fb632bSRamuthevar Vadivel Murugan 74131fb632bSRamuthevar Vadivel Murugan tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns); 74231fb632bSRamuthevar Vadivel Murugan tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns); 74331fb632bSRamuthevar Vadivel Murugan tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns); 74431fb632bSRamuthevar Vadivel Murugan 74531fb632bSRamuthevar Vadivel Murugan reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK) 74631fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSHSL_LSB; 74731fb632bSRamuthevar Vadivel Murugan reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK) 74831fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TCHSH_LSB; 74931fb632bSRamuthevar Vadivel Murugan reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK) 75031fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSLCH_LSB; 75131fb632bSRamuthevar Vadivel Murugan reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK) 75231fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSD2D_LSB; 75331fb632bSRamuthevar Vadivel Murugan writel(reg, iobase + CQSPI_REG_DELAY); 75431fb632bSRamuthevar Vadivel Murugan } 75531fb632bSRamuthevar Vadivel Murugan 75631fb632bSRamuthevar Vadivel Murugan static void cqspi_config_baudrate_div(struct cqspi_st *cqspi) 75731fb632bSRamuthevar Vadivel Murugan { 75831fb632bSRamuthevar Vadivel Murugan const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 75931fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 76031fb632bSRamuthevar Vadivel Murugan u32 reg, div; 76131fb632bSRamuthevar Vadivel Murugan 76231fb632bSRamuthevar Vadivel Murugan /* Recalculate the baudrate divisor based on QSPI specification. */ 76331fb632bSRamuthevar Vadivel Murugan div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1; 76431fb632bSRamuthevar Vadivel Murugan 76531fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG); 76631fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); 76731fb632bSRamuthevar Vadivel Murugan reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB; 76831fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG); 76931fb632bSRamuthevar Vadivel Murugan } 77031fb632bSRamuthevar Vadivel Murugan 77131fb632bSRamuthevar Vadivel Murugan static void cqspi_readdata_capture(struct cqspi_st *cqspi, 77231fb632bSRamuthevar Vadivel Murugan const bool bypass, 77331fb632bSRamuthevar Vadivel Murugan const unsigned int delay) 77431fb632bSRamuthevar Vadivel Murugan { 77531fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 77631fb632bSRamuthevar Vadivel Murugan unsigned int reg; 77731fb632bSRamuthevar Vadivel Murugan 77831fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_READCAPTURE); 77931fb632bSRamuthevar Vadivel Murugan 78031fb632bSRamuthevar Vadivel Murugan if (bypass) 78131fb632bSRamuthevar Vadivel Murugan reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 78231fb632bSRamuthevar Vadivel Murugan else 78331fb632bSRamuthevar Vadivel Murugan reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 78431fb632bSRamuthevar Vadivel Murugan 78531fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK 78631fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_READCAPTURE_DELAY_LSB); 78731fb632bSRamuthevar Vadivel Murugan 78831fb632bSRamuthevar Vadivel Murugan reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK) 78931fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_READCAPTURE_DELAY_LSB; 79031fb632bSRamuthevar Vadivel Murugan 79131fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_READCAPTURE); 79231fb632bSRamuthevar Vadivel Murugan } 79331fb632bSRamuthevar Vadivel Murugan 79431fb632bSRamuthevar Vadivel Murugan static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable) 79531fb632bSRamuthevar Vadivel Murugan { 79631fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 79731fb632bSRamuthevar Vadivel Murugan unsigned int reg; 79831fb632bSRamuthevar Vadivel Murugan 79931fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG); 80031fb632bSRamuthevar Vadivel Murugan 80131fb632bSRamuthevar Vadivel Murugan if (enable) 80231fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CONFIG_ENABLE_MASK; 80331fb632bSRamuthevar Vadivel Murugan else 80431fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; 80531fb632bSRamuthevar Vadivel Murugan 80631fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG); 80731fb632bSRamuthevar Vadivel Murugan } 80831fb632bSRamuthevar Vadivel Murugan 80931fb632bSRamuthevar Vadivel Murugan static void cqspi_configure(struct cqspi_flash_pdata *f_pdata, 81031fb632bSRamuthevar Vadivel Murugan unsigned long sclk) 81131fb632bSRamuthevar Vadivel Murugan { 81231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 81331fb632bSRamuthevar Vadivel Murugan int switch_cs = (cqspi->current_cs != f_pdata->cs); 81431fb632bSRamuthevar Vadivel Murugan int switch_ck = (cqspi->sclk != sclk); 81531fb632bSRamuthevar Vadivel Murugan 81631fb632bSRamuthevar Vadivel Murugan if (switch_cs || switch_ck) 81731fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 81831fb632bSRamuthevar Vadivel Murugan 81931fb632bSRamuthevar Vadivel Murugan /* Switch chip select. */ 82031fb632bSRamuthevar Vadivel Murugan if (switch_cs) { 82131fb632bSRamuthevar Vadivel Murugan cqspi->current_cs = f_pdata->cs; 82231fb632bSRamuthevar Vadivel Murugan cqspi_chipselect(f_pdata); 82331fb632bSRamuthevar Vadivel Murugan } 82431fb632bSRamuthevar Vadivel Murugan 82531fb632bSRamuthevar Vadivel Murugan /* Setup baudrate divisor and delays */ 82631fb632bSRamuthevar Vadivel Murugan if (switch_ck) { 82731fb632bSRamuthevar Vadivel Murugan cqspi->sclk = sclk; 82831fb632bSRamuthevar Vadivel Murugan cqspi_config_baudrate_div(cqspi); 82931fb632bSRamuthevar Vadivel Murugan cqspi_delay(f_pdata); 83031fb632bSRamuthevar Vadivel Murugan cqspi_readdata_capture(cqspi, !cqspi->rclk_en, 83131fb632bSRamuthevar Vadivel Murugan f_pdata->read_delay); 83231fb632bSRamuthevar Vadivel Murugan } 83331fb632bSRamuthevar Vadivel Murugan 83431fb632bSRamuthevar Vadivel Murugan if (switch_cs || switch_ck) 83531fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1); 83631fb632bSRamuthevar Vadivel Murugan } 83731fb632bSRamuthevar Vadivel Murugan 83831fb632bSRamuthevar Vadivel Murugan static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata, 83931fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 84031fb632bSRamuthevar Vadivel Murugan { 84131fb632bSRamuthevar Vadivel Murugan f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE; 84231fb632bSRamuthevar Vadivel Murugan f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE; 84331fb632bSRamuthevar Vadivel Murugan f_pdata->data_width = CQSPI_INST_TYPE_SINGLE; 84431fb632bSRamuthevar Vadivel Murugan 84531fb632bSRamuthevar Vadivel Murugan if (op->data.dir == SPI_MEM_DATA_IN) { 84631fb632bSRamuthevar Vadivel Murugan switch (op->data.buswidth) { 84731fb632bSRamuthevar Vadivel Murugan case 1: 84831fb632bSRamuthevar Vadivel Murugan f_pdata->data_width = CQSPI_INST_TYPE_SINGLE; 84931fb632bSRamuthevar Vadivel Murugan break; 85031fb632bSRamuthevar Vadivel Murugan case 2: 85131fb632bSRamuthevar Vadivel Murugan f_pdata->data_width = CQSPI_INST_TYPE_DUAL; 85231fb632bSRamuthevar Vadivel Murugan break; 85331fb632bSRamuthevar Vadivel Murugan case 4: 85431fb632bSRamuthevar Vadivel Murugan f_pdata->data_width = CQSPI_INST_TYPE_QUAD; 85531fb632bSRamuthevar Vadivel Murugan break; 85631fb632bSRamuthevar Vadivel Murugan case 8: 85731fb632bSRamuthevar Vadivel Murugan f_pdata->data_width = CQSPI_INST_TYPE_OCTAL; 85831fb632bSRamuthevar Vadivel Murugan break; 85931fb632bSRamuthevar Vadivel Murugan default: 86031fb632bSRamuthevar Vadivel Murugan return -EINVAL; 86131fb632bSRamuthevar Vadivel Murugan } 86231fb632bSRamuthevar Vadivel Murugan } 86331fb632bSRamuthevar Vadivel Murugan 86431fb632bSRamuthevar Vadivel Murugan return 0; 86531fb632bSRamuthevar Vadivel Murugan } 86631fb632bSRamuthevar Vadivel Murugan 86731fb632bSRamuthevar Vadivel Murugan static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata, 86831fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 86931fb632bSRamuthevar Vadivel Murugan { 87031fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 87131fb632bSRamuthevar Vadivel Murugan loff_t to = op->addr.val; 87231fb632bSRamuthevar Vadivel Murugan size_t len = op->data.nbytes; 87331fb632bSRamuthevar Vadivel Murugan const u_char *buf = op->data.buf.out; 87431fb632bSRamuthevar Vadivel Murugan int ret; 87531fb632bSRamuthevar Vadivel Murugan 87631fb632bSRamuthevar Vadivel Murugan ret = cqspi_set_protocol(f_pdata, op); 87731fb632bSRamuthevar Vadivel Murugan if (ret) 87831fb632bSRamuthevar Vadivel Murugan return ret; 87931fb632bSRamuthevar Vadivel Murugan 88031fb632bSRamuthevar Vadivel Murugan ret = cqspi_write_setup(f_pdata, op); 88131fb632bSRamuthevar Vadivel Murugan if (ret) 88231fb632bSRamuthevar Vadivel Murugan return ret; 88331fb632bSRamuthevar Vadivel Murugan 88431fb632bSRamuthevar Vadivel Murugan if (cqspi->use_direct_mode && ((to + len) <= cqspi->ahb_size)) { 88531fb632bSRamuthevar Vadivel Murugan memcpy_toio(cqspi->ahb_base + to, buf, len); 88631fb632bSRamuthevar Vadivel Murugan return cqspi_wait_idle(cqspi); 88731fb632bSRamuthevar Vadivel Murugan } 88831fb632bSRamuthevar Vadivel Murugan 88931fb632bSRamuthevar Vadivel Murugan return cqspi_indirect_write_execute(f_pdata, to, buf, len); 89031fb632bSRamuthevar Vadivel Murugan } 89131fb632bSRamuthevar Vadivel Murugan 89231fb632bSRamuthevar Vadivel Murugan static void cqspi_rx_dma_callback(void *param) 89331fb632bSRamuthevar Vadivel Murugan { 89431fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = param; 89531fb632bSRamuthevar Vadivel Murugan 89631fb632bSRamuthevar Vadivel Murugan complete(&cqspi->rx_dma_complete); 89731fb632bSRamuthevar Vadivel Murugan } 89831fb632bSRamuthevar Vadivel Murugan 89931fb632bSRamuthevar Vadivel Murugan static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata, 90031fb632bSRamuthevar Vadivel Murugan u_char *buf, loff_t from, size_t len) 90131fb632bSRamuthevar Vadivel Murugan { 90231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 90331fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 90431fb632bSRamuthevar Vadivel Murugan enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; 90531fb632bSRamuthevar Vadivel Murugan dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from; 90631fb632bSRamuthevar Vadivel Murugan int ret = 0; 90731fb632bSRamuthevar Vadivel Murugan struct dma_async_tx_descriptor *tx; 90831fb632bSRamuthevar Vadivel Murugan dma_cookie_t cookie; 90931fb632bSRamuthevar Vadivel Murugan dma_addr_t dma_dst; 91031fb632bSRamuthevar Vadivel Murugan 91131fb632bSRamuthevar Vadivel Murugan if (!cqspi->rx_chan || !virt_addr_valid(buf)) { 91231fb632bSRamuthevar Vadivel Murugan memcpy_fromio(buf, cqspi->ahb_base + from, len); 91331fb632bSRamuthevar Vadivel Murugan return 0; 91431fb632bSRamuthevar Vadivel Murugan } 91531fb632bSRamuthevar Vadivel Murugan 91631fb632bSRamuthevar Vadivel Murugan dma_dst = dma_map_single(dev, buf, len, DMA_FROM_DEVICE); 91731fb632bSRamuthevar Vadivel Murugan if (dma_mapping_error(dev, dma_dst)) { 91831fb632bSRamuthevar Vadivel Murugan dev_err(dev, "dma mapping failed\n"); 91931fb632bSRamuthevar Vadivel Murugan return -ENOMEM; 92031fb632bSRamuthevar Vadivel Murugan } 92131fb632bSRamuthevar Vadivel Murugan tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src, 92231fb632bSRamuthevar Vadivel Murugan len, flags); 92331fb632bSRamuthevar Vadivel Murugan if (!tx) { 92431fb632bSRamuthevar Vadivel Murugan dev_err(dev, "device_prep_dma_memcpy error\n"); 92531fb632bSRamuthevar Vadivel Murugan ret = -EIO; 92631fb632bSRamuthevar Vadivel Murugan goto err_unmap; 92731fb632bSRamuthevar Vadivel Murugan } 92831fb632bSRamuthevar Vadivel Murugan 92931fb632bSRamuthevar Vadivel Murugan tx->callback = cqspi_rx_dma_callback; 93031fb632bSRamuthevar Vadivel Murugan tx->callback_param = cqspi; 93131fb632bSRamuthevar Vadivel Murugan cookie = tx->tx_submit(tx); 93231fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->rx_dma_complete); 93331fb632bSRamuthevar Vadivel Murugan 93431fb632bSRamuthevar Vadivel Murugan ret = dma_submit_error(cookie); 93531fb632bSRamuthevar Vadivel Murugan if (ret) { 93631fb632bSRamuthevar Vadivel Murugan dev_err(dev, "dma_submit_error %d\n", cookie); 93731fb632bSRamuthevar Vadivel Murugan ret = -EIO; 93831fb632bSRamuthevar Vadivel Murugan goto err_unmap; 93931fb632bSRamuthevar Vadivel Murugan } 94031fb632bSRamuthevar Vadivel Murugan 94131fb632bSRamuthevar Vadivel Murugan dma_async_issue_pending(cqspi->rx_chan); 94231fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->rx_dma_complete, 94331fb632bSRamuthevar Vadivel Murugan msecs_to_jiffies(len))) { 94431fb632bSRamuthevar Vadivel Murugan dmaengine_terminate_sync(cqspi->rx_chan); 94531fb632bSRamuthevar Vadivel Murugan dev_err(dev, "DMA wait_for_completion_timeout\n"); 94631fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 94731fb632bSRamuthevar Vadivel Murugan goto err_unmap; 94831fb632bSRamuthevar Vadivel Murugan } 94931fb632bSRamuthevar Vadivel Murugan 95031fb632bSRamuthevar Vadivel Murugan err_unmap: 95131fb632bSRamuthevar Vadivel Murugan dma_unmap_single(dev, dma_dst, len, DMA_FROM_DEVICE); 95231fb632bSRamuthevar Vadivel Murugan 95331fb632bSRamuthevar Vadivel Murugan return ret; 95431fb632bSRamuthevar Vadivel Murugan } 95531fb632bSRamuthevar Vadivel Murugan 95631fb632bSRamuthevar Vadivel Murugan static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata, 95731fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 95831fb632bSRamuthevar Vadivel Murugan { 95931fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 96031fb632bSRamuthevar Vadivel Murugan loff_t from = op->addr.val; 96131fb632bSRamuthevar Vadivel Murugan size_t len = op->data.nbytes; 96231fb632bSRamuthevar Vadivel Murugan u_char *buf = op->data.buf.in; 96331fb632bSRamuthevar Vadivel Murugan int ret; 96431fb632bSRamuthevar Vadivel Murugan 96531fb632bSRamuthevar Vadivel Murugan ret = cqspi_set_protocol(f_pdata, op); 96631fb632bSRamuthevar Vadivel Murugan if (ret) 96731fb632bSRamuthevar Vadivel Murugan return ret; 96831fb632bSRamuthevar Vadivel Murugan 96931fb632bSRamuthevar Vadivel Murugan ret = cqspi_read_setup(f_pdata, op); 97031fb632bSRamuthevar Vadivel Murugan if (ret) 97131fb632bSRamuthevar Vadivel Murugan return ret; 97231fb632bSRamuthevar Vadivel Murugan 97331fb632bSRamuthevar Vadivel Murugan if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) 97431fb632bSRamuthevar Vadivel Murugan return cqspi_direct_read_execute(f_pdata, buf, from, len); 97531fb632bSRamuthevar Vadivel Murugan 97631fb632bSRamuthevar Vadivel Murugan return cqspi_indirect_read_execute(f_pdata, buf, from, len); 97731fb632bSRamuthevar Vadivel Murugan } 97831fb632bSRamuthevar Vadivel Murugan 97931fb632bSRamuthevar Vadivel Murugan static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op) 98031fb632bSRamuthevar Vadivel Murugan { 98131fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); 98231fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata; 98331fb632bSRamuthevar Vadivel Murugan 98431fb632bSRamuthevar Vadivel Murugan f_pdata = &cqspi->f_pdata[mem->spi->chip_select]; 98531fb632bSRamuthevar Vadivel Murugan cqspi_configure(f_pdata, mem->spi->max_speed_hz); 98631fb632bSRamuthevar Vadivel Murugan 98731fb632bSRamuthevar Vadivel Murugan if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { 98831fb632bSRamuthevar Vadivel Murugan if (!op->addr.nbytes) 98931fb632bSRamuthevar Vadivel Murugan return cqspi_command_read(f_pdata, op); 99031fb632bSRamuthevar Vadivel Murugan 99131fb632bSRamuthevar Vadivel Murugan return cqspi_read(f_pdata, op); 99231fb632bSRamuthevar Vadivel Murugan } 99331fb632bSRamuthevar Vadivel Murugan 99431fb632bSRamuthevar Vadivel Murugan if (!op->addr.nbytes || !op->data.buf.out) 99531fb632bSRamuthevar Vadivel Murugan return cqspi_command_write(f_pdata, op); 99631fb632bSRamuthevar Vadivel Murugan 99731fb632bSRamuthevar Vadivel Murugan return cqspi_write(f_pdata, op); 99831fb632bSRamuthevar Vadivel Murugan } 99931fb632bSRamuthevar Vadivel Murugan 100031fb632bSRamuthevar Vadivel Murugan static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) 100131fb632bSRamuthevar Vadivel Murugan { 100231fb632bSRamuthevar Vadivel Murugan int ret; 100331fb632bSRamuthevar Vadivel Murugan 100431fb632bSRamuthevar Vadivel Murugan ret = cqspi_mem_process(mem, op); 100531fb632bSRamuthevar Vadivel Murugan if (ret) 100631fb632bSRamuthevar Vadivel Murugan dev_err(&mem->spi->dev, "operation failed with %d\n", ret); 100731fb632bSRamuthevar Vadivel Murugan 100831fb632bSRamuthevar Vadivel Murugan return ret; 100931fb632bSRamuthevar Vadivel Murugan } 101031fb632bSRamuthevar Vadivel Murugan 101131fb632bSRamuthevar Vadivel Murugan static int cqspi_of_get_flash_pdata(struct platform_device *pdev, 101231fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata, 101331fb632bSRamuthevar Vadivel Murugan struct device_node *np) 101431fb632bSRamuthevar Vadivel Murugan { 101531fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) { 101631fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine read-delay\n"); 101731fb632bSRamuthevar Vadivel Murugan return -ENXIO; 101831fb632bSRamuthevar Vadivel Murugan } 101931fb632bSRamuthevar Vadivel Murugan 102031fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) { 102131fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tshsl-ns\n"); 102231fb632bSRamuthevar Vadivel Murugan return -ENXIO; 102331fb632bSRamuthevar Vadivel Murugan } 102431fb632bSRamuthevar Vadivel Murugan 102531fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) { 102631fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n"); 102731fb632bSRamuthevar Vadivel Murugan return -ENXIO; 102831fb632bSRamuthevar Vadivel Murugan } 102931fb632bSRamuthevar Vadivel Murugan 103031fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) { 103131fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tchsh-ns\n"); 103231fb632bSRamuthevar Vadivel Murugan return -ENXIO; 103331fb632bSRamuthevar Vadivel Murugan } 103431fb632bSRamuthevar Vadivel Murugan 103531fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) { 103631fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tslch-ns\n"); 103731fb632bSRamuthevar Vadivel Murugan return -ENXIO; 103831fb632bSRamuthevar Vadivel Murugan } 103931fb632bSRamuthevar Vadivel Murugan 104031fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) { 104131fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n"); 104231fb632bSRamuthevar Vadivel Murugan return -ENXIO; 104331fb632bSRamuthevar Vadivel Murugan } 104431fb632bSRamuthevar Vadivel Murugan 104531fb632bSRamuthevar Vadivel Murugan return 0; 104631fb632bSRamuthevar Vadivel Murugan } 104731fb632bSRamuthevar Vadivel Murugan 104831fb632bSRamuthevar Vadivel Murugan static int cqspi_of_get_pdata(struct cqspi_st *cqspi) 104931fb632bSRamuthevar Vadivel Murugan { 105031fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 105131fb632bSRamuthevar Vadivel Murugan struct device_node *np = dev->of_node; 105231fb632bSRamuthevar Vadivel Murugan 105331fb632bSRamuthevar Vadivel Murugan cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); 105431fb632bSRamuthevar Vadivel Murugan 105531fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { 105631fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine fifo-depth\n"); 105731fb632bSRamuthevar Vadivel Murugan return -ENXIO; 105831fb632bSRamuthevar Vadivel Murugan } 105931fb632bSRamuthevar Vadivel Murugan 106031fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) { 106131fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine fifo-width\n"); 106231fb632bSRamuthevar Vadivel Murugan return -ENXIO; 106331fb632bSRamuthevar Vadivel Murugan } 106431fb632bSRamuthevar Vadivel Murugan 106531fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,trigger-address", 106631fb632bSRamuthevar Vadivel Murugan &cqspi->trigger_address)) { 106731fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine trigger-address\n"); 106831fb632bSRamuthevar Vadivel Murugan return -ENXIO; 106931fb632bSRamuthevar Vadivel Murugan } 107031fb632bSRamuthevar Vadivel Murugan 107131fb632bSRamuthevar Vadivel Murugan cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); 107231fb632bSRamuthevar Vadivel Murugan 107331fb632bSRamuthevar Vadivel Murugan return 0; 107431fb632bSRamuthevar Vadivel Murugan } 107531fb632bSRamuthevar Vadivel Murugan 107631fb632bSRamuthevar Vadivel Murugan static void cqspi_controller_init(struct cqspi_st *cqspi) 107731fb632bSRamuthevar Vadivel Murugan { 107831fb632bSRamuthevar Vadivel Murugan u32 reg; 107931fb632bSRamuthevar Vadivel Murugan 108031fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 108131fb632bSRamuthevar Vadivel Murugan 108231fb632bSRamuthevar Vadivel Murugan /* Configure the remap address register, no remap */ 108331fb632bSRamuthevar Vadivel Murugan writel(0, cqspi->iobase + CQSPI_REG_REMAP); 108431fb632bSRamuthevar Vadivel Murugan 108531fb632bSRamuthevar Vadivel Murugan /* Disable all interrupts. */ 108631fb632bSRamuthevar Vadivel Murugan writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); 108731fb632bSRamuthevar Vadivel Murugan 108831fb632bSRamuthevar Vadivel Murugan /* Configure the SRAM split to 1:1 . */ 108931fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); 109031fb632bSRamuthevar Vadivel Murugan 109131fb632bSRamuthevar Vadivel Murugan /* Load indirect trigger address. */ 109231fb632bSRamuthevar Vadivel Murugan writel(cqspi->trigger_address, 109331fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); 109431fb632bSRamuthevar Vadivel Murugan 109531fb632bSRamuthevar Vadivel Murugan /* Program read watermark -- 1/2 of the FIFO. */ 109631fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth * cqspi->fifo_width / 2, 109731fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); 109831fb632bSRamuthevar Vadivel Murugan /* Program write watermark -- 1/8 of the FIFO. */ 109931fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth * cqspi->fifo_width / 8, 110031fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); 110131fb632bSRamuthevar Vadivel Murugan 110231fb632bSRamuthevar Vadivel Murugan /* Enable Direct Access Controller */ 110331fb632bSRamuthevar Vadivel Murugan reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 110431fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL; 110531fb632bSRamuthevar Vadivel Murugan writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 110631fb632bSRamuthevar Vadivel Murugan 110731fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1); 110831fb632bSRamuthevar Vadivel Murugan } 110931fb632bSRamuthevar Vadivel Murugan 111031fb632bSRamuthevar Vadivel Murugan static int cqspi_request_mmap_dma(struct cqspi_st *cqspi) 111131fb632bSRamuthevar Vadivel Murugan { 111231fb632bSRamuthevar Vadivel Murugan dma_cap_mask_t mask; 111331fb632bSRamuthevar Vadivel Murugan 111431fb632bSRamuthevar Vadivel Murugan dma_cap_zero(mask); 111531fb632bSRamuthevar Vadivel Murugan dma_cap_set(DMA_MEMCPY, mask); 111631fb632bSRamuthevar Vadivel Murugan 111731fb632bSRamuthevar Vadivel Murugan cqspi->rx_chan = dma_request_chan_by_mask(&mask); 111831fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->rx_chan)) { 111931fb632bSRamuthevar Vadivel Murugan int ret = PTR_ERR(cqspi->rx_chan); 112031fb632bSRamuthevar Vadivel Murugan cqspi->rx_chan = NULL; 1121436a5c20SKrzysztof Kozlowski return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n"); 112231fb632bSRamuthevar Vadivel Murugan } 112331fb632bSRamuthevar Vadivel Murugan init_completion(&cqspi->rx_dma_complete); 112431fb632bSRamuthevar Vadivel Murugan 112531fb632bSRamuthevar Vadivel Murugan return 0; 112631fb632bSRamuthevar Vadivel Murugan } 112731fb632bSRamuthevar Vadivel Murugan 112831fb632bSRamuthevar Vadivel Murugan static const struct spi_controller_mem_ops cqspi_mem_ops = { 112931fb632bSRamuthevar Vadivel Murugan .exec_op = cqspi_exec_mem_op, 113031fb632bSRamuthevar Vadivel Murugan }; 113131fb632bSRamuthevar Vadivel Murugan 113231fb632bSRamuthevar Vadivel Murugan static int cqspi_setup_flash(struct cqspi_st *cqspi) 113331fb632bSRamuthevar Vadivel Murugan { 113431fb632bSRamuthevar Vadivel Murugan struct platform_device *pdev = cqspi->pdev; 113531fb632bSRamuthevar Vadivel Murugan struct device *dev = &pdev->dev; 113631fb632bSRamuthevar Vadivel Murugan struct device_node *np = dev->of_node; 113731fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata; 113831fb632bSRamuthevar Vadivel Murugan unsigned int cs; 113931fb632bSRamuthevar Vadivel Murugan int ret; 114031fb632bSRamuthevar Vadivel Murugan 114131fb632bSRamuthevar Vadivel Murugan /* Get flash device data */ 114231fb632bSRamuthevar Vadivel Murugan for_each_available_child_of_node(dev->of_node, np) { 114331fb632bSRamuthevar Vadivel Murugan ret = of_property_read_u32(np, "reg", &cs); 114431fb632bSRamuthevar Vadivel Murugan if (ret) { 114531fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Couldn't determine chip select.\n"); 114631fb632bSRamuthevar Vadivel Murugan return ret; 114731fb632bSRamuthevar Vadivel Murugan } 114831fb632bSRamuthevar Vadivel Murugan 114931fb632bSRamuthevar Vadivel Murugan if (cs >= CQSPI_MAX_CHIPSELECT) { 115031fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Chip select %d out of range.\n", cs); 115131fb632bSRamuthevar Vadivel Murugan return -EINVAL; 115231fb632bSRamuthevar Vadivel Murugan } 115331fb632bSRamuthevar Vadivel Murugan 115431fb632bSRamuthevar Vadivel Murugan f_pdata = &cqspi->f_pdata[cs]; 115531fb632bSRamuthevar Vadivel Murugan f_pdata->cqspi = cqspi; 115631fb632bSRamuthevar Vadivel Murugan f_pdata->cs = cs; 115731fb632bSRamuthevar Vadivel Murugan 115831fb632bSRamuthevar Vadivel Murugan ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np); 115931fb632bSRamuthevar Vadivel Murugan if (ret) 116031fb632bSRamuthevar Vadivel Murugan return ret; 116131fb632bSRamuthevar Vadivel Murugan } 116231fb632bSRamuthevar Vadivel Murugan 116331fb632bSRamuthevar Vadivel Murugan return 0; 116431fb632bSRamuthevar Vadivel Murugan } 116531fb632bSRamuthevar Vadivel Murugan 116631fb632bSRamuthevar Vadivel Murugan static int cqspi_probe(struct platform_device *pdev) 116731fb632bSRamuthevar Vadivel Murugan { 116831fb632bSRamuthevar Vadivel Murugan const struct cqspi_driver_platdata *ddata; 116931fb632bSRamuthevar Vadivel Murugan struct reset_control *rstc, *rstc_ocp; 117031fb632bSRamuthevar Vadivel Murugan struct device *dev = &pdev->dev; 117131fb632bSRamuthevar Vadivel Murugan struct spi_master *master; 117231fb632bSRamuthevar Vadivel Murugan struct resource *res_ahb; 117331fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi; 117431fb632bSRamuthevar Vadivel Murugan struct resource *res; 117531fb632bSRamuthevar Vadivel Murugan int ret; 117631fb632bSRamuthevar Vadivel Murugan int irq; 117731fb632bSRamuthevar Vadivel Murugan 117831fb632bSRamuthevar Vadivel Murugan master = spi_alloc_master(&pdev->dev, sizeof(*cqspi)); 117931fb632bSRamuthevar Vadivel Murugan if (!master) { 118031fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "spi_alloc_master failed\n"); 118131fb632bSRamuthevar Vadivel Murugan return -ENOMEM; 118231fb632bSRamuthevar Vadivel Murugan } 118331fb632bSRamuthevar Vadivel Murugan master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; 118431fb632bSRamuthevar Vadivel Murugan master->mem_ops = &cqspi_mem_ops; 118531fb632bSRamuthevar Vadivel Murugan master->dev.of_node = pdev->dev.of_node; 118631fb632bSRamuthevar Vadivel Murugan 118731fb632bSRamuthevar Vadivel Murugan cqspi = spi_master_get_devdata(master); 118831fb632bSRamuthevar Vadivel Murugan 118931fb632bSRamuthevar Vadivel Murugan cqspi->pdev = pdev; 119031fb632bSRamuthevar Vadivel Murugan 119131fb632bSRamuthevar Vadivel Murugan /* Obtain configuration from OF. */ 119231fb632bSRamuthevar Vadivel Murugan ret = cqspi_of_get_pdata(cqspi); 119331fb632bSRamuthevar Vadivel Murugan if (ret) { 119431fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get mandatory OF data.\n"); 119531fb632bSRamuthevar Vadivel Murugan ret = -ENODEV; 119631fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 119731fb632bSRamuthevar Vadivel Murugan } 119831fb632bSRamuthevar Vadivel Murugan 119931fb632bSRamuthevar Vadivel Murugan /* Obtain QSPI clock. */ 120031fb632bSRamuthevar Vadivel Murugan cqspi->clk = devm_clk_get(dev, NULL); 120131fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->clk)) { 120231fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot claim QSPI clock.\n"); 120331fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->clk); 120431fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 120531fb632bSRamuthevar Vadivel Murugan } 120631fb632bSRamuthevar Vadivel Murugan 120731fb632bSRamuthevar Vadivel Murugan /* Obtain and remap controller address. */ 120831fb632bSRamuthevar Vadivel Murugan res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 120931fb632bSRamuthevar Vadivel Murugan cqspi->iobase = devm_ioremap_resource(dev, res); 121031fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->iobase)) { 121131fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot remap controller address.\n"); 121231fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->iobase); 121331fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 121431fb632bSRamuthevar Vadivel Murugan } 121531fb632bSRamuthevar Vadivel Murugan 121631fb632bSRamuthevar Vadivel Murugan /* Obtain and remap AHB address. */ 121731fb632bSRamuthevar Vadivel Murugan res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1); 121831fb632bSRamuthevar Vadivel Murugan cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb); 121931fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->ahb_base)) { 122031fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot remap AHB address.\n"); 122131fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->ahb_base); 122231fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 122331fb632bSRamuthevar Vadivel Murugan } 122431fb632bSRamuthevar Vadivel Murugan cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start; 122531fb632bSRamuthevar Vadivel Murugan cqspi->ahb_size = resource_size(res_ahb); 122631fb632bSRamuthevar Vadivel Murugan 122731fb632bSRamuthevar Vadivel Murugan init_completion(&cqspi->transfer_complete); 122831fb632bSRamuthevar Vadivel Murugan 122931fb632bSRamuthevar Vadivel Murugan /* Obtain IRQ line. */ 123031fb632bSRamuthevar Vadivel Murugan irq = platform_get_irq(pdev, 0); 123131fb632bSRamuthevar Vadivel Murugan if (irq < 0) { 123231fb632bSRamuthevar Vadivel Murugan ret = -ENXIO; 123331fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 123431fb632bSRamuthevar Vadivel Murugan } 123531fb632bSRamuthevar Vadivel Murugan 123631fb632bSRamuthevar Vadivel Murugan pm_runtime_enable(dev); 123731fb632bSRamuthevar Vadivel Murugan ret = pm_runtime_get_sync(dev); 123831fb632bSRamuthevar Vadivel Murugan if (ret < 0) { 123931fb632bSRamuthevar Vadivel Murugan pm_runtime_put_noidle(dev); 124031fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 124131fb632bSRamuthevar Vadivel Murugan } 124231fb632bSRamuthevar Vadivel Murugan 124331fb632bSRamuthevar Vadivel Murugan ret = clk_prepare_enable(cqspi->clk); 124431fb632bSRamuthevar Vadivel Murugan if (ret) { 124531fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot enable QSPI clock.\n"); 124631fb632bSRamuthevar Vadivel Murugan goto probe_clk_failed; 124731fb632bSRamuthevar Vadivel Murugan } 124831fb632bSRamuthevar Vadivel Murugan 124931fb632bSRamuthevar Vadivel Murugan /* Obtain QSPI reset control */ 125031fb632bSRamuthevar Vadivel Murugan rstc = devm_reset_control_get_optional_exclusive(dev, "qspi"); 125131fb632bSRamuthevar Vadivel Murugan if (IS_ERR(rstc)) { 125231fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get QSPI reset.\n"); 125331fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 125431fb632bSRamuthevar Vadivel Murugan } 125531fb632bSRamuthevar Vadivel Murugan 125631fb632bSRamuthevar Vadivel Murugan rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); 125731fb632bSRamuthevar Vadivel Murugan if (IS_ERR(rstc_ocp)) { 125831fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get QSPI OCP reset.\n"); 125931fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 126031fb632bSRamuthevar Vadivel Murugan } 126131fb632bSRamuthevar Vadivel Murugan 126231fb632bSRamuthevar Vadivel Murugan reset_control_assert(rstc); 126331fb632bSRamuthevar Vadivel Murugan reset_control_deassert(rstc); 126431fb632bSRamuthevar Vadivel Murugan 126531fb632bSRamuthevar Vadivel Murugan reset_control_assert(rstc_ocp); 126631fb632bSRamuthevar Vadivel Murugan reset_control_deassert(rstc_ocp); 126731fb632bSRamuthevar Vadivel Murugan 126831fb632bSRamuthevar Vadivel Murugan cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); 126931fb632bSRamuthevar Vadivel Murugan ddata = of_device_get_match_data(dev); 127031fb632bSRamuthevar Vadivel Murugan if (ddata) { 127131fb632bSRamuthevar Vadivel Murugan if (ddata->quirks & CQSPI_NEEDS_WR_DELAY) 127231fb632bSRamuthevar Vadivel Murugan cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC, 127331fb632bSRamuthevar Vadivel Murugan cqspi->master_ref_clk_hz); 127431fb632bSRamuthevar Vadivel Murugan if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL) 127531fb632bSRamuthevar Vadivel Murugan master->mode_bits |= SPI_RX_OCTAL; 127631fb632bSRamuthevar Vadivel Murugan if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) 127731fb632bSRamuthevar Vadivel Murugan cqspi->use_direct_mode = true; 127831fb632bSRamuthevar Vadivel Murugan } 127931fb632bSRamuthevar Vadivel Murugan 128031fb632bSRamuthevar Vadivel Murugan ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0, 128131fb632bSRamuthevar Vadivel Murugan pdev->name, cqspi); 128231fb632bSRamuthevar Vadivel Murugan if (ret) { 128331fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot request IRQ.\n"); 128431fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 128531fb632bSRamuthevar Vadivel Murugan } 128631fb632bSRamuthevar Vadivel Murugan 128731fb632bSRamuthevar Vadivel Murugan cqspi_wait_idle(cqspi); 128831fb632bSRamuthevar Vadivel Murugan cqspi_controller_init(cqspi); 128931fb632bSRamuthevar Vadivel Murugan cqspi->current_cs = -1; 129031fb632bSRamuthevar Vadivel Murugan cqspi->sclk = 0; 129131fb632bSRamuthevar Vadivel Murugan 129231fb632bSRamuthevar Vadivel Murugan ret = cqspi_setup_flash(cqspi); 129331fb632bSRamuthevar Vadivel Murugan if (ret) { 129431fb632bSRamuthevar Vadivel Murugan dev_err(dev, "failed to setup flash parameters %d\n", ret); 129531fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 129631fb632bSRamuthevar Vadivel Murugan } 129731fb632bSRamuthevar Vadivel Murugan 129831fb632bSRamuthevar Vadivel Murugan if (cqspi->use_direct_mode) { 129931fb632bSRamuthevar Vadivel Murugan ret = cqspi_request_mmap_dma(cqspi); 130031fb632bSRamuthevar Vadivel Murugan if (ret == -EPROBE_DEFER) 130131fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 130231fb632bSRamuthevar Vadivel Murugan } 130331fb632bSRamuthevar Vadivel Murugan 130431fb632bSRamuthevar Vadivel Murugan ret = devm_spi_register_master(dev, master); 130531fb632bSRamuthevar Vadivel Murugan if (ret) { 130631fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret); 130731fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 130831fb632bSRamuthevar Vadivel Murugan } 130931fb632bSRamuthevar Vadivel Murugan 131031fb632bSRamuthevar Vadivel Murugan return 0; 131131fb632bSRamuthevar Vadivel Murugan probe_setup_failed: 131231fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 131331fb632bSRamuthevar Vadivel Murugan probe_reset_failed: 131431fb632bSRamuthevar Vadivel Murugan clk_disable_unprepare(cqspi->clk); 131531fb632bSRamuthevar Vadivel Murugan probe_clk_failed: 131631fb632bSRamuthevar Vadivel Murugan pm_runtime_put_sync(dev); 131731fb632bSRamuthevar Vadivel Murugan pm_runtime_disable(dev); 131831fb632bSRamuthevar Vadivel Murugan probe_master_put: 131931fb632bSRamuthevar Vadivel Murugan spi_master_put(master); 132031fb632bSRamuthevar Vadivel Murugan return ret; 132131fb632bSRamuthevar Vadivel Murugan } 132231fb632bSRamuthevar Vadivel Murugan 132331fb632bSRamuthevar Vadivel Murugan static int cqspi_remove(struct platform_device *pdev) 132431fb632bSRamuthevar Vadivel Murugan { 132531fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = platform_get_drvdata(pdev); 132631fb632bSRamuthevar Vadivel Murugan 132731fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 132831fb632bSRamuthevar Vadivel Murugan 132931fb632bSRamuthevar Vadivel Murugan if (cqspi->rx_chan) 133031fb632bSRamuthevar Vadivel Murugan dma_release_channel(cqspi->rx_chan); 133131fb632bSRamuthevar Vadivel Murugan 133231fb632bSRamuthevar Vadivel Murugan clk_disable_unprepare(cqspi->clk); 133331fb632bSRamuthevar Vadivel Murugan 133431fb632bSRamuthevar Vadivel Murugan pm_runtime_put_sync(&pdev->dev); 133531fb632bSRamuthevar Vadivel Murugan pm_runtime_disable(&pdev->dev); 133631fb632bSRamuthevar Vadivel Murugan 133731fb632bSRamuthevar Vadivel Murugan return 0; 133831fb632bSRamuthevar Vadivel Murugan } 133931fb632bSRamuthevar Vadivel Murugan 134031fb632bSRamuthevar Vadivel Murugan #ifdef CONFIG_PM_SLEEP 134131fb632bSRamuthevar Vadivel Murugan static int cqspi_suspend(struct device *dev) 134231fb632bSRamuthevar Vadivel Murugan { 134331fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev_get_drvdata(dev); 134431fb632bSRamuthevar Vadivel Murugan 134531fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 134631fb632bSRamuthevar Vadivel Murugan return 0; 134731fb632bSRamuthevar Vadivel Murugan } 134831fb632bSRamuthevar Vadivel Murugan 134931fb632bSRamuthevar Vadivel Murugan static int cqspi_resume(struct device *dev) 135031fb632bSRamuthevar Vadivel Murugan { 135131fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev_get_drvdata(dev); 135231fb632bSRamuthevar Vadivel Murugan 135331fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1); 135431fb632bSRamuthevar Vadivel Murugan return 0; 135531fb632bSRamuthevar Vadivel Murugan } 135631fb632bSRamuthevar Vadivel Murugan 135731fb632bSRamuthevar Vadivel Murugan static const struct dev_pm_ops cqspi__dev_pm_ops = { 135831fb632bSRamuthevar Vadivel Murugan .suspend = cqspi_suspend, 135931fb632bSRamuthevar Vadivel Murugan .resume = cqspi_resume, 136031fb632bSRamuthevar Vadivel Murugan }; 136131fb632bSRamuthevar Vadivel Murugan 136231fb632bSRamuthevar Vadivel Murugan #define CQSPI_DEV_PM_OPS (&cqspi__dev_pm_ops) 136331fb632bSRamuthevar Vadivel Murugan #else 136431fb632bSRamuthevar Vadivel Murugan #define CQSPI_DEV_PM_OPS NULL 136531fb632bSRamuthevar Vadivel Murugan #endif 136631fb632bSRamuthevar Vadivel Murugan 136731fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata cdns_qspi = { 136831fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_DISABLE_DAC_MODE, 136931fb632bSRamuthevar Vadivel Murugan }; 137031fb632bSRamuthevar Vadivel Murugan 137131fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata k2g_qspi = { 137231fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_NEEDS_WR_DELAY, 137331fb632bSRamuthevar Vadivel Murugan }; 137431fb632bSRamuthevar Vadivel Murugan 137531fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata am654_ospi = { 137631fb632bSRamuthevar Vadivel Murugan .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 137731fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_NEEDS_WR_DELAY, 137831fb632bSRamuthevar Vadivel Murugan }; 137931fb632bSRamuthevar Vadivel Murugan 138031fb632bSRamuthevar Vadivel Murugan static const struct of_device_id cqspi_dt_ids[] = { 138131fb632bSRamuthevar Vadivel Murugan { 138231fb632bSRamuthevar Vadivel Murugan .compatible = "cdns,qspi-nor", 138331fb632bSRamuthevar Vadivel Murugan .data = &cdns_qspi, 138431fb632bSRamuthevar Vadivel Murugan }, 138531fb632bSRamuthevar Vadivel Murugan { 138631fb632bSRamuthevar Vadivel Murugan .compatible = "ti,k2g-qspi", 138731fb632bSRamuthevar Vadivel Murugan .data = &k2g_qspi, 138831fb632bSRamuthevar Vadivel Murugan }, 138931fb632bSRamuthevar Vadivel Murugan { 139031fb632bSRamuthevar Vadivel Murugan .compatible = "ti,am654-ospi", 139131fb632bSRamuthevar Vadivel Murugan .data = &am654_ospi, 139231fb632bSRamuthevar Vadivel Murugan }, 139331fb632bSRamuthevar Vadivel Murugan { /* end of table */ } 139431fb632bSRamuthevar Vadivel Murugan }; 139531fb632bSRamuthevar Vadivel Murugan 139631fb632bSRamuthevar Vadivel Murugan MODULE_DEVICE_TABLE(of, cqspi_dt_ids); 139731fb632bSRamuthevar Vadivel Murugan 139831fb632bSRamuthevar Vadivel Murugan static struct platform_driver cqspi_platform_driver = { 139931fb632bSRamuthevar Vadivel Murugan .probe = cqspi_probe, 140031fb632bSRamuthevar Vadivel Murugan .remove = cqspi_remove, 140131fb632bSRamuthevar Vadivel Murugan .driver = { 140231fb632bSRamuthevar Vadivel Murugan .name = CQSPI_NAME, 140331fb632bSRamuthevar Vadivel Murugan .pm = CQSPI_DEV_PM_OPS, 140431fb632bSRamuthevar Vadivel Murugan .of_match_table = cqspi_dt_ids, 140531fb632bSRamuthevar Vadivel Murugan }, 140631fb632bSRamuthevar Vadivel Murugan }; 140731fb632bSRamuthevar Vadivel Murugan 140831fb632bSRamuthevar Vadivel Murugan module_platform_driver(cqspi_platform_driver); 140931fb632bSRamuthevar Vadivel Murugan 141031fb632bSRamuthevar Vadivel Murugan MODULE_DESCRIPTION("Cadence QSPI Controller Driver"); 141131fb632bSRamuthevar Vadivel Murugan MODULE_LICENSE("GPL v2"); 141231fb632bSRamuthevar Vadivel Murugan MODULE_ALIAS("platform:" CQSPI_NAME); 141331fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>"); 141431fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>"); 141531fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>"); 141631fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>"); 1417