131fb632bSRamuthevar Vadivel Murugan // SPDX-License-Identifier: GPL-2.0-only 231fb632bSRamuthevar Vadivel Murugan // 331fb632bSRamuthevar Vadivel Murugan // Driver for Cadence QSPI Controller 431fb632bSRamuthevar Vadivel Murugan // 531fb632bSRamuthevar Vadivel Murugan // Copyright Altera Corporation (C) 2012-2014. All rights reserved. 631fb632bSRamuthevar Vadivel Murugan // Copyright Intel Corporation (C) 2019-2020. All rights reserved. 731fb632bSRamuthevar Vadivel Murugan // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 831fb632bSRamuthevar Vadivel Murugan 931fb632bSRamuthevar Vadivel Murugan #include <linux/clk.h> 1031fb632bSRamuthevar Vadivel Murugan #include <linux/completion.h> 1131fb632bSRamuthevar Vadivel Murugan #include <linux/delay.h> 1231fb632bSRamuthevar Vadivel Murugan #include <linux/dma-mapping.h> 1331fb632bSRamuthevar Vadivel Murugan #include <linux/dmaengine.h> 1431fb632bSRamuthevar Vadivel Murugan #include <linux/err.h> 1531fb632bSRamuthevar Vadivel Murugan #include <linux/errno.h> 1609e393e3SSai Krishna Potthuri #include <linux/firmware/xlnx-zynqmp.h> 1731fb632bSRamuthevar Vadivel Murugan #include <linux/interrupt.h> 1831fb632bSRamuthevar Vadivel Murugan #include <linux/io.h> 1931fb632bSRamuthevar Vadivel Murugan #include <linux/iopoll.h> 2031fb632bSRamuthevar Vadivel Murugan #include <linux/jiffies.h> 2131fb632bSRamuthevar Vadivel Murugan #include <linux/kernel.h> 2231fb632bSRamuthevar Vadivel Murugan #include <linux/module.h> 2331fb632bSRamuthevar Vadivel Murugan #include <linux/of_device.h> 2431fb632bSRamuthevar Vadivel Murugan #include <linux/of.h> 2531fb632bSRamuthevar Vadivel Murugan #include <linux/platform_device.h> 2631fb632bSRamuthevar Vadivel Murugan #include <linux/pm_runtime.h> 2731fb632bSRamuthevar Vadivel Murugan #include <linux/reset.h> 2831fb632bSRamuthevar Vadivel Murugan #include <linux/sched.h> 2931fb632bSRamuthevar Vadivel Murugan #include <linux/spi/spi.h> 3031fb632bSRamuthevar Vadivel Murugan #include <linux/spi/spi-mem.h> 3131fb632bSRamuthevar Vadivel Murugan #include <linux/timer.h> 3231fb632bSRamuthevar Vadivel Murugan 3331fb632bSRamuthevar Vadivel Murugan #define CQSPI_NAME "cadence-qspi" 3431fb632bSRamuthevar Vadivel Murugan #define CQSPI_MAX_CHIPSELECT 16 3531fb632bSRamuthevar Vadivel Murugan 3631fb632bSRamuthevar Vadivel Murugan /* Quirks */ 3731fb632bSRamuthevar Vadivel Murugan #define CQSPI_NEEDS_WR_DELAY BIT(0) 3831fb632bSRamuthevar Vadivel Murugan #define CQSPI_DISABLE_DAC_MODE BIT(1) 39*1a6f854fSSai Krishna Potthuri #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) 4031fb632bSRamuthevar Vadivel Murugan 4131fb632bSRamuthevar Vadivel Murugan /* Capabilities */ 4231fb632bSRamuthevar Vadivel Murugan #define CQSPI_SUPPORTS_OCTAL BIT(0) 4331fb632bSRamuthevar Vadivel Murugan 4431fb632bSRamuthevar Vadivel Murugan struct cqspi_st; 4531fb632bSRamuthevar Vadivel Murugan 4631fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata { 4731fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi; 4831fb632bSRamuthevar Vadivel Murugan u32 clk_rate; 4931fb632bSRamuthevar Vadivel Murugan u32 read_delay; 5031fb632bSRamuthevar Vadivel Murugan u32 tshsl_ns; 5131fb632bSRamuthevar Vadivel Murugan u32 tsd2d_ns; 5231fb632bSRamuthevar Vadivel Murugan u32 tchsh_ns; 5331fb632bSRamuthevar Vadivel Murugan u32 tslch_ns; 5431fb632bSRamuthevar Vadivel Murugan u8 inst_width; 5531fb632bSRamuthevar Vadivel Murugan u8 addr_width; 5631fb632bSRamuthevar Vadivel Murugan u8 data_width; 57f453f293SPratyush Yadav bool dtr; 5831fb632bSRamuthevar Vadivel Murugan u8 cs; 5931fb632bSRamuthevar Vadivel Murugan }; 6031fb632bSRamuthevar Vadivel Murugan 6131fb632bSRamuthevar Vadivel Murugan struct cqspi_st { 6231fb632bSRamuthevar Vadivel Murugan struct platform_device *pdev; 6331fb632bSRamuthevar Vadivel Murugan 6431fb632bSRamuthevar Vadivel Murugan struct clk *clk; 6531fb632bSRamuthevar Vadivel Murugan unsigned int sclk; 6631fb632bSRamuthevar Vadivel Murugan 6731fb632bSRamuthevar Vadivel Murugan void __iomem *iobase; 6831fb632bSRamuthevar Vadivel Murugan void __iomem *ahb_base; 6931fb632bSRamuthevar Vadivel Murugan resource_size_t ahb_size; 7031fb632bSRamuthevar Vadivel Murugan struct completion transfer_complete; 7131fb632bSRamuthevar Vadivel Murugan 7231fb632bSRamuthevar Vadivel Murugan struct dma_chan *rx_chan; 7331fb632bSRamuthevar Vadivel Murugan struct completion rx_dma_complete; 7431fb632bSRamuthevar Vadivel Murugan dma_addr_t mmap_phys_base; 7531fb632bSRamuthevar Vadivel Murugan 7631fb632bSRamuthevar Vadivel Murugan int current_cs; 7731fb632bSRamuthevar Vadivel Murugan unsigned long master_ref_clk_hz; 7831fb632bSRamuthevar Vadivel Murugan bool is_decoded_cs; 7931fb632bSRamuthevar Vadivel Murugan u32 fifo_depth; 8031fb632bSRamuthevar Vadivel Murugan u32 fifo_width; 81b436fb7dSRamuthevar Vadivel Murugan u32 num_chipselect; 8231fb632bSRamuthevar Vadivel Murugan bool rclk_en; 8331fb632bSRamuthevar Vadivel Murugan u32 trigger_address; 8431fb632bSRamuthevar Vadivel Murugan u32 wr_delay; 8531fb632bSRamuthevar Vadivel Murugan bool use_direct_mode; 8631fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; 87*1a6f854fSSai Krishna Potthuri bool use_dma_read; 8809e393e3SSai Krishna Potthuri u32 pd_dev_id; 8931fb632bSRamuthevar Vadivel Murugan }; 9031fb632bSRamuthevar Vadivel Murugan 9131fb632bSRamuthevar Vadivel Murugan struct cqspi_driver_platdata { 9231fb632bSRamuthevar Vadivel Murugan u32 hwcaps_mask; 9331fb632bSRamuthevar Vadivel Murugan u8 quirks; 94*1a6f854fSSai Krishna Potthuri int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata, 95*1a6f854fSSai Krishna Potthuri u_char *rxbuf, loff_t from_addr, size_t n_rx); 96*1a6f854fSSai Krishna Potthuri u32 (*get_dma_status)(struct cqspi_st *cqspi); 9731fb632bSRamuthevar Vadivel Murugan }; 9831fb632bSRamuthevar Vadivel Murugan 9931fb632bSRamuthevar Vadivel Murugan /* Operation timeout value */ 10031fb632bSRamuthevar Vadivel Murugan #define CQSPI_TIMEOUT_MS 500 10131fb632bSRamuthevar Vadivel Murugan #define CQSPI_READ_TIMEOUT_MS 10 10231fb632bSRamuthevar Vadivel Murugan 10331fb632bSRamuthevar Vadivel Murugan /* Instruction type */ 10431fb632bSRamuthevar Vadivel Murugan #define CQSPI_INST_TYPE_SINGLE 0 10531fb632bSRamuthevar Vadivel Murugan #define CQSPI_INST_TYPE_DUAL 1 10631fb632bSRamuthevar Vadivel Murugan #define CQSPI_INST_TYPE_QUAD 2 10731fb632bSRamuthevar Vadivel Murugan #define CQSPI_INST_TYPE_OCTAL 3 10831fb632bSRamuthevar Vadivel Murugan 10931fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_CLKS_PER_BYTE 8 11031fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_BYTES_MAX 4 11131fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_CLKS_MAX 31 11231fb632bSRamuthevar Vadivel Murugan 11331fb632bSRamuthevar Vadivel Murugan #define CQSPI_STIG_DATA_LEN_MAX 8 11431fb632bSRamuthevar Vadivel Murugan 11531fb632bSRamuthevar Vadivel Murugan /* Register map */ 11631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG 0x00 11731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0) 11831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7) 11931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9) 12031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 12131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_DMA_MASK BIT(15) 12231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_BAUD_LSB 19 123f453f293SPratyush Yadav #define CQSPI_REG_CONFIG_DTR_PROTO BIT(24) 124f453f293SPratyush Yadav #define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30) 12531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_IDLE_LSB 31 12631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF 12731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_BAUD_MASK 0xF 12831fb632bSRamuthevar Vadivel Murugan 12931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR 0x04 13031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 13131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 13231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 13331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 13431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 13531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 13631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 13731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 13831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 13931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F 14031fb632bSRamuthevar Vadivel Murugan 14131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR 0x08 14231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 14331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12 14431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16 14531fb632bSRamuthevar Vadivel Murugan 14631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY 0x0C 14731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSLCH_LSB 0 14831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TCHSH_LSB 8 14931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSD2D_LSB 16 15031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSHSL_LSB 24 15131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF 15231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF 15331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF 15431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF 15531fb632bSRamuthevar Vadivel Murugan 15631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE 0x10 15731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0 15831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_DELAY_LSB 1 15931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF 16031fb632bSRamuthevar Vadivel Murugan 16131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE 0x14 16231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_ADDRESS_LSB 0 16331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_PAGE_LSB 4 16431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_BLOCK_LSB 16 16531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF 16631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF 16731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F 16831fb632bSRamuthevar Vadivel Murugan 16931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SRAMPARTITION 0x18 17031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTTRIGGER 0x1C 17131fb632bSRamuthevar Vadivel Murugan 17231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA 0x20 17331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_SINGLE_LSB 0 17431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_BURST_LSB 8 17531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_SINGLE_MASK 0xFF 17631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_BURST_MASK 0xFF 17731fb632bSRamuthevar Vadivel Murugan 17831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_REMAP 0x24 17931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_MODE_BIT 0x28 18031fb632bSRamuthevar Vadivel Murugan 18131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL 0x2C 18231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 18331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 18431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF 18531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF 18631fb632bSRamuthevar Vadivel Murugan 187f453f293SPratyush Yadav #define CQSPI_REG_WR_COMPLETION_CTRL 0x38 188f453f293SPratyush Yadav #define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14) 189f453f293SPratyush Yadav 19031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQSTATUS 0x40 19131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQMASK 0x44 19231fb632bSRamuthevar Vadivel Murugan 19331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD 0x60 19431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0) 19531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1) 19631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5) 19731fb632bSRamuthevar Vadivel Murugan 19831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDWATERMARK 0x64 19931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 20031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDBYTES 0x6C 20131fb632bSRamuthevar Vadivel Murugan 20231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL 0x90 20331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0) 20431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1) 205888d517bSPratyush Yadav #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 20631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 20731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 20831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 20931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 21031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 21131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 21231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 21331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 21431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 21531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 216888d517bSPratyush Yadav #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F 21731fb632bSRamuthevar Vadivel Murugan 21831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR 0x70 21931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0) 22031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1) 22131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5) 22231fb632bSRamuthevar Vadivel Murugan 22331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRWATERMARK 0x74 22431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 22531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRBYTES 0x7C 22631fb632bSRamuthevar Vadivel Murugan 227*1a6f854fSSai Krishna Potthuri #define CQSPI_REG_INDTRIG_ADDRRANGE 0x80 228*1a6f854fSSai Krishna Potthuri 22931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDADDRESS 0x94 23031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDREADDATALOWER 0xA0 23131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDREADDATAUPPER 0xA4 23231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDWRITEDATALOWER 0xA8 23331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC 23431fb632bSRamuthevar Vadivel Murugan 235f453f293SPratyush Yadav #define CQSPI_REG_POLLING_STATUS 0xB0 236f453f293SPratyush Yadav #define CQSPI_REG_POLLING_STATUS_DUMMY_LSB 16 237f453f293SPratyush Yadav 238f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_LOWER 0xE0 239f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_READ_LSB 24 240f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_WRITE_LSB 16 241f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_STIG_LSB 0 242f453f293SPratyush Yadav 243*1a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_SRC_ADDR 0x1000 244*1a6f854fSSai Krishna Potthuri 245*1a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_ADDR 0x1800 246*1a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_SIZE 0x1804 247*1a6f854fSSai Krishna Potthuri 248*1a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_CTRL 0x180C 249*1a6f854fSSai Krishna Potthuri 250*1a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_I_STS 0x1814 251*1a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_I_EN 0x1818 252*1a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_I_DIS 0x181C 253*1a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_DONE_MASK BIT(1) 254*1a6f854fSSai Krishna Potthuri 255*1a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB 0x1828 256*1a6f854fSSai Krishna Potthuri 257*1a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL 0xF43FFA00 258*1a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL 0x6 259*1a6f854fSSai Krishna Potthuri 26031fb632bSRamuthevar Vadivel Murugan /* Interrupt status bits */ 26131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_MODE_ERR BIT(0) 26231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_UNDERFLOW BIT(1) 26331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_COMP BIT(2) 26431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3) 26531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4) 26631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5) 26731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_WATERMARK BIT(6) 26831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12) 26931fb632bSRamuthevar Vadivel Murugan 27031fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \ 27131fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_IND_SRAM_FULL | \ 27231fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_IND_COMP) 27331fb632bSRamuthevar Vadivel Murugan 27431fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \ 27531fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_WATERMARK | \ 27631fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_UNDERFLOW) 27731fb632bSRamuthevar Vadivel Murugan 27831fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_STATUS_MASK 0x1FFFF 279*1a6f854fSSai Krishna Potthuri #define CQSPI_DMA_UNALIGN 0x3 280*1a6f854fSSai Krishna Potthuri 281*1a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_VAL 0x602 28231fb632bSRamuthevar Vadivel Murugan 28331fb632bSRamuthevar Vadivel Murugan static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr) 28431fb632bSRamuthevar Vadivel Murugan { 28531fb632bSRamuthevar Vadivel Murugan u32 val; 28631fb632bSRamuthevar Vadivel Murugan 28731fb632bSRamuthevar Vadivel Murugan return readl_relaxed_poll_timeout(reg, val, 28831fb632bSRamuthevar Vadivel Murugan (((clr ? ~val : val) & mask) == mask), 28931fb632bSRamuthevar Vadivel Murugan 10, CQSPI_TIMEOUT_MS * 1000); 29031fb632bSRamuthevar Vadivel Murugan } 29131fb632bSRamuthevar Vadivel Murugan 29231fb632bSRamuthevar Vadivel Murugan static bool cqspi_is_idle(struct cqspi_st *cqspi) 29331fb632bSRamuthevar Vadivel Murugan { 29431fb632bSRamuthevar Vadivel Murugan u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 29531fb632bSRamuthevar Vadivel Murugan 29631890269SJay Fang return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB); 29731fb632bSRamuthevar Vadivel Murugan } 29831fb632bSRamuthevar Vadivel Murugan 29931fb632bSRamuthevar Vadivel Murugan static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi) 30031fb632bSRamuthevar Vadivel Murugan { 30131fb632bSRamuthevar Vadivel Murugan u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL); 30231fb632bSRamuthevar Vadivel Murugan 30331fb632bSRamuthevar Vadivel Murugan reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB; 30431fb632bSRamuthevar Vadivel Murugan return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK; 30531fb632bSRamuthevar Vadivel Murugan } 30631fb632bSRamuthevar Vadivel Murugan 307*1a6f854fSSai Krishna Potthuri static u32 cqspi_get_versal_dma_status(struct cqspi_st *cqspi) 308*1a6f854fSSai Krishna Potthuri { 309*1a6f854fSSai Krishna Potthuri u32 dma_status; 310*1a6f854fSSai Krishna Potthuri 311*1a6f854fSSai Krishna Potthuri dma_status = readl(cqspi->iobase + 312*1a6f854fSSai Krishna Potthuri CQSPI_REG_VERSAL_DMA_DST_I_STS); 313*1a6f854fSSai Krishna Potthuri writel(dma_status, cqspi->iobase + 314*1a6f854fSSai Krishna Potthuri CQSPI_REG_VERSAL_DMA_DST_I_STS); 315*1a6f854fSSai Krishna Potthuri 316*1a6f854fSSai Krishna Potthuri return dma_status & CQSPI_REG_VERSAL_DMA_DST_DONE_MASK; 317*1a6f854fSSai Krishna Potthuri } 318*1a6f854fSSai Krishna Potthuri 31931fb632bSRamuthevar Vadivel Murugan static irqreturn_t cqspi_irq_handler(int this_irq, void *dev) 32031fb632bSRamuthevar Vadivel Murugan { 32131fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev; 32231fb632bSRamuthevar Vadivel Murugan unsigned int irq_status; 323*1a6f854fSSai Krishna Potthuri struct device *device = &cqspi->pdev->dev; 324*1a6f854fSSai Krishna Potthuri const struct cqspi_driver_platdata *ddata; 325*1a6f854fSSai Krishna Potthuri 326*1a6f854fSSai Krishna Potthuri ddata = of_device_get_match_data(device); 32731fb632bSRamuthevar Vadivel Murugan 32831fb632bSRamuthevar Vadivel Murugan /* Read interrupt status */ 32931fb632bSRamuthevar Vadivel Murugan irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS); 33031fb632bSRamuthevar Vadivel Murugan 33131fb632bSRamuthevar Vadivel Murugan /* Clear interrupt */ 33231fb632bSRamuthevar Vadivel Murugan writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS); 33331fb632bSRamuthevar Vadivel Murugan 334*1a6f854fSSai Krishna Potthuri if (cqspi->use_dma_read && ddata && ddata->get_dma_status) { 335*1a6f854fSSai Krishna Potthuri if (ddata->get_dma_status(cqspi)) { 336*1a6f854fSSai Krishna Potthuri complete(&cqspi->transfer_complete); 337*1a6f854fSSai Krishna Potthuri return IRQ_HANDLED; 338*1a6f854fSSai Krishna Potthuri } 339*1a6f854fSSai Krishna Potthuri } 340*1a6f854fSSai Krishna Potthuri 34131fb632bSRamuthevar Vadivel Murugan irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR; 34231fb632bSRamuthevar Vadivel Murugan 34331fb632bSRamuthevar Vadivel Murugan if (irq_status) 34431fb632bSRamuthevar Vadivel Murugan complete(&cqspi->transfer_complete); 34531fb632bSRamuthevar Vadivel Murugan 34631fb632bSRamuthevar Vadivel Murugan return IRQ_HANDLED; 34731fb632bSRamuthevar Vadivel Murugan } 34831fb632bSRamuthevar Vadivel Murugan 34931fb632bSRamuthevar Vadivel Murugan static unsigned int cqspi_calc_rdreg(struct cqspi_flash_pdata *f_pdata) 35031fb632bSRamuthevar Vadivel Murugan { 35131fb632bSRamuthevar Vadivel Murugan u32 rdreg = 0; 35231fb632bSRamuthevar Vadivel Murugan 35331fb632bSRamuthevar Vadivel Murugan rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; 35431fb632bSRamuthevar Vadivel Murugan rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; 35531fb632bSRamuthevar Vadivel Murugan rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; 35631fb632bSRamuthevar Vadivel Murugan 35731fb632bSRamuthevar Vadivel Murugan return rdreg; 35831fb632bSRamuthevar Vadivel Murugan } 35931fb632bSRamuthevar Vadivel Murugan 360f453f293SPratyush Yadav static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op, bool dtr) 361888d517bSPratyush Yadav { 3620ccfd1baSYoshitaka Ikeda unsigned int dummy_clk; 363888d517bSPratyush Yadav 3640e85ee89SYoshitaka Ikeda if (!op->dummy.nbytes) 3650e85ee89SYoshitaka Ikeda return 0; 3660e85ee89SYoshitaka Ikeda 3677512eaf5SPratyush Yadav dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth); 368f453f293SPratyush Yadav if (dtr) 369f453f293SPratyush Yadav dummy_clk /= 2; 370888d517bSPratyush Yadav 371888d517bSPratyush Yadav return dummy_clk; 372888d517bSPratyush Yadav } 373888d517bSPratyush Yadav 374f453f293SPratyush Yadav static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata, 375f453f293SPratyush Yadav const struct spi_mem_op *op) 376f453f293SPratyush Yadav { 377f453f293SPratyush Yadav f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE; 378f453f293SPratyush Yadav f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE; 379f453f293SPratyush Yadav f_pdata->data_width = CQSPI_INST_TYPE_SINGLE; 3800395be96SApurva Nandan 3810395be96SApurva Nandan /* 3820395be96SApurva Nandan * For an op to be DTR, cmd phase along with every other non-empty 3830395be96SApurva Nandan * phase should have dtr field set to 1. If an op phase has zero 3840395be96SApurva Nandan * nbytes, ignore its dtr field; otherwise, check its dtr field. 3850395be96SApurva Nandan */ 3860395be96SApurva Nandan f_pdata->dtr = op->cmd.dtr && 3870395be96SApurva Nandan (!op->addr.nbytes || op->addr.dtr) && 3880395be96SApurva Nandan (!op->data.nbytes || op->data.dtr); 389f453f293SPratyush Yadav 390f453f293SPratyush Yadav switch (op->data.buswidth) { 391f453f293SPratyush Yadav case 0: 392f453f293SPratyush Yadav break; 393f453f293SPratyush Yadav case 1: 394f453f293SPratyush Yadav f_pdata->data_width = CQSPI_INST_TYPE_SINGLE; 395f453f293SPratyush Yadav break; 396f453f293SPratyush Yadav case 2: 397f453f293SPratyush Yadav f_pdata->data_width = CQSPI_INST_TYPE_DUAL; 398f453f293SPratyush Yadav break; 399f453f293SPratyush Yadav case 4: 400f453f293SPratyush Yadav f_pdata->data_width = CQSPI_INST_TYPE_QUAD; 401f453f293SPratyush Yadav break; 402f453f293SPratyush Yadav case 8: 403f453f293SPratyush Yadav f_pdata->data_width = CQSPI_INST_TYPE_OCTAL; 404f453f293SPratyush Yadav break; 405f453f293SPratyush Yadav default: 406f453f293SPratyush Yadav return -EINVAL; 407f453f293SPratyush Yadav } 408f453f293SPratyush Yadav 409f453f293SPratyush Yadav /* Right now we only support 8-8-8 DTR mode. */ 410f453f293SPratyush Yadav if (f_pdata->dtr) { 411f453f293SPratyush Yadav switch (op->cmd.buswidth) { 412f453f293SPratyush Yadav case 0: 413f453f293SPratyush Yadav break; 414f453f293SPratyush Yadav case 8: 415f453f293SPratyush Yadav f_pdata->inst_width = CQSPI_INST_TYPE_OCTAL; 416f453f293SPratyush Yadav break; 417f453f293SPratyush Yadav default: 418f453f293SPratyush Yadav return -EINVAL; 419f453f293SPratyush Yadav } 420f453f293SPratyush Yadav 421f453f293SPratyush Yadav switch (op->addr.buswidth) { 422f453f293SPratyush Yadav case 0: 423f453f293SPratyush Yadav break; 424f453f293SPratyush Yadav case 8: 425f453f293SPratyush Yadav f_pdata->addr_width = CQSPI_INST_TYPE_OCTAL; 426f453f293SPratyush Yadav break; 427f453f293SPratyush Yadav default: 428f453f293SPratyush Yadav return -EINVAL; 429f453f293SPratyush Yadav } 430f453f293SPratyush Yadav 431f453f293SPratyush Yadav switch (op->data.buswidth) { 432f453f293SPratyush Yadav case 0: 433f453f293SPratyush Yadav break; 434f453f293SPratyush Yadav case 8: 435f453f293SPratyush Yadav f_pdata->data_width = CQSPI_INST_TYPE_OCTAL; 436f453f293SPratyush Yadav break; 437f453f293SPratyush Yadav default: 438f453f293SPratyush Yadav return -EINVAL; 439f453f293SPratyush Yadav } 440f453f293SPratyush Yadav } 441f453f293SPratyush Yadav 442f453f293SPratyush Yadav return 0; 443f453f293SPratyush Yadav } 444f453f293SPratyush Yadav 44531fb632bSRamuthevar Vadivel Murugan static int cqspi_wait_idle(struct cqspi_st *cqspi) 44631fb632bSRamuthevar Vadivel Murugan { 44731fb632bSRamuthevar Vadivel Murugan const unsigned int poll_idle_retry = 3; 44831fb632bSRamuthevar Vadivel Murugan unsigned int count = 0; 44931fb632bSRamuthevar Vadivel Murugan unsigned long timeout; 45031fb632bSRamuthevar Vadivel Murugan 45131fb632bSRamuthevar Vadivel Murugan timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS); 45231fb632bSRamuthevar Vadivel Murugan while (1) { 45331fb632bSRamuthevar Vadivel Murugan /* 45431fb632bSRamuthevar Vadivel Murugan * Read few times in succession to ensure the controller 45531fb632bSRamuthevar Vadivel Murugan * is indeed idle, that is, the bit does not transition 45631fb632bSRamuthevar Vadivel Murugan * low again. 45731fb632bSRamuthevar Vadivel Murugan */ 45831fb632bSRamuthevar Vadivel Murugan if (cqspi_is_idle(cqspi)) 45931fb632bSRamuthevar Vadivel Murugan count++; 46031fb632bSRamuthevar Vadivel Murugan else 46131fb632bSRamuthevar Vadivel Murugan count = 0; 46231fb632bSRamuthevar Vadivel Murugan 46331fb632bSRamuthevar Vadivel Murugan if (count >= poll_idle_retry) 46431fb632bSRamuthevar Vadivel Murugan return 0; 46531fb632bSRamuthevar Vadivel Murugan 46631fb632bSRamuthevar Vadivel Murugan if (time_after(jiffies, timeout)) { 46731fb632bSRamuthevar Vadivel Murugan /* Timeout, in busy mode. */ 46831fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 46931fb632bSRamuthevar Vadivel Murugan "QSPI is still busy after %dms timeout.\n", 47031fb632bSRamuthevar Vadivel Murugan CQSPI_TIMEOUT_MS); 47131fb632bSRamuthevar Vadivel Murugan return -ETIMEDOUT; 47231fb632bSRamuthevar Vadivel Murugan } 47331fb632bSRamuthevar Vadivel Murugan 47431fb632bSRamuthevar Vadivel Murugan cpu_relax(); 47531fb632bSRamuthevar Vadivel Murugan } 47631fb632bSRamuthevar Vadivel Murugan } 47731fb632bSRamuthevar Vadivel Murugan 47831fb632bSRamuthevar Vadivel Murugan static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg) 47931fb632bSRamuthevar Vadivel Murugan { 48031fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 48131fb632bSRamuthevar Vadivel Murugan int ret; 48231fb632bSRamuthevar Vadivel Murugan 48331fb632bSRamuthevar Vadivel Murugan /* Write the CMDCTRL without start execution. */ 48431fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CMDCTRL); 48531fb632bSRamuthevar Vadivel Murugan /* Start execute */ 48631fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK; 48731fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CMDCTRL); 48831fb632bSRamuthevar Vadivel Murugan 48931fb632bSRamuthevar Vadivel Murugan /* Polling for completion. */ 49031fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL, 49131fb632bSRamuthevar Vadivel Murugan CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1); 49231fb632bSRamuthevar Vadivel Murugan if (ret) { 49331fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 49431fb632bSRamuthevar Vadivel Murugan "Flash command execution timed out.\n"); 49531fb632bSRamuthevar Vadivel Murugan return ret; 49631fb632bSRamuthevar Vadivel Murugan } 49731fb632bSRamuthevar Vadivel Murugan 49831fb632bSRamuthevar Vadivel Murugan /* Polling QSPI idle status. */ 49931fb632bSRamuthevar Vadivel Murugan return cqspi_wait_idle(cqspi); 50031fb632bSRamuthevar Vadivel Murugan } 50131fb632bSRamuthevar Vadivel Murugan 502f453f293SPratyush Yadav static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata, 503f453f293SPratyush Yadav const struct spi_mem_op *op, 504f453f293SPratyush Yadav unsigned int shift) 505f453f293SPratyush Yadav { 506f453f293SPratyush Yadav struct cqspi_st *cqspi = f_pdata->cqspi; 507f453f293SPratyush Yadav void __iomem *reg_base = cqspi->iobase; 508f453f293SPratyush Yadav unsigned int reg; 509f453f293SPratyush Yadav u8 ext; 510f453f293SPratyush Yadav 511f453f293SPratyush Yadav if (op->cmd.nbytes != 2) 512f453f293SPratyush Yadav return -EINVAL; 513f453f293SPratyush Yadav 514f453f293SPratyush Yadav /* Opcode extension is the LSB. */ 515f453f293SPratyush Yadav ext = op->cmd.opcode & 0xff; 516f453f293SPratyush Yadav 517f453f293SPratyush Yadav reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER); 518f453f293SPratyush Yadav reg &= ~(0xff << shift); 519f453f293SPratyush Yadav reg |= ext << shift; 520f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER); 521f453f293SPratyush Yadav 522f453f293SPratyush Yadav return 0; 523f453f293SPratyush Yadav } 524f453f293SPratyush Yadav 525f453f293SPratyush Yadav static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata, 526f453f293SPratyush Yadav const struct spi_mem_op *op, unsigned int shift, 527f453f293SPratyush Yadav bool enable) 528f453f293SPratyush Yadav { 529f453f293SPratyush Yadav struct cqspi_st *cqspi = f_pdata->cqspi; 530f453f293SPratyush Yadav void __iomem *reg_base = cqspi->iobase; 531f453f293SPratyush Yadav unsigned int reg; 532f453f293SPratyush Yadav int ret; 533f453f293SPratyush Yadav 534f453f293SPratyush Yadav reg = readl(reg_base + CQSPI_REG_CONFIG); 535f453f293SPratyush Yadav 536f453f293SPratyush Yadav /* 537f453f293SPratyush Yadav * We enable dual byte opcode here. The callers have to set up the 538f453f293SPratyush Yadav * extension opcode based on which type of operation it is. 539f453f293SPratyush Yadav */ 540f453f293SPratyush Yadav if (enable) { 541f453f293SPratyush Yadav reg |= CQSPI_REG_CONFIG_DTR_PROTO; 542f453f293SPratyush Yadav reg |= CQSPI_REG_CONFIG_DUAL_OPCODE; 543f453f293SPratyush Yadav 544f453f293SPratyush Yadav /* Set up command opcode extension. */ 545f453f293SPratyush Yadav ret = cqspi_setup_opcode_ext(f_pdata, op, shift); 546f453f293SPratyush Yadav if (ret) 547f453f293SPratyush Yadav return ret; 548f453f293SPratyush Yadav } else { 549f453f293SPratyush Yadav reg &= ~CQSPI_REG_CONFIG_DTR_PROTO; 550f453f293SPratyush Yadav reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE; 551f453f293SPratyush Yadav } 552f453f293SPratyush Yadav 553f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_CONFIG); 554f453f293SPratyush Yadav 555f453f293SPratyush Yadav return cqspi_wait_idle(cqspi); 556f453f293SPratyush Yadav } 557f453f293SPratyush Yadav 55831fb632bSRamuthevar Vadivel Murugan static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, 55931fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 56031fb632bSRamuthevar Vadivel Murugan { 56131fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 56231fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 56331fb632bSRamuthevar Vadivel Murugan u8 *rxbuf = op->data.buf.in; 564f453f293SPratyush Yadav u8 opcode; 56531fb632bSRamuthevar Vadivel Murugan size_t n_rx = op->data.nbytes; 56631fb632bSRamuthevar Vadivel Murugan unsigned int rdreg; 56731fb632bSRamuthevar Vadivel Murugan unsigned int reg; 568888d517bSPratyush Yadav unsigned int dummy_clk; 56931fb632bSRamuthevar Vadivel Murugan size_t read_len; 57031fb632bSRamuthevar Vadivel Murugan int status; 57131fb632bSRamuthevar Vadivel Murugan 572f453f293SPratyush Yadav status = cqspi_set_protocol(f_pdata, op); 573f453f293SPratyush Yadav if (status) 574f453f293SPratyush Yadav return status; 575f453f293SPratyush Yadav 576f453f293SPratyush Yadav status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB, 577f453f293SPratyush Yadav f_pdata->dtr); 578f453f293SPratyush Yadav if (status) 579f453f293SPratyush Yadav return status; 580f453f293SPratyush Yadav 58131fb632bSRamuthevar Vadivel Murugan if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) { 58231fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 58331fb632bSRamuthevar Vadivel Murugan "Invalid input argument, len %zu rxbuf 0x%p\n", 58431fb632bSRamuthevar Vadivel Murugan n_rx, rxbuf); 58531fb632bSRamuthevar Vadivel Murugan return -EINVAL; 58631fb632bSRamuthevar Vadivel Murugan } 58731fb632bSRamuthevar Vadivel Murugan 588f453f293SPratyush Yadav if (f_pdata->dtr) 589f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 590f453f293SPratyush Yadav else 591f453f293SPratyush Yadav opcode = op->cmd.opcode; 592f453f293SPratyush Yadav 59331fb632bSRamuthevar Vadivel Murugan reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 59431fb632bSRamuthevar Vadivel Murugan 59531fb632bSRamuthevar Vadivel Murugan rdreg = cqspi_calc_rdreg(f_pdata); 59631fb632bSRamuthevar Vadivel Murugan writel(rdreg, reg_base + CQSPI_REG_RD_INSTR); 59731fb632bSRamuthevar Vadivel Murugan 598f453f293SPratyush Yadav dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr); 599888d517bSPratyush Yadav if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 600888d517bSPratyush Yadav return -EOPNOTSUPP; 601888d517bSPratyush Yadav 602888d517bSPratyush Yadav if (dummy_clk) 603888d517bSPratyush Yadav reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK) 604888d517bSPratyush Yadav << CQSPI_REG_CMDCTRL_DUMMY_LSB; 605888d517bSPratyush Yadav 60631fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); 60731fb632bSRamuthevar Vadivel Murugan 60831fb632bSRamuthevar Vadivel Murugan /* 0 means 1 byte. */ 60931fb632bSRamuthevar Vadivel Murugan reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) 61031fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); 61131fb632bSRamuthevar Vadivel Murugan status = cqspi_exec_flash_cmd(cqspi, reg); 61231fb632bSRamuthevar Vadivel Murugan if (status) 61331fb632bSRamuthevar Vadivel Murugan return status; 61431fb632bSRamuthevar Vadivel Murugan 61531fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER); 61631fb632bSRamuthevar Vadivel Murugan 61731fb632bSRamuthevar Vadivel Murugan /* Put the read value into rx_buf */ 61831fb632bSRamuthevar Vadivel Murugan read_len = (n_rx > 4) ? 4 : n_rx; 61931fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, ®, read_len); 62031fb632bSRamuthevar Vadivel Murugan rxbuf += read_len; 62131fb632bSRamuthevar Vadivel Murugan 62231fb632bSRamuthevar Vadivel Murugan if (n_rx > 4) { 62331fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER); 62431fb632bSRamuthevar Vadivel Murugan 62531fb632bSRamuthevar Vadivel Murugan read_len = n_rx - read_len; 62631fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, ®, read_len); 62731fb632bSRamuthevar Vadivel Murugan } 62831fb632bSRamuthevar Vadivel Murugan 62931fb632bSRamuthevar Vadivel Murugan return 0; 63031fb632bSRamuthevar Vadivel Murugan } 63131fb632bSRamuthevar Vadivel Murugan 63231fb632bSRamuthevar Vadivel Murugan static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata, 63331fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 63431fb632bSRamuthevar Vadivel Murugan { 63531fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 63631fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 637f453f293SPratyush Yadav u8 opcode; 63831fb632bSRamuthevar Vadivel Murugan const u8 *txbuf = op->data.buf.out; 63931fb632bSRamuthevar Vadivel Murugan size_t n_tx = op->data.nbytes; 64031fb632bSRamuthevar Vadivel Murugan unsigned int reg; 64131fb632bSRamuthevar Vadivel Murugan unsigned int data; 64231fb632bSRamuthevar Vadivel Murugan size_t write_len; 643f453f293SPratyush Yadav int ret; 644f453f293SPratyush Yadav 645f453f293SPratyush Yadav ret = cqspi_set_protocol(f_pdata, op); 646f453f293SPratyush Yadav if (ret) 647f453f293SPratyush Yadav return ret; 648f453f293SPratyush Yadav 649f453f293SPratyush Yadav ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB, 650f453f293SPratyush Yadav f_pdata->dtr); 651f453f293SPratyush Yadav if (ret) 652f453f293SPratyush Yadav return ret; 65331fb632bSRamuthevar Vadivel Murugan 65431fb632bSRamuthevar Vadivel Murugan if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) { 65531fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 65631fb632bSRamuthevar Vadivel Murugan "Invalid input argument, cmdlen %zu txbuf 0x%p\n", 65731fb632bSRamuthevar Vadivel Murugan n_tx, txbuf); 65831fb632bSRamuthevar Vadivel Murugan return -EINVAL; 65931fb632bSRamuthevar Vadivel Murugan } 66031fb632bSRamuthevar Vadivel Murugan 661f453f293SPratyush Yadav reg = cqspi_calc_rdreg(f_pdata); 662f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_RD_INSTR); 663f453f293SPratyush Yadav 664f453f293SPratyush Yadav if (f_pdata->dtr) 665f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 666f453f293SPratyush Yadav else 667f453f293SPratyush Yadav opcode = op->cmd.opcode; 668f453f293SPratyush Yadav 66931fb632bSRamuthevar Vadivel Murugan reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 67031fb632bSRamuthevar Vadivel Murugan 67131fb632bSRamuthevar Vadivel Murugan if (op->addr.nbytes) { 67231fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 67331fb632bSRamuthevar Vadivel Murugan reg |= ((op->addr.nbytes - 1) & 67431fb632bSRamuthevar Vadivel Murugan CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) 67531fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; 67631fb632bSRamuthevar Vadivel Murugan 67731fb632bSRamuthevar Vadivel Murugan writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); 67831fb632bSRamuthevar Vadivel Murugan } 67931fb632bSRamuthevar Vadivel Murugan 68031fb632bSRamuthevar Vadivel Murugan if (n_tx) { 68131fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB); 68231fb632bSRamuthevar Vadivel Murugan reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) 68331fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_WR_BYTES_LSB; 68431fb632bSRamuthevar Vadivel Murugan data = 0; 68531fb632bSRamuthevar Vadivel Murugan write_len = (n_tx > 4) ? 4 : n_tx; 68631fb632bSRamuthevar Vadivel Murugan memcpy(&data, txbuf, write_len); 68731fb632bSRamuthevar Vadivel Murugan txbuf += write_len; 68831fb632bSRamuthevar Vadivel Murugan writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER); 68931fb632bSRamuthevar Vadivel Murugan 69031fb632bSRamuthevar Vadivel Murugan if (n_tx > 4) { 69131fb632bSRamuthevar Vadivel Murugan data = 0; 69231fb632bSRamuthevar Vadivel Murugan write_len = n_tx - 4; 69331fb632bSRamuthevar Vadivel Murugan memcpy(&data, txbuf, write_len); 69431fb632bSRamuthevar Vadivel Murugan writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER); 69531fb632bSRamuthevar Vadivel Murugan } 69631fb632bSRamuthevar Vadivel Murugan } 69731fb632bSRamuthevar Vadivel Murugan 69831fb632bSRamuthevar Vadivel Murugan return cqspi_exec_flash_cmd(cqspi, reg); 69931fb632bSRamuthevar Vadivel Murugan } 70031fb632bSRamuthevar Vadivel Murugan 70131fb632bSRamuthevar Vadivel Murugan static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata, 70231fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 70331fb632bSRamuthevar Vadivel Murugan { 70431fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 70531fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 70631fb632bSRamuthevar Vadivel Murugan unsigned int dummy_clk = 0; 70731fb632bSRamuthevar Vadivel Murugan unsigned int reg; 708f453f293SPratyush Yadav int ret; 709f453f293SPratyush Yadav u8 opcode; 71031fb632bSRamuthevar Vadivel Murugan 711f453f293SPratyush Yadav ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB, 712f453f293SPratyush Yadav f_pdata->dtr); 713f453f293SPratyush Yadav if (ret) 714f453f293SPratyush Yadav return ret; 715f453f293SPratyush Yadav 716f453f293SPratyush Yadav if (f_pdata->dtr) 717f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 718f453f293SPratyush Yadav else 719f453f293SPratyush Yadav opcode = op->cmd.opcode; 720f453f293SPratyush Yadav 721f453f293SPratyush Yadav reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB; 72231fb632bSRamuthevar Vadivel Murugan reg |= cqspi_calc_rdreg(f_pdata); 72331fb632bSRamuthevar Vadivel Murugan 72431fb632bSRamuthevar Vadivel Murugan /* Setup dummy clock cycles */ 725f453f293SPratyush Yadav dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr); 726888d517bSPratyush Yadav 72731fb632bSRamuthevar Vadivel Murugan if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 728ceeda328SPratyush Yadav return -EOPNOTSUPP; 72931fb632bSRamuthevar Vadivel Murugan 73031fb632bSRamuthevar Vadivel Murugan if (dummy_clk) 73131fb632bSRamuthevar Vadivel Murugan reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK) 73231fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_RD_INSTR_DUMMY_LSB; 73331fb632bSRamuthevar Vadivel Murugan 73431fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_RD_INSTR); 73531fb632bSRamuthevar Vadivel Murugan 73631fb632bSRamuthevar Vadivel Murugan /* Set address width */ 73731fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_SIZE); 73831fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 73931fb632bSRamuthevar Vadivel Murugan reg |= (op->addr.nbytes - 1); 74031fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_SIZE); 74131fb632bSRamuthevar Vadivel Murugan return 0; 74231fb632bSRamuthevar Vadivel Murugan } 74331fb632bSRamuthevar Vadivel Murugan 74431fb632bSRamuthevar Vadivel Murugan static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, 74531fb632bSRamuthevar Vadivel Murugan u8 *rxbuf, loff_t from_addr, 74631fb632bSRamuthevar Vadivel Murugan const size_t n_rx) 74731fb632bSRamuthevar Vadivel Murugan { 74831fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 74931fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 75031fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 75131fb632bSRamuthevar Vadivel Murugan void __iomem *ahb_base = cqspi->ahb_base; 75231fb632bSRamuthevar Vadivel Murugan unsigned int remaining = n_rx; 75331fb632bSRamuthevar Vadivel Murugan unsigned int mod_bytes = n_rx % 4; 75431fb632bSRamuthevar Vadivel Murugan unsigned int bytes_to_read = 0; 75531fb632bSRamuthevar Vadivel Murugan u8 *rxbuf_end = rxbuf + n_rx; 75631fb632bSRamuthevar Vadivel Murugan int ret = 0; 75731fb632bSRamuthevar Vadivel Murugan 75831fb632bSRamuthevar Vadivel Murugan writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 75931fb632bSRamuthevar Vadivel Murugan writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES); 76031fb632bSRamuthevar Vadivel Murugan 76131fb632bSRamuthevar Vadivel Murugan /* Clear all interrupts. */ 76231fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 76331fb632bSRamuthevar Vadivel Murugan 76431fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK); 76531fb632bSRamuthevar Vadivel Murugan 76631fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 76731fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTRD_START_MASK, 76831fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTRD); 76931fb632bSRamuthevar Vadivel Murugan 77031fb632bSRamuthevar Vadivel Murugan while (remaining > 0) { 77131fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->transfer_complete, 77231fb632bSRamuthevar Vadivel Murugan msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) 77331fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 77431fb632bSRamuthevar Vadivel Murugan 77531fb632bSRamuthevar Vadivel Murugan bytes_to_read = cqspi_get_rd_sram_level(cqspi); 77631fb632bSRamuthevar Vadivel Murugan 77731fb632bSRamuthevar Vadivel Murugan if (ret && bytes_to_read == 0) { 77831fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect read timeout, no bytes\n"); 77931fb632bSRamuthevar Vadivel Murugan goto failrd; 78031fb632bSRamuthevar Vadivel Murugan } 78131fb632bSRamuthevar Vadivel Murugan 78231fb632bSRamuthevar Vadivel Murugan while (bytes_to_read != 0) { 78331fb632bSRamuthevar Vadivel Murugan unsigned int word_remain = round_down(remaining, 4); 78431fb632bSRamuthevar Vadivel Murugan 78531fb632bSRamuthevar Vadivel Murugan bytes_to_read *= cqspi->fifo_width; 78631fb632bSRamuthevar Vadivel Murugan bytes_to_read = bytes_to_read > remaining ? 78731fb632bSRamuthevar Vadivel Murugan remaining : bytes_to_read; 78831fb632bSRamuthevar Vadivel Murugan bytes_to_read = round_down(bytes_to_read, 4); 78931fb632bSRamuthevar Vadivel Murugan /* Read 4 byte word chunks then single bytes */ 79031fb632bSRamuthevar Vadivel Murugan if (bytes_to_read) { 79131fb632bSRamuthevar Vadivel Murugan ioread32_rep(ahb_base, rxbuf, 79231fb632bSRamuthevar Vadivel Murugan (bytes_to_read / 4)); 79331fb632bSRamuthevar Vadivel Murugan } else if (!word_remain && mod_bytes) { 79431fb632bSRamuthevar Vadivel Murugan unsigned int temp = ioread32(ahb_base); 79531fb632bSRamuthevar Vadivel Murugan 79631fb632bSRamuthevar Vadivel Murugan bytes_to_read = mod_bytes; 79731fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, &temp, min((unsigned int) 79831fb632bSRamuthevar Vadivel Murugan (rxbuf_end - rxbuf), 79931fb632bSRamuthevar Vadivel Murugan bytes_to_read)); 80031fb632bSRamuthevar Vadivel Murugan } 80131fb632bSRamuthevar Vadivel Murugan rxbuf += bytes_to_read; 80231fb632bSRamuthevar Vadivel Murugan remaining -= bytes_to_read; 80331fb632bSRamuthevar Vadivel Murugan bytes_to_read = cqspi_get_rd_sram_level(cqspi); 80431fb632bSRamuthevar Vadivel Murugan } 80531fb632bSRamuthevar Vadivel Murugan 80631fb632bSRamuthevar Vadivel Murugan if (remaining > 0) 80731fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 80831fb632bSRamuthevar Vadivel Murugan } 80931fb632bSRamuthevar Vadivel Murugan 81031fb632bSRamuthevar Vadivel Murugan /* Check indirect done status */ 81131fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD, 81231fb632bSRamuthevar Vadivel Murugan CQSPI_REG_INDIRECTRD_DONE_MASK, 0); 81331fb632bSRamuthevar Vadivel Murugan if (ret) { 81431fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect read completion error (%i)\n", ret); 81531fb632bSRamuthevar Vadivel Murugan goto failrd; 81631fb632bSRamuthevar Vadivel Murugan } 81731fb632bSRamuthevar Vadivel Murugan 81831fb632bSRamuthevar Vadivel Murugan /* Disable interrupt */ 81931fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 82031fb632bSRamuthevar Vadivel Murugan 82131fb632bSRamuthevar Vadivel Murugan /* Clear indirect completion status */ 82231fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD); 82331fb632bSRamuthevar Vadivel Murugan 82431fb632bSRamuthevar Vadivel Murugan return 0; 82531fb632bSRamuthevar Vadivel Murugan 82631fb632bSRamuthevar Vadivel Murugan failrd: 82731fb632bSRamuthevar Vadivel Murugan /* Disable interrupt */ 82831fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 82931fb632bSRamuthevar Vadivel Murugan 83031fb632bSRamuthevar Vadivel Murugan /* Cancel the indirect read */ 83131fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 83231fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTRD); 83331fb632bSRamuthevar Vadivel Murugan return ret; 83431fb632bSRamuthevar Vadivel Murugan } 83531fb632bSRamuthevar Vadivel Murugan 836*1a6f854fSSai Krishna Potthuri static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata, 837*1a6f854fSSai Krishna Potthuri u_char *rxbuf, loff_t from_addr, 838*1a6f854fSSai Krishna Potthuri size_t n_rx) 839*1a6f854fSSai Krishna Potthuri { 840*1a6f854fSSai Krishna Potthuri struct cqspi_st *cqspi = f_pdata->cqspi; 841*1a6f854fSSai Krishna Potthuri struct device *dev = &cqspi->pdev->dev; 842*1a6f854fSSai Krishna Potthuri void __iomem *reg_base = cqspi->iobase; 843*1a6f854fSSai Krishna Potthuri u32 reg, bytes_to_dma; 844*1a6f854fSSai Krishna Potthuri loff_t addr = from_addr; 845*1a6f854fSSai Krishna Potthuri void *buf = rxbuf; 846*1a6f854fSSai Krishna Potthuri dma_addr_t dma_addr; 847*1a6f854fSSai Krishna Potthuri u8 bytes_rem; 848*1a6f854fSSai Krishna Potthuri int ret = 0; 849*1a6f854fSSai Krishna Potthuri 850*1a6f854fSSai Krishna Potthuri bytes_rem = n_rx % 4; 851*1a6f854fSSai Krishna Potthuri bytes_to_dma = (n_rx - bytes_rem); 852*1a6f854fSSai Krishna Potthuri 853*1a6f854fSSai Krishna Potthuri if (!bytes_to_dma) 854*1a6f854fSSai Krishna Potthuri goto nondmard; 855*1a6f854fSSai Krishna Potthuri 856*1a6f854fSSai Krishna Potthuri ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA); 857*1a6f854fSSai Krishna Potthuri if (ret) 858*1a6f854fSSai Krishna Potthuri return ret; 859*1a6f854fSSai Krishna Potthuri 860*1a6f854fSSai Krishna Potthuri reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 861*1a6f854fSSai Krishna Potthuri reg |= CQSPI_REG_CONFIG_DMA_MASK; 862*1a6f854fSSai Krishna Potthuri writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 863*1a6f854fSSai Krishna Potthuri 864*1a6f854fSSai Krishna Potthuri dma_addr = dma_map_single(dev, rxbuf, bytes_to_dma, DMA_FROM_DEVICE); 865*1a6f854fSSai Krishna Potthuri if (dma_mapping_error(dev, dma_addr)) { 866*1a6f854fSSai Krishna Potthuri dev_err(dev, "dma mapping failed\n"); 867*1a6f854fSSai Krishna Potthuri return -ENOMEM; 868*1a6f854fSSai Krishna Potthuri } 869*1a6f854fSSai Krishna Potthuri 870*1a6f854fSSai Krishna Potthuri writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 871*1a6f854fSSai Krishna Potthuri writel(bytes_to_dma, reg_base + CQSPI_REG_INDIRECTRDBYTES); 872*1a6f854fSSai Krishna Potthuri writel(CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL, 873*1a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_INDTRIG_ADDRRANGE); 874*1a6f854fSSai Krishna Potthuri 875*1a6f854fSSai Krishna Potthuri /* Clear all interrupts. */ 876*1a6f854fSSai Krishna Potthuri writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 877*1a6f854fSSai Krishna Potthuri 878*1a6f854fSSai Krishna Potthuri /* Enable DMA done interrupt */ 879*1a6f854fSSai Krishna Potthuri writel(CQSPI_REG_VERSAL_DMA_DST_DONE_MASK, 880*1a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_VERSAL_DMA_DST_I_EN); 881*1a6f854fSSai Krishna Potthuri 882*1a6f854fSSai Krishna Potthuri /* Default DMA periph configuration */ 883*1a6f854fSSai Krishna Potthuri writel(CQSPI_REG_VERSAL_DMA_VAL, reg_base + CQSPI_REG_DMA); 884*1a6f854fSSai Krishna Potthuri 885*1a6f854fSSai Krishna Potthuri /* Configure DMA Dst address */ 886*1a6f854fSSai Krishna Potthuri writel(lower_32_bits(dma_addr), 887*1a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR); 888*1a6f854fSSai Krishna Potthuri writel(upper_32_bits(dma_addr), 889*1a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB); 890*1a6f854fSSai Krishna Potthuri 891*1a6f854fSSai Krishna Potthuri /* Configure DMA Src address */ 892*1a6f854fSSai Krishna Potthuri writel(cqspi->trigger_address, reg_base + 893*1a6f854fSSai Krishna Potthuri CQSPI_REG_VERSAL_DMA_SRC_ADDR); 894*1a6f854fSSai Krishna Potthuri 895*1a6f854fSSai Krishna Potthuri /* Set DMA destination size */ 896*1a6f854fSSai Krishna Potthuri writel(bytes_to_dma, reg_base + CQSPI_REG_VERSAL_DMA_DST_SIZE); 897*1a6f854fSSai Krishna Potthuri 898*1a6f854fSSai Krishna Potthuri /* Set DMA destination control */ 899*1a6f854fSSai Krishna Potthuri writel(CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL, 900*1a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_VERSAL_DMA_DST_CTRL); 901*1a6f854fSSai Krishna Potthuri 902*1a6f854fSSai Krishna Potthuri writel(CQSPI_REG_INDIRECTRD_START_MASK, 903*1a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_INDIRECTRD); 904*1a6f854fSSai Krishna Potthuri 905*1a6f854fSSai Krishna Potthuri reinit_completion(&cqspi->transfer_complete); 906*1a6f854fSSai Krishna Potthuri 907*1a6f854fSSai Krishna Potthuri if (!wait_for_completion_timeout(&cqspi->transfer_complete, 908*1a6f854fSSai Krishna Potthuri msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) { 909*1a6f854fSSai Krishna Potthuri ret = -ETIMEDOUT; 910*1a6f854fSSai Krishna Potthuri goto failrd; 911*1a6f854fSSai Krishna Potthuri } 912*1a6f854fSSai Krishna Potthuri 913*1a6f854fSSai Krishna Potthuri /* Disable DMA interrupt */ 914*1a6f854fSSai Krishna Potthuri writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS); 915*1a6f854fSSai Krishna Potthuri 916*1a6f854fSSai Krishna Potthuri /* Clear indirect completion status */ 917*1a6f854fSSai Krishna Potthuri writel(CQSPI_REG_INDIRECTRD_DONE_MASK, 918*1a6f854fSSai Krishna Potthuri cqspi->iobase + CQSPI_REG_INDIRECTRD); 919*1a6f854fSSai Krishna Potthuri dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE); 920*1a6f854fSSai Krishna Potthuri 921*1a6f854fSSai Krishna Potthuri reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 922*1a6f854fSSai Krishna Potthuri reg &= ~CQSPI_REG_CONFIG_DMA_MASK; 923*1a6f854fSSai Krishna Potthuri writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 924*1a6f854fSSai Krishna Potthuri 925*1a6f854fSSai Krishna Potthuri ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, 926*1a6f854fSSai Krishna Potthuri PM_OSPI_MUX_SEL_LINEAR); 927*1a6f854fSSai Krishna Potthuri if (ret) 928*1a6f854fSSai Krishna Potthuri return ret; 929*1a6f854fSSai Krishna Potthuri 930*1a6f854fSSai Krishna Potthuri nondmard: 931*1a6f854fSSai Krishna Potthuri if (bytes_rem) { 932*1a6f854fSSai Krishna Potthuri addr += bytes_to_dma; 933*1a6f854fSSai Krishna Potthuri buf += bytes_to_dma; 934*1a6f854fSSai Krishna Potthuri ret = cqspi_indirect_read_execute(f_pdata, buf, addr, 935*1a6f854fSSai Krishna Potthuri bytes_rem); 936*1a6f854fSSai Krishna Potthuri if (ret) 937*1a6f854fSSai Krishna Potthuri return ret; 938*1a6f854fSSai Krishna Potthuri } 939*1a6f854fSSai Krishna Potthuri 940*1a6f854fSSai Krishna Potthuri return 0; 941*1a6f854fSSai Krishna Potthuri 942*1a6f854fSSai Krishna Potthuri failrd: 943*1a6f854fSSai Krishna Potthuri /* Disable DMA interrupt */ 944*1a6f854fSSai Krishna Potthuri writel(0x0, reg_base + CQSPI_REG_VERSAL_DMA_DST_I_DIS); 945*1a6f854fSSai Krishna Potthuri 946*1a6f854fSSai Krishna Potthuri /* Cancel the indirect read */ 947*1a6f854fSSai Krishna Potthuri writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 948*1a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_INDIRECTRD); 949*1a6f854fSSai Krishna Potthuri 950*1a6f854fSSai Krishna Potthuri dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_DEV_TO_MEM); 951*1a6f854fSSai Krishna Potthuri 952*1a6f854fSSai Krishna Potthuri reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 953*1a6f854fSSai Krishna Potthuri reg &= ~CQSPI_REG_CONFIG_DMA_MASK; 954*1a6f854fSSai Krishna Potthuri writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 955*1a6f854fSSai Krishna Potthuri 956*1a6f854fSSai Krishna Potthuri zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR); 957*1a6f854fSSai Krishna Potthuri 958*1a6f854fSSai Krishna Potthuri return ret; 959*1a6f854fSSai Krishna Potthuri } 960*1a6f854fSSai Krishna Potthuri 96131fb632bSRamuthevar Vadivel Murugan static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata, 96231fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 96331fb632bSRamuthevar Vadivel Murugan { 96431fb632bSRamuthevar Vadivel Murugan unsigned int reg; 965f453f293SPratyush Yadav int ret; 96631fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 96731fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 968f453f293SPratyush Yadav u8 opcode; 969f453f293SPratyush Yadav 970f453f293SPratyush Yadav ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB, 971f453f293SPratyush Yadav f_pdata->dtr); 972f453f293SPratyush Yadav if (ret) 973f453f293SPratyush Yadav return ret; 974f453f293SPratyush Yadav 975f453f293SPratyush Yadav if (f_pdata->dtr) 976f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 977f453f293SPratyush Yadav else 978f453f293SPratyush Yadav opcode = op->cmd.opcode; 97931fb632bSRamuthevar Vadivel Murugan 98031fb632bSRamuthevar Vadivel Murugan /* Set opcode. */ 981f453f293SPratyush Yadav reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; 982f453f293SPratyush Yadav reg |= f_pdata->data_width << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; 983f453f293SPratyush Yadav reg |= f_pdata->addr_width << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; 98431fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_WR_INSTR); 98531fb632bSRamuthevar Vadivel Murugan reg = cqspi_calc_rdreg(f_pdata); 98631fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_RD_INSTR); 98731fb632bSRamuthevar Vadivel Murugan 988f453f293SPratyush Yadav /* 9899cb2ff11SApurva Nandan * SPI NAND flashes require the address of the status register to be 9909cb2ff11SApurva Nandan * passed in the Read SR command. Also, some SPI NOR flashes like the 9919cb2ff11SApurva Nandan * cypress Semper flash expect a 4-byte dummy address in the Read SR 9929cb2ff11SApurva Nandan * command in DTR mode. 9939cb2ff11SApurva Nandan * 9949cb2ff11SApurva Nandan * But this controller does not support address phase in the Read SR 9959cb2ff11SApurva Nandan * command when doing auto-HW polling. So, disable write completion 9969cb2ff11SApurva Nandan * polling on the controller's side. spinand and spi-nor will take 9979cb2ff11SApurva Nandan * care of polling the status register. 998f453f293SPratyush Yadav */ 999f453f293SPratyush Yadav reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL); 1000f453f293SPratyush Yadav reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL; 1001f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL); 1002f453f293SPratyush Yadav 100331fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_SIZE); 100431fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 100531fb632bSRamuthevar Vadivel Murugan reg |= (op->addr.nbytes - 1); 100631fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_SIZE); 100731fb632bSRamuthevar Vadivel Murugan return 0; 100831fb632bSRamuthevar Vadivel Murugan } 100931fb632bSRamuthevar Vadivel Murugan 101031fb632bSRamuthevar Vadivel Murugan static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, 101131fb632bSRamuthevar Vadivel Murugan loff_t to_addr, const u8 *txbuf, 101231fb632bSRamuthevar Vadivel Murugan const size_t n_tx) 101331fb632bSRamuthevar Vadivel Murugan { 101431fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 101531fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 101631fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 101731fb632bSRamuthevar Vadivel Murugan unsigned int remaining = n_tx; 101831fb632bSRamuthevar Vadivel Murugan unsigned int write_bytes; 101931fb632bSRamuthevar Vadivel Murugan int ret; 102031fb632bSRamuthevar Vadivel Murugan 102131fb632bSRamuthevar Vadivel Murugan writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR); 102231fb632bSRamuthevar Vadivel Murugan writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES); 102331fb632bSRamuthevar Vadivel Murugan 102431fb632bSRamuthevar Vadivel Murugan /* Clear all interrupts. */ 102531fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 102631fb632bSRamuthevar Vadivel Murugan 102731fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK); 102831fb632bSRamuthevar Vadivel Murugan 102931fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 103031fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_START_MASK, 103131fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTWR); 103231fb632bSRamuthevar Vadivel Murugan /* 103331fb632bSRamuthevar Vadivel Murugan * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access 103431fb632bSRamuthevar Vadivel Murugan * Controller programming sequence, couple of cycles of 103531fb632bSRamuthevar Vadivel Murugan * QSPI_REF_CLK delay is required for the above bit to 103631fb632bSRamuthevar Vadivel Murugan * be internally synchronized by the QSPI module. Provide 5 103731fb632bSRamuthevar Vadivel Murugan * cycles of delay. 103831fb632bSRamuthevar Vadivel Murugan */ 103931fb632bSRamuthevar Vadivel Murugan if (cqspi->wr_delay) 104031fb632bSRamuthevar Vadivel Murugan ndelay(cqspi->wr_delay); 104131fb632bSRamuthevar Vadivel Murugan 104231fb632bSRamuthevar Vadivel Murugan while (remaining > 0) { 104331fb632bSRamuthevar Vadivel Murugan size_t write_words, mod_bytes; 104431fb632bSRamuthevar Vadivel Murugan 104531fb632bSRamuthevar Vadivel Murugan write_bytes = remaining; 104631fb632bSRamuthevar Vadivel Murugan write_words = write_bytes / 4; 104731fb632bSRamuthevar Vadivel Murugan mod_bytes = write_bytes % 4; 104831fb632bSRamuthevar Vadivel Murugan /* Write 4 bytes at a time then single bytes. */ 104931fb632bSRamuthevar Vadivel Murugan if (write_words) { 105031fb632bSRamuthevar Vadivel Murugan iowrite32_rep(cqspi->ahb_base, txbuf, write_words); 105131fb632bSRamuthevar Vadivel Murugan txbuf += (write_words * 4); 105231fb632bSRamuthevar Vadivel Murugan } 105331fb632bSRamuthevar Vadivel Murugan if (mod_bytes) { 105431fb632bSRamuthevar Vadivel Murugan unsigned int temp = 0xFFFFFFFF; 105531fb632bSRamuthevar Vadivel Murugan 105631fb632bSRamuthevar Vadivel Murugan memcpy(&temp, txbuf, mod_bytes); 105731fb632bSRamuthevar Vadivel Murugan iowrite32(temp, cqspi->ahb_base); 105831fb632bSRamuthevar Vadivel Murugan txbuf += mod_bytes; 105931fb632bSRamuthevar Vadivel Murugan } 106031fb632bSRamuthevar Vadivel Murugan 106131fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->transfer_complete, 106231fb632bSRamuthevar Vadivel Murugan msecs_to_jiffies(CQSPI_TIMEOUT_MS))) { 106331fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect write timeout\n"); 106431fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 106531fb632bSRamuthevar Vadivel Murugan goto failwr; 106631fb632bSRamuthevar Vadivel Murugan } 106731fb632bSRamuthevar Vadivel Murugan 106831fb632bSRamuthevar Vadivel Murugan remaining -= write_bytes; 106931fb632bSRamuthevar Vadivel Murugan 107031fb632bSRamuthevar Vadivel Murugan if (remaining > 0) 107131fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 107231fb632bSRamuthevar Vadivel Murugan } 107331fb632bSRamuthevar Vadivel Murugan 107431fb632bSRamuthevar Vadivel Murugan /* Check indirect done status */ 107531fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR, 107631fb632bSRamuthevar Vadivel Murugan CQSPI_REG_INDIRECTWR_DONE_MASK, 0); 107731fb632bSRamuthevar Vadivel Murugan if (ret) { 107831fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect write completion error (%i)\n", ret); 107931fb632bSRamuthevar Vadivel Murugan goto failwr; 108031fb632bSRamuthevar Vadivel Murugan } 108131fb632bSRamuthevar Vadivel Murugan 108231fb632bSRamuthevar Vadivel Murugan /* Disable interrupt. */ 108331fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 108431fb632bSRamuthevar Vadivel Murugan 108531fb632bSRamuthevar Vadivel Murugan /* Clear indirect completion status */ 108631fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR); 108731fb632bSRamuthevar Vadivel Murugan 108831fb632bSRamuthevar Vadivel Murugan cqspi_wait_idle(cqspi); 108931fb632bSRamuthevar Vadivel Murugan 109031fb632bSRamuthevar Vadivel Murugan return 0; 109131fb632bSRamuthevar Vadivel Murugan 109231fb632bSRamuthevar Vadivel Murugan failwr: 109331fb632bSRamuthevar Vadivel Murugan /* Disable interrupt. */ 109431fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 109531fb632bSRamuthevar Vadivel Murugan 109631fb632bSRamuthevar Vadivel Murugan /* Cancel the indirect write */ 109731fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 109831fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTWR); 109931fb632bSRamuthevar Vadivel Murugan return ret; 110031fb632bSRamuthevar Vadivel Murugan } 110131fb632bSRamuthevar Vadivel Murugan 110231fb632bSRamuthevar Vadivel Murugan static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata) 110331fb632bSRamuthevar Vadivel Murugan { 110431fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 110531fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 110631fb632bSRamuthevar Vadivel Murugan unsigned int chip_select = f_pdata->cs; 110731fb632bSRamuthevar Vadivel Murugan unsigned int reg; 110831fb632bSRamuthevar Vadivel Murugan 110931fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG); 111031fb632bSRamuthevar Vadivel Murugan if (cqspi->is_decoded_cs) { 111131fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CONFIG_DECODE_MASK; 111231fb632bSRamuthevar Vadivel Murugan } else { 111331fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; 111431fb632bSRamuthevar Vadivel Murugan 111531fb632bSRamuthevar Vadivel Murugan /* Convert CS if without decoder. 111631fb632bSRamuthevar Vadivel Murugan * CS0 to 4b'1110 111731fb632bSRamuthevar Vadivel Murugan * CS1 to 4b'1101 111831fb632bSRamuthevar Vadivel Murugan * CS2 to 4b'1011 111931fb632bSRamuthevar Vadivel Murugan * CS3 to 4b'0111 112031fb632bSRamuthevar Vadivel Murugan */ 112131fb632bSRamuthevar Vadivel Murugan chip_select = 0xF & ~(1 << chip_select); 112231fb632bSRamuthevar Vadivel Murugan } 112331fb632bSRamuthevar Vadivel Murugan 112431fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK 112531fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CONFIG_CHIPSELECT_LSB); 112631fb632bSRamuthevar Vadivel Murugan reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK) 112731fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CONFIG_CHIPSELECT_LSB; 112831fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG); 112931fb632bSRamuthevar Vadivel Murugan } 113031fb632bSRamuthevar Vadivel Murugan 113131fb632bSRamuthevar Vadivel Murugan static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz, 113231fb632bSRamuthevar Vadivel Murugan const unsigned int ns_val) 113331fb632bSRamuthevar Vadivel Murugan { 113431fb632bSRamuthevar Vadivel Murugan unsigned int ticks; 113531fb632bSRamuthevar Vadivel Murugan 113631fb632bSRamuthevar Vadivel Murugan ticks = ref_clk_hz / 1000; /* kHz */ 113731fb632bSRamuthevar Vadivel Murugan ticks = DIV_ROUND_UP(ticks * ns_val, 1000000); 113831fb632bSRamuthevar Vadivel Murugan 113931fb632bSRamuthevar Vadivel Murugan return ticks; 114031fb632bSRamuthevar Vadivel Murugan } 114131fb632bSRamuthevar Vadivel Murugan 114231fb632bSRamuthevar Vadivel Murugan static void cqspi_delay(struct cqspi_flash_pdata *f_pdata) 114331fb632bSRamuthevar Vadivel Murugan { 114431fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 114531fb632bSRamuthevar Vadivel Murugan void __iomem *iobase = cqspi->iobase; 114631fb632bSRamuthevar Vadivel Murugan const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 114731fb632bSRamuthevar Vadivel Murugan unsigned int tshsl, tchsh, tslch, tsd2d; 114831fb632bSRamuthevar Vadivel Murugan unsigned int reg; 114931fb632bSRamuthevar Vadivel Murugan unsigned int tsclk; 115031fb632bSRamuthevar Vadivel Murugan 115131fb632bSRamuthevar Vadivel Murugan /* calculate the number of ref ticks for one sclk tick */ 115231fb632bSRamuthevar Vadivel Murugan tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk); 115331fb632bSRamuthevar Vadivel Murugan 115431fb632bSRamuthevar Vadivel Murugan tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns); 115531fb632bSRamuthevar Vadivel Murugan /* this particular value must be at least one sclk */ 115631fb632bSRamuthevar Vadivel Murugan if (tshsl < tsclk) 115731fb632bSRamuthevar Vadivel Murugan tshsl = tsclk; 115831fb632bSRamuthevar Vadivel Murugan 115931fb632bSRamuthevar Vadivel Murugan tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns); 116031fb632bSRamuthevar Vadivel Murugan tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns); 116131fb632bSRamuthevar Vadivel Murugan tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns); 116231fb632bSRamuthevar Vadivel Murugan 116331fb632bSRamuthevar Vadivel Murugan reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK) 116431fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSHSL_LSB; 116531fb632bSRamuthevar Vadivel Murugan reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK) 116631fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TCHSH_LSB; 116731fb632bSRamuthevar Vadivel Murugan reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK) 116831fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSLCH_LSB; 116931fb632bSRamuthevar Vadivel Murugan reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK) 117031fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSD2D_LSB; 117131fb632bSRamuthevar Vadivel Murugan writel(reg, iobase + CQSPI_REG_DELAY); 117231fb632bSRamuthevar Vadivel Murugan } 117331fb632bSRamuthevar Vadivel Murugan 117431fb632bSRamuthevar Vadivel Murugan static void cqspi_config_baudrate_div(struct cqspi_st *cqspi) 117531fb632bSRamuthevar Vadivel Murugan { 117631fb632bSRamuthevar Vadivel Murugan const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 117731fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 117831fb632bSRamuthevar Vadivel Murugan u32 reg, div; 117931fb632bSRamuthevar Vadivel Murugan 118031fb632bSRamuthevar Vadivel Murugan /* Recalculate the baudrate divisor based on QSPI specification. */ 118131fb632bSRamuthevar Vadivel Murugan div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1; 118231fb632bSRamuthevar Vadivel Murugan 118331fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG); 118431fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); 118531fb632bSRamuthevar Vadivel Murugan reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB; 118631fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG); 118731fb632bSRamuthevar Vadivel Murugan } 118831fb632bSRamuthevar Vadivel Murugan 118931fb632bSRamuthevar Vadivel Murugan static void cqspi_readdata_capture(struct cqspi_st *cqspi, 119031fb632bSRamuthevar Vadivel Murugan const bool bypass, 119131fb632bSRamuthevar Vadivel Murugan const unsigned int delay) 119231fb632bSRamuthevar Vadivel Murugan { 119331fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 119431fb632bSRamuthevar Vadivel Murugan unsigned int reg; 119531fb632bSRamuthevar Vadivel Murugan 119631fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_READCAPTURE); 119731fb632bSRamuthevar Vadivel Murugan 119831fb632bSRamuthevar Vadivel Murugan if (bypass) 119931fb632bSRamuthevar Vadivel Murugan reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 120031fb632bSRamuthevar Vadivel Murugan else 120131fb632bSRamuthevar Vadivel Murugan reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 120231fb632bSRamuthevar Vadivel Murugan 120331fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK 120431fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_READCAPTURE_DELAY_LSB); 120531fb632bSRamuthevar Vadivel Murugan 120631fb632bSRamuthevar Vadivel Murugan reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK) 120731fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_READCAPTURE_DELAY_LSB; 120831fb632bSRamuthevar Vadivel Murugan 120931fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_READCAPTURE); 121031fb632bSRamuthevar Vadivel Murugan } 121131fb632bSRamuthevar Vadivel Murugan 121231fb632bSRamuthevar Vadivel Murugan static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable) 121331fb632bSRamuthevar Vadivel Murugan { 121431fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 121531fb632bSRamuthevar Vadivel Murugan unsigned int reg; 121631fb632bSRamuthevar Vadivel Murugan 121731fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG); 121831fb632bSRamuthevar Vadivel Murugan 121931fb632bSRamuthevar Vadivel Murugan if (enable) 122031fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CONFIG_ENABLE_MASK; 122131fb632bSRamuthevar Vadivel Murugan else 122231fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; 122331fb632bSRamuthevar Vadivel Murugan 122431fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG); 122531fb632bSRamuthevar Vadivel Murugan } 122631fb632bSRamuthevar Vadivel Murugan 122731fb632bSRamuthevar Vadivel Murugan static void cqspi_configure(struct cqspi_flash_pdata *f_pdata, 122831fb632bSRamuthevar Vadivel Murugan unsigned long sclk) 122931fb632bSRamuthevar Vadivel Murugan { 123031fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 123131fb632bSRamuthevar Vadivel Murugan int switch_cs = (cqspi->current_cs != f_pdata->cs); 123231fb632bSRamuthevar Vadivel Murugan int switch_ck = (cqspi->sclk != sclk); 123331fb632bSRamuthevar Vadivel Murugan 123431fb632bSRamuthevar Vadivel Murugan if (switch_cs || switch_ck) 123531fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 123631fb632bSRamuthevar Vadivel Murugan 123731fb632bSRamuthevar Vadivel Murugan /* Switch chip select. */ 123831fb632bSRamuthevar Vadivel Murugan if (switch_cs) { 123931fb632bSRamuthevar Vadivel Murugan cqspi->current_cs = f_pdata->cs; 124031fb632bSRamuthevar Vadivel Murugan cqspi_chipselect(f_pdata); 124131fb632bSRamuthevar Vadivel Murugan } 124231fb632bSRamuthevar Vadivel Murugan 124331fb632bSRamuthevar Vadivel Murugan /* Setup baudrate divisor and delays */ 124431fb632bSRamuthevar Vadivel Murugan if (switch_ck) { 124531fb632bSRamuthevar Vadivel Murugan cqspi->sclk = sclk; 124631fb632bSRamuthevar Vadivel Murugan cqspi_config_baudrate_div(cqspi); 124731fb632bSRamuthevar Vadivel Murugan cqspi_delay(f_pdata); 124831fb632bSRamuthevar Vadivel Murugan cqspi_readdata_capture(cqspi, !cqspi->rclk_en, 124931fb632bSRamuthevar Vadivel Murugan f_pdata->read_delay); 125031fb632bSRamuthevar Vadivel Murugan } 125131fb632bSRamuthevar Vadivel Murugan 125231fb632bSRamuthevar Vadivel Murugan if (switch_cs || switch_ck) 125331fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1); 125431fb632bSRamuthevar Vadivel Murugan } 125531fb632bSRamuthevar Vadivel Murugan 125631fb632bSRamuthevar Vadivel Murugan static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata, 125731fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 125831fb632bSRamuthevar Vadivel Murugan { 125931fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 126031fb632bSRamuthevar Vadivel Murugan loff_t to = op->addr.val; 126131fb632bSRamuthevar Vadivel Murugan size_t len = op->data.nbytes; 126231fb632bSRamuthevar Vadivel Murugan const u_char *buf = op->data.buf.out; 126331fb632bSRamuthevar Vadivel Murugan int ret; 126431fb632bSRamuthevar Vadivel Murugan 126531fb632bSRamuthevar Vadivel Murugan ret = cqspi_set_protocol(f_pdata, op); 126631fb632bSRamuthevar Vadivel Murugan if (ret) 126731fb632bSRamuthevar Vadivel Murugan return ret; 126831fb632bSRamuthevar Vadivel Murugan 126931fb632bSRamuthevar Vadivel Murugan ret = cqspi_write_setup(f_pdata, op); 127031fb632bSRamuthevar Vadivel Murugan if (ret) 127131fb632bSRamuthevar Vadivel Murugan return ret; 127231fb632bSRamuthevar Vadivel Murugan 1273f453f293SPratyush Yadav /* 1274f453f293SPratyush Yadav * Some flashes like the Cypress Semper flash expect a dummy 4-byte 1275f453f293SPratyush Yadav * address (all 0s) with the read status register command in DTR mode. 1276f453f293SPratyush Yadav * But this controller does not support sending dummy address bytes to 1277f453f293SPratyush Yadav * the flash when it is polling the write completion register in DTR 1278f453f293SPratyush Yadav * mode. So, we can not use direct mode when in DTR mode for writing 1279f453f293SPratyush Yadav * data. 1280f453f293SPratyush Yadav */ 1281f453f293SPratyush Yadav if (!f_pdata->dtr && cqspi->use_direct_mode && 1282f453f293SPratyush Yadav ((to + len) <= cqspi->ahb_size)) { 128331fb632bSRamuthevar Vadivel Murugan memcpy_toio(cqspi->ahb_base + to, buf, len); 128431fb632bSRamuthevar Vadivel Murugan return cqspi_wait_idle(cqspi); 128531fb632bSRamuthevar Vadivel Murugan } 128631fb632bSRamuthevar Vadivel Murugan 128731fb632bSRamuthevar Vadivel Murugan return cqspi_indirect_write_execute(f_pdata, to, buf, len); 128831fb632bSRamuthevar Vadivel Murugan } 128931fb632bSRamuthevar Vadivel Murugan 129031fb632bSRamuthevar Vadivel Murugan static void cqspi_rx_dma_callback(void *param) 129131fb632bSRamuthevar Vadivel Murugan { 129231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = param; 129331fb632bSRamuthevar Vadivel Murugan 129431fb632bSRamuthevar Vadivel Murugan complete(&cqspi->rx_dma_complete); 129531fb632bSRamuthevar Vadivel Murugan } 129631fb632bSRamuthevar Vadivel Murugan 129731fb632bSRamuthevar Vadivel Murugan static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata, 129831fb632bSRamuthevar Vadivel Murugan u_char *buf, loff_t from, size_t len) 129931fb632bSRamuthevar Vadivel Murugan { 130031fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 130131fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 130231fb632bSRamuthevar Vadivel Murugan enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; 130331fb632bSRamuthevar Vadivel Murugan dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from; 130431fb632bSRamuthevar Vadivel Murugan int ret = 0; 130531fb632bSRamuthevar Vadivel Murugan struct dma_async_tx_descriptor *tx; 130631fb632bSRamuthevar Vadivel Murugan dma_cookie_t cookie; 130731fb632bSRamuthevar Vadivel Murugan dma_addr_t dma_dst; 130883048015SVignesh Raghavendra struct device *ddev; 130931fb632bSRamuthevar Vadivel Murugan 131031fb632bSRamuthevar Vadivel Murugan if (!cqspi->rx_chan || !virt_addr_valid(buf)) { 131131fb632bSRamuthevar Vadivel Murugan memcpy_fromio(buf, cqspi->ahb_base + from, len); 131231fb632bSRamuthevar Vadivel Murugan return 0; 131331fb632bSRamuthevar Vadivel Murugan } 131431fb632bSRamuthevar Vadivel Murugan 131583048015SVignesh Raghavendra ddev = cqspi->rx_chan->device->dev; 131683048015SVignesh Raghavendra dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE); 131783048015SVignesh Raghavendra if (dma_mapping_error(ddev, dma_dst)) { 131831fb632bSRamuthevar Vadivel Murugan dev_err(dev, "dma mapping failed\n"); 131931fb632bSRamuthevar Vadivel Murugan return -ENOMEM; 132031fb632bSRamuthevar Vadivel Murugan } 132131fb632bSRamuthevar Vadivel Murugan tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src, 132231fb632bSRamuthevar Vadivel Murugan len, flags); 132331fb632bSRamuthevar Vadivel Murugan if (!tx) { 132431fb632bSRamuthevar Vadivel Murugan dev_err(dev, "device_prep_dma_memcpy error\n"); 132531fb632bSRamuthevar Vadivel Murugan ret = -EIO; 132631fb632bSRamuthevar Vadivel Murugan goto err_unmap; 132731fb632bSRamuthevar Vadivel Murugan } 132831fb632bSRamuthevar Vadivel Murugan 132931fb632bSRamuthevar Vadivel Murugan tx->callback = cqspi_rx_dma_callback; 133031fb632bSRamuthevar Vadivel Murugan tx->callback_param = cqspi; 133131fb632bSRamuthevar Vadivel Murugan cookie = tx->tx_submit(tx); 133231fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->rx_dma_complete); 133331fb632bSRamuthevar Vadivel Murugan 133431fb632bSRamuthevar Vadivel Murugan ret = dma_submit_error(cookie); 133531fb632bSRamuthevar Vadivel Murugan if (ret) { 133631fb632bSRamuthevar Vadivel Murugan dev_err(dev, "dma_submit_error %d\n", cookie); 133731fb632bSRamuthevar Vadivel Murugan ret = -EIO; 133831fb632bSRamuthevar Vadivel Murugan goto err_unmap; 133931fb632bSRamuthevar Vadivel Murugan } 134031fb632bSRamuthevar Vadivel Murugan 134131fb632bSRamuthevar Vadivel Murugan dma_async_issue_pending(cqspi->rx_chan); 134231fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->rx_dma_complete, 13432ef0170eSPratyush Yadav msecs_to_jiffies(max_t(size_t, len, 500)))) { 134431fb632bSRamuthevar Vadivel Murugan dmaengine_terminate_sync(cqspi->rx_chan); 134531fb632bSRamuthevar Vadivel Murugan dev_err(dev, "DMA wait_for_completion_timeout\n"); 134631fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 134731fb632bSRamuthevar Vadivel Murugan goto err_unmap; 134831fb632bSRamuthevar Vadivel Murugan } 134931fb632bSRamuthevar Vadivel Murugan 135031fb632bSRamuthevar Vadivel Murugan err_unmap: 135183048015SVignesh Raghavendra dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE); 135231fb632bSRamuthevar Vadivel Murugan 135331fb632bSRamuthevar Vadivel Murugan return ret; 135431fb632bSRamuthevar Vadivel Murugan } 135531fb632bSRamuthevar Vadivel Murugan 135631fb632bSRamuthevar Vadivel Murugan static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata, 135731fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 135831fb632bSRamuthevar Vadivel Murugan { 135931fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 1360*1a6f854fSSai Krishna Potthuri struct device *dev = &cqspi->pdev->dev; 1361*1a6f854fSSai Krishna Potthuri const struct cqspi_driver_platdata *ddata; 136231fb632bSRamuthevar Vadivel Murugan loff_t from = op->addr.val; 136331fb632bSRamuthevar Vadivel Murugan size_t len = op->data.nbytes; 136431fb632bSRamuthevar Vadivel Murugan u_char *buf = op->data.buf.in; 1365*1a6f854fSSai Krishna Potthuri u64 dma_align = (u64)(uintptr_t)buf; 136631fb632bSRamuthevar Vadivel Murugan int ret; 136731fb632bSRamuthevar Vadivel Murugan 1368*1a6f854fSSai Krishna Potthuri ddata = of_device_get_match_data(dev); 136931fb632bSRamuthevar Vadivel Murugan ret = cqspi_set_protocol(f_pdata, op); 137031fb632bSRamuthevar Vadivel Murugan if (ret) 137131fb632bSRamuthevar Vadivel Murugan return ret; 137231fb632bSRamuthevar Vadivel Murugan 137331fb632bSRamuthevar Vadivel Murugan ret = cqspi_read_setup(f_pdata, op); 137431fb632bSRamuthevar Vadivel Murugan if (ret) 137531fb632bSRamuthevar Vadivel Murugan return ret; 137631fb632bSRamuthevar Vadivel Murugan 137731fb632bSRamuthevar Vadivel Murugan if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) 137831fb632bSRamuthevar Vadivel Murugan return cqspi_direct_read_execute(f_pdata, buf, from, len); 137931fb632bSRamuthevar Vadivel Murugan 1380*1a6f854fSSai Krishna Potthuri if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma && 1381*1a6f854fSSai Krishna Potthuri virt_addr_valid(buf) && ((dma_align & CQSPI_DMA_UNALIGN) == 0)) 1382*1a6f854fSSai Krishna Potthuri return ddata->indirect_read_dma(f_pdata, buf, from, len); 1383*1a6f854fSSai Krishna Potthuri 138431fb632bSRamuthevar Vadivel Murugan return cqspi_indirect_read_execute(f_pdata, buf, from, len); 138531fb632bSRamuthevar Vadivel Murugan } 138631fb632bSRamuthevar Vadivel Murugan 138731fb632bSRamuthevar Vadivel Murugan static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op) 138831fb632bSRamuthevar Vadivel Murugan { 138931fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); 139031fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata; 139131fb632bSRamuthevar Vadivel Murugan 139231fb632bSRamuthevar Vadivel Murugan f_pdata = &cqspi->f_pdata[mem->spi->chip_select]; 139331fb632bSRamuthevar Vadivel Murugan cqspi_configure(f_pdata, mem->spi->max_speed_hz); 139431fb632bSRamuthevar Vadivel Murugan 139531fb632bSRamuthevar Vadivel Murugan if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { 139631fb632bSRamuthevar Vadivel Murugan if (!op->addr.nbytes) 139731fb632bSRamuthevar Vadivel Murugan return cqspi_command_read(f_pdata, op); 139831fb632bSRamuthevar Vadivel Murugan 139931fb632bSRamuthevar Vadivel Murugan return cqspi_read(f_pdata, op); 140031fb632bSRamuthevar Vadivel Murugan } 140131fb632bSRamuthevar Vadivel Murugan 140231fb632bSRamuthevar Vadivel Murugan if (!op->addr.nbytes || !op->data.buf.out) 140331fb632bSRamuthevar Vadivel Murugan return cqspi_command_write(f_pdata, op); 140431fb632bSRamuthevar Vadivel Murugan 140531fb632bSRamuthevar Vadivel Murugan return cqspi_write(f_pdata, op); 140631fb632bSRamuthevar Vadivel Murugan } 140731fb632bSRamuthevar Vadivel Murugan 140831fb632bSRamuthevar Vadivel Murugan static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) 140931fb632bSRamuthevar Vadivel Murugan { 141031fb632bSRamuthevar Vadivel Murugan int ret; 141131fb632bSRamuthevar Vadivel Murugan 141231fb632bSRamuthevar Vadivel Murugan ret = cqspi_mem_process(mem, op); 141331fb632bSRamuthevar Vadivel Murugan if (ret) 141431fb632bSRamuthevar Vadivel Murugan dev_err(&mem->spi->dev, "operation failed with %d\n", ret); 141531fb632bSRamuthevar Vadivel Murugan 141631fb632bSRamuthevar Vadivel Murugan return ret; 141731fb632bSRamuthevar Vadivel Murugan } 141831fb632bSRamuthevar Vadivel Murugan 1419a273596bSPratyush Yadav static bool cqspi_supports_mem_op(struct spi_mem *mem, 1420a273596bSPratyush Yadav const struct spi_mem_op *op) 1421a273596bSPratyush Yadav { 1422f453f293SPratyush Yadav bool all_true, all_false; 1423f453f293SPratyush Yadav 14240395be96SApurva Nandan /* 14250395be96SApurva Nandan * op->dummy.dtr is required for converting nbytes into ncycles. 14260395be96SApurva Nandan * Also, don't check the dtr field of the op phase having zero nbytes. 14270395be96SApurva Nandan */ 14280395be96SApurva Nandan all_true = op->cmd.dtr && 14290395be96SApurva Nandan (!op->addr.nbytes || op->addr.dtr) && 14300395be96SApurva Nandan (!op->dummy.nbytes || op->dummy.dtr) && 14310395be96SApurva Nandan (!op->data.nbytes || op->data.dtr); 14320395be96SApurva Nandan 1433f453f293SPratyush Yadav all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && 1434f453f293SPratyush Yadav !op->data.dtr; 1435f453f293SPratyush Yadav 1436f453f293SPratyush Yadav /* Mixed DTR modes not supported. */ 1437f453f293SPratyush Yadav if (!(all_true || all_false)) 1438f453f293SPratyush Yadav return false; 1439f453f293SPratyush Yadav 1440d2275139SPratyush Yadav if (all_true) 1441d2275139SPratyush Yadav return spi_mem_dtr_supports_op(mem, op); 1442d2275139SPratyush Yadav else 1443d2275139SPratyush Yadav return spi_mem_default_supports_op(mem, op); 1444a273596bSPratyush Yadav } 1445a273596bSPratyush Yadav 144631fb632bSRamuthevar Vadivel Murugan static int cqspi_of_get_flash_pdata(struct platform_device *pdev, 144731fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata, 144831fb632bSRamuthevar Vadivel Murugan struct device_node *np) 144931fb632bSRamuthevar Vadivel Murugan { 145031fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) { 145131fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine read-delay\n"); 145231fb632bSRamuthevar Vadivel Murugan return -ENXIO; 145331fb632bSRamuthevar Vadivel Murugan } 145431fb632bSRamuthevar Vadivel Murugan 145531fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) { 145631fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tshsl-ns\n"); 145731fb632bSRamuthevar Vadivel Murugan return -ENXIO; 145831fb632bSRamuthevar Vadivel Murugan } 145931fb632bSRamuthevar Vadivel Murugan 146031fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) { 146131fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n"); 146231fb632bSRamuthevar Vadivel Murugan return -ENXIO; 146331fb632bSRamuthevar Vadivel Murugan } 146431fb632bSRamuthevar Vadivel Murugan 146531fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) { 146631fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tchsh-ns\n"); 146731fb632bSRamuthevar Vadivel Murugan return -ENXIO; 146831fb632bSRamuthevar Vadivel Murugan } 146931fb632bSRamuthevar Vadivel Murugan 147031fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) { 147131fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tslch-ns\n"); 147231fb632bSRamuthevar Vadivel Murugan return -ENXIO; 147331fb632bSRamuthevar Vadivel Murugan } 147431fb632bSRamuthevar Vadivel Murugan 147531fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) { 147631fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n"); 147731fb632bSRamuthevar Vadivel Murugan return -ENXIO; 147831fb632bSRamuthevar Vadivel Murugan } 147931fb632bSRamuthevar Vadivel Murugan 148031fb632bSRamuthevar Vadivel Murugan return 0; 148131fb632bSRamuthevar Vadivel Murugan } 148231fb632bSRamuthevar Vadivel Murugan 148331fb632bSRamuthevar Vadivel Murugan static int cqspi_of_get_pdata(struct cqspi_st *cqspi) 148431fb632bSRamuthevar Vadivel Murugan { 148531fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 148631fb632bSRamuthevar Vadivel Murugan struct device_node *np = dev->of_node; 148709e393e3SSai Krishna Potthuri u32 id[2]; 148831fb632bSRamuthevar Vadivel Murugan 148931fb632bSRamuthevar Vadivel Murugan cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); 149031fb632bSRamuthevar Vadivel Murugan 149131fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { 149231fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine fifo-depth\n"); 149331fb632bSRamuthevar Vadivel Murugan return -ENXIO; 149431fb632bSRamuthevar Vadivel Murugan } 149531fb632bSRamuthevar Vadivel Murugan 149631fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) { 149731fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine fifo-width\n"); 149831fb632bSRamuthevar Vadivel Murugan return -ENXIO; 149931fb632bSRamuthevar Vadivel Murugan } 150031fb632bSRamuthevar Vadivel Murugan 150131fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,trigger-address", 150231fb632bSRamuthevar Vadivel Murugan &cqspi->trigger_address)) { 150331fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine trigger-address\n"); 150431fb632bSRamuthevar Vadivel Murugan return -ENXIO; 150531fb632bSRamuthevar Vadivel Murugan } 150631fb632bSRamuthevar Vadivel Murugan 1507b436fb7dSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) 1508b436fb7dSRamuthevar Vadivel Murugan cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT; 1509b436fb7dSRamuthevar Vadivel Murugan 151031fb632bSRamuthevar Vadivel Murugan cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); 151131fb632bSRamuthevar Vadivel Murugan 151209e393e3SSai Krishna Potthuri if (!of_property_read_u32_array(np, "power-domains", id, 151309e393e3SSai Krishna Potthuri ARRAY_SIZE(id))) 151409e393e3SSai Krishna Potthuri cqspi->pd_dev_id = id[1]; 151509e393e3SSai Krishna Potthuri 151631fb632bSRamuthevar Vadivel Murugan return 0; 151731fb632bSRamuthevar Vadivel Murugan } 151831fb632bSRamuthevar Vadivel Murugan 151931fb632bSRamuthevar Vadivel Murugan static void cqspi_controller_init(struct cqspi_st *cqspi) 152031fb632bSRamuthevar Vadivel Murugan { 152131fb632bSRamuthevar Vadivel Murugan u32 reg; 152231fb632bSRamuthevar Vadivel Murugan 152331fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 152431fb632bSRamuthevar Vadivel Murugan 152531fb632bSRamuthevar Vadivel Murugan /* Configure the remap address register, no remap */ 152631fb632bSRamuthevar Vadivel Murugan writel(0, cqspi->iobase + CQSPI_REG_REMAP); 152731fb632bSRamuthevar Vadivel Murugan 152831fb632bSRamuthevar Vadivel Murugan /* Disable all interrupts. */ 152931fb632bSRamuthevar Vadivel Murugan writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); 153031fb632bSRamuthevar Vadivel Murugan 153131fb632bSRamuthevar Vadivel Murugan /* Configure the SRAM split to 1:1 . */ 153231fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); 153331fb632bSRamuthevar Vadivel Murugan 153431fb632bSRamuthevar Vadivel Murugan /* Load indirect trigger address. */ 153531fb632bSRamuthevar Vadivel Murugan writel(cqspi->trigger_address, 153631fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); 153731fb632bSRamuthevar Vadivel Murugan 153831fb632bSRamuthevar Vadivel Murugan /* Program read watermark -- 1/2 of the FIFO. */ 153931fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth * cqspi->fifo_width / 2, 154031fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); 154131fb632bSRamuthevar Vadivel Murugan /* Program write watermark -- 1/8 of the FIFO. */ 154231fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth * cqspi->fifo_width / 8, 154331fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); 154431fb632bSRamuthevar Vadivel Murugan 1545ad2775dcSRamuthevar Vadivel Murugan /* Disable direct access controller */ 1546ad2775dcSRamuthevar Vadivel Murugan if (!cqspi->use_direct_mode) { 154731fb632bSRamuthevar Vadivel Murugan reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 1548ad2775dcSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL; 154931fb632bSRamuthevar Vadivel Murugan writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 1550ad2775dcSRamuthevar Vadivel Murugan } 155131fb632bSRamuthevar Vadivel Murugan 1552*1a6f854fSSai Krishna Potthuri /* Enable DMA interface */ 1553*1a6f854fSSai Krishna Potthuri if (cqspi->use_dma_read) { 1554*1a6f854fSSai Krishna Potthuri reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 1555*1a6f854fSSai Krishna Potthuri reg |= CQSPI_REG_CONFIG_DMA_MASK; 1556*1a6f854fSSai Krishna Potthuri writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 1557*1a6f854fSSai Krishna Potthuri } 1558*1a6f854fSSai Krishna Potthuri 155931fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1); 156031fb632bSRamuthevar Vadivel Murugan } 156131fb632bSRamuthevar Vadivel Murugan 156231fb632bSRamuthevar Vadivel Murugan static int cqspi_request_mmap_dma(struct cqspi_st *cqspi) 156331fb632bSRamuthevar Vadivel Murugan { 156431fb632bSRamuthevar Vadivel Murugan dma_cap_mask_t mask; 156531fb632bSRamuthevar Vadivel Murugan 156631fb632bSRamuthevar Vadivel Murugan dma_cap_zero(mask); 156731fb632bSRamuthevar Vadivel Murugan dma_cap_set(DMA_MEMCPY, mask); 156831fb632bSRamuthevar Vadivel Murugan 156931fb632bSRamuthevar Vadivel Murugan cqspi->rx_chan = dma_request_chan_by_mask(&mask); 157031fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->rx_chan)) { 157131fb632bSRamuthevar Vadivel Murugan int ret = PTR_ERR(cqspi->rx_chan); 157231fb632bSRamuthevar Vadivel Murugan cqspi->rx_chan = NULL; 1573436a5c20SKrzysztof Kozlowski return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n"); 157431fb632bSRamuthevar Vadivel Murugan } 157531fb632bSRamuthevar Vadivel Murugan init_completion(&cqspi->rx_dma_complete); 157631fb632bSRamuthevar Vadivel Murugan 157731fb632bSRamuthevar Vadivel Murugan return 0; 157831fb632bSRamuthevar Vadivel Murugan } 157931fb632bSRamuthevar Vadivel Murugan 15802ea370a9SVignesh Raghavendra static const char *cqspi_get_name(struct spi_mem *mem) 15812ea370a9SVignesh Raghavendra { 15822ea370a9SVignesh Raghavendra struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); 15832ea370a9SVignesh Raghavendra struct device *dev = &cqspi->pdev->dev; 15842ea370a9SVignesh Raghavendra 15852ea370a9SVignesh Raghavendra return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select); 15862ea370a9SVignesh Raghavendra } 15872ea370a9SVignesh Raghavendra 158831fb632bSRamuthevar Vadivel Murugan static const struct spi_controller_mem_ops cqspi_mem_ops = { 158931fb632bSRamuthevar Vadivel Murugan .exec_op = cqspi_exec_mem_op, 15902ea370a9SVignesh Raghavendra .get_name = cqspi_get_name, 1591a273596bSPratyush Yadav .supports_op = cqspi_supports_mem_op, 159231fb632bSRamuthevar Vadivel Murugan }; 159331fb632bSRamuthevar Vadivel Murugan 159431fb632bSRamuthevar Vadivel Murugan static int cqspi_setup_flash(struct cqspi_st *cqspi) 159531fb632bSRamuthevar Vadivel Murugan { 159631fb632bSRamuthevar Vadivel Murugan struct platform_device *pdev = cqspi->pdev; 159731fb632bSRamuthevar Vadivel Murugan struct device *dev = &pdev->dev; 159831fb632bSRamuthevar Vadivel Murugan struct device_node *np = dev->of_node; 159931fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata; 160031fb632bSRamuthevar Vadivel Murugan unsigned int cs; 160131fb632bSRamuthevar Vadivel Murugan int ret; 160231fb632bSRamuthevar Vadivel Murugan 160331fb632bSRamuthevar Vadivel Murugan /* Get flash device data */ 160431fb632bSRamuthevar Vadivel Murugan for_each_available_child_of_node(dev->of_node, np) { 160531fb632bSRamuthevar Vadivel Murugan ret = of_property_read_u32(np, "reg", &cs); 160631fb632bSRamuthevar Vadivel Murugan if (ret) { 160731fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Couldn't determine chip select.\n"); 160887d62d8fSJunlin Yang of_node_put(np); 160931fb632bSRamuthevar Vadivel Murugan return ret; 161031fb632bSRamuthevar Vadivel Murugan } 161131fb632bSRamuthevar Vadivel Murugan 161231fb632bSRamuthevar Vadivel Murugan if (cs >= CQSPI_MAX_CHIPSELECT) { 161331fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Chip select %d out of range.\n", cs); 161487d62d8fSJunlin Yang of_node_put(np); 161531fb632bSRamuthevar Vadivel Murugan return -EINVAL; 161631fb632bSRamuthevar Vadivel Murugan } 161731fb632bSRamuthevar Vadivel Murugan 161831fb632bSRamuthevar Vadivel Murugan f_pdata = &cqspi->f_pdata[cs]; 161931fb632bSRamuthevar Vadivel Murugan f_pdata->cqspi = cqspi; 162031fb632bSRamuthevar Vadivel Murugan f_pdata->cs = cs; 162131fb632bSRamuthevar Vadivel Murugan 162231fb632bSRamuthevar Vadivel Murugan ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np); 162387d62d8fSJunlin Yang if (ret) { 162487d62d8fSJunlin Yang of_node_put(np); 162531fb632bSRamuthevar Vadivel Murugan return ret; 162631fb632bSRamuthevar Vadivel Murugan } 162787d62d8fSJunlin Yang } 162831fb632bSRamuthevar Vadivel Murugan 162931fb632bSRamuthevar Vadivel Murugan return 0; 163031fb632bSRamuthevar Vadivel Murugan } 163131fb632bSRamuthevar Vadivel Murugan 163231fb632bSRamuthevar Vadivel Murugan static int cqspi_probe(struct platform_device *pdev) 163331fb632bSRamuthevar Vadivel Murugan { 163431fb632bSRamuthevar Vadivel Murugan const struct cqspi_driver_platdata *ddata; 163531fb632bSRamuthevar Vadivel Murugan struct reset_control *rstc, *rstc_ocp; 163631fb632bSRamuthevar Vadivel Murugan struct device *dev = &pdev->dev; 163731fb632bSRamuthevar Vadivel Murugan struct spi_master *master; 163831fb632bSRamuthevar Vadivel Murugan struct resource *res_ahb; 163931fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi; 164031fb632bSRamuthevar Vadivel Murugan struct resource *res; 164131fb632bSRamuthevar Vadivel Murugan int ret; 164231fb632bSRamuthevar Vadivel Murugan int irq; 164331fb632bSRamuthevar Vadivel Murugan 164431fb632bSRamuthevar Vadivel Murugan master = spi_alloc_master(&pdev->dev, sizeof(*cqspi)); 164531fb632bSRamuthevar Vadivel Murugan if (!master) { 164631fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "spi_alloc_master failed\n"); 164731fb632bSRamuthevar Vadivel Murugan return -ENOMEM; 164831fb632bSRamuthevar Vadivel Murugan } 164931fb632bSRamuthevar Vadivel Murugan master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; 165031fb632bSRamuthevar Vadivel Murugan master->mem_ops = &cqspi_mem_ops; 165131fb632bSRamuthevar Vadivel Murugan master->dev.of_node = pdev->dev.of_node; 165231fb632bSRamuthevar Vadivel Murugan 165331fb632bSRamuthevar Vadivel Murugan cqspi = spi_master_get_devdata(master); 165431fb632bSRamuthevar Vadivel Murugan 165531fb632bSRamuthevar Vadivel Murugan cqspi->pdev = pdev; 1656ea94191eSMeng Li platform_set_drvdata(pdev, cqspi); 165731fb632bSRamuthevar Vadivel Murugan 165831fb632bSRamuthevar Vadivel Murugan /* Obtain configuration from OF. */ 165931fb632bSRamuthevar Vadivel Murugan ret = cqspi_of_get_pdata(cqspi); 166031fb632bSRamuthevar Vadivel Murugan if (ret) { 166131fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get mandatory OF data.\n"); 166231fb632bSRamuthevar Vadivel Murugan ret = -ENODEV; 166331fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 166431fb632bSRamuthevar Vadivel Murugan } 166531fb632bSRamuthevar Vadivel Murugan 166631fb632bSRamuthevar Vadivel Murugan /* Obtain QSPI clock. */ 166731fb632bSRamuthevar Vadivel Murugan cqspi->clk = devm_clk_get(dev, NULL); 166831fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->clk)) { 166931fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot claim QSPI clock.\n"); 167031fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->clk); 167131fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 167231fb632bSRamuthevar Vadivel Murugan } 167331fb632bSRamuthevar Vadivel Murugan 167431fb632bSRamuthevar Vadivel Murugan /* Obtain and remap controller address. */ 167531fb632bSRamuthevar Vadivel Murugan res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 167631fb632bSRamuthevar Vadivel Murugan cqspi->iobase = devm_ioremap_resource(dev, res); 167731fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->iobase)) { 167831fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot remap controller address.\n"); 167931fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->iobase); 168031fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 168131fb632bSRamuthevar Vadivel Murugan } 168231fb632bSRamuthevar Vadivel Murugan 168331fb632bSRamuthevar Vadivel Murugan /* Obtain and remap AHB address. */ 168431fb632bSRamuthevar Vadivel Murugan res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1); 168531fb632bSRamuthevar Vadivel Murugan cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb); 168631fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->ahb_base)) { 168731fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot remap AHB address.\n"); 168831fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->ahb_base); 168931fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 169031fb632bSRamuthevar Vadivel Murugan } 169131fb632bSRamuthevar Vadivel Murugan cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start; 169231fb632bSRamuthevar Vadivel Murugan cqspi->ahb_size = resource_size(res_ahb); 169331fb632bSRamuthevar Vadivel Murugan 169431fb632bSRamuthevar Vadivel Murugan init_completion(&cqspi->transfer_complete); 169531fb632bSRamuthevar Vadivel Murugan 169631fb632bSRamuthevar Vadivel Murugan /* Obtain IRQ line. */ 169731fb632bSRamuthevar Vadivel Murugan irq = platform_get_irq(pdev, 0); 169831fb632bSRamuthevar Vadivel Murugan if (irq < 0) { 169931fb632bSRamuthevar Vadivel Murugan ret = -ENXIO; 170031fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 170131fb632bSRamuthevar Vadivel Murugan } 170231fb632bSRamuthevar Vadivel Murugan 170331fb632bSRamuthevar Vadivel Murugan pm_runtime_enable(dev); 170431fb632bSRamuthevar Vadivel Murugan ret = pm_runtime_get_sync(dev); 170531fb632bSRamuthevar Vadivel Murugan if (ret < 0) { 170631fb632bSRamuthevar Vadivel Murugan pm_runtime_put_noidle(dev); 170731fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 170831fb632bSRamuthevar Vadivel Murugan } 170931fb632bSRamuthevar Vadivel Murugan 171031fb632bSRamuthevar Vadivel Murugan ret = clk_prepare_enable(cqspi->clk); 171131fb632bSRamuthevar Vadivel Murugan if (ret) { 171231fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot enable QSPI clock.\n"); 171331fb632bSRamuthevar Vadivel Murugan goto probe_clk_failed; 171431fb632bSRamuthevar Vadivel Murugan } 171531fb632bSRamuthevar Vadivel Murugan 171631fb632bSRamuthevar Vadivel Murugan /* Obtain QSPI reset control */ 171731fb632bSRamuthevar Vadivel Murugan rstc = devm_reset_control_get_optional_exclusive(dev, "qspi"); 171831fb632bSRamuthevar Vadivel Murugan if (IS_ERR(rstc)) { 1719ac9978fcSZhihao Cheng ret = PTR_ERR(rstc); 172031fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get QSPI reset.\n"); 172131fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 172231fb632bSRamuthevar Vadivel Murugan } 172331fb632bSRamuthevar Vadivel Murugan 172431fb632bSRamuthevar Vadivel Murugan rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); 172531fb632bSRamuthevar Vadivel Murugan if (IS_ERR(rstc_ocp)) { 1726ac9978fcSZhihao Cheng ret = PTR_ERR(rstc_ocp); 172731fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get QSPI OCP reset.\n"); 172831fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 172931fb632bSRamuthevar Vadivel Murugan } 173031fb632bSRamuthevar Vadivel Murugan 173131fb632bSRamuthevar Vadivel Murugan reset_control_assert(rstc); 173231fb632bSRamuthevar Vadivel Murugan reset_control_deassert(rstc); 173331fb632bSRamuthevar Vadivel Murugan 173431fb632bSRamuthevar Vadivel Murugan reset_control_assert(rstc_ocp); 173531fb632bSRamuthevar Vadivel Murugan reset_control_deassert(rstc_ocp); 173631fb632bSRamuthevar Vadivel Murugan 173731fb632bSRamuthevar Vadivel Murugan cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); 17383a5c09c8SPratyush Yadav master->max_speed_hz = cqspi->master_ref_clk_hz; 173931fb632bSRamuthevar Vadivel Murugan ddata = of_device_get_match_data(dev); 174031fb632bSRamuthevar Vadivel Murugan if (ddata) { 174131fb632bSRamuthevar Vadivel Murugan if (ddata->quirks & CQSPI_NEEDS_WR_DELAY) 1742f453f293SPratyush Yadav cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, 174331fb632bSRamuthevar Vadivel Murugan cqspi->master_ref_clk_hz); 174431fb632bSRamuthevar Vadivel Murugan if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL) 1745f453f293SPratyush Yadav master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; 174631fb632bSRamuthevar Vadivel Murugan if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) 174731fb632bSRamuthevar Vadivel Murugan cqspi->use_direct_mode = true; 1748*1a6f854fSSai Krishna Potthuri if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA) 1749*1a6f854fSSai Krishna Potthuri cqspi->use_dma_read = true; 1750*1a6f854fSSai Krishna Potthuri 175109e393e3SSai Krishna Potthuri if (of_device_is_compatible(pdev->dev.of_node, 1752*1a6f854fSSai Krishna Potthuri "xlnx,versal-ospi-1.0")) 1753*1a6f854fSSai Krishna Potthuri dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); 175431fb632bSRamuthevar Vadivel Murugan } 175531fb632bSRamuthevar Vadivel Murugan 175631fb632bSRamuthevar Vadivel Murugan ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0, 175731fb632bSRamuthevar Vadivel Murugan pdev->name, cqspi); 175831fb632bSRamuthevar Vadivel Murugan if (ret) { 175931fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot request IRQ.\n"); 176031fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 176131fb632bSRamuthevar Vadivel Murugan } 176231fb632bSRamuthevar Vadivel Murugan 176331fb632bSRamuthevar Vadivel Murugan cqspi_wait_idle(cqspi); 176431fb632bSRamuthevar Vadivel Murugan cqspi_controller_init(cqspi); 176531fb632bSRamuthevar Vadivel Murugan cqspi->current_cs = -1; 176631fb632bSRamuthevar Vadivel Murugan cqspi->sclk = 0; 176731fb632bSRamuthevar Vadivel Murugan 1768b436fb7dSRamuthevar Vadivel Murugan master->num_chipselect = cqspi->num_chipselect; 1769b436fb7dSRamuthevar Vadivel Murugan 177031fb632bSRamuthevar Vadivel Murugan ret = cqspi_setup_flash(cqspi); 177131fb632bSRamuthevar Vadivel Murugan if (ret) { 177231fb632bSRamuthevar Vadivel Murugan dev_err(dev, "failed to setup flash parameters %d\n", ret); 177331fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 177431fb632bSRamuthevar Vadivel Murugan } 177531fb632bSRamuthevar Vadivel Murugan 177631fb632bSRamuthevar Vadivel Murugan if (cqspi->use_direct_mode) { 177731fb632bSRamuthevar Vadivel Murugan ret = cqspi_request_mmap_dma(cqspi); 177831fb632bSRamuthevar Vadivel Murugan if (ret == -EPROBE_DEFER) 177931fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 178031fb632bSRamuthevar Vadivel Murugan } 178131fb632bSRamuthevar Vadivel Murugan 178231fb632bSRamuthevar Vadivel Murugan ret = devm_spi_register_master(dev, master); 178331fb632bSRamuthevar Vadivel Murugan if (ret) { 178431fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret); 178531fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 178631fb632bSRamuthevar Vadivel Murugan } 178731fb632bSRamuthevar Vadivel Murugan 178831fb632bSRamuthevar Vadivel Murugan return 0; 178931fb632bSRamuthevar Vadivel Murugan probe_setup_failed: 179031fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 179131fb632bSRamuthevar Vadivel Murugan probe_reset_failed: 179231fb632bSRamuthevar Vadivel Murugan clk_disable_unprepare(cqspi->clk); 179331fb632bSRamuthevar Vadivel Murugan probe_clk_failed: 179431fb632bSRamuthevar Vadivel Murugan pm_runtime_put_sync(dev); 179531fb632bSRamuthevar Vadivel Murugan pm_runtime_disable(dev); 179631fb632bSRamuthevar Vadivel Murugan probe_master_put: 179731fb632bSRamuthevar Vadivel Murugan spi_master_put(master); 179831fb632bSRamuthevar Vadivel Murugan return ret; 179931fb632bSRamuthevar Vadivel Murugan } 180031fb632bSRamuthevar Vadivel Murugan 180131fb632bSRamuthevar Vadivel Murugan static int cqspi_remove(struct platform_device *pdev) 180231fb632bSRamuthevar Vadivel Murugan { 180331fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = platform_get_drvdata(pdev); 180431fb632bSRamuthevar Vadivel Murugan 180531fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 180631fb632bSRamuthevar Vadivel Murugan 180731fb632bSRamuthevar Vadivel Murugan if (cqspi->rx_chan) 180831fb632bSRamuthevar Vadivel Murugan dma_release_channel(cqspi->rx_chan); 180931fb632bSRamuthevar Vadivel Murugan 181031fb632bSRamuthevar Vadivel Murugan clk_disable_unprepare(cqspi->clk); 181131fb632bSRamuthevar Vadivel Murugan 181231fb632bSRamuthevar Vadivel Murugan pm_runtime_put_sync(&pdev->dev); 181331fb632bSRamuthevar Vadivel Murugan pm_runtime_disable(&pdev->dev); 181431fb632bSRamuthevar Vadivel Murugan 181531fb632bSRamuthevar Vadivel Murugan return 0; 181631fb632bSRamuthevar Vadivel Murugan } 181731fb632bSRamuthevar Vadivel Murugan 181831fb632bSRamuthevar Vadivel Murugan #ifdef CONFIG_PM_SLEEP 181931fb632bSRamuthevar Vadivel Murugan static int cqspi_suspend(struct device *dev) 182031fb632bSRamuthevar Vadivel Murugan { 182131fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev_get_drvdata(dev); 182231fb632bSRamuthevar Vadivel Murugan 182331fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 182431fb632bSRamuthevar Vadivel Murugan return 0; 182531fb632bSRamuthevar Vadivel Murugan } 182631fb632bSRamuthevar Vadivel Murugan 182731fb632bSRamuthevar Vadivel Murugan static int cqspi_resume(struct device *dev) 182831fb632bSRamuthevar Vadivel Murugan { 182931fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev_get_drvdata(dev); 183031fb632bSRamuthevar Vadivel Murugan 183131fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1); 183231fb632bSRamuthevar Vadivel Murugan return 0; 183331fb632bSRamuthevar Vadivel Murugan } 183431fb632bSRamuthevar Vadivel Murugan 183531fb632bSRamuthevar Vadivel Murugan static const struct dev_pm_ops cqspi__dev_pm_ops = { 183631fb632bSRamuthevar Vadivel Murugan .suspend = cqspi_suspend, 183731fb632bSRamuthevar Vadivel Murugan .resume = cqspi_resume, 183831fb632bSRamuthevar Vadivel Murugan }; 183931fb632bSRamuthevar Vadivel Murugan 184031fb632bSRamuthevar Vadivel Murugan #define CQSPI_DEV_PM_OPS (&cqspi__dev_pm_ops) 184131fb632bSRamuthevar Vadivel Murugan #else 184231fb632bSRamuthevar Vadivel Murugan #define CQSPI_DEV_PM_OPS NULL 184331fb632bSRamuthevar Vadivel Murugan #endif 184431fb632bSRamuthevar Vadivel Murugan 184531fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata cdns_qspi = { 184631fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_DISABLE_DAC_MODE, 184731fb632bSRamuthevar Vadivel Murugan }; 184831fb632bSRamuthevar Vadivel Murugan 184931fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata k2g_qspi = { 185031fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_NEEDS_WR_DELAY, 185131fb632bSRamuthevar Vadivel Murugan }; 185231fb632bSRamuthevar Vadivel Murugan 185331fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata am654_ospi = { 185431fb632bSRamuthevar Vadivel Murugan .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 185531fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_NEEDS_WR_DELAY, 185631fb632bSRamuthevar Vadivel Murugan }; 185731fb632bSRamuthevar Vadivel Murugan 1858ad2775dcSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata intel_lgm_qspi = { 1859ad2775dcSRamuthevar Vadivel Murugan .quirks = CQSPI_DISABLE_DAC_MODE, 1860ad2775dcSRamuthevar Vadivel Murugan }; 1861ad2775dcSRamuthevar Vadivel Murugan 186209e393e3SSai Krishna Potthuri static const struct cqspi_driver_platdata versal_ospi = { 186309e393e3SSai Krishna Potthuri .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 1864*1a6f854fSSai Krishna Potthuri .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA, 1865*1a6f854fSSai Krishna Potthuri .indirect_read_dma = cqspi_versal_indirect_read_dma, 1866*1a6f854fSSai Krishna Potthuri .get_dma_status = cqspi_get_versal_dma_status, 186709e393e3SSai Krishna Potthuri }; 186809e393e3SSai Krishna Potthuri 186931fb632bSRamuthevar Vadivel Murugan static const struct of_device_id cqspi_dt_ids[] = { 187031fb632bSRamuthevar Vadivel Murugan { 187131fb632bSRamuthevar Vadivel Murugan .compatible = "cdns,qspi-nor", 187231fb632bSRamuthevar Vadivel Murugan .data = &cdns_qspi, 187331fb632bSRamuthevar Vadivel Murugan }, 187431fb632bSRamuthevar Vadivel Murugan { 187531fb632bSRamuthevar Vadivel Murugan .compatible = "ti,k2g-qspi", 187631fb632bSRamuthevar Vadivel Murugan .data = &k2g_qspi, 187731fb632bSRamuthevar Vadivel Murugan }, 187831fb632bSRamuthevar Vadivel Murugan { 187931fb632bSRamuthevar Vadivel Murugan .compatible = "ti,am654-ospi", 188031fb632bSRamuthevar Vadivel Murugan .data = &am654_ospi, 188131fb632bSRamuthevar Vadivel Murugan }, 1882ab2d2875SRamuthevar Vadivel Murugan { 1883ab2d2875SRamuthevar Vadivel Murugan .compatible = "intel,lgm-qspi", 1884ad2775dcSRamuthevar Vadivel Murugan .data = &intel_lgm_qspi, 1885ab2d2875SRamuthevar Vadivel Murugan }, 188609e393e3SSai Krishna Potthuri { 188709e393e3SSai Krishna Potthuri .compatible = "xlnx,versal-ospi-1.0", 188809e393e3SSai Krishna Potthuri .data = (void *)&versal_ospi, 188909e393e3SSai Krishna Potthuri }, 189031fb632bSRamuthevar Vadivel Murugan { /* end of table */ } 189131fb632bSRamuthevar Vadivel Murugan }; 189231fb632bSRamuthevar Vadivel Murugan 189331fb632bSRamuthevar Vadivel Murugan MODULE_DEVICE_TABLE(of, cqspi_dt_ids); 189431fb632bSRamuthevar Vadivel Murugan 189531fb632bSRamuthevar Vadivel Murugan static struct platform_driver cqspi_platform_driver = { 189631fb632bSRamuthevar Vadivel Murugan .probe = cqspi_probe, 189731fb632bSRamuthevar Vadivel Murugan .remove = cqspi_remove, 189831fb632bSRamuthevar Vadivel Murugan .driver = { 189931fb632bSRamuthevar Vadivel Murugan .name = CQSPI_NAME, 190031fb632bSRamuthevar Vadivel Murugan .pm = CQSPI_DEV_PM_OPS, 190131fb632bSRamuthevar Vadivel Murugan .of_match_table = cqspi_dt_ids, 190231fb632bSRamuthevar Vadivel Murugan }, 190331fb632bSRamuthevar Vadivel Murugan }; 190431fb632bSRamuthevar Vadivel Murugan 190531fb632bSRamuthevar Vadivel Murugan module_platform_driver(cqspi_platform_driver); 190631fb632bSRamuthevar Vadivel Murugan 190731fb632bSRamuthevar Vadivel Murugan MODULE_DESCRIPTION("Cadence QSPI Controller Driver"); 190831fb632bSRamuthevar Vadivel Murugan MODULE_LICENSE("GPL v2"); 190931fb632bSRamuthevar Vadivel Murugan MODULE_ALIAS("platform:" CQSPI_NAME); 191031fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>"); 191131fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>"); 191231fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>"); 191331fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>"); 1914f453f293SPratyush Yadav MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>"); 1915