131fb632bSRamuthevar Vadivel Murugan // SPDX-License-Identifier: GPL-2.0-only 231fb632bSRamuthevar Vadivel Murugan // 331fb632bSRamuthevar Vadivel Murugan // Driver for Cadence QSPI Controller 431fb632bSRamuthevar Vadivel Murugan // 531fb632bSRamuthevar Vadivel Murugan // Copyright Altera Corporation (C) 2012-2014. All rights reserved. 631fb632bSRamuthevar Vadivel Murugan // Copyright Intel Corporation (C) 2019-2020. All rights reserved. 731fb632bSRamuthevar Vadivel Murugan // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 831fb632bSRamuthevar Vadivel Murugan 931fb632bSRamuthevar Vadivel Murugan #include <linux/clk.h> 1031fb632bSRamuthevar Vadivel Murugan #include <linux/completion.h> 1131fb632bSRamuthevar Vadivel Murugan #include <linux/delay.h> 1231fb632bSRamuthevar Vadivel Murugan #include <linux/dma-mapping.h> 1331fb632bSRamuthevar Vadivel Murugan #include <linux/dmaengine.h> 1431fb632bSRamuthevar Vadivel Murugan #include <linux/err.h> 1531fb632bSRamuthevar Vadivel Murugan #include <linux/errno.h> 1631fb632bSRamuthevar Vadivel Murugan #include <linux/interrupt.h> 1731fb632bSRamuthevar Vadivel Murugan #include <linux/io.h> 1831fb632bSRamuthevar Vadivel Murugan #include <linux/iopoll.h> 1931fb632bSRamuthevar Vadivel Murugan #include <linux/jiffies.h> 2031fb632bSRamuthevar Vadivel Murugan #include <linux/kernel.h> 2131fb632bSRamuthevar Vadivel Murugan #include <linux/module.h> 2231fb632bSRamuthevar Vadivel Murugan #include <linux/of_device.h> 2331fb632bSRamuthevar Vadivel Murugan #include <linux/of.h> 2431fb632bSRamuthevar Vadivel Murugan #include <linux/platform_device.h> 2531fb632bSRamuthevar Vadivel Murugan #include <linux/pm_runtime.h> 2631fb632bSRamuthevar Vadivel Murugan #include <linux/reset.h> 2731fb632bSRamuthevar Vadivel Murugan #include <linux/sched.h> 2831fb632bSRamuthevar Vadivel Murugan #include <linux/spi/spi.h> 2931fb632bSRamuthevar Vadivel Murugan #include <linux/spi/spi-mem.h> 3031fb632bSRamuthevar Vadivel Murugan #include <linux/timer.h> 3131fb632bSRamuthevar Vadivel Murugan 3231fb632bSRamuthevar Vadivel Murugan #define CQSPI_NAME "cadence-qspi" 3331fb632bSRamuthevar Vadivel Murugan #define CQSPI_MAX_CHIPSELECT 16 3431fb632bSRamuthevar Vadivel Murugan 3531fb632bSRamuthevar Vadivel Murugan /* Quirks */ 3631fb632bSRamuthevar Vadivel Murugan #define CQSPI_NEEDS_WR_DELAY BIT(0) 3731fb632bSRamuthevar Vadivel Murugan #define CQSPI_DISABLE_DAC_MODE BIT(1) 3831fb632bSRamuthevar Vadivel Murugan 3931fb632bSRamuthevar Vadivel Murugan /* Capabilities */ 4031fb632bSRamuthevar Vadivel Murugan #define CQSPI_SUPPORTS_OCTAL BIT(0) 4131fb632bSRamuthevar Vadivel Murugan 4231fb632bSRamuthevar Vadivel Murugan struct cqspi_st; 4331fb632bSRamuthevar Vadivel Murugan 4431fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata { 4531fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi; 4631fb632bSRamuthevar Vadivel Murugan u32 clk_rate; 4731fb632bSRamuthevar Vadivel Murugan u32 read_delay; 4831fb632bSRamuthevar Vadivel Murugan u32 tshsl_ns; 4931fb632bSRamuthevar Vadivel Murugan u32 tsd2d_ns; 5031fb632bSRamuthevar Vadivel Murugan u32 tchsh_ns; 5131fb632bSRamuthevar Vadivel Murugan u32 tslch_ns; 5231fb632bSRamuthevar Vadivel Murugan u8 inst_width; 5331fb632bSRamuthevar Vadivel Murugan u8 addr_width; 5431fb632bSRamuthevar Vadivel Murugan u8 data_width; 55f453f293SPratyush Yadav bool dtr; 5631fb632bSRamuthevar Vadivel Murugan u8 cs; 5731fb632bSRamuthevar Vadivel Murugan }; 5831fb632bSRamuthevar Vadivel Murugan 5931fb632bSRamuthevar Vadivel Murugan struct cqspi_st { 6031fb632bSRamuthevar Vadivel Murugan struct platform_device *pdev; 6131fb632bSRamuthevar Vadivel Murugan 6231fb632bSRamuthevar Vadivel Murugan struct clk *clk; 6331fb632bSRamuthevar Vadivel Murugan unsigned int sclk; 6431fb632bSRamuthevar Vadivel Murugan 6531fb632bSRamuthevar Vadivel Murugan void __iomem *iobase; 6631fb632bSRamuthevar Vadivel Murugan void __iomem *ahb_base; 6731fb632bSRamuthevar Vadivel Murugan resource_size_t ahb_size; 6831fb632bSRamuthevar Vadivel Murugan struct completion transfer_complete; 6931fb632bSRamuthevar Vadivel Murugan 7031fb632bSRamuthevar Vadivel Murugan struct dma_chan *rx_chan; 7131fb632bSRamuthevar Vadivel Murugan struct completion rx_dma_complete; 7231fb632bSRamuthevar Vadivel Murugan dma_addr_t mmap_phys_base; 7331fb632bSRamuthevar Vadivel Murugan 7431fb632bSRamuthevar Vadivel Murugan int current_cs; 7531fb632bSRamuthevar Vadivel Murugan unsigned long master_ref_clk_hz; 7631fb632bSRamuthevar Vadivel Murugan bool is_decoded_cs; 7731fb632bSRamuthevar Vadivel Murugan u32 fifo_depth; 7831fb632bSRamuthevar Vadivel Murugan u32 fifo_width; 79b436fb7dSRamuthevar Vadivel Murugan u32 num_chipselect; 8031fb632bSRamuthevar Vadivel Murugan bool rclk_en; 8131fb632bSRamuthevar Vadivel Murugan u32 trigger_address; 8231fb632bSRamuthevar Vadivel Murugan u32 wr_delay; 8331fb632bSRamuthevar Vadivel Murugan bool use_direct_mode; 8431fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; 8531fb632bSRamuthevar Vadivel Murugan }; 8631fb632bSRamuthevar Vadivel Murugan 8731fb632bSRamuthevar Vadivel Murugan struct cqspi_driver_platdata { 8831fb632bSRamuthevar Vadivel Murugan u32 hwcaps_mask; 8931fb632bSRamuthevar Vadivel Murugan u8 quirks; 9031fb632bSRamuthevar Vadivel Murugan }; 9131fb632bSRamuthevar Vadivel Murugan 9231fb632bSRamuthevar Vadivel Murugan /* Operation timeout value */ 9331fb632bSRamuthevar Vadivel Murugan #define CQSPI_TIMEOUT_MS 500 9431fb632bSRamuthevar Vadivel Murugan #define CQSPI_READ_TIMEOUT_MS 10 9531fb632bSRamuthevar Vadivel Murugan 9631fb632bSRamuthevar Vadivel Murugan /* Instruction type */ 9731fb632bSRamuthevar Vadivel Murugan #define CQSPI_INST_TYPE_SINGLE 0 9831fb632bSRamuthevar Vadivel Murugan #define CQSPI_INST_TYPE_DUAL 1 9931fb632bSRamuthevar Vadivel Murugan #define CQSPI_INST_TYPE_QUAD 2 10031fb632bSRamuthevar Vadivel Murugan #define CQSPI_INST_TYPE_OCTAL 3 10131fb632bSRamuthevar Vadivel Murugan 10231fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_CLKS_PER_BYTE 8 10331fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_BYTES_MAX 4 10431fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_CLKS_MAX 31 10531fb632bSRamuthevar Vadivel Murugan 10631fb632bSRamuthevar Vadivel Murugan #define CQSPI_STIG_DATA_LEN_MAX 8 10731fb632bSRamuthevar Vadivel Murugan 10831fb632bSRamuthevar Vadivel Murugan /* Register map */ 10931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG 0x00 11031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0) 11131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7) 11231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9) 11331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 11431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_DMA_MASK BIT(15) 11531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_BAUD_LSB 19 116f453f293SPratyush Yadav #define CQSPI_REG_CONFIG_DTR_PROTO BIT(24) 117f453f293SPratyush Yadav #define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30) 11831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_IDLE_LSB 31 11931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF 12031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_BAUD_MASK 0xF 12131fb632bSRamuthevar Vadivel Murugan 12231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR 0x04 12331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 12431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 12531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 12631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 12731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 12831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 12931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 13031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 13131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 13231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F 13331fb632bSRamuthevar Vadivel Murugan 13431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR 0x08 13531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 13631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12 13731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16 13831fb632bSRamuthevar Vadivel Murugan 13931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY 0x0C 14031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSLCH_LSB 0 14131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TCHSH_LSB 8 14231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSD2D_LSB 16 14331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSHSL_LSB 24 14431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF 14531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF 14631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF 14731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF 14831fb632bSRamuthevar Vadivel Murugan 14931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE 0x10 15031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0 15131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_DELAY_LSB 1 15231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF 15331fb632bSRamuthevar Vadivel Murugan 15431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE 0x14 15531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_ADDRESS_LSB 0 15631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_PAGE_LSB 4 15731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_BLOCK_LSB 16 15831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF 15931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF 16031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F 16131fb632bSRamuthevar Vadivel Murugan 16231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SRAMPARTITION 0x18 16331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTTRIGGER 0x1C 16431fb632bSRamuthevar Vadivel Murugan 16531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA 0x20 16631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_SINGLE_LSB 0 16731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_BURST_LSB 8 16831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_SINGLE_MASK 0xFF 16931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_BURST_MASK 0xFF 17031fb632bSRamuthevar Vadivel Murugan 17131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_REMAP 0x24 17231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_MODE_BIT 0x28 17331fb632bSRamuthevar Vadivel Murugan 17431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL 0x2C 17531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 17631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 17731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF 17831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF 17931fb632bSRamuthevar Vadivel Murugan 180f453f293SPratyush Yadav #define CQSPI_REG_WR_COMPLETION_CTRL 0x38 181f453f293SPratyush Yadav #define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14) 182f453f293SPratyush Yadav 18331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQSTATUS 0x40 18431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQMASK 0x44 18531fb632bSRamuthevar Vadivel Murugan 18631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD 0x60 18731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0) 18831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1) 18931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5) 19031fb632bSRamuthevar Vadivel Murugan 19131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDWATERMARK 0x64 19231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 19331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDBYTES 0x6C 19431fb632bSRamuthevar Vadivel Murugan 19531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL 0x90 19631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0) 19731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1) 198888d517bSPratyush Yadav #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 19931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 20031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 20131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 20231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 20331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 20431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 20531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 20631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 20731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 20831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 209888d517bSPratyush Yadav #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F 21031fb632bSRamuthevar Vadivel Murugan 21131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR 0x70 21231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0) 21331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1) 21431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5) 21531fb632bSRamuthevar Vadivel Murugan 21631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRWATERMARK 0x74 21731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 21831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRBYTES 0x7C 21931fb632bSRamuthevar Vadivel Murugan 22031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDADDRESS 0x94 22131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDREADDATALOWER 0xA0 22231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDREADDATAUPPER 0xA4 22331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDWRITEDATALOWER 0xA8 22431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC 22531fb632bSRamuthevar Vadivel Murugan 226f453f293SPratyush Yadav #define CQSPI_REG_POLLING_STATUS 0xB0 227f453f293SPratyush Yadav #define CQSPI_REG_POLLING_STATUS_DUMMY_LSB 16 228f453f293SPratyush Yadav 229f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_LOWER 0xE0 230f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_READ_LSB 24 231f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_WRITE_LSB 16 232f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_STIG_LSB 0 233f453f293SPratyush Yadav 23431fb632bSRamuthevar Vadivel Murugan /* Interrupt status bits */ 23531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_MODE_ERR BIT(0) 23631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_UNDERFLOW BIT(1) 23731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_COMP BIT(2) 23831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3) 23931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4) 24031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5) 24131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_WATERMARK BIT(6) 24231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12) 24331fb632bSRamuthevar Vadivel Murugan 24431fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \ 24531fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_IND_SRAM_FULL | \ 24631fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_IND_COMP) 24731fb632bSRamuthevar Vadivel Murugan 24831fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \ 24931fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_WATERMARK | \ 25031fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_UNDERFLOW) 25131fb632bSRamuthevar Vadivel Murugan 25231fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_STATUS_MASK 0x1FFFF 25331fb632bSRamuthevar Vadivel Murugan 25431fb632bSRamuthevar Vadivel Murugan static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr) 25531fb632bSRamuthevar Vadivel Murugan { 25631fb632bSRamuthevar Vadivel Murugan u32 val; 25731fb632bSRamuthevar Vadivel Murugan 25831fb632bSRamuthevar Vadivel Murugan return readl_relaxed_poll_timeout(reg, val, 25931fb632bSRamuthevar Vadivel Murugan (((clr ? ~val : val) & mask) == mask), 26031fb632bSRamuthevar Vadivel Murugan 10, CQSPI_TIMEOUT_MS * 1000); 26131fb632bSRamuthevar Vadivel Murugan } 26231fb632bSRamuthevar Vadivel Murugan 26331fb632bSRamuthevar Vadivel Murugan static bool cqspi_is_idle(struct cqspi_st *cqspi) 26431fb632bSRamuthevar Vadivel Murugan { 26531fb632bSRamuthevar Vadivel Murugan u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 26631fb632bSRamuthevar Vadivel Murugan 26731890269SJay Fang return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB); 26831fb632bSRamuthevar Vadivel Murugan } 26931fb632bSRamuthevar Vadivel Murugan 27031fb632bSRamuthevar Vadivel Murugan static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi) 27131fb632bSRamuthevar Vadivel Murugan { 27231fb632bSRamuthevar Vadivel Murugan u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL); 27331fb632bSRamuthevar Vadivel Murugan 27431fb632bSRamuthevar Vadivel Murugan reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB; 27531fb632bSRamuthevar Vadivel Murugan return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK; 27631fb632bSRamuthevar Vadivel Murugan } 27731fb632bSRamuthevar Vadivel Murugan 27831fb632bSRamuthevar Vadivel Murugan static irqreturn_t cqspi_irq_handler(int this_irq, void *dev) 27931fb632bSRamuthevar Vadivel Murugan { 28031fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev; 28131fb632bSRamuthevar Vadivel Murugan unsigned int irq_status; 28231fb632bSRamuthevar Vadivel Murugan 28331fb632bSRamuthevar Vadivel Murugan /* Read interrupt status */ 28431fb632bSRamuthevar Vadivel Murugan irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS); 28531fb632bSRamuthevar Vadivel Murugan 28631fb632bSRamuthevar Vadivel Murugan /* Clear interrupt */ 28731fb632bSRamuthevar Vadivel Murugan writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS); 28831fb632bSRamuthevar Vadivel Murugan 28931fb632bSRamuthevar Vadivel Murugan irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR; 29031fb632bSRamuthevar Vadivel Murugan 29131fb632bSRamuthevar Vadivel Murugan if (irq_status) 29231fb632bSRamuthevar Vadivel Murugan complete(&cqspi->transfer_complete); 29331fb632bSRamuthevar Vadivel Murugan 29431fb632bSRamuthevar Vadivel Murugan return IRQ_HANDLED; 29531fb632bSRamuthevar Vadivel Murugan } 29631fb632bSRamuthevar Vadivel Murugan 29731fb632bSRamuthevar Vadivel Murugan static unsigned int cqspi_calc_rdreg(struct cqspi_flash_pdata *f_pdata) 29831fb632bSRamuthevar Vadivel Murugan { 29931fb632bSRamuthevar Vadivel Murugan u32 rdreg = 0; 30031fb632bSRamuthevar Vadivel Murugan 30131fb632bSRamuthevar Vadivel Murugan rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; 30231fb632bSRamuthevar Vadivel Murugan rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; 30331fb632bSRamuthevar Vadivel Murugan rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; 30431fb632bSRamuthevar Vadivel Murugan 30531fb632bSRamuthevar Vadivel Murugan return rdreg; 30631fb632bSRamuthevar Vadivel Murugan } 30731fb632bSRamuthevar Vadivel Murugan 308f453f293SPratyush Yadav static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op, bool dtr) 309888d517bSPratyush Yadav { 3100ccfd1baSYoshitaka Ikeda unsigned int dummy_clk; 311888d517bSPratyush Yadav 3120e85ee89SYoshitaka Ikeda if (!op->dummy.nbytes) 3130e85ee89SYoshitaka Ikeda return 0; 3140e85ee89SYoshitaka Ikeda 3157512eaf5SPratyush Yadav dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth); 316f453f293SPratyush Yadav if (dtr) 317f453f293SPratyush Yadav dummy_clk /= 2; 318888d517bSPratyush Yadav 319888d517bSPratyush Yadav return dummy_clk; 320888d517bSPratyush Yadav } 321888d517bSPratyush Yadav 322f453f293SPratyush Yadav static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata, 323f453f293SPratyush Yadav const struct spi_mem_op *op) 324f453f293SPratyush Yadav { 325f453f293SPratyush Yadav f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE; 326f453f293SPratyush Yadav f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE; 327f453f293SPratyush Yadav f_pdata->data_width = CQSPI_INST_TYPE_SINGLE; 328*0395be96SApurva Nandan 329*0395be96SApurva Nandan /* 330*0395be96SApurva Nandan * For an op to be DTR, cmd phase along with every other non-empty 331*0395be96SApurva Nandan * phase should have dtr field set to 1. If an op phase has zero 332*0395be96SApurva Nandan * nbytes, ignore its dtr field; otherwise, check its dtr field. 333*0395be96SApurva Nandan */ 334*0395be96SApurva Nandan f_pdata->dtr = op->cmd.dtr && 335*0395be96SApurva Nandan (!op->addr.nbytes || op->addr.dtr) && 336*0395be96SApurva Nandan (!op->data.nbytes || op->data.dtr); 337f453f293SPratyush Yadav 338f453f293SPratyush Yadav switch (op->data.buswidth) { 339f453f293SPratyush Yadav case 0: 340f453f293SPratyush Yadav break; 341f453f293SPratyush Yadav case 1: 342f453f293SPratyush Yadav f_pdata->data_width = CQSPI_INST_TYPE_SINGLE; 343f453f293SPratyush Yadav break; 344f453f293SPratyush Yadav case 2: 345f453f293SPratyush Yadav f_pdata->data_width = CQSPI_INST_TYPE_DUAL; 346f453f293SPratyush Yadav break; 347f453f293SPratyush Yadav case 4: 348f453f293SPratyush Yadav f_pdata->data_width = CQSPI_INST_TYPE_QUAD; 349f453f293SPratyush Yadav break; 350f453f293SPratyush Yadav case 8: 351f453f293SPratyush Yadav f_pdata->data_width = CQSPI_INST_TYPE_OCTAL; 352f453f293SPratyush Yadav break; 353f453f293SPratyush Yadav default: 354f453f293SPratyush Yadav return -EINVAL; 355f453f293SPratyush Yadav } 356f453f293SPratyush Yadav 357f453f293SPratyush Yadav /* Right now we only support 8-8-8 DTR mode. */ 358f453f293SPratyush Yadav if (f_pdata->dtr) { 359f453f293SPratyush Yadav switch (op->cmd.buswidth) { 360f453f293SPratyush Yadav case 0: 361f453f293SPratyush Yadav break; 362f453f293SPratyush Yadav case 8: 363f453f293SPratyush Yadav f_pdata->inst_width = CQSPI_INST_TYPE_OCTAL; 364f453f293SPratyush Yadav break; 365f453f293SPratyush Yadav default: 366f453f293SPratyush Yadav return -EINVAL; 367f453f293SPratyush Yadav } 368f453f293SPratyush Yadav 369f453f293SPratyush Yadav switch (op->addr.buswidth) { 370f453f293SPratyush Yadav case 0: 371f453f293SPratyush Yadav break; 372f453f293SPratyush Yadav case 8: 373f453f293SPratyush Yadav f_pdata->addr_width = CQSPI_INST_TYPE_OCTAL; 374f453f293SPratyush Yadav break; 375f453f293SPratyush Yadav default: 376f453f293SPratyush Yadav return -EINVAL; 377f453f293SPratyush Yadav } 378f453f293SPratyush Yadav 379f453f293SPratyush Yadav switch (op->data.buswidth) { 380f453f293SPratyush Yadav case 0: 381f453f293SPratyush Yadav break; 382f453f293SPratyush Yadav case 8: 383f453f293SPratyush Yadav f_pdata->data_width = CQSPI_INST_TYPE_OCTAL; 384f453f293SPratyush Yadav break; 385f453f293SPratyush Yadav default: 386f453f293SPratyush Yadav return -EINVAL; 387f453f293SPratyush Yadav } 388f453f293SPratyush Yadav } 389f453f293SPratyush Yadav 390f453f293SPratyush Yadav return 0; 391f453f293SPratyush Yadav } 392f453f293SPratyush Yadav 39331fb632bSRamuthevar Vadivel Murugan static int cqspi_wait_idle(struct cqspi_st *cqspi) 39431fb632bSRamuthevar Vadivel Murugan { 39531fb632bSRamuthevar Vadivel Murugan const unsigned int poll_idle_retry = 3; 39631fb632bSRamuthevar Vadivel Murugan unsigned int count = 0; 39731fb632bSRamuthevar Vadivel Murugan unsigned long timeout; 39831fb632bSRamuthevar Vadivel Murugan 39931fb632bSRamuthevar Vadivel Murugan timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS); 40031fb632bSRamuthevar Vadivel Murugan while (1) { 40131fb632bSRamuthevar Vadivel Murugan /* 40231fb632bSRamuthevar Vadivel Murugan * Read few times in succession to ensure the controller 40331fb632bSRamuthevar Vadivel Murugan * is indeed idle, that is, the bit does not transition 40431fb632bSRamuthevar Vadivel Murugan * low again. 40531fb632bSRamuthevar Vadivel Murugan */ 40631fb632bSRamuthevar Vadivel Murugan if (cqspi_is_idle(cqspi)) 40731fb632bSRamuthevar Vadivel Murugan count++; 40831fb632bSRamuthevar Vadivel Murugan else 40931fb632bSRamuthevar Vadivel Murugan count = 0; 41031fb632bSRamuthevar Vadivel Murugan 41131fb632bSRamuthevar Vadivel Murugan if (count >= poll_idle_retry) 41231fb632bSRamuthevar Vadivel Murugan return 0; 41331fb632bSRamuthevar Vadivel Murugan 41431fb632bSRamuthevar Vadivel Murugan if (time_after(jiffies, timeout)) { 41531fb632bSRamuthevar Vadivel Murugan /* Timeout, in busy mode. */ 41631fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 41731fb632bSRamuthevar Vadivel Murugan "QSPI is still busy after %dms timeout.\n", 41831fb632bSRamuthevar Vadivel Murugan CQSPI_TIMEOUT_MS); 41931fb632bSRamuthevar Vadivel Murugan return -ETIMEDOUT; 42031fb632bSRamuthevar Vadivel Murugan } 42131fb632bSRamuthevar Vadivel Murugan 42231fb632bSRamuthevar Vadivel Murugan cpu_relax(); 42331fb632bSRamuthevar Vadivel Murugan } 42431fb632bSRamuthevar Vadivel Murugan } 42531fb632bSRamuthevar Vadivel Murugan 42631fb632bSRamuthevar Vadivel Murugan static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg) 42731fb632bSRamuthevar Vadivel Murugan { 42831fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 42931fb632bSRamuthevar Vadivel Murugan int ret; 43031fb632bSRamuthevar Vadivel Murugan 43131fb632bSRamuthevar Vadivel Murugan /* Write the CMDCTRL without start execution. */ 43231fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CMDCTRL); 43331fb632bSRamuthevar Vadivel Murugan /* Start execute */ 43431fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK; 43531fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CMDCTRL); 43631fb632bSRamuthevar Vadivel Murugan 43731fb632bSRamuthevar Vadivel Murugan /* Polling for completion. */ 43831fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL, 43931fb632bSRamuthevar Vadivel Murugan CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1); 44031fb632bSRamuthevar Vadivel Murugan if (ret) { 44131fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 44231fb632bSRamuthevar Vadivel Murugan "Flash command execution timed out.\n"); 44331fb632bSRamuthevar Vadivel Murugan return ret; 44431fb632bSRamuthevar Vadivel Murugan } 44531fb632bSRamuthevar Vadivel Murugan 44631fb632bSRamuthevar Vadivel Murugan /* Polling QSPI idle status. */ 44731fb632bSRamuthevar Vadivel Murugan return cqspi_wait_idle(cqspi); 44831fb632bSRamuthevar Vadivel Murugan } 44931fb632bSRamuthevar Vadivel Murugan 450f453f293SPratyush Yadav static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata, 451f453f293SPratyush Yadav const struct spi_mem_op *op, 452f453f293SPratyush Yadav unsigned int shift) 453f453f293SPratyush Yadav { 454f453f293SPratyush Yadav struct cqspi_st *cqspi = f_pdata->cqspi; 455f453f293SPratyush Yadav void __iomem *reg_base = cqspi->iobase; 456f453f293SPratyush Yadav unsigned int reg; 457f453f293SPratyush Yadav u8 ext; 458f453f293SPratyush Yadav 459f453f293SPratyush Yadav if (op->cmd.nbytes != 2) 460f453f293SPratyush Yadav return -EINVAL; 461f453f293SPratyush Yadav 462f453f293SPratyush Yadav /* Opcode extension is the LSB. */ 463f453f293SPratyush Yadav ext = op->cmd.opcode & 0xff; 464f453f293SPratyush Yadav 465f453f293SPratyush Yadav reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER); 466f453f293SPratyush Yadav reg &= ~(0xff << shift); 467f453f293SPratyush Yadav reg |= ext << shift; 468f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER); 469f453f293SPratyush Yadav 470f453f293SPratyush Yadav return 0; 471f453f293SPratyush Yadav } 472f453f293SPratyush Yadav 473f453f293SPratyush Yadav static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata, 474f453f293SPratyush Yadav const struct spi_mem_op *op, unsigned int shift, 475f453f293SPratyush Yadav bool enable) 476f453f293SPratyush Yadav { 477f453f293SPratyush Yadav struct cqspi_st *cqspi = f_pdata->cqspi; 478f453f293SPratyush Yadav void __iomem *reg_base = cqspi->iobase; 479f453f293SPratyush Yadav unsigned int reg; 480f453f293SPratyush Yadav int ret; 481f453f293SPratyush Yadav 482f453f293SPratyush Yadav reg = readl(reg_base + CQSPI_REG_CONFIG); 483f453f293SPratyush Yadav 484f453f293SPratyush Yadav /* 485f453f293SPratyush Yadav * We enable dual byte opcode here. The callers have to set up the 486f453f293SPratyush Yadav * extension opcode based on which type of operation it is. 487f453f293SPratyush Yadav */ 488f453f293SPratyush Yadav if (enable) { 489f453f293SPratyush Yadav reg |= CQSPI_REG_CONFIG_DTR_PROTO; 490f453f293SPratyush Yadav reg |= CQSPI_REG_CONFIG_DUAL_OPCODE; 491f453f293SPratyush Yadav 492f453f293SPratyush Yadav /* Set up command opcode extension. */ 493f453f293SPratyush Yadav ret = cqspi_setup_opcode_ext(f_pdata, op, shift); 494f453f293SPratyush Yadav if (ret) 495f453f293SPratyush Yadav return ret; 496f453f293SPratyush Yadav } else { 497f453f293SPratyush Yadav reg &= ~CQSPI_REG_CONFIG_DTR_PROTO; 498f453f293SPratyush Yadav reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE; 499f453f293SPratyush Yadav } 500f453f293SPratyush Yadav 501f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_CONFIG); 502f453f293SPratyush Yadav 503f453f293SPratyush Yadav return cqspi_wait_idle(cqspi); 504f453f293SPratyush Yadav } 505f453f293SPratyush Yadav 50631fb632bSRamuthevar Vadivel Murugan static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, 50731fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 50831fb632bSRamuthevar Vadivel Murugan { 50931fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 51031fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 51131fb632bSRamuthevar Vadivel Murugan u8 *rxbuf = op->data.buf.in; 512f453f293SPratyush Yadav u8 opcode; 51331fb632bSRamuthevar Vadivel Murugan size_t n_rx = op->data.nbytes; 51431fb632bSRamuthevar Vadivel Murugan unsigned int rdreg; 51531fb632bSRamuthevar Vadivel Murugan unsigned int reg; 516888d517bSPratyush Yadav unsigned int dummy_clk; 51731fb632bSRamuthevar Vadivel Murugan size_t read_len; 51831fb632bSRamuthevar Vadivel Murugan int status; 51931fb632bSRamuthevar Vadivel Murugan 520f453f293SPratyush Yadav status = cqspi_set_protocol(f_pdata, op); 521f453f293SPratyush Yadav if (status) 522f453f293SPratyush Yadav return status; 523f453f293SPratyush Yadav 524f453f293SPratyush Yadav status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB, 525f453f293SPratyush Yadav f_pdata->dtr); 526f453f293SPratyush Yadav if (status) 527f453f293SPratyush Yadav return status; 528f453f293SPratyush Yadav 52931fb632bSRamuthevar Vadivel Murugan if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) { 53031fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 53131fb632bSRamuthevar Vadivel Murugan "Invalid input argument, len %zu rxbuf 0x%p\n", 53231fb632bSRamuthevar Vadivel Murugan n_rx, rxbuf); 53331fb632bSRamuthevar Vadivel Murugan return -EINVAL; 53431fb632bSRamuthevar Vadivel Murugan } 53531fb632bSRamuthevar Vadivel Murugan 536f453f293SPratyush Yadav if (f_pdata->dtr) 537f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 538f453f293SPratyush Yadav else 539f453f293SPratyush Yadav opcode = op->cmd.opcode; 540f453f293SPratyush Yadav 54131fb632bSRamuthevar Vadivel Murugan reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 54231fb632bSRamuthevar Vadivel Murugan 54331fb632bSRamuthevar Vadivel Murugan rdreg = cqspi_calc_rdreg(f_pdata); 54431fb632bSRamuthevar Vadivel Murugan writel(rdreg, reg_base + CQSPI_REG_RD_INSTR); 54531fb632bSRamuthevar Vadivel Murugan 546f453f293SPratyush Yadav dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr); 547888d517bSPratyush Yadav if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 548888d517bSPratyush Yadav return -EOPNOTSUPP; 549888d517bSPratyush Yadav 550888d517bSPratyush Yadav if (dummy_clk) 551888d517bSPratyush Yadav reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK) 552888d517bSPratyush Yadav << CQSPI_REG_CMDCTRL_DUMMY_LSB; 553888d517bSPratyush Yadav 55431fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); 55531fb632bSRamuthevar Vadivel Murugan 55631fb632bSRamuthevar Vadivel Murugan /* 0 means 1 byte. */ 55731fb632bSRamuthevar Vadivel Murugan reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) 55831fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); 55931fb632bSRamuthevar Vadivel Murugan status = cqspi_exec_flash_cmd(cqspi, reg); 56031fb632bSRamuthevar Vadivel Murugan if (status) 56131fb632bSRamuthevar Vadivel Murugan return status; 56231fb632bSRamuthevar Vadivel Murugan 56331fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER); 56431fb632bSRamuthevar Vadivel Murugan 56531fb632bSRamuthevar Vadivel Murugan /* Put the read value into rx_buf */ 56631fb632bSRamuthevar Vadivel Murugan read_len = (n_rx > 4) ? 4 : n_rx; 56731fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, ®, read_len); 56831fb632bSRamuthevar Vadivel Murugan rxbuf += read_len; 56931fb632bSRamuthevar Vadivel Murugan 57031fb632bSRamuthevar Vadivel Murugan if (n_rx > 4) { 57131fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER); 57231fb632bSRamuthevar Vadivel Murugan 57331fb632bSRamuthevar Vadivel Murugan read_len = n_rx - read_len; 57431fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, ®, read_len); 57531fb632bSRamuthevar Vadivel Murugan } 57631fb632bSRamuthevar Vadivel Murugan 57731fb632bSRamuthevar Vadivel Murugan return 0; 57831fb632bSRamuthevar Vadivel Murugan } 57931fb632bSRamuthevar Vadivel Murugan 58031fb632bSRamuthevar Vadivel Murugan static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata, 58131fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 58231fb632bSRamuthevar Vadivel Murugan { 58331fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 58431fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 585f453f293SPratyush Yadav u8 opcode; 58631fb632bSRamuthevar Vadivel Murugan const u8 *txbuf = op->data.buf.out; 58731fb632bSRamuthevar Vadivel Murugan size_t n_tx = op->data.nbytes; 58831fb632bSRamuthevar Vadivel Murugan unsigned int reg; 58931fb632bSRamuthevar Vadivel Murugan unsigned int data; 59031fb632bSRamuthevar Vadivel Murugan size_t write_len; 591f453f293SPratyush Yadav int ret; 592f453f293SPratyush Yadav 593f453f293SPratyush Yadav ret = cqspi_set_protocol(f_pdata, op); 594f453f293SPratyush Yadav if (ret) 595f453f293SPratyush Yadav return ret; 596f453f293SPratyush Yadav 597f453f293SPratyush Yadav ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB, 598f453f293SPratyush Yadav f_pdata->dtr); 599f453f293SPratyush Yadav if (ret) 600f453f293SPratyush Yadav return ret; 60131fb632bSRamuthevar Vadivel Murugan 60231fb632bSRamuthevar Vadivel Murugan if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) { 60331fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev, 60431fb632bSRamuthevar Vadivel Murugan "Invalid input argument, cmdlen %zu txbuf 0x%p\n", 60531fb632bSRamuthevar Vadivel Murugan n_tx, txbuf); 60631fb632bSRamuthevar Vadivel Murugan return -EINVAL; 60731fb632bSRamuthevar Vadivel Murugan } 60831fb632bSRamuthevar Vadivel Murugan 609f453f293SPratyush Yadav reg = cqspi_calc_rdreg(f_pdata); 610f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_RD_INSTR); 611f453f293SPratyush Yadav 612f453f293SPratyush Yadav if (f_pdata->dtr) 613f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 614f453f293SPratyush Yadav else 615f453f293SPratyush Yadav opcode = op->cmd.opcode; 616f453f293SPratyush Yadav 61731fb632bSRamuthevar Vadivel Murugan reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 61831fb632bSRamuthevar Vadivel Murugan 61931fb632bSRamuthevar Vadivel Murugan if (op->addr.nbytes) { 62031fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 62131fb632bSRamuthevar Vadivel Murugan reg |= ((op->addr.nbytes - 1) & 62231fb632bSRamuthevar Vadivel Murugan CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) 62331fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; 62431fb632bSRamuthevar Vadivel Murugan 62531fb632bSRamuthevar Vadivel Murugan writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); 62631fb632bSRamuthevar Vadivel Murugan } 62731fb632bSRamuthevar Vadivel Murugan 62831fb632bSRamuthevar Vadivel Murugan if (n_tx) { 62931fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB); 63031fb632bSRamuthevar Vadivel Murugan reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) 63131fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_WR_BYTES_LSB; 63231fb632bSRamuthevar Vadivel Murugan data = 0; 63331fb632bSRamuthevar Vadivel Murugan write_len = (n_tx > 4) ? 4 : n_tx; 63431fb632bSRamuthevar Vadivel Murugan memcpy(&data, txbuf, write_len); 63531fb632bSRamuthevar Vadivel Murugan txbuf += write_len; 63631fb632bSRamuthevar Vadivel Murugan writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER); 63731fb632bSRamuthevar Vadivel Murugan 63831fb632bSRamuthevar Vadivel Murugan if (n_tx > 4) { 63931fb632bSRamuthevar Vadivel Murugan data = 0; 64031fb632bSRamuthevar Vadivel Murugan write_len = n_tx - 4; 64131fb632bSRamuthevar Vadivel Murugan memcpy(&data, txbuf, write_len); 64231fb632bSRamuthevar Vadivel Murugan writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER); 64331fb632bSRamuthevar Vadivel Murugan } 64431fb632bSRamuthevar Vadivel Murugan } 64531fb632bSRamuthevar Vadivel Murugan 64631fb632bSRamuthevar Vadivel Murugan return cqspi_exec_flash_cmd(cqspi, reg); 64731fb632bSRamuthevar Vadivel Murugan } 64831fb632bSRamuthevar Vadivel Murugan 64931fb632bSRamuthevar Vadivel Murugan static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata, 65031fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 65131fb632bSRamuthevar Vadivel Murugan { 65231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 65331fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 65431fb632bSRamuthevar Vadivel Murugan unsigned int dummy_clk = 0; 65531fb632bSRamuthevar Vadivel Murugan unsigned int reg; 656f453f293SPratyush Yadav int ret; 657f453f293SPratyush Yadav u8 opcode; 65831fb632bSRamuthevar Vadivel Murugan 659f453f293SPratyush Yadav ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB, 660f453f293SPratyush Yadav f_pdata->dtr); 661f453f293SPratyush Yadav if (ret) 662f453f293SPratyush Yadav return ret; 663f453f293SPratyush Yadav 664f453f293SPratyush Yadav if (f_pdata->dtr) 665f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 666f453f293SPratyush Yadav else 667f453f293SPratyush Yadav opcode = op->cmd.opcode; 668f453f293SPratyush Yadav 669f453f293SPratyush Yadav reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB; 67031fb632bSRamuthevar Vadivel Murugan reg |= cqspi_calc_rdreg(f_pdata); 67131fb632bSRamuthevar Vadivel Murugan 67231fb632bSRamuthevar Vadivel Murugan /* Setup dummy clock cycles */ 673f453f293SPratyush Yadav dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr); 674888d517bSPratyush Yadav 67531fb632bSRamuthevar Vadivel Murugan if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 676ceeda328SPratyush Yadav return -EOPNOTSUPP; 67731fb632bSRamuthevar Vadivel Murugan 67831fb632bSRamuthevar Vadivel Murugan if (dummy_clk) 67931fb632bSRamuthevar Vadivel Murugan reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK) 68031fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_RD_INSTR_DUMMY_LSB; 68131fb632bSRamuthevar Vadivel Murugan 68231fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_RD_INSTR); 68331fb632bSRamuthevar Vadivel Murugan 68431fb632bSRamuthevar Vadivel Murugan /* Set address width */ 68531fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_SIZE); 68631fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 68731fb632bSRamuthevar Vadivel Murugan reg |= (op->addr.nbytes - 1); 68831fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_SIZE); 68931fb632bSRamuthevar Vadivel Murugan return 0; 69031fb632bSRamuthevar Vadivel Murugan } 69131fb632bSRamuthevar Vadivel Murugan 69231fb632bSRamuthevar Vadivel Murugan static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, 69331fb632bSRamuthevar Vadivel Murugan u8 *rxbuf, loff_t from_addr, 69431fb632bSRamuthevar Vadivel Murugan const size_t n_rx) 69531fb632bSRamuthevar Vadivel Murugan { 69631fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 69731fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 69831fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 69931fb632bSRamuthevar Vadivel Murugan void __iomem *ahb_base = cqspi->ahb_base; 70031fb632bSRamuthevar Vadivel Murugan unsigned int remaining = n_rx; 70131fb632bSRamuthevar Vadivel Murugan unsigned int mod_bytes = n_rx % 4; 70231fb632bSRamuthevar Vadivel Murugan unsigned int bytes_to_read = 0; 70331fb632bSRamuthevar Vadivel Murugan u8 *rxbuf_end = rxbuf + n_rx; 70431fb632bSRamuthevar Vadivel Murugan int ret = 0; 70531fb632bSRamuthevar Vadivel Murugan 70631fb632bSRamuthevar Vadivel Murugan writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 70731fb632bSRamuthevar Vadivel Murugan writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES); 70831fb632bSRamuthevar Vadivel Murugan 70931fb632bSRamuthevar Vadivel Murugan /* Clear all interrupts. */ 71031fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 71131fb632bSRamuthevar Vadivel Murugan 71231fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK); 71331fb632bSRamuthevar Vadivel Murugan 71431fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 71531fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTRD_START_MASK, 71631fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTRD); 71731fb632bSRamuthevar Vadivel Murugan 71831fb632bSRamuthevar Vadivel Murugan while (remaining > 0) { 71931fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->transfer_complete, 72031fb632bSRamuthevar Vadivel Murugan msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) 72131fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 72231fb632bSRamuthevar Vadivel Murugan 72331fb632bSRamuthevar Vadivel Murugan bytes_to_read = cqspi_get_rd_sram_level(cqspi); 72431fb632bSRamuthevar Vadivel Murugan 72531fb632bSRamuthevar Vadivel Murugan if (ret && bytes_to_read == 0) { 72631fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect read timeout, no bytes\n"); 72731fb632bSRamuthevar Vadivel Murugan goto failrd; 72831fb632bSRamuthevar Vadivel Murugan } 72931fb632bSRamuthevar Vadivel Murugan 73031fb632bSRamuthevar Vadivel Murugan while (bytes_to_read != 0) { 73131fb632bSRamuthevar Vadivel Murugan unsigned int word_remain = round_down(remaining, 4); 73231fb632bSRamuthevar Vadivel Murugan 73331fb632bSRamuthevar Vadivel Murugan bytes_to_read *= cqspi->fifo_width; 73431fb632bSRamuthevar Vadivel Murugan bytes_to_read = bytes_to_read > remaining ? 73531fb632bSRamuthevar Vadivel Murugan remaining : bytes_to_read; 73631fb632bSRamuthevar Vadivel Murugan bytes_to_read = round_down(bytes_to_read, 4); 73731fb632bSRamuthevar Vadivel Murugan /* Read 4 byte word chunks then single bytes */ 73831fb632bSRamuthevar Vadivel Murugan if (bytes_to_read) { 73931fb632bSRamuthevar Vadivel Murugan ioread32_rep(ahb_base, rxbuf, 74031fb632bSRamuthevar Vadivel Murugan (bytes_to_read / 4)); 74131fb632bSRamuthevar Vadivel Murugan } else if (!word_remain && mod_bytes) { 74231fb632bSRamuthevar Vadivel Murugan unsigned int temp = ioread32(ahb_base); 74331fb632bSRamuthevar Vadivel Murugan 74431fb632bSRamuthevar Vadivel Murugan bytes_to_read = mod_bytes; 74531fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, &temp, min((unsigned int) 74631fb632bSRamuthevar Vadivel Murugan (rxbuf_end - rxbuf), 74731fb632bSRamuthevar Vadivel Murugan bytes_to_read)); 74831fb632bSRamuthevar Vadivel Murugan } 74931fb632bSRamuthevar Vadivel Murugan rxbuf += bytes_to_read; 75031fb632bSRamuthevar Vadivel Murugan remaining -= bytes_to_read; 75131fb632bSRamuthevar Vadivel Murugan bytes_to_read = cqspi_get_rd_sram_level(cqspi); 75231fb632bSRamuthevar Vadivel Murugan } 75331fb632bSRamuthevar Vadivel Murugan 75431fb632bSRamuthevar Vadivel Murugan if (remaining > 0) 75531fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 75631fb632bSRamuthevar Vadivel Murugan } 75731fb632bSRamuthevar Vadivel Murugan 75831fb632bSRamuthevar Vadivel Murugan /* Check indirect done status */ 75931fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD, 76031fb632bSRamuthevar Vadivel Murugan CQSPI_REG_INDIRECTRD_DONE_MASK, 0); 76131fb632bSRamuthevar Vadivel Murugan if (ret) { 76231fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect read completion error (%i)\n", ret); 76331fb632bSRamuthevar Vadivel Murugan goto failrd; 76431fb632bSRamuthevar Vadivel Murugan } 76531fb632bSRamuthevar Vadivel Murugan 76631fb632bSRamuthevar Vadivel Murugan /* Disable interrupt */ 76731fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 76831fb632bSRamuthevar Vadivel Murugan 76931fb632bSRamuthevar Vadivel Murugan /* Clear indirect completion status */ 77031fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD); 77131fb632bSRamuthevar Vadivel Murugan 77231fb632bSRamuthevar Vadivel Murugan return 0; 77331fb632bSRamuthevar Vadivel Murugan 77431fb632bSRamuthevar Vadivel Murugan failrd: 77531fb632bSRamuthevar Vadivel Murugan /* Disable interrupt */ 77631fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 77731fb632bSRamuthevar Vadivel Murugan 77831fb632bSRamuthevar Vadivel Murugan /* Cancel the indirect read */ 77931fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 78031fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTRD); 78131fb632bSRamuthevar Vadivel Murugan return ret; 78231fb632bSRamuthevar Vadivel Murugan } 78331fb632bSRamuthevar Vadivel Murugan 78431fb632bSRamuthevar Vadivel Murugan static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata, 78531fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 78631fb632bSRamuthevar Vadivel Murugan { 78731fb632bSRamuthevar Vadivel Murugan unsigned int reg; 788f453f293SPratyush Yadav int ret; 78931fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 79031fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 791f453f293SPratyush Yadav u8 opcode; 792f453f293SPratyush Yadav 793f453f293SPratyush Yadav ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB, 794f453f293SPratyush Yadav f_pdata->dtr); 795f453f293SPratyush Yadav if (ret) 796f453f293SPratyush Yadav return ret; 797f453f293SPratyush Yadav 798f453f293SPratyush Yadav if (f_pdata->dtr) 799f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8; 800f453f293SPratyush Yadav else 801f453f293SPratyush Yadav opcode = op->cmd.opcode; 80231fb632bSRamuthevar Vadivel Murugan 80331fb632bSRamuthevar Vadivel Murugan /* Set opcode. */ 804f453f293SPratyush Yadav reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; 805f453f293SPratyush Yadav reg |= f_pdata->data_width << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; 806f453f293SPratyush Yadav reg |= f_pdata->addr_width << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; 80731fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_WR_INSTR); 80831fb632bSRamuthevar Vadivel Murugan reg = cqspi_calc_rdreg(f_pdata); 80931fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_RD_INSTR); 81031fb632bSRamuthevar Vadivel Murugan 811f453f293SPratyush Yadav /* 8129cb2ff11SApurva Nandan * SPI NAND flashes require the address of the status register to be 8139cb2ff11SApurva Nandan * passed in the Read SR command. Also, some SPI NOR flashes like the 8149cb2ff11SApurva Nandan * cypress Semper flash expect a 4-byte dummy address in the Read SR 8159cb2ff11SApurva Nandan * command in DTR mode. 8169cb2ff11SApurva Nandan * 8179cb2ff11SApurva Nandan * But this controller does not support address phase in the Read SR 8189cb2ff11SApurva Nandan * command when doing auto-HW polling. So, disable write completion 8199cb2ff11SApurva Nandan * polling on the controller's side. spinand and spi-nor will take 8209cb2ff11SApurva Nandan * care of polling the status register. 821f453f293SPratyush Yadav */ 822f453f293SPratyush Yadav reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL); 823f453f293SPratyush Yadav reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL; 824f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL); 825f453f293SPratyush Yadav 82631fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_SIZE); 82731fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 82831fb632bSRamuthevar Vadivel Murugan reg |= (op->addr.nbytes - 1); 82931fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_SIZE); 83031fb632bSRamuthevar Vadivel Murugan return 0; 83131fb632bSRamuthevar Vadivel Murugan } 83231fb632bSRamuthevar Vadivel Murugan 83331fb632bSRamuthevar Vadivel Murugan static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, 83431fb632bSRamuthevar Vadivel Murugan loff_t to_addr, const u8 *txbuf, 83531fb632bSRamuthevar Vadivel Murugan const size_t n_tx) 83631fb632bSRamuthevar Vadivel Murugan { 83731fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 83831fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 83931fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 84031fb632bSRamuthevar Vadivel Murugan unsigned int remaining = n_tx; 84131fb632bSRamuthevar Vadivel Murugan unsigned int write_bytes; 84231fb632bSRamuthevar Vadivel Murugan int ret; 84331fb632bSRamuthevar Vadivel Murugan 84431fb632bSRamuthevar Vadivel Murugan writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR); 84531fb632bSRamuthevar Vadivel Murugan writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES); 84631fb632bSRamuthevar Vadivel Murugan 84731fb632bSRamuthevar Vadivel Murugan /* Clear all interrupts. */ 84831fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 84931fb632bSRamuthevar Vadivel Murugan 85031fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK); 85131fb632bSRamuthevar Vadivel Murugan 85231fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 85331fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_START_MASK, 85431fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTWR); 85531fb632bSRamuthevar Vadivel Murugan /* 85631fb632bSRamuthevar Vadivel Murugan * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access 85731fb632bSRamuthevar Vadivel Murugan * Controller programming sequence, couple of cycles of 85831fb632bSRamuthevar Vadivel Murugan * QSPI_REF_CLK delay is required for the above bit to 85931fb632bSRamuthevar Vadivel Murugan * be internally synchronized by the QSPI module. Provide 5 86031fb632bSRamuthevar Vadivel Murugan * cycles of delay. 86131fb632bSRamuthevar Vadivel Murugan */ 86231fb632bSRamuthevar Vadivel Murugan if (cqspi->wr_delay) 86331fb632bSRamuthevar Vadivel Murugan ndelay(cqspi->wr_delay); 86431fb632bSRamuthevar Vadivel Murugan 86531fb632bSRamuthevar Vadivel Murugan while (remaining > 0) { 86631fb632bSRamuthevar Vadivel Murugan size_t write_words, mod_bytes; 86731fb632bSRamuthevar Vadivel Murugan 86831fb632bSRamuthevar Vadivel Murugan write_bytes = remaining; 86931fb632bSRamuthevar Vadivel Murugan write_words = write_bytes / 4; 87031fb632bSRamuthevar Vadivel Murugan mod_bytes = write_bytes % 4; 87131fb632bSRamuthevar Vadivel Murugan /* Write 4 bytes at a time then single bytes. */ 87231fb632bSRamuthevar Vadivel Murugan if (write_words) { 87331fb632bSRamuthevar Vadivel Murugan iowrite32_rep(cqspi->ahb_base, txbuf, write_words); 87431fb632bSRamuthevar Vadivel Murugan txbuf += (write_words * 4); 87531fb632bSRamuthevar Vadivel Murugan } 87631fb632bSRamuthevar Vadivel Murugan if (mod_bytes) { 87731fb632bSRamuthevar Vadivel Murugan unsigned int temp = 0xFFFFFFFF; 87831fb632bSRamuthevar Vadivel Murugan 87931fb632bSRamuthevar Vadivel Murugan memcpy(&temp, txbuf, mod_bytes); 88031fb632bSRamuthevar Vadivel Murugan iowrite32(temp, cqspi->ahb_base); 88131fb632bSRamuthevar Vadivel Murugan txbuf += mod_bytes; 88231fb632bSRamuthevar Vadivel Murugan } 88331fb632bSRamuthevar Vadivel Murugan 88431fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->transfer_complete, 88531fb632bSRamuthevar Vadivel Murugan msecs_to_jiffies(CQSPI_TIMEOUT_MS))) { 88631fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect write timeout\n"); 88731fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 88831fb632bSRamuthevar Vadivel Murugan goto failwr; 88931fb632bSRamuthevar Vadivel Murugan } 89031fb632bSRamuthevar Vadivel Murugan 89131fb632bSRamuthevar Vadivel Murugan remaining -= write_bytes; 89231fb632bSRamuthevar Vadivel Murugan 89331fb632bSRamuthevar Vadivel Murugan if (remaining > 0) 89431fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete); 89531fb632bSRamuthevar Vadivel Murugan } 89631fb632bSRamuthevar Vadivel Murugan 89731fb632bSRamuthevar Vadivel Murugan /* Check indirect done status */ 89831fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR, 89931fb632bSRamuthevar Vadivel Murugan CQSPI_REG_INDIRECTWR_DONE_MASK, 0); 90031fb632bSRamuthevar Vadivel Murugan if (ret) { 90131fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect write completion error (%i)\n", ret); 90231fb632bSRamuthevar Vadivel Murugan goto failwr; 90331fb632bSRamuthevar Vadivel Murugan } 90431fb632bSRamuthevar Vadivel Murugan 90531fb632bSRamuthevar Vadivel Murugan /* Disable interrupt. */ 90631fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 90731fb632bSRamuthevar Vadivel Murugan 90831fb632bSRamuthevar Vadivel Murugan /* Clear indirect completion status */ 90931fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR); 91031fb632bSRamuthevar Vadivel Murugan 91131fb632bSRamuthevar Vadivel Murugan cqspi_wait_idle(cqspi); 91231fb632bSRamuthevar Vadivel Murugan 91331fb632bSRamuthevar Vadivel Murugan return 0; 91431fb632bSRamuthevar Vadivel Murugan 91531fb632bSRamuthevar Vadivel Murugan failwr: 91631fb632bSRamuthevar Vadivel Murugan /* Disable interrupt. */ 91731fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK); 91831fb632bSRamuthevar Vadivel Murugan 91931fb632bSRamuthevar Vadivel Murugan /* Cancel the indirect write */ 92031fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 92131fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTWR); 92231fb632bSRamuthevar Vadivel Murugan return ret; 92331fb632bSRamuthevar Vadivel Murugan } 92431fb632bSRamuthevar Vadivel Murugan 92531fb632bSRamuthevar Vadivel Murugan static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata) 92631fb632bSRamuthevar Vadivel Murugan { 92731fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 92831fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 92931fb632bSRamuthevar Vadivel Murugan unsigned int chip_select = f_pdata->cs; 93031fb632bSRamuthevar Vadivel Murugan unsigned int reg; 93131fb632bSRamuthevar Vadivel Murugan 93231fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG); 93331fb632bSRamuthevar Vadivel Murugan if (cqspi->is_decoded_cs) { 93431fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CONFIG_DECODE_MASK; 93531fb632bSRamuthevar Vadivel Murugan } else { 93631fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; 93731fb632bSRamuthevar Vadivel Murugan 93831fb632bSRamuthevar Vadivel Murugan /* Convert CS if without decoder. 93931fb632bSRamuthevar Vadivel Murugan * CS0 to 4b'1110 94031fb632bSRamuthevar Vadivel Murugan * CS1 to 4b'1101 94131fb632bSRamuthevar Vadivel Murugan * CS2 to 4b'1011 94231fb632bSRamuthevar Vadivel Murugan * CS3 to 4b'0111 94331fb632bSRamuthevar Vadivel Murugan */ 94431fb632bSRamuthevar Vadivel Murugan chip_select = 0xF & ~(1 << chip_select); 94531fb632bSRamuthevar Vadivel Murugan } 94631fb632bSRamuthevar Vadivel Murugan 94731fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK 94831fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CONFIG_CHIPSELECT_LSB); 94931fb632bSRamuthevar Vadivel Murugan reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK) 95031fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CONFIG_CHIPSELECT_LSB; 95131fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG); 95231fb632bSRamuthevar Vadivel Murugan } 95331fb632bSRamuthevar Vadivel Murugan 95431fb632bSRamuthevar Vadivel Murugan static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz, 95531fb632bSRamuthevar Vadivel Murugan const unsigned int ns_val) 95631fb632bSRamuthevar Vadivel Murugan { 95731fb632bSRamuthevar Vadivel Murugan unsigned int ticks; 95831fb632bSRamuthevar Vadivel Murugan 95931fb632bSRamuthevar Vadivel Murugan ticks = ref_clk_hz / 1000; /* kHz */ 96031fb632bSRamuthevar Vadivel Murugan ticks = DIV_ROUND_UP(ticks * ns_val, 1000000); 96131fb632bSRamuthevar Vadivel Murugan 96231fb632bSRamuthevar Vadivel Murugan return ticks; 96331fb632bSRamuthevar Vadivel Murugan } 96431fb632bSRamuthevar Vadivel Murugan 96531fb632bSRamuthevar Vadivel Murugan static void cqspi_delay(struct cqspi_flash_pdata *f_pdata) 96631fb632bSRamuthevar Vadivel Murugan { 96731fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 96831fb632bSRamuthevar Vadivel Murugan void __iomem *iobase = cqspi->iobase; 96931fb632bSRamuthevar Vadivel Murugan const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 97031fb632bSRamuthevar Vadivel Murugan unsigned int tshsl, tchsh, tslch, tsd2d; 97131fb632bSRamuthevar Vadivel Murugan unsigned int reg; 97231fb632bSRamuthevar Vadivel Murugan unsigned int tsclk; 97331fb632bSRamuthevar Vadivel Murugan 97431fb632bSRamuthevar Vadivel Murugan /* calculate the number of ref ticks for one sclk tick */ 97531fb632bSRamuthevar Vadivel Murugan tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk); 97631fb632bSRamuthevar Vadivel Murugan 97731fb632bSRamuthevar Vadivel Murugan tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns); 97831fb632bSRamuthevar Vadivel Murugan /* this particular value must be at least one sclk */ 97931fb632bSRamuthevar Vadivel Murugan if (tshsl < tsclk) 98031fb632bSRamuthevar Vadivel Murugan tshsl = tsclk; 98131fb632bSRamuthevar Vadivel Murugan 98231fb632bSRamuthevar Vadivel Murugan tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns); 98331fb632bSRamuthevar Vadivel Murugan tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns); 98431fb632bSRamuthevar Vadivel Murugan tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns); 98531fb632bSRamuthevar Vadivel Murugan 98631fb632bSRamuthevar Vadivel Murugan reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK) 98731fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSHSL_LSB; 98831fb632bSRamuthevar Vadivel Murugan reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK) 98931fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TCHSH_LSB; 99031fb632bSRamuthevar Vadivel Murugan reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK) 99131fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSLCH_LSB; 99231fb632bSRamuthevar Vadivel Murugan reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK) 99331fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSD2D_LSB; 99431fb632bSRamuthevar Vadivel Murugan writel(reg, iobase + CQSPI_REG_DELAY); 99531fb632bSRamuthevar Vadivel Murugan } 99631fb632bSRamuthevar Vadivel Murugan 99731fb632bSRamuthevar Vadivel Murugan static void cqspi_config_baudrate_div(struct cqspi_st *cqspi) 99831fb632bSRamuthevar Vadivel Murugan { 99931fb632bSRamuthevar Vadivel Murugan const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 100031fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 100131fb632bSRamuthevar Vadivel Murugan u32 reg, div; 100231fb632bSRamuthevar Vadivel Murugan 100331fb632bSRamuthevar Vadivel Murugan /* Recalculate the baudrate divisor based on QSPI specification. */ 100431fb632bSRamuthevar Vadivel Murugan div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1; 100531fb632bSRamuthevar Vadivel Murugan 100631fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG); 100731fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); 100831fb632bSRamuthevar Vadivel Murugan reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB; 100931fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG); 101031fb632bSRamuthevar Vadivel Murugan } 101131fb632bSRamuthevar Vadivel Murugan 101231fb632bSRamuthevar Vadivel Murugan static void cqspi_readdata_capture(struct cqspi_st *cqspi, 101331fb632bSRamuthevar Vadivel Murugan const bool bypass, 101431fb632bSRamuthevar Vadivel Murugan const unsigned int delay) 101531fb632bSRamuthevar Vadivel Murugan { 101631fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 101731fb632bSRamuthevar Vadivel Murugan unsigned int reg; 101831fb632bSRamuthevar Vadivel Murugan 101931fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_READCAPTURE); 102031fb632bSRamuthevar Vadivel Murugan 102131fb632bSRamuthevar Vadivel Murugan if (bypass) 102231fb632bSRamuthevar Vadivel Murugan reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 102331fb632bSRamuthevar Vadivel Murugan else 102431fb632bSRamuthevar Vadivel Murugan reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 102531fb632bSRamuthevar Vadivel Murugan 102631fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK 102731fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_READCAPTURE_DELAY_LSB); 102831fb632bSRamuthevar Vadivel Murugan 102931fb632bSRamuthevar Vadivel Murugan reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK) 103031fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_READCAPTURE_DELAY_LSB; 103131fb632bSRamuthevar Vadivel Murugan 103231fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_READCAPTURE); 103331fb632bSRamuthevar Vadivel Murugan } 103431fb632bSRamuthevar Vadivel Murugan 103531fb632bSRamuthevar Vadivel Murugan static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable) 103631fb632bSRamuthevar Vadivel Murugan { 103731fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase; 103831fb632bSRamuthevar Vadivel Murugan unsigned int reg; 103931fb632bSRamuthevar Vadivel Murugan 104031fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG); 104131fb632bSRamuthevar Vadivel Murugan 104231fb632bSRamuthevar Vadivel Murugan if (enable) 104331fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CONFIG_ENABLE_MASK; 104431fb632bSRamuthevar Vadivel Murugan else 104531fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; 104631fb632bSRamuthevar Vadivel Murugan 104731fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG); 104831fb632bSRamuthevar Vadivel Murugan } 104931fb632bSRamuthevar Vadivel Murugan 105031fb632bSRamuthevar Vadivel Murugan static void cqspi_configure(struct cqspi_flash_pdata *f_pdata, 105131fb632bSRamuthevar Vadivel Murugan unsigned long sclk) 105231fb632bSRamuthevar Vadivel Murugan { 105331fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 105431fb632bSRamuthevar Vadivel Murugan int switch_cs = (cqspi->current_cs != f_pdata->cs); 105531fb632bSRamuthevar Vadivel Murugan int switch_ck = (cqspi->sclk != sclk); 105631fb632bSRamuthevar Vadivel Murugan 105731fb632bSRamuthevar Vadivel Murugan if (switch_cs || switch_ck) 105831fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 105931fb632bSRamuthevar Vadivel Murugan 106031fb632bSRamuthevar Vadivel Murugan /* Switch chip select. */ 106131fb632bSRamuthevar Vadivel Murugan if (switch_cs) { 106231fb632bSRamuthevar Vadivel Murugan cqspi->current_cs = f_pdata->cs; 106331fb632bSRamuthevar Vadivel Murugan cqspi_chipselect(f_pdata); 106431fb632bSRamuthevar Vadivel Murugan } 106531fb632bSRamuthevar Vadivel Murugan 106631fb632bSRamuthevar Vadivel Murugan /* Setup baudrate divisor and delays */ 106731fb632bSRamuthevar Vadivel Murugan if (switch_ck) { 106831fb632bSRamuthevar Vadivel Murugan cqspi->sclk = sclk; 106931fb632bSRamuthevar Vadivel Murugan cqspi_config_baudrate_div(cqspi); 107031fb632bSRamuthevar Vadivel Murugan cqspi_delay(f_pdata); 107131fb632bSRamuthevar Vadivel Murugan cqspi_readdata_capture(cqspi, !cqspi->rclk_en, 107231fb632bSRamuthevar Vadivel Murugan f_pdata->read_delay); 107331fb632bSRamuthevar Vadivel Murugan } 107431fb632bSRamuthevar Vadivel Murugan 107531fb632bSRamuthevar Vadivel Murugan if (switch_cs || switch_ck) 107631fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1); 107731fb632bSRamuthevar Vadivel Murugan } 107831fb632bSRamuthevar Vadivel Murugan 107931fb632bSRamuthevar Vadivel Murugan static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata, 108031fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 108131fb632bSRamuthevar Vadivel Murugan { 108231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 108331fb632bSRamuthevar Vadivel Murugan loff_t to = op->addr.val; 108431fb632bSRamuthevar Vadivel Murugan size_t len = op->data.nbytes; 108531fb632bSRamuthevar Vadivel Murugan const u_char *buf = op->data.buf.out; 108631fb632bSRamuthevar Vadivel Murugan int ret; 108731fb632bSRamuthevar Vadivel Murugan 108831fb632bSRamuthevar Vadivel Murugan ret = cqspi_set_protocol(f_pdata, op); 108931fb632bSRamuthevar Vadivel Murugan if (ret) 109031fb632bSRamuthevar Vadivel Murugan return ret; 109131fb632bSRamuthevar Vadivel Murugan 109231fb632bSRamuthevar Vadivel Murugan ret = cqspi_write_setup(f_pdata, op); 109331fb632bSRamuthevar Vadivel Murugan if (ret) 109431fb632bSRamuthevar Vadivel Murugan return ret; 109531fb632bSRamuthevar Vadivel Murugan 1096f453f293SPratyush Yadav /* 1097f453f293SPratyush Yadav * Some flashes like the Cypress Semper flash expect a dummy 4-byte 1098f453f293SPratyush Yadav * address (all 0s) with the read status register command in DTR mode. 1099f453f293SPratyush Yadav * But this controller does not support sending dummy address bytes to 1100f453f293SPratyush Yadav * the flash when it is polling the write completion register in DTR 1101f453f293SPratyush Yadav * mode. So, we can not use direct mode when in DTR mode for writing 1102f453f293SPratyush Yadav * data. 1103f453f293SPratyush Yadav */ 1104f453f293SPratyush Yadav if (!f_pdata->dtr && cqspi->use_direct_mode && 1105f453f293SPratyush Yadav ((to + len) <= cqspi->ahb_size)) { 110631fb632bSRamuthevar Vadivel Murugan memcpy_toio(cqspi->ahb_base + to, buf, len); 110731fb632bSRamuthevar Vadivel Murugan return cqspi_wait_idle(cqspi); 110831fb632bSRamuthevar Vadivel Murugan } 110931fb632bSRamuthevar Vadivel Murugan 111031fb632bSRamuthevar Vadivel Murugan return cqspi_indirect_write_execute(f_pdata, to, buf, len); 111131fb632bSRamuthevar Vadivel Murugan } 111231fb632bSRamuthevar Vadivel Murugan 111331fb632bSRamuthevar Vadivel Murugan static void cqspi_rx_dma_callback(void *param) 111431fb632bSRamuthevar Vadivel Murugan { 111531fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = param; 111631fb632bSRamuthevar Vadivel Murugan 111731fb632bSRamuthevar Vadivel Murugan complete(&cqspi->rx_dma_complete); 111831fb632bSRamuthevar Vadivel Murugan } 111931fb632bSRamuthevar Vadivel Murugan 112031fb632bSRamuthevar Vadivel Murugan static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata, 112131fb632bSRamuthevar Vadivel Murugan u_char *buf, loff_t from, size_t len) 112231fb632bSRamuthevar Vadivel Murugan { 112331fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 112431fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 112531fb632bSRamuthevar Vadivel Murugan enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; 112631fb632bSRamuthevar Vadivel Murugan dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from; 112731fb632bSRamuthevar Vadivel Murugan int ret = 0; 112831fb632bSRamuthevar Vadivel Murugan struct dma_async_tx_descriptor *tx; 112931fb632bSRamuthevar Vadivel Murugan dma_cookie_t cookie; 113031fb632bSRamuthevar Vadivel Murugan dma_addr_t dma_dst; 113183048015SVignesh Raghavendra struct device *ddev; 113231fb632bSRamuthevar Vadivel Murugan 113331fb632bSRamuthevar Vadivel Murugan if (!cqspi->rx_chan || !virt_addr_valid(buf)) { 113431fb632bSRamuthevar Vadivel Murugan memcpy_fromio(buf, cqspi->ahb_base + from, len); 113531fb632bSRamuthevar Vadivel Murugan return 0; 113631fb632bSRamuthevar Vadivel Murugan } 113731fb632bSRamuthevar Vadivel Murugan 113883048015SVignesh Raghavendra ddev = cqspi->rx_chan->device->dev; 113983048015SVignesh Raghavendra dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE); 114083048015SVignesh Raghavendra if (dma_mapping_error(ddev, dma_dst)) { 114131fb632bSRamuthevar Vadivel Murugan dev_err(dev, "dma mapping failed\n"); 114231fb632bSRamuthevar Vadivel Murugan return -ENOMEM; 114331fb632bSRamuthevar Vadivel Murugan } 114431fb632bSRamuthevar Vadivel Murugan tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src, 114531fb632bSRamuthevar Vadivel Murugan len, flags); 114631fb632bSRamuthevar Vadivel Murugan if (!tx) { 114731fb632bSRamuthevar Vadivel Murugan dev_err(dev, "device_prep_dma_memcpy error\n"); 114831fb632bSRamuthevar Vadivel Murugan ret = -EIO; 114931fb632bSRamuthevar Vadivel Murugan goto err_unmap; 115031fb632bSRamuthevar Vadivel Murugan } 115131fb632bSRamuthevar Vadivel Murugan 115231fb632bSRamuthevar Vadivel Murugan tx->callback = cqspi_rx_dma_callback; 115331fb632bSRamuthevar Vadivel Murugan tx->callback_param = cqspi; 115431fb632bSRamuthevar Vadivel Murugan cookie = tx->tx_submit(tx); 115531fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->rx_dma_complete); 115631fb632bSRamuthevar Vadivel Murugan 115731fb632bSRamuthevar Vadivel Murugan ret = dma_submit_error(cookie); 115831fb632bSRamuthevar Vadivel Murugan if (ret) { 115931fb632bSRamuthevar Vadivel Murugan dev_err(dev, "dma_submit_error %d\n", cookie); 116031fb632bSRamuthevar Vadivel Murugan ret = -EIO; 116131fb632bSRamuthevar Vadivel Murugan goto err_unmap; 116231fb632bSRamuthevar Vadivel Murugan } 116331fb632bSRamuthevar Vadivel Murugan 116431fb632bSRamuthevar Vadivel Murugan dma_async_issue_pending(cqspi->rx_chan); 116531fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->rx_dma_complete, 11662ef0170eSPratyush Yadav msecs_to_jiffies(max_t(size_t, len, 500)))) { 116731fb632bSRamuthevar Vadivel Murugan dmaengine_terminate_sync(cqspi->rx_chan); 116831fb632bSRamuthevar Vadivel Murugan dev_err(dev, "DMA wait_for_completion_timeout\n"); 116931fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT; 117031fb632bSRamuthevar Vadivel Murugan goto err_unmap; 117131fb632bSRamuthevar Vadivel Murugan } 117231fb632bSRamuthevar Vadivel Murugan 117331fb632bSRamuthevar Vadivel Murugan err_unmap: 117483048015SVignesh Raghavendra dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE); 117531fb632bSRamuthevar Vadivel Murugan 117631fb632bSRamuthevar Vadivel Murugan return ret; 117731fb632bSRamuthevar Vadivel Murugan } 117831fb632bSRamuthevar Vadivel Murugan 117931fb632bSRamuthevar Vadivel Murugan static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata, 118031fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op) 118131fb632bSRamuthevar Vadivel Murugan { 118231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi; 118331fb632bSRamuthevar Vadivel Murugan loff_t from = op->addr.val; 118431fb632bSRamuthevar Vadivel Murugan size_t len = op->data.nbytes; 118531fb632bSRamuthevar Vadivel Murugan u_char *buf = op->data.buf.in; 118631fb632bSRamuthevar Vadivel Murugan int ret; 118731fb632bSRamuthevar Vadivel Murugan 118831fb632bSRamuthevar Vadivel Murugan ret = cqspi_set_protocol(f_pdata, op); 118931fb632bSRamuthevar Vadivel Murugan if (ret) 119031fb632bSRamuthevar Vadivel Murugan return ret; 119131fb632bSRamuthevar Vadivel Murugan 119231fb632bSRamuthevar Vadivel Murugan ret = cqspi_read_setup(f_pdata, op); 119331fb632bSRamuthevar Vadivel Murugan if (ret) 119431fb632bSRamuthevar Vadivel Murugan return ret; 119531fb632bSRamuthevar Vadivel Murugan 119631fb632bSRamuthevar Vadivel Murugan if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) 119731fb632bSRamuthevar Vadivel Murugan return cqspi_direct_read_execute(f_pdata, buf, from, len); 119831fb632bSRamuthevar Vadivel Murugan 119931fb632bSRamuthevar Vadivel Murugan return cqspi_indirect_read_execute(f_pdata, buf, from, len); 120031fb632bSRamuthevar Vadivel Murugan } 120131fb632bSRamuthevar Vadivel Murugan 120231fb632bSRamuthevar Vadivel Murugan static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op) 120331fb632bSRamuthevar Vadivel Murugan { 120431fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); 120531fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata; 120631fb632bSRamuthevar Vadivel Murugan 120731fb632bSRamuthevar Vadivel Murugan f_pdata = &cqspi->f_pdata[mem->spi->chip_select]; 120831fb632bSRamuthevar Vadivel Murugan cqspi_configure(f_pdata, mem->spi->max_speed_hz); 120931fb632bSRamuthevar Vadivel Murugan 121031fb632bSRamuthevar Vadivel Murugan if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { 121131fb632bSRamuthevar Vadivel Murugan if (!op->addr.nbytes) 121231fb632bSRamuthevar Vadivel Murugan return cqspi_command_read(f_pdata, op); 121331fb632bSRamuthevar Vadivel Murugan 121431fb632bSRamuthevar Vadivel Murugan return cqspi_read(f_pdata, op); 121531fb632bSRamuthevar Vadivel Murugan } 121631fb632bSRamuthevar Vadivel Murugan 121731fb632bSRamuthevar Vadivel Murugan if (!op->addr.nbytes || !op->data.buf.out) 121831fb632bSRamuthevar Vadivel Murugan return cqspi_command_write(f_pdata, op); 121931fb632bSRamuthevar Vadivel Murugan 122031fb632bSRamuthevar Vadivel Murugan return cqspi_write(f_pdata, op); 122131fb632bSRamuthevar Vadivel Murugan } 122231fb632bSRamuthevar Vadivel Murugan 122331fb632bSRamuthevar Vadivel Murugan static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) 122431fb632bSRamuthevar Vadivel Murugan { 122531fb632bSRamuthevar Vadivel Murugan int ret; 122631fb632bSRamuthevar Vadivel Murugan 122731fb632bSRamuthevar Vadivel Murugan ret = cqspi_mem_process(mem, op); 122831fb632bSRamuthevar Vadivel Murugan if (ret) 122931fb632bSRamuthevar Vadivel Murugan dev_err(&mem->spi->dev, "operation failed with %d\n", ret); 123031fb632bSRamuthevar Vadivel Murugan 123131fb632bSRamuthevar Vadivel Murugan return ret; 123231fb632bSRamuthevar Vadivel Murugan } 123331fb632bSRamuthevar Vadivel Murugan 1234a273596bSPratyush Yadav static bool cqspi_supports_mem_op(struct spi_mem *mem, 1235a273596bSPratyush Yadav const struct spi_mem_op *op) 1236a273596bSPratyush Yadav { 1237f453f293SPratyush Yadav bool all_true, all_false; 1238f453f293SPratyush Yadav 1239*0395be96SApurva Nandan /* 1240*0395be96SApurva Nandan * op->dummy.dtr is required for converting nbytes into ncycles. 1241*0395be96SApurva Nandan * Also, don't check the dtr field of the op phase having zero nbytes. 1242*0395be96SApurva Nandan */ 1243*0395be96SApurva Nandan all_true = op->cmd.dtr && 1244*0395be96SApurva Nandan (!op->addr.nbytes || op->addr.dtr) && 1245*0395be96SApurva Nandan (!op->dummy.nbytes || op->dummy.dtr) && 1246*0395be96SApurva Nandan (!op->data.nbytes || op->data.dtr); 1247*0395be96SApurva Nandan 1248f453f293SPratyush Yadav all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && 1249f453f293SPratyush Yadav !op->data.dtr; 1250f453f293SPratyush Yadav 1251f453f293SPratyush Yadav /* Mixed DTR modes not supported. */ 1252f453f293SPratyush Yadav if (!(all_true || all_false)) 1253f453f293SPratyush Yadav return false; 1254f453f293SPratyush Yadav 1255d2275139SPratyush Yadav if (all_true) 1256d2275139SPratyush Yadav return spi_mem_dtr_supports_op(mem, op); 1257d2275139SPratyush Yadav else 1258d2275139SPratyush Yadav return spi_mem_default_supports_op(mem, op); 1259a273596bSPratyush Yadav } 1260a273596bSPratyush Yadav 126131fb632bSRamuthevar Vadivel Murugan static int cqspi_of_get_flash_pdata(struct platform_device *pdev, 126231fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata, 126331fb632bSRamuthevar Vadivel Murugan struct device_node *np) 126431fb632bSRamuthevar Vadivel Murugan { 126531fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) { 126631fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine read-delay\n"); 126731fb632bSRamuthevar Vadivel Murugan return -ENXIO; 126831fb632bSRamuthevar Vadivel Murugan } 126931fb632bSRamuthevar Vadivel Murugan 127031fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) { 127131fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tshsl-ns\n"); 127231fb632bSRamuthevar Vadivel Murugan return -ENXIO; 127331fb632bSRamuthevar Vadivel Murugan } 127431fb632bSRamuthevar Vadivel Murugan 127531fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) { 127631fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n"); 127731fb632bSRamuthevar Vadivel Murugan return -ENXIO; 127831fb632bSRamuthevar Vadivel Murugan } 127931fb632bSRamuthevar Vadivel Murugan 128031fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) { 128131fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tchsh-ns\n"); 128231fb632bSRamuthevar Vadivel Murugan return -ENXIO; 128331fb632bSRamuthevar Vadivel Murugan } 128431fb632bSRamuthevar Vadivel Murugan 128531fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) { 128631fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tslch-ns\n"); 128731fb632bSRamuthevar Vadivel Murugan return -ENXIO; 128831fb632bSRamuthevar Vadivel Murugan } 128931fb632bSRamuthevar Vadivel Murugan 129031fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) { 129131fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n"); 129231fb632bSRamuthevar Vadivel Murugan return -ENXIO; 129331fb632bSRamuthevar Vadivel Murugan } 129431fb632bSRamuthevar Vadivel Murugan 129531fb632bSRamuthevar Vadivel Murugan return 0; 129631fb632bSRamuthevar Vadivel Murugan } 129731fb632bSRamuthevar Vadivel Murugan 129831fb632bSRamuthevar Vadivel Murugan static int cqspi_of_get_pdata(struct cqspi_st *cqspi) 129931fb632bSRamuthevar Vadivel Murugan { 130031fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev; 130131fb632bSRamuthevar Vadivel Murugan struct device_node *np = dev->of_node; 130231fb632bSRamuthevar Vadivel Murugan 130331fb632bSRamuthevar Vadivel Murugan cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); 130431fb632bSRamuthevar Vadivel Murugan 130531fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { 130631fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine fifo-depth\n"); 130731fb632bSRamuthevar Vadivel Murugan return -ENXIO; 130831fb632bSRamuthevar Vadivel Murugan } 130931fb632bSRamuthevar Vadivel Murugan 131031fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) { 131131fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine fifo-width\n"); 131231fb632bSRamuthevar Vadivel Murugan return -ENXIO; 131331fb632bSRamuthevar Vadivel Murugan } 131431fb632bSRamuthevar Vadivel Murugan 131531fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,trigger-address", 131631fb632bSRamuthevar Vadivel Murugan &cqspi->trigger_address)) { 131731fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine trigger-address\n"); 131831fb632bSRamuthevar Vadivel Murugan return -ENXIO; 131931fb632bSRamuthevar Vadivel Murugan } 132031fb632bSRamuthevar Vadivel Murugan 1321b436fb7dSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) 1322b436fb7dSRamuthevar Vadivel Murugan cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT; 1323b436fb7dSRamuthevar Vadivel Murugan 132431fb632bSRamuthevar Vadivel Murugan cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); 132531fb632bSRamuthevar Vadivel Murugan 132631fb632bSRamuthevar Vadivel Murugan return 0; 132731fb632bSRamuthevar Vadivel Murugan } 132831fb632bSRamuthevar Vadivel Murugan 132931fb632bSRamuthevar Vadivel Murugan static void cqspi_controller_init(struct cqspi_st *cqspi) 133031fb632bSRamuthevar Vadivel Murugan { 133131fb632bSRamuthevar Vadivel Murugan u32 reg; 133231fb632bSRamuthevar Vadivel Murugan 133331fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 133431fb632bSRamuthevar Vadivel Murugan 133531fb632bSRamuthevar Vadivel Murugan /* Configure the remap address register, no remap */ 133631fb632bSRamuthevar Vadivel Murugan writel(0, cqspi->iobase + CQSPI_REG_REMAP); 133731fb632bSRamuthevar Vadivel Murugan 133831fb632bSRamuthevar Vadivel Murugan /* Disable all interrupts. */ 133931fb632bSRamuthevar Vadivel Murugan writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); 134031fb632bSRamuthevar Vadivel Murugan 134131fb632bSRamuthevar Vadivel Murugan /* Configure the SRAM split to 1:1 . */ 134231fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); 134331fb632bSRamuthevar Vadivel Murugan 134431fb632bSRamuthevar Vadivel Murugan /* Load indirect trigger address. */ 134531fb632bSRamuthevar Vadivel Murugan writel(cqspi->trigger_address, 134631fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); 134731fb632bSRamuthevar Vadivel Murugan 134831fb632bSRamuthevar Vadivel Murugan /* Program read watermark -- 1/2 of the FIFO. */ 134931fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth * cqspi->fifo_width / 2, 135031fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); 135131fb632bSRamuthevar Vadivel Murugan /* Program write watermark -- 1/8 of the FIFO. */ 135231fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth * cqspi->fifo_width / 8, 135331fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); 135431fb632bSRamuthevar Vadivel Murugan 1355ad2775dcSRamuthevar Vadivel Murugan /* Disable direct access controller */ 1356ad2775dcSRamuthevar Vadivel Murugan if (!cqspi->use_direct_mode) { 135731fb632bSRamuthevar Vadivel Murugan reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 1358ad2775dcSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL; 135931fb632bSRamuthevar Vadivel Murugan writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 1360ad2775dcSRamuthevar Vadivel Murugan } 136131fb632bSRamuthevar Vadivel Murugan 136231fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1); 136331fb632bSRamuthevar Vadivel Murugan } 136431fb632bSRamuthevar Vadivel Murugan 136531fb632bSRamuthevar Vadivel Murugan static int cqspi_request_mmap_dma(struct cqspi_st *cqspi) 136631fb632bSRamuthevar Vadivel Murugan { 136731fb632bSRamuthevar Vadivel Murugan dma_cap_mask_t mask; 136831fb632bSRamuthevar Vadivel Murugan 136931fb632bSRamuthevar Vadivel Murugan dma_cap_zero(mask); 137031fb632bSRamuthevar Vadivel Murugan dma_cap_set(DMA_MEMCPY, mask); 137131fb632bSRamuthevar Vadivel Murugan 137231fb632bSRamuthevar Vadivel Murugan cqspi->rx_chan = dma_request_chan_by_mask(&mask); 137331fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->rx_chan)) { 137431fb632bSRamuthevar Vadivel Murugan int ret = PTR_ERR(cqspi->rx_chan); 137531fb632bSRamuthevar Vadivel Murugan cqspi->rx_chan = NULL; 1376436a5c20SKrzysztof Kozlowski return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n"); 137731fb632bSRamuthevar Vadivel Murugan } 137831fb632bSRamuthevar Vadivel Murugan init_completion(&cqspi->rx_dma_complete); 137931fb632bSRamuthevar Vadivel Murugan 138031fb632bSRamuthevar Vadivel Murugan return 0; 138131fb632bSRamuthevar Vadivel Murugan } 138231fb632bSRamuthevar Vadivel Murugan 13832ea370a9SVignesh Raghavendra static const char *cqspi_get_name(struct spi_mem *mem) 13842ea370a9SVignesh Raghavendra { 13852ea370a9SVignesh Raghavendra struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); 13862ea370a9SVignesh Raghavendra struct device *dev = &cqspi->pdev->dev; 13872ea370a9SVignesh Raghavendra 13882ea370a9SVignesh Raghavendra return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select); 13892ea370a9SVignesh Raghavendra } 13902ea370a9SVignesh Raghavendra 139131fb632bSRamuthevar Vadivel Murugan static const struct spi_controller_mem_ops cqspi_mem_ops = { 139231fb632bSRamuthevar Vadivel Murugan .exec_op = cqspi_exec_mem_op, 13932ea370a9SVignesh Raghavendra .get_name = cqspi_get_name, 1394a273596bSPratyush Yadav .supports_op = cqspi_supports_mem_op, 139531fb632bSRamuthevar Vadivel Murugan }; 139631fb632bSRamuthevar Vadivel Murugan 139731fb632bSRamuthevar Vadivel Murugan static int cqspi_setup_flash(struct cqspi_st *cqspi) 139831fb632bSRamuthevar Vadivel Murugan { 139931fb632bSRamuthevar Vadivel Murugan struct platform_device *pdev = cqspi->pdev; 140031fb632bSRamuthevar Vadivel Murugan struct device *dev = &pdev->dev; 140131fb632bSRamuthevar Vadivel Murugan struct device_node *np = dev->of_node; 140231fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata; 140331fb632bSRamuthevar Vadivel Murugan unsigned int cs; 140431fb632bSRamuthevar Vadivel Murugan int ret; 140531fb632bSRamuthevar Vadivel Murugan 140631fb632bSRamuthevar Vadivel Murugan /* Get flash device data */ 140731fb632bSRamuthevar Vadivel Murugan for_each_available_child_of_node(dev->of_node, np) { 140831fb632bSRamuthevar Vadivel Murugan ret = of_property_read_u32(np, "reg", &cs); 140931fb632bSRamuthevar Vadivel Murugan if (ret) { 141031fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Couldn't determine chip select.\n"); 141187d62d8fSJunlin Yang of_node_put(np); 141231fb632bSRamuthevar Vadivel Murugan return ret; 141331fb632bSRamuthevar Vadivel Murugan } 141431fb632bSRamuthevar Vadivel Murugan 141531fb632bSRamuthevar Vadivel Murugan if (cs >= CQSPI_MAX_CHIPSELECT) { 141631fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Chip select %d out of range.\n", cs); 141787d62d8fSJunlin Yang of_node_put(np); 141831fb632bSRamuthevar Vadivel Murugan return -EINVAL; 141931fb632bSRamuthevar Vadivel Murugan } 142031fb632bSRamuthevar Vadivel Murugan 142131fb632bSRamuthevar Vadivel Murugan f_pdata = &cqspi->f_pdata[cs]; 142231fb632bSRamuthevar Vadivel Murugan f_pdata->cqspi = cqspi; 142331fb632bSRamuthevar Vadivel Murugan f_pdata->cs = cs; 142431fb632bSRamuthevar Vadivel Murugan 142531fb632bSRamuthevar Vadivel Murugan ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np); 142687d62d8fSJunlin Yang if (ret) { 142787d62d8fSJunlin Yang of_node_put(np); 142831fb632bSRamuthevar Vadivel Murugan return ret; 142931fb632bSRamuthevar Vadivel Murugan } 143087d62d8fSJunlin Yang } 143131fb632bSRamuthevar Vadivel Murugan 143231fb632bSRamuthevar Vadivel Murugan return 0; 143331fb632bSRamuthevar Vadivel Murugan } 143431fb632bSRamuthevar Vadivel Murugan 143531fb632bSRamuthevar Vadivel Murugan static int cqspi_probe(struct platform_device *pdev) 143631fb632bSRamuthevar Vadivel Murugan { 143731fb632bSRamuthevar Vadivel Murugan const struct cqspi_driver_platdata *ddata; 143831fb632bSRamuthevar Vadivel Murugan struct reset_control *rstc, *rstc_ocp; 143931fb632bSRamuthevar Vadivel Murugan struct device *dev = &pdev->dev; 144031fb632bSRamuthevar Vadivel Murugan struct spi_master *master; 144131fb632bSRamuthevar Vadivel Murugan struct resource *res_ahb; 144231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi; 144331fb632bSRamuthevar Vadivel Murugan struct resource *res; 144431fb632bSRamuthevar Vadivel Murugan int ret; 144531fb632bSRamuthevar Vadivel Murugan int irq; 144631fb632bSRamuthevar Vadivel Murugan 144731fb632bSRamuthevar Vadivel Murugan master = spi_alloc_master(&pdev->dev, sizeof(*cqspi)); 144831fb632bSRamuthevar Vadivel Murugan if (!master) { 144931fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "spi_alloc_master failed\n"); 145031fb632bSRamuthevar Vadivel Murugan return -ENOMEM; 145131fb632bSRamuthevar Vadivel Murugan } 145231fb632bSRamuthevar Vadivel Murugan master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; 145331fb632bSRamuthevar Vadivel Murugan master->mem_ops = &cqspi_mem_ops; 145431fb632bSRamuthevar Vadivel Murugan master->dev.of_node = pdev->dev.of_node; 145531fb632bSRamuthevar Vadivel Murugan 145631fb632bSRamuthevar Vadivel Murugan cqspi = spi_master_get_devdata(master); 145731fb632bSRamuthevar Vadivel Murugan 145831fb632bSRamuthevar Vadivel Murugan cqspi->pdev = pdev; 1459ea94191eSMeng Li platform_set_drvdata(pdev, cqspi); 146031fb632bSRamuthevar Vadivel Murugan 146131fb632bSRamuthevar Vadivel Murugan /* Obtain configuration from OF. */ 146231fb632bSRamuthevar Vadivel Murugan ret = cqspi_of_get_pdata(cqspi); 146331fb632bSRamuthevar Vadivel Murugan if (ret) { 146431fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get mandatory OF data.\n"); 146531fb632bSRamuthevar Vadivel Murugan ret = -ENODEV; 146631fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 146731fb632bSRamuthevar Vadivel Murugan } 146831fb632bSRamuthevar Vadivel Murugan 146931fb632bSRamuthevar Vadivel Murugan /* Obtain QSPI clock. */ 147031fb632bSRamuthevar Vadivel Murugan cqspi->clk = devm_clk_get(dev, NULL); 147131fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->clk)) { 147231fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot claim QSPI clock.\n"); 147331fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->clk); 147431fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 147531fb632bSRamuthevar Vadivel Murugan } 147631fb632bSRamuthevar Vadivel Murugan 147731fb632bSRamuthevar Vadivel Murugan /* Obtain and remap controller address. */ 147831fb632bSRamuthevar Vadivel Murugan res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 147931fb632bSRamuthevar Vadivel Murugan cqspi->iobase = devm_ioremap_resource(dev, res); 148031fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->iobase)) { 148131fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot remap controller address.\n"); 148231fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->iobase); 148331fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 148431fb632bSRamuthevar Vadivel Murugan } 148531fb632bSRamuthevar Vadivel Murugan 148631fb632bSRamuthevar Vadivel Murugan /* Obtain and remap AHB address. */ 148731fb632bSRamuthevar Vadivel Murugan res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1); 148831fb632bSRamuthevar Vadivel Murugan cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb); 148931fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->ahb_base)) { 149031fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot remap AHB address.\n"); 149131fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->ahb_base); 149231fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 149331fb632bSRamuthevar Vadivel Murugan } 149431fb632bSRamuthevar Vadivel Murugan cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start; 149531fb632bSRamuthevar Vadivel Murugan cqspi->ahb_size = resource_size(res_ahb); 149631fb632bSRamuthevar Vadivel Murugan 149731fb632bSRamuthevar Vadivel Murugan init_completion(&cqspi->transfer_complete); 149831fb632bSRamuthevar Vadivel Murugan 149931fb632bSRamuthevar Vadivel Murugan /* Obtain IRQ line. */ 150031fb632bSRamuthevar Vadivel Murugan irq = platform_get_irq(pdev, 0); 150131fb632bSRamuthevar Vadivel Murugan if (irq < 0) { 150231fb632bSRamuthevar Vadivel Murugan ret = -ENXIO; 150331fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 150431fb632bSRamuthevar Vadivel Murugan } 150531fb632bSRamuthevar Vadivel Murugan 150631fb632bSRamuthevar Vadivel Murugan pm_runtime_enable(dev); 150731fb632bSRamuthevar Vadivel Murugan ret = pm_runtime_get_sync(dev); 150831fb632bSRamuthevar Vadivel Murugan if (ret < 0) { 150931fb632bSRamuthevar Vadivel Murugan pm_runtime_put_noidle(dev); 151031fb632bSRamuthevar Vadivel Murugan goto probe_master_put; 151131fb632bSRamuthevar Vadivel Murugan } 151231fb632bSRamuthevar Vadivel Murugan 151331fb632bSRamuthevar Vadivel Murugan ret = clk_prepare_enable(cqspi->clk); 151431fb632bSRamuthevar Vadivel Murugan if (ret) { 151531fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot enable QSPI clock.\n"); 151631fb632bSRamuthevar Vadivel Murugan goto probe_clk_failed; 151731fb632bSRamuthevar Vadivel Murugan } 151831fb632bSRamuthevar Vadivel Murugan 151931fb632bSRamuthevar Vadivel Murugan /* Obtain QSPI reset control */ 152031fb632bSRamuthevar Vadivel Murugan rstc = devm_reset_control_get_optional_exclusive(dev, "qspi"); 152131fb632bSRamuthevar Vadivel Murugan if (IS_ERR(rstc)) { 1522ac9978fcSZhihao Cheng ret = PTR_ERR(rstc); 152331fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get QSPI reset.\n"); 152431fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 152531fb632bSRamuthevar Vadivel Murugan } 152631fb632bSRamuthevar Vadivel Murugan 152731fb632bSRamuthevar Vadivel Murugan rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); 152831fb632bSRamuthevar Vadivel Murugan if (IS_ERR(rstc_ocp)) { 1529ac9978fcSZhihao Cheng ret = PTR_ERR(rstc_ocp); 153031fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get QSPI OCP reset.\n"); 153131fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 153231fb632bSRamuthevar Vadivel Murugan } 153331fb632bSRamuthevar Vadivel Murugan 153431fb632bSRamuthevar Vadivel Murugan reset_control_assert(rstc); 153531fb632bSRamuthevar Vadivel Murugan reset_control_deassert(rstc); 153631fb632bSRamuthevar Vadivel Murugan 153731fb632bSRamuthevar Vadivel Murugan reset_control_assert(rstc_ocp); 153831fb632bSRamuthevar Vadivel Murugan reset_control_deassert(rstc_ocp); 153931fb632bSRamuthevar Vadivel Murugan 154031fb632bSRamuthevar Vadivel Murugan cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); 15413a5c09c8SPratyush Yadav master->max_speed_hz = cqspi->master_ref_clk_hz; 154231fb632bSRamuthevar Vadivel Murugan ddata = of_device_get_match_data(dev); 154331fb632bSRamuthevar Vadivel Murugan if (ddata) { 154431fb632bSRamuthevar Vadivel Murugan if (ddata->quirks & CQSPI_NEEDS_WR_DELAY) 1545f453f293SPratyush Yadav cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, 154631fb632bSRamuthevar Vadivel Murugan cqspi->master_ref_clk_hz); 154731fb632bSRamuthevar Vadivel Murugan if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL) 1548f453f293SPratyush Yadav master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; 154931fb632bSRamuthevar Vadivel Murugan if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) 155031fb632bSRamuthevar Vadivel Murugan cqspi->use_direct_mode = true; 155131fb632bSRamuthevar Vadivel Murugan } 155231fb632bSRamuthevar Vadivel Murugan 155331fb632bSRamuthevar Vadivel Murugan ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0, 155431fb632bSRamuthevar Vadivel Murugan pdev->name, cqspi); 155531fb632bSRamuthevar Vadivel Murugan if (ret) { 155631fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot request IRQ.\n"); 155731fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed; 155831fb632bSRamuthevar Vadivel Murugan } 155931fb632bSRamuthevar Vadivel Murugan 156031fb632bSRamuthevar Vadivel Murugan cqspi_wait_idle(cqspi); 156131fb632bSRamuthevar Vadivel Murugan cqspi_controller_init(cqspi); 156231fb632bSRamuthevar Vadivel Murugan cqspi->current_cs = -1; 156331fb632bSRamuthevar Vadivel Murugan cqspi->sclk = 0; 156431fb632bSRamuthevar Vadivel Murugan 1565b436fb7dSRamuthevar Vadivel Murugan master->num_chipselect = cqspi->num_chipselect; 1566b436fb7dSRamuthevar Vadivel Murugan 156731fb632bSRamuthevar Vadivel Murugan ret = cqspi_setup_flash(cqspi); 156831fb632bSRamuthevar Vadivel Murugan if (ret) { 156931fb632bSRamuthevar Vadivel Murugan dev_err(dev, "failed to setup flash parameters %d\n", ret); 157031fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 157131fb632bSRamuthevar Vadivel Murugan } 157231fb632bSRamuthevar Vadivel Murugan 157331fb632bSRamuthevar Vadivel Murugan if (cqspi->use_direct_mode) { 157431fb632bSRamuthevar Vadivel Murugan ret = cqspi_request_mmap_dma(cqspi); 157531fb632bSRamuthevar Vadivel Murugan if (ret == -EPROBE_DEFER) 157631fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 157731fb632bSRamuthevar Vadivel Murugan } 157831fb632bSRamuthevar Vadivel Murugan 157931fb632bSRamuthevar Vadivel Murugan ret = devm_spi_register_master(dev, master); 158031fb632bSRamuthevar Vadivel Murugan if (ret) { 158131fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret); 158231fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed; 158331fb632bSRamuthevar Vadivel Murugan } 158431fb632bSRamuthevar Vadivel Murugan 158531fb632bSRamuthevar Vadivel Murugan return 0; 158631fb632bSRamuthevar Vadivel Murugan probe_setup_failed: 158731fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 158831fb632bSRamuthevar Vadivel Murugan probe_reset_failed: 158931fb632bSRamuthevar Vadivel Murugan clk_disable_unprepare(cqspi->clk); 159031fb632bSRamuthevar Vadivel Murugan probe_clk_failed: 159131fb632bSRamuthevar Vadivel Murugan pm_runtime_put_sync(dev); 159231fb632bSRamuthevar Vadivel Murugan pm_runtime_disable(dev); 159331fb632bSRamuthevar Vadivel Murugan probe_master_put: 159431fb632bSRamuthevar Vadivel Murugan spi_master_put(master); 159531fb632bSRamuthevar Vadivel Murugan return ret; 159631fb632bSRamuthevar Vadivel Murugan } 159731fb632bSRamuthevar Vadivel Murugan 159831fb632bSRamuthevar Vadivel Murugan static int cqspi_remove(struct platform_device *pdev) 159931fb632bSRamuthevar Vadivel Murugan { 160031fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = platform_get_drvdata(pdev); 160131fb632bSRamuthevar Vadivel Murugan 160231fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 160331fb632bSRamuthevar Vadivel Murugan 160431fb632bSRamuthevar Vadivel Murugan if (cqspi->rx_chan) 160531fb632bSRamuthevar Vadivel Murugan dma_release_channel(cqspi->rx_chan); 160631fb632bSRamuthevar Vadivel Murugan 160731fb632bSRamuthevar Vadivel Murugan clk_disable_unprepare(cqspi->clk); 160831fb632bSRamuthevar Vadivel Murugan 160931fb632bSRamuthevar Vadivel Murugan pm_runtime_put_sync(&pdev->dev); 161031fb632bSRamuthevar Vadivel Murugan pm_runtime_disable(&pdev->dev); 161131fb632bSRamuthevar Vadivel Murugan 161231fb632bSRamuthevar Vadivel Murugan return 0; 161331fb632bSRamuthevar Vadivel Murugan } 161431fb632bSRamuthevar Vadivel Murugan 161531fb632bSRamuthevar Vadivel Murugan #ifdef CONFIG_PM_SLEEP 161631fb632bSRamuthevar Vadivel Murugan static int cqspi_suspend(struct device *dev) 161731fb632bSRamuthevar Vadivel Murugan { 161831fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev_get_drvdata(dev); 161931fb632bSRamuthevar Vadivel Murugan 162031fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0); 162131fb632bSRamuthevar Vadivel Murugan return 0; 162231fb632bSRamuthevar Vadivel Murugan } 162331fb632bSRamuthevar Vadivel Murugan 162431fb632bSRamuthevar Vadivel Murugan static int cqspi_resume(struct device *dev) 162531fb632bSRamuthevar Vadivel Murugan { 162631fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev_get_drvdata(dev); 162731fb632bSRamuthevar Vadivel Murugan 162831fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1); 162931fb632bSRamuthevar Vadivel Murugan return 0; 163031fb632bSRamuthevar Vadivel Murugan } 163131fb632bSRamuthevar Vadivel Murugan 163231fb632bSRamuthevar Vadivel Murugan static const struct dev_pm_ops cqspi__dev_pm_ops = { 163331fb632bSRamuthevar Vadivel Murugan .suspend = cqspi_suspend, 163431fb632bSRamuthevar Vadivel Murugan .resume = cqspi_resume, 163531fb632bSRamuthevar Vadivel Murugan }; 163631fb632bSRamuthevar Vadivel Murugan 163731fb632bSRamuthevar Vadivel Murugan #define CQSPI_DEV_PM_OPS (&cqspi__dev_pm_ops) 163831fb632bSRamuthevar Vadivel Murugan #else 163931fb632bSRamuthevar Vadivel Murugan #define CQSPI_DEV_PM_OPS NULL 164031fb632bSRamuthevar Vadivel Murugan #endif 164131fb632bSRamuthevar Vadivel Murugan 164231fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata cdns_qspi = { 164331fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_DISABLE_DAC_MODE, 164431fb632bSRamuthevar Vadivel Murugan }; 164531fb632bSRamuthevar Vadivel Murugan 164631fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata k2g_qspi = { 164731fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_NEEDS_WR_DELAY, 164831fb632bSRamuthevar Vadivel Murugan }; 164931fb632bSRamuthevar Vadivel Murugan 165031fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata am654_ospi = { 165131fb632bSRamuthevar Vadivel Murugan .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 165231fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_NEEDS_WR_DELAY, 165331fb632bSRamuthevar Vadivel Murugan }; 165431fb632bSRamuthevar Vadivel Murugan 1655ad2775dcSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata intel_lgm_qspi = { 1656ad2775dcSRamuthevar Vadivel Murugan .quirks = CQSPI_DISABLE_DAC_MODE, 1657ad2775dcSRamuthevar Vadivel Murugan }; 1658ad2775dcSRamuthevar Vadivel Murugan 165931fb632bSRamuthevar Vadivel Murugan static const struct of_device_id cqspi_dt_ids[] = { 166031fb632bSRamuthevar Vadivel Murugan { 166131fb632bSRamuthevar Vadivel Murugan .compatible = "cdns,qspi-nor", 166231fb632bSRamuthevar Vadivel Murugan .data = &cdns_qspi, 166331fb632bSRamuthevar Vadivel Murugan }, 166431fb632bSRamuthevar Vadivel Murugan { 166531fb632bSRamuthevar Vadivel Murugan .compatible = "ti,k2g-qspi", 166631fb632bSRamuthevar Vadivel Murugan .data = &k2g_qspi, 166731fb632bSRamuthevar Vadivel Murugan }, 166831fb632bSRamuthevar Vadivel Murugan { 166931fb632bSRamuthevar Vadivel Murugan .compatible = "ti,am654-ospi", 167031fb632bSRamuthevar Vadivel Murugan .data = &am654_ospi, 167131fb632bSRamuthevar Vadivel Murugan }, 1672ab2d2875SRamuthevar Vadivel Murugan { 1673ab2d2875SRamuthevar Vadivel Murugan .compatible = "intel,lgm-qspi", 1674ad2775dcSRamuthevar Vadivel Murugan .data = &intel_lgm_qspi, 1675ab2d2875SRamuthevar Vadivel Murugan }, 167631fb632bSRamuthevar Vadivel Murugan { /* end of table */ } 167731fb632bSRamuthevar Vadivel Murugan }; 167831fb632bSRamuthevar Vadivel Murugan 167931fb632bSRamuthevar Vadivel Murugan MODULE_DEVICE_TABLE(of, cqspi_dt_ids); 168031fb632bSRamuthevar Vadivel Murugan 168131fb632bSRamuthevar Vadivel Murugan static struct platform_driver cqspi_platform_driver = { 168231fb632bSRamuthevar Vadivel Murugan .probe = cqspi_probe, 168331fb632bSRamuthevar Vadivel Murugan .remove = cqspi_remove, 168431fb632bSRamuthevar Vadivel Murugan .driver = { 168531fb632bSRamuthevar Vadivel Murugan .name = CQSPI_NAME, 168631fb632bSRamuthevar Vadivel Murugan .pm = CQSPI_DEV_PM_OPS, 168731fb632bSRamuthevar Vadivel Murugan .of_match_table = cqspi_dt_ids, 168831fb632bSRamuthevar Vadivel Murugan }, 168931fb632bSRamuthevar Vadivel Murugan }; 169031fb632bSRamuthevar Vadivel Murugan 169131fb632bSRamuthevar Vadivel Murugan module_platform_driver(cqspi_platform_driver); 169231fb632bSRamuthevar Vadivel Murugan 169331fb632bSRamuthevar Vadivel Murugan MODULE_DESCRIPTION("Cadence QSPI Controller Driver"); 169431fb632bSRamuthevar Vadivel Murugan MODULE_LICENSE("GPL v2"); 169531fb632bSRamuthevar Vadivel Murugan MODULE_ALIAS("platform:" CQSPI_NAME); 169631fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>"); 169731fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>"); 169831fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>"); 169931fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>"); 1700f453f293SPratyush Yadav MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>"); 1701