1 /* 2 * polling/bitbanging SPI master controller driver utilities 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 */ 18 19 #include <linux/init.h> 20 #include <linux/spinlock.h> 21 #include <linux/workqueue.h> 22 #include <linux/interrupt.h> 23 #include <linux/module.h> 24 #include <linux/delay.h> 25 #include <linux/errno.h> 26 #include <linux/platform_device.h> 27 #include <linux/slab.h> 28 29 #include <linux/spi/spi.h> 30 #include <linux/spi/spi_bitbang.h> 31 32 33 /*----------------------------------------------------------------------*/ 34 35 /* 36 * FIRST PART (OPTIONAL): word-at-a-time spi_transfer support. 37 * Use this for GPIO or shift-register level hardware APIs. 38 * 39 * spi_bitbang_cs is in spi_device->controller_state, which is unavailable 40 * to glue code. These bitbang setup() and cleanup() routines are always 41 * used, though maybe they're called from controller-aware code. 42 * 43 * chipselect() and friends may use spi_device->controller_data and 44 * controller registers as appropriate. 45 * 46 * 47 * NOTE: SPI controller pins can often be used as GPIO pins instead, 48 * which means you could use a bitbang driver either to get hardware 49 * working quickly, or testing for differences that aren't speed related. 50 */ 51 52 struct spi_bitbang_cs { 53 unsigned nsecs; /* (clock cycle time)/2 */ 54 u32 (*txrx_word)(struct spi_device *spi, unsigned nsecs, 55 u32 word, u8 bits); 56 unsigned (*txrx_bufs)(struct spi_device *, 57 u32 (*txrx_word)( 58 struct spi_device *spi, 59 unsigned nsecs, 60 u32 word, u8 bits), 61 unsigned, struct spi_transfer *); 62 }; 63 64 static unsigned bitbang_txrx_8( 65 struct spi_device *spi, 66 u32 (*txrx_word)(struct spi_device *spi, 67 unsigned nsecs, 68 u32 word, u8 bits), 69 unsigned ns, 70 struct spi_transfer *t 71 ) { 72 unsigned bits = t->bits_per_word; 73 unsigned count = t->len; 74 const u8 *tx = t->tx_buf; 75 u8 *rx = t->rx_buf; 76 77 while (likely(count > 0)) { 78 u8 word = 0; 79 80 if (tx) 81 word = *tx++; 82 word = txrx_word(spi, ns, word, bits); 83 if (rx) 84 *rx++ = word; 85 count -= 1; 86 } 87 return t->len - count; 88 } 89 90 static unsigned bitbang_txrx_16( 91 struct spi_device *spi, 92 u32 (*txrx_word)(struct spi_device *spi, 93 unsigned nsecs, 94 u32 word, u8 bits), 95 unsigned ns, 96 struct spi_transfer *t 97 ) { 98 unsigned bits = t->bits_per_word; 99 unsigned count = t->len; 100 const u16 *tx = t->tx_buf; 101 u16 *rx = t->rx_buf; 102 103 while (likely(count > 1)) { 104 u16 word = 0; 105 106 if (tx) 107 word = *tx++; 108 word = txrx_word(spi, ns, word, bits); 109 if (rx) 110 *rx++ = word; 111 count -= 2; 112 } 113 return t->len - count; 114 } 115 116 static unsigned bitbang_txrx_32( 117 struct spi_device *spi, 118 u32 (*txrx_word)(struct spi_device *spi, 119 unsigned nsecs, 120 u32 word, u8 bits), 121 unsigned ns, 122 struct spi_transfer *t 123 ) { 124 unsigned bits = t->bits_per_word; 125 unsigned count = t->len; 126 const u32 *tx = t->tx_buf; 127 u32 *rx = t->rx_buf; 128 129 while (likely(count > 3)) { 130 u32 word = 0; 131 132 if (tx) 133 word = *tx++; 134 word = txrx_word(spi, ns, word, bits); 135 if (rx) 136 *rx++ = word; 137 count -= 4; 138 } 139 return t->len - count; 140 } 141 142 int spi_bitbang_setup_transfer(struct spi_device *spi, struct spi_transfer *t) 143 { 144 struct spi_bitbang_cs *cs = spi->controller_state; 145 u8 bits_per_word; 146 u32 hz; 147 148 if (t) { 149 bits_per_word = t->bits_per_word; 150 hz = t->speed_hz; 151 } else { 152 bits_per_word = 0; 153 hz = 0; 154 } 155 156 /* spi_transfer level calls that work per-word */ 157 if (!bits_per_word) 158 bits_per_word = spi->bits_per_word; 159 if (bits_per_word <= 8) 160 cs->txrx_bufs = bitbang_txrx_8; 161 else if (bits_per_word <= 16) 162 cs->txrx_bufs = bitbang_txrx_16; 163 else if (bits_per_word <= 32) 164 cs->txrx_bufs = bitbang_txrx_32; 165 else 166 return -EINVAL; 167 168 /* nsecs = (clock period)/2 */ 169 if (!hz) 170 hz = spi->max_speed_hz; 171 if (hz) { 172 cs->nsecs = (1000000000/2) / hz; 173 if (cs->nsecs > (MAX_UDELAY_MS * 1000 * 1000)) 174 return -EINVAL; 175 } 176 177 return 0; 178 } 179 EXPORT_SYMBOL_GPL(spi_bitbang_setup_transfer); 180 181 /** 182 * spi_bitbang_setup - default setup for per-word I/O loops 183 */ 184 int spi_bitbang_setup(struct spi_device *spi) 185 { 186 struct spi_bitbang_cs *cs = spi->controller_state; 187 struct spi_bitbang *bitbang; 188 int retval; 189 unsigned long flags; 190 191 bitbang = spi_master_get_devdata(spi->master); 192 193 if (!cs) { 194 cs = kzalloc(sizeof(*cs), GFP_KERNEL); 195 if (!cs) 196 return -ENOMEM; 197 spi->controller_state = cs; 198 } 199 200 /* per-word shift register access, in hardware or bitbanging */ 201 cs->txrx_word = bitbang->txrx_word[spi->mode & (SPI_CPOL|SPI_CPHA)]; 202 if (!cs->txrx_word) 203 return -EINVAL; 204 205 retval = bitbang->setup_transfer(spi, NULL); 206 if (retval < 0) 207 return retval; 208 209 dev_dbg(&spi->dev, "%s, %u nsec/bit\n", __func__, 2 * cs->nsecs); 210 211 /* NOTE we _need_ to call chipselect() early, ideally with adapter 212 * setup, unless the hardware defaults cooperate to avoid confusion 213 * between normal (active low) and inverted chipselects. 214 */ 215 216 /* deselect chip (low or high) */ 217 spin_lock_irqsave(&bitbang->lock, flags); 218 if (!bitbang->busy) { 219 bitbang->chipselect(spi, BITBANG_CS_INACTIVE); 220 ndelay(cs->nsecs); 221 } 222 spin_unlock_irqrestore(&bitbang->lock, flags); 223 224 return 0; 225 } 226 EXPORT_SYMBOL_GPL(spi_bitbang_setup); 227 228 /** 229 * spi_bitbang_cleanup - default cleanup for per-word I/O loops 230 */ 231 void spi_bitbang_cleanup(struct spi_device *spi) 232 { 233 kfree(spi->controller_state); 234 } 235 EXPORT_SYMBOL_GPL(spi_bitbang_cleanup); 236 237 static int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t) 238 { 239 struct spi_bitbang_cs *cs = spi->controller_state; 240 unsigned nsecs = cs->nsecs; 241 242 return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t); 243 } 244 245 /*----------------------------------------------------------------------*/ 246 247 /* 248 * SECOND PART ... simple transfer queue runner. 249 * 250 * This costs a task context per controller, running the queue by 251 * performing each transfer in sequence. Smarter hardware can queue 252 * several DMA transfers at once, and process several controller queues 253 * in parallel; this driver doesn't match such hardware very well. 254 * 255 * Drivers can provide word-at-a-time i/o primitives, or provide 256 * transfer-at-a-time ones to leverage dma or fifo hardware. 257 */ 258 259 static int spi_bitbang_prepare_hardware(struct spi_master *spi) 260 { 261 struct spi_bitbang *bitbang; 262 unsigned long flags; 263 264 bitbang = spi_master_get_devdata(spi); 265 266 spin_lock_irqsave(&bitbang->lock, flags); 267 bitbang->busy = 1; 268 spin_unlock_irqrestore(&bitbang->lock, flags); 269 270 return 0; 271 } 272 273 static int spi_bitbang_transfer_one(struct spi_master *master, 274 struct spi_message *m) 275 { 276 struct spi_bitbang *bitbang; 277 unsigned nsecs; 278 struct spi_transfer *t = NULL; 279 unsigned cs_change; 280 int status; 281 int do_setup = -1; 282 struct spi_device *spi = m->spi; 283 284 bitbang = spi_master_get_devdata(master); 285 286 /* FIXME this is made-up ... the correct value is known to 287 * word-at-a-time bitbang code, and presumably chipselect() 288 * should enforce these requirements too? 289 */ 290 nsecs = 100; 291 292 cs_change = 1; 293 status = 0; 294 295 list_for_each_entry(t, &m->transfers, transfer_list) { 296 297 /* override speed or wordsize? */ 298 if (t->speed_hz || t->bits_per_word) 299 do_setup = 1; 300 301 /* init (-1) or override (1) transfer params */ 302 if (do_setup != 0) { 303 status = bitbang->setup_transfer(spi, t); 304 if (status < 0) 305 break; 306 if (do_setup == -1) 307 do_setup = 0; 308 } 309 310 /* set up default clock polarity, and activate chip; 311 * this implicitly updates clock and spi modes as 312 * previously recorded for this device via setup(). 313 * (and also deselects any other chip that might be 314 * selected ...) 315 */ 316 if (cs_change) { 317 bitbang->chipselect(spi, BITBANG_CS_ACTIVE); 318 ndelay(nsecs); 319 } 320 cs_change = t->cs_change; 321 if (!t->tx_buf && !t->rx_buf && t->len) { 322 status = -EINVAL; 323 break; 324 } 325 326 /* transfer data. the lower level code handles any 327 * new dma mappings it needs. our caller always gave 328 * us dma-safe buffers. 329 */ 330 if (t->len) { 331 /* REVISIT dma API still needs a designated 332 * DMA_ADDR_INVALID; ~0 might be better. 333 */ 334 if (!m->is_dma_mapped) 335 t->rx_dma = t->tx_dma = 0; 336 status = bitbang->txrx_bufs(spi, t); 337 } 338 if (status > 0) 339 m->actual_length += status; 340 if (status != t->len) { 341 /* always report some kind of error */ 342 if (status >= 0) 343 status = -EREMOTEIO; 344 break; 345 } 346 status = 0; 347 348 /* protocol tweaks before next transfer */ 349 if (t->delay_usecs) 350 udelay(t->delay_usecs); 351 352 if (cs_change && 353 !list_is_last(&t->transfer_list, &m->transfers)) { 354 /* sometimes a short mid-message deselect of the chip 355 * may be needed to terminate a mode or command 356 */ 357 ndelay(nsecs); 358 bitbang->chipselect(spi, BITBANG_CS_INACTIVE); 359 ndelay(nsecs); 360 } 361 } 362 363 m->status = status; 364 365 /* normally deactivate chipselect ... unless no error and 366 * cs_change has hinted that the next message will probably 367 * be for this chip too. 368 */ 369 if (!(status == 0 && cs_change)) { 370 ndelay(nsecs); 371 bitbang->chipselect(spi, BITBANG_CS_INACTIVE); 372 ndelay(nsecs); 373 } 374 375 spi_finalize_current_message(master); 376 377 return status; 378 } 379 380 static int spi_bitbang_unprepare_hardware(struct spi_master *spi) 381 { 382 struct spi_bitbang *bitbang; 383 unsigned long flags; 384 385 bitbang = spi_master_get_devdata(spi); 386 387 spin_lock_irqsave(&bitbang->lock, flags); 388 bitbang->busy = 0; 389 spin_unlock_irqrestore(&bitbang->lock, flags); 390 391 return 0; 392 } 393 394 /*----------------------------------------------------------------------*/ 395 396 /** 397 * spi_bitbang_start - start up a polled/bitbanging SPI master driver 398 * @bitbang: driver handle 399 * 400 * Caller should have zero-initialized all parts of the structure, and then 401 * provided callbacks for chip selection and I/O loops. If the master has 402 * a transfer method, its final step should call spi_bitbang_transfer; or, 403 * that's the default if the transfer routine is not initialized. It should 404 * also set up the bus number and number of chipselects. 405 * 406 * For i/o loops, provide callbacks either per-word (for bitbanging, or for 407 * hardware that basically exposes a shift register) or per-spi_transfer 408 * (which takes better advantage of hardware like fifos or DMA engines). 409 * 410 * Drivers using per-word I/O loops should use (or call) spi_bitbang_setup, 411 * spi_bitbang_cleanup and spi_bitbang_setup_transfer to handle those spi 412 * master methods. Those methods are the defaults if the bitbang->txrx_bufs 413 * routine isn't initialized. 414 * 415 * This routine registers the spi_master, which will process requests in a 416 * dedicated task, keeping IRQs unblocked most of the time. To stop 417 * processing those requests, call spi_bitbang_stop(). 418 * 419 * On success, this routine will take a reference to master. The caller is 420 * responsible for calling spi_bitbang_stop() to decrement the reference and 421 * spi_master_put() as counterpart of spi_alloc_master() to prevent a memory 422 * leak. 423 */ 424 int spi_bitbang_start(struct spi_bitbang *bitbang) 425 { 426 struct spi_master *master = bitbang->master; 427 int ret; 428 429 if (!master || !bitbang->chipselect) 430 return -EINVAL; 431 432 spin_lock_init(&bitbang->lock); 433 434 if (!master->mode_bits) 435 master->mode_bits = SPI_CPOL | SPI_CPHA | bitbang->flags; 436 437 if (master->transfer || master->transfer_one_message) 438 return -EINVAL; 439 440 master->prepare_transfer_hardware = spi_bitbang_prepare_hardware; 441 master->unprepare_transfer_hardware = spi_bitbang_unprepare_hardware; 442 master->transfer_one_message = spi_bitbang_transfer_one; 443 444 if (!bitbang->txrx_bufs) { 445 bitbang->use_dma = 0; 446 bitbang->txrx_bufs = spi_bitbang_bufs; 447 if (!master->setup) { 448 if (!bitbang->setup_transfer) 449 bitbang->setup_transfer = 450 spi_bitbang_setup_transfer; 451 master->setup = spi_bitbang_setup; 452 master->cleanup = spi_bitbang_cleanup; 453 } 454 } 455 456 /* driver may get busy before register() returns, especially 457 * if someone registered boardinfo for devices 458 */ 459 ret = spi_register_master(spi_master_get(master)); 460 if (ret) 461 spi_master_put(master); 462 463 return 0; 464 } 465 EXPORT_SYMBOL_GPL(spi_bitbang_start); 466 467 /** 468 * spi_bitbang_stop - stops the task providing spi communication 469 */ 470 int spi_bitbang_stop(struct spi_bitbang *bitbang) 471 { 472 spi_unregister_master(bitbang->master); 473 474 return 0; 475 } 476 EXPORT_SYMBOL_GPL(spi_bitbang_stop); 477 478 MODULE_LICENSE("GPL"); 479 480