1 /* 2 * Broadcom BCM63xx SPI controller support 3 * 4 * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org> 5 * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 2 10 * of the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/clk.h> 20 #include <linux/io.h> 21 #include <linux/module.h> 22 #include <linux/platform_device.h> 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/spi/spi.h> 26 #include <linux/completion.h> 27 #include <linux/err.h> 28 #include <linux/pm_runtime.h> 29 30 #include <bcm63xx_dev_spi.h> 31 32 #define BCM63XX_SPI_MAX_PREPEND 15 33 34 #define BCM63XX_SPI_MAX_CS 8 35 #define BCM63XX_SPI_BUS_NUM 0 36 37 struct bcm63xx_spi { 38 struct completion done; 39 40 void __iomem *regs; 41 int irq; 42 43 /* Platform data */ 44 unsigned fifo_size; 45 unsigned int msg_type_shift; 46 unsigned int msg_ctl_width; 47 48 /* data iomem */ 49 u8 __iomem *tx_io; 50 const u8 __iomem *rx_io; 51 52 struct clk *clk; 53 struct platform_device *pdev; 54 }; 55 56 static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs, 57 unsigned int offset) 58 { 59 return readb(bs->regs + bcm63xx_spireg(offset)); 60 } 61 62 static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs, 63 unsigned int offset) 64 { 65 #ifdef CONFIG_CPU_BIG_ENDIAN 66 return ioread16be(bs->regs + bcm63xx_spireg(offset)); 67 #else 68 return readw(bs->regs + bcm63xx_spireg(offset)); 69 #endif 70 } 71 72 static inline void bcm_spi_writeb(struct bcm63xx_spi *bs, 73 u8 value, unsigned int offset) 74 { 75 writeb(value, bs->regs + bcm63xx_spireg(offset)); 76 } 77 78 static inline void bcm_spi_writew(struct bcm63xx_spi *bs, 79 u16 value, unsigned int offset) 80 { 81 #ifdef CONFIG_CPU_BIG_ENDIAN 82 iowrite16be(value, bs->regs + bcm63xx_spireg(offset)); 83 #else 84 writew(value, bs->regs + bcm63xx_spireg(offset)); 85 #endif 86 } 87 88 static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = { 89 { 20000000, SPI_CLK_20MHZ }, 90 { 12500000, SPI_CLK_12_50MHZ }, 91 { 6250000, SPI_CLK_6_250MHZ }, 92 { 3125000, SPI_CLK_3_125MHZ }, 93 { 1563000, SPI_CLK_1_563MHZ }, 94 { 781000, SPI_CLK_0_781MHZ }, 95 { 391000, SPI_CLK_0_391MHZ } 96 }; 97 98 static void bcm63xx_spi_setup_transfer(struct spi_device *spi, 99 struct spi_transfer *t) 100 { 101 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); 102 u8 clk_cfg, reg; 103 int i; 104 105 /* Find the closest clock configuration */ 106 for (i = 0; i < SPI_CLK_MASK; i++) { 107 if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) { 108 clk_cfg = bcm63xx_spi_freq_table[i][1]; 109 break; 110 } 111 } 112 113 /* No matching configuration found, default to lowest */ 114 if (i == SPI_CLK_MASK) 115 clk_cfg = SPI_CLK_0_391MHZ; 116 117 /* clear existing clock configuration bits of the register */ 118 reg = bcm_spi_readb(bs, SPI_CLK_CFG); 119 reg &= ~SPI_CLK_MASK; 120 reg |= clk_cfg; 121 122 bcm_spi_writeb(bs, reg, SPI_CLK_CFG); 123 dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n", 124 clk_cfg, t->speed_hz); 125 } 126 127 /* the spi->mode bits understood by this driver: */ 128 #define MODEBITS (SPI_CPOL | SPI_CPHA) 129 130 static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first, 131 unsigned int num_transfers) 132 { 133 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); 134 u16 msg_ctl; 135 u16 cmd; 136 unsigned int i, timeout = 0, prepend_len = 0, len = 0; 137 struct spi_transfer *t = first; 138 bool do_rx = false; 139 bool do_tx = false; 140 141 /* Disable the CMD_DONE interrupt */ 142 bcm_spi_writeb(bs, 0, SPI_INT_MASK); 143 144 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", 145 t->tx_buf, t->rx_buf, t->len); 146 147 if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND) 148 prepend_len = t->len; 149 150 /* prepare the buffer */ 151 for (i = 0; i < num_transfers; i++) { 152 if (t->tx_buf) { 153 do_tx = true; 154 memcpy_toio(bs->tx_io + len, t->tx_buf, t->len); 155 156 /* don't prepend more than one tx */ 157 if (t != first) 158 prepend_len = 0; 159 } 160 161 if (t->rx_buf) { 162 do_rx = true; 163 /* prepend is half-duplex write only */ 164 if (t == first) 165 prepend_len = 0; 166 } 167 168 len += t->len; 169 170 t = list_entry(t->transfer_list.next, struct spi_transfer, 171 transfer_list); 172 } 173 174 reinit_completion(&bs->done); 175 176 /* Fill in the Message control register */ 177 msg_ctl = (len << SPI_BYTE_CNT_SHIFT); 178 179 if (do_rx && do_tx && prepend_len == 0) 180 msg_ctl |= (SPI_FD_RW << bs->msg_type_shift); 181 else if (do_rx) 182 msg_ctl |= (SPI_HD_R << bs->msg_type_shift); 183 else if (do_tx) 184 msg_ctl |= (SPI_HD_W << bs->msg_type_shift); 185 186 switch (bs->msg_ctl_width) { 187 case 8: 188 bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL); 189 break; 190 case 16: 191 bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL); 192 break; 193 } 194 195 /* Issue the transfer */ 196 cmd = SPI_CMD_START_IMMEDIATE; 197 cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT); 198 cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT); 199 bcm_spi_writew(bs, cmd, SPI_CMD); 200 201 /* Enable the CMD_DONE interrupt */ 202 bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK); 203 204 timeout = wait_for_completion_timeout(&bs->done, HZ); 205 if (!timeout) 206 return -ETIMEDOUT; 207 208 if (!do_rx) 209 return 0; 210 211 len = 0; 212 t = first; 213 /* Read out all the data */ 214 for (i = 0; i < num_transfers; i++) { 215 if (t->rx_buf) 216 memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len); 217 218 if (t != first || prepend_len == 0) 219 len += t->len; 220 221 t = list_entry(t->transfer_list.next, struct spi_transfer, 222 transfer_list); 223 } 224 225 return 0; 226 } 227 228 static int bcm63xx_spi_transfer_one(struct spi_master *master, 229 struct spi_message *m) 230 { 231 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 232 struct spi_transfer *t, *first = NULL; 233 struct spi_device *spi = m->spi; 234 int status = 0; 235 unsigned int n_transfers = 0, total_len = 0; 236 bool can_use_prepend = false; 237 238 /* 239 * This SPI controller does not support keeping CS active after a 240 * transfer. 241 * Work around this by merging as many transfers we can into one big 242 * full-duplex transfers. 243 */ 244 list_for_each_entry(t, &m->transfers, transfer_list) { 245 if (!first) 246 first = t; 247 248 n_transfers++; 249 total_len += t->len; 250 251 if (n_transfers == 2 && !first->rx_buf && !t->tx_buf && 252 first->len <= BCM63XX_SPI_MAX_PREPEND) 253 can_use_prepend = true; 254 else if (can_use_prepend && t->tx_buf) 255 can_use_prepend = false; 256 257 /* we can only transfer one fifo worth of data */ 258 if ((can_use_prepend && 259 total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) || 260 (!can_use_prepend && total_len > bs->fifo_size)) { 261 dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n", 262 total_len, bs->fifo_size); 263 status = -EINVAL; 264 goto exit; 265 } 266 267 /* all combined transfers have to have the same speed */ 268 if (t->speed_hz != first->speed_hz) { 269 dev_err(&spi->dev, "unable to change speed between transfers\n"); 270 status = -EINVAL; 271 goto exit; 272 } 273 274 /* CS will be deasserted directly after transfer */ 275 if (t->delay_usecs) { 276 dev_err(&spi->dev, "unable to keep CS asserted after transfer\n"); 277 status = -EINVAL; 278 goto exit; 279 } 280 281 if (t->cs_change || 282 list_is_last(&t->transfer_list, &m->transfers)) { 283 /* configure adapter for a new transfer */ 284 bcm63xx_spi_setup_transfer(spi, first); 285 286 /* send the data */ 287 status = bcm63xx_txrx_bufs(spi, first, n_transfers); 288 if (status) 289 goto exit; 290 291 m->actual_length += total_len; 292 293 first = NULL; 294 n_transfers = 0; 295 total_len = 0; 296 can_use_prepend = false; 297 } 298 } 299 exit: 300 m->status = status; 301 spi_finalize_current_message(master); 302 303 return 0; 304 } 305 306 /* This driver supports single master mode only. Hence 307 * CMD_DONE is the only interrupt we care about 308 */ 309 static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id) 310 { 311 struct spi_master *master = (struct spi_master *)dev_id; 312 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 313 u8 intr; 314 315 /* Read interupts and clear them immediately */ 316 intr = bcm_spi_readb(bs, SPI_INT_STATUS); 317 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); 318 bcm_spi_writeb(bs, 0, SPI_INT_MASK); 319 320 /* A transfer completed */ 321 if (intr & SPI_INTR_CMD_DONE) 322 complete(&bs->done); 323 324 return IRQ_HANDLED; 325 } 326 327 328 static int bcm63xx_spi_probe(struct platform_device *pdev) 329 { 330 struct resource *r; 331 struct device *dev = &pdev->dev; 332 int irq; 333 struct spi_master *master; 334 struct clk *clk; 335 struct bcm63xx_spi *bs; 336 int ret; 337 338 irq = platform_get_irq(pdev, 0); 339 if (irq < 0) { 340 dev_err(dev, "no irq\n"); 341 return -ENXIO; 342 } 343 344 clk = devm_clk_get(dev, "spi"); 345 if (IS_ERR(clk)) { 346 dev_err(dev, "no clock for device\n"); 347 return PTR_ERR(clk); 348 } 349 350 master = spi_alloc_master(dev, sizeof(*bs)); 351 if (!master) { 352 dev_err(dev, "out of memory\n"); 353 return -ENOMEM; 354 } 355 356 bs = spi_master_get_devdata(master); 357 init_completion(&bs->done); 358 359 platform_set_drvdata(pdev, master); 360 bs->pdev = pdev; 361 362 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 363 bs->regs = devm_ioremap_resource(&pdev->dev, r); 364 if (IS_ERR(bs->regs)) { 365 ret = PTR_ERR(bs->regs); 366 goto out_err; 367 } 368 369 bs->irq = irq; 370 bs->clk = clk; 371 bs->fifo_size = bcm63xx_spireg(SPI_MSG_DATA_SIZE); 372 373 ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0, 374 pdev->name, master); 375 if (ret) { 376 dev_err(dev, "unable to request irq\n"); 377 goto out_err; 378 } 379 380 master->bus_num = BCM63XX_SPI_BUS_NUM; 381 master->num_chipselect = BCM63XX_SPI_MAX_CS; 382 master->transfer_one_message = bcm63xx_spi_transfer_one; 383 master->mode_bits = MODEBITS; 384 master->bits_per_word_mask = SPI_BPW_MASK(8); 385 master->auto_runtime_pm = true; 386 bs->msg_type_shift = bcm63xx_spireg(SPI_MSG_TYPE_SHIFT); 387 bs->msg_ctl_width = bcm63xx_spireg(SPI_MSG_CTL_WIDTH); 388 bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA)); 389 bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA)); 390 391 switch (bs->msg_ctl_width) { 392 case 8: 393 case 16: 394 break; 395 default: 396 dev_err(dev, "unsupported MSG_CTL width: %d\n", 397 bs->msg_ctl_width); 398 goto out_err; 399 } 400 401 /* Initialize hardware */ 402 ret = clk_prepare_enable(bs->clk); 403 if (ret) 404 goto out_err; 405 406 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); 407 408 /* register and we are done */ 409 ret = devm_spi_register_master(dev, master); 410 if (ret) { 411 dev_err(dev, "spi register failed\n"); 412 goto out_clk_disable; 413 } 414 415 dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n", 416 r->start, irq, bs->fifo_size); 417 418 return 0; 419 420 out_clk_disable: 421 clk_disable_unprepare(clk); 422 out_err: 423 spi_master_put(master); 424 return ret; 425 } 426 427 static int bcm63xx_spi_remove(struct platform_device *pdev) 428 { 429 struct spi_master *master = platform_get_drvdata(pdev); 430 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 431 432 /* reset spi block */ 433 bcm_spi_writeb(bs, 0, SPI_INT_MASK); 434 435 /* HW shutdown */ 436 clk_disable_unprepare(bs->clk); 437 438 return 0; 439 } 440 441 #ifdef CONFIG_PM_SLEEP 442 static int bcm63xx_spi_suspend(struct device *dev) 443 { 444 struct spi_master *master = dev_get_drvdata(dev); 445 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 446 447 spi_master_suspend(master); 448 449 clk_disable_unprepare(bs->clk); 450 451 return 0; 452 } 453 454 static int bcm63xx_spi_resume(struct device *dev) 455 { 456 struct spi_master *master = dev_get_drvdata(dev); 457 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 458 int ret; 459 460 ret = clk_prepare_enable(bs->clk); 461 if (ret) 462 return ret; 463 464 spi_master_resume(master); 465 466 return 0; 467 } 468 #endif 469 470 static const struct dev_pm_ops bcm63xx_spi_pm_ops = { 471 SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_spi_suspend, bcm63xx_spi_resume) 472 }; 473 474 static struct platform_driver bcm63xx_spi_driver = { 475 .driver = { 476 .name = "bcm63xx-spi", 477 .pm = &bcm63xx_spi_pm_ops, 478 }, 479 .probe = bcm63xx_spi_probe, 480 .remove = bcm63xx_spi_remove, 481 }; 482 483 module_platform_driver(bcm63xx_spi_driver); 484 485 MODULE_ALIAS("platform:bcm63xx_spi"); 486 MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>"); 487 MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>"); 488 MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver"); 489 MODULE_LICENSE("GPL"); 490