1 /* 2 * Broadcom BCM63xx SPI controller support 3 * 4 * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org> 5 * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 2 10 * of the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the 19 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/clk.h> 24 #include <linux/io.h> 25 #include <linux/module.h> 26 #include <linux/platform_device.h> 27 #include <linux/delay.h> 28 #include <linux/interrupt.h> 29 #include <linux/spi/spi.h> 30 #include <linux/completion.h> 31 #include <linux/err.h> 32 #include <linux/workqueue.h> 33 #include <linux/pm_runtime.h> 34 35 #include <bcm63xx_dev_spi.h> 36 37 #define BCM63XX_SPI_MAX_PREPEND 15 38 39 struct bcm63xx_spi { 40 struct completion done; 41 42 void __iomem *regs; 43 int irq; 44 45 /* Platform data */ 46 unsigned fifo_size; 47 unsigned int msg_type_shift; 48 unsigned int msg_ctl_width; 49 50 /* data iomem */ 51 u8 __iomem *tx_io; 52 const u8 __iomem *rx_io; 53 54 struct clk *clk; 55 struct platform_device *pdev; 56 }; 57 58 static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs, 59 unsigned int offset) 60 { 61 return bcm_readb(bs->regs + bcm63xx_spireg(offset)); 62 } 63 64 static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs, 65 unsigned int offset) 66 { 67 return bcm_readw(bs->regs + bcm63xx_spireg(offset)); 68 } 69 70 static inline void bcm_spi_writeb(struct bcm63xx_spi *bs, 71 u8 value, unsigned int offset) 72 { 73 bcm_writeb(value, bs->regs + bcm63xx_spireg(offset)); 74 } 75 76 static inline void bcm_spi_writew(struct bcm63xx_spi *bs, 77 u16 value, unsigned int offset) 78 { 79 bcm_writew(value, bs->regs + bcm63xx_spireg(offset)); 80 } 81 82 static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = { 83 { 20000000, SPI_CLK_20MHZ }, 84 { 12500000, SPI_CLK_12_50MHZ }, 85 { 6250000, SPI_CLK_6_250MHZ }, 86 { 3125000, SPI_CLK_3_125MHZ }, 87 { 1563000, SPI_CLK_1_563MHZ }, 88 { 781000, SPI_CLK_0_781MHZ }, 89 { 391000, SPI_CLK_0_391MHZ } 90 }; 91 92 static void bcm63xx_spi_setup_transfer(struct spi_device *spi, 93 struct spi_transfer *t) 94 { 95 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); 96 u8 clk_cfg, reg; 97 int i; 98 99 /* Find the closest clock configuration */ 100 for (i = 0; i < SPI_CLK_MASK; i++) { 101 if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) { 102 clk_cfg = bcm63xx_spi_freq_table[i][1]; 103 break; 104 } 105 } 106 107 /* No matching configuration found, default to lowest */ 108 if (i == SPI_CLK_MASK) 109 clk_cfg = SPI_CLK_0_391MHZ; 110 111 /* clear existing clock configuration bits of the register */ 112 reg = bcm_spi_readb(bs, SPI_CLK_CFG); 113 reg &= ~SPI_CLK_MASK; 114 reg |= clk_cfg; 115 116 bcm_spi_writeb(bs, reg, SPI_CLK_CFG); 117 dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n", 118 clk_cfg, t->speed_hz); 119 } 120 121 /* the spi->mode bits understood by this driver: */ 122 #define MODEBITS (SPI_CPOL | SPI_CPHA) 123 124 static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first, 125 unsigned int num_transfers) 126 { 127 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); 128 u16 msg_ctl; 129 u16 cmd; 130 u8 rx_tail; 131 unsigned int i, timeout = 0, prepend_len = 0, len = 0; 132 struct spi_transfer *t = first; 133 bool do_rx = false; 134 bool do_tx = false; 135 136 /* Disable the CMD_DONE interrupt */ 137 bcm_spi_writeb(bs, 0, SPI_INT_MASK); 138 139 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", 140 t->tx_buf, t->rx_buf, t->len); 141 142 if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND) 143 prepend_len = t->len; 144 145 /* prepare the buffer */ 146 for (i = 0; i < num_transfers; i++) { 147 if (t->tx_buf) { 148 do_tx = true; 149 memcpy_toio(bs->tx_io + len, t->tx_buf, t->len); 150 151 /* don't prepend more than one tx */ 152 if (t != first) 153 prepend_len = 0; 154 } 155 156 if (t->rx_buf) { 157 do_rx = true; 158 /* prepend is half-duplex write only */ 159 if (t == first) 160 prepend_len = 0; 161 } 162 163 len += t->len; 164 165 t = list_entry(t->transfer_list.next, struct spi_transfer, 166 transfer_list); 167 } 168 169 reinit_completion(&bs->done); 170 171 /* Fill in the Message control register */ 172 msg_ctl = (len << SPI_BYTE_CNT_SHIFT); 173 174 if (do_rx && do_tx && prepend_len == 0) 175 msg_ctl |= (SPI_FD_RW << bs->msg_type_shift); 176 else if (do_rx) 177 msg_ctl |= (SPI_HD_R << bs->msg_type_shift); 178 else if (do_tx) 179 msg_ctl |= (SPI_HD_W << bs->msg_type_shift); 180 181 switch (bs->msg_ctl_width) { 182 case 8: 183 bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL); 184 break; 185 case 16: 186 bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL); 187 break; 188 } 189 190 /* Issue the transfer */ 191 cmd = SPI_CMD_START_IMMEDIATE; 192 cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT); 193 cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT); 194 bcm_spi_writew(bs, cmd, SPI_CMD); 195 196 /* Enable the CMD_DONE interrupt */ 197 bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK); 198 199 timeout = wait_for_completion_timeout(&bs->done, HZ); 200 if (!timeout) 201 return -ETIMEDOUT; 202 203 if (!do_rx) 204 return 0; 205 206 len = 0; 207 t = first; 208 /* Read out all the data */ 209 for (i = 0; i < num_transfers; i++) { 210 if (t->rx_buf) 211 memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len); 212 213 if (t != first || prepend_len == 0) 214 len += t->len; 215 216 t = list_entry(t->transfer_list.next, struct spi_transfer, 217 transfer_list); 218 } 219 220 return 0; 221 } 222 223 static int bcm63xx_spi_transfer_one(struct spi_master *master, 224 struct spi_message *m) 225 { 226 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 227 struct spi_transfer *t, *first = NULL; 228 struct spi_device *spi = m->spi; 229 int status = 0; 230 unsigned int n_transfers = 0, total_len = 0; 231 bool can_use_prepend = false; 232 233 /* 234 * This SPI controller does not support keeping CS active after a 235 * transfer. 236 * Work around this by merging as many transfers we can into one big 237 * full-duplex transfers. 238 */ 239 list_for_each_entry(t, &m->transfers, transfer_list) { 240 if (!first) 241 first = t; 242 243 n_transfers++; 244 total_len += t->len; 245 246 if (n_transfers == 2 && !first->rx_buf && !t->tx_buf && 247 first->len <= BCM63XX_SPI_MAX_PREPEND) 248 can_use_prepend = true; 249 else if (can_use_prepend && t->tx_buf) 250 can_use_prepend = false; 251 252 /* we can only transfer one fifo worth of data */ 253 if ((can_use_prepend && 254 total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) || 255 (!can_use_prepend && total_len > bs->fifo_size)) { 256 dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n", 257 total_len, bs->fifo_size); 258 status = -EINVAL; 259 goto exit; 260 } 261 262 /* all combined transfers have to have the same speed */ 263 if (t->speed_hz != first->speed_hz) { 264 dev_err(&spi->dev, "unable to change speed between transfers\n"); 265 status = -EINVAL; 266 goto exit; 267 } 268 269 /* CS will be deasserted directly after transfer */ 270 if (t->delay_usecs) { 271 dev_err(&spi->dev, "unable to keep CS asserted after transfer\n"); 272 status = -EINVAL; 273 goto exit; 274 } 275 276 if (t->cs_change || 277 list_is_last(&t->transfer_list, &m->transfers)) { 278 /* configure adapter for a new transfer */ 279 bcm63xx_spi_setup_transfer(spi, first); 280 281 /* send the data */ 282 status = bcm63xx_txrx_bufs(spi, first, n_transfers); 283 if (status) 284 goto exit; 285 286 m->actual_length += total_len; 287 288 first = NULL; 289 n_transfers = 0; 290 total_len = 0; 291 can_use_prepend = false; 292 } 293 } 294 exit: 295 m->status = status; 296 spi_finalize_current_message(master); 297 298 return 0; 299 } 300 301 /* This driver supports single master mode only. Hence 302 * CMD_DONE is the only interrupt we care about 303 */ 304 static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id) 305 { 306 struct spi_master *master = (struct spi_master *)dev_id; 307 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 308 u8 intr; 309 310 /* Read interupts and clear them immediately */ 311 intr = bcm_spi_readb(bs, SPI_INT_STATUS); 312 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); 313 bcm_spi_writeb(bs, 0, SPI_INT_MASK); 314 315 /* A transfer completed */ 316 if (intr & SPI_INTR_CMD_DONE) 317 complete(&bs->done); 318 319 return IRQ_HANDLED; 320 } 321 322 323 static int bcm63xx_spi_probe(struct platform_device *pdev) 324 { 325 struct resource *r; 326 struct device *dev = &pdev->dev; 327 struct bcm63xx_spi_pdata *pdata = dev_get_platdata(&pdev->dev); 328 int irq; 329 struct spi_master *master; 330 struct clk *clk; 331 struct bcm63xx_spi *bs; 332 int ret; 333 334 irq = platform_get_irq(pdev, 0); 335 if (irq < 0) { 336 dev_err(dev, "no irq\n"); 337 return -ENXIO; 338 } 339 340 clk = devm_clk_get(dev, "spi"); 341 if (IS_ERR(clk)) { 342 dev_err(dev, "no clock for device\n"); 343 return PTR_ERR(clk); 344 } 345 346 master = spi_alloc_master(dev, sizeof(*bs)); 347 if (!master) { 348 dev_err(dev, "out of memory\n"); 349 return -ENOMEM; 350 } 351 352 bs = spi_master_get_devdata(master); 353 init_completion(&bs->done); 354 355 platform_set_drvdata(pdev, master); 356 bs->pdev = pdev; 357 358 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 359 bs->regs = devm_ioremap_resource(&pdev->dev, r); 360 if (IS_ERR(bs->regs)) { 361 ret = PTR_ERR(bs->regs); 362 goto out_err; 363 } 364 365 bs->irq = irq; 366 bs->clk = clk; 367 bs->fifo_size = pdata->fifo_size; 368 369 ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0, 370 pdev->name, master); 371 if (ret) { 372 dev_err(dev, "unable to request irq\n"); 373 goto out_err; 374 } 375 376 master->bus_num = pdata->bus_num; 377 master->num_chipselect = pdata->num_chipselect; 378 master->transfer_one_message = bcm63xx_spi_transfer_one; 379 master->mode_bits = MODEBITS; 380 master->bits_per_word_mask = SPI_BPW_MASK(8); 381 master->auto_runtime_pm = true; 382 bs->msg_type_shift = pdata->msg_type_shift; 383 bs->msg_ctl_width = pdata->msg_ctl_width; 384 bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA)); 385 bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA)); 386 387 switch (bs->msg_ctl_width) { 388 case 8: 389 case 16: 390 break; 391 default: 392 dev_err(dev, "unsupported MSG_CTL width: %d\n", 393 bs->msg_ctl_width); 394 goto out_err; 395 } 396 397 /* Initialize hardware */ 398 ret = clk_prepare_enable(bs->clk); 399 if (ret) 400 goto out_err; 401 402 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); 403 404 /* register and we are done */ 405 ret = devm_spi_register_master(dev, master); 406 if (ret) { 407 dev_err(dev, "spi register failed\n"); 408 goto out_clk_disable; 409 } 410 411 dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n", 412 r->start, irq, bs->fifo_size); 413 414 return 0; 415 416 out_clk_disable: 417 clk_disable_unprepare(clk); 418 out_err: 419 spi_master_put(master); 420 return ret; 421 } 422 423 static int bcm63xx_spi_remove(struct platform_device *pdev) 424 { 425 struct spi_master *master = platform_get_drvdata(pdev); 426 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 427 428 /* reset spi block */ 429 bcm_spi_writeb(bs, 0, SPI_INT_MASK); 430 431 /* HW shutdown */ 432 clk_disable_unprepare(bs->clk); 433 434 return 0; 435 } 436 437 #ifdef CONFIG_PM_SLEEP 438 static int bcm63xx_spi_suspend(struct device *dev) 439 { 440 struct spi_master *master = dev_get_drvdata(dev); 441 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 442 443 spi_master_suspend(master); 444 445 clk_disable_unprepare(bs->clk); 446 447 return 0; 448 } 449 450 static int bcm63xx_spi_resume(struct device *dev) 451 { 452 struct spi_master *master = dev_get_drvdata(dev); 453 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 454 int ret; 455 456 ret = clk_prepare_enable(bs->clk); 457 if (ret) 458 return ret; 459 460 spi_master_resume(master); 461 462 return 0; 463 } 464 #endif 465 466 static const struct dev_pm_ops bcm63xx_spi_pm_ops = { 467 SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_spi_suspend, bcm63xx_spi_resume) 468 }; 469 470 static struct platform_driver bcm63xx_spi_driver = { 471 .driver = { 472 .name = "bcm63xx-spi", 473 .owner = THIS_MODULE, 474 .pm = &bcm63xx_spi_pm_ops, 475 }, 476 .probe = bcm63xx_spi_probe, 477 .remove = bcm63xx_spi_remove, 478 }; 479 480 module_platform_driver(bcm63xx_spi_driver); 481 482 MODULE_ALIAS("platform:bcm63xx_spi"); 483 MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>"); 484 MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>"); 485 MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver"); 486 MODULE_LICENSE("GPL"); 487