1 /* 2 * Broadcom BCM63xx SPI controller support 3 * 4 * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org> 5 * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 2 10 * of the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the 19 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/init.h> 24 #include <linux/clk.h> 25 #include <linux/io.h> 26 #include <linux/module.h> 27 #include <linux/platform_device.h> 28 #include <linux/delay.h> 29 #include <linux/interrupt.h> 30 #include <linux/spi/spi.h> 31 #include <linux/completion.h> 32 #include <linux/err.h> 33 #include <linux/workqueue.h> 34 #include <linux/pm_runtime.h> 35 36 #include <bcm63xx_dev_spi.h> 37 38 #define PFX KBUILD_MODNAME 39 40 #define BCM63XX_SPI_MAX_PREPEND 15 41 42 struct bcm63xx_spi { 43 struct completion done; 44 45 void __iomem *regs; 46 int irq; 47 48 /* Platform data */ 49 unsigned fifo_size; 50 unsigned int msg_type_shift; 51 unsigned int msg_ctl_width; 52 53 /* data iomem */ 54 u8 __iomem *tx_io; 55 const u8 __iomem *rx_io; 56 57 struct clk *clk; 58 struct platform_device *pdev; 59 }; 60 61 static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs, 62 unsigned int offset) 63 { 64 return bcm_readb(bs->regs + bcm63xx_spireg(offset)); 65 } 66 67 static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs, 68 unsigned int offset) 69 { 70 return bcm_readw(bs->regs + bcm63xx_spireg(offset)); 71 } 72 73 static inline void bcm_spi_writeb(struct bcm63xx_spi *bs, 74 u8 value, unsigned int offset) 75 { 76 bcm_writeb(value, bs->regs + bcm63xx_spireg(offset)); 77 } 78 79 static inline void bcm_spi_writew(struct bcm63xx_spi *bs, 80 u16 value, unsigned int offset) 81 { 82 bcm_writew(value, bs->regs + bcm63xx_spireg(offset)); 83 } 84 85 static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = { 86 { 20000000, SPI_CLK_20MHZ }, 87 { 12500000, SPI_CLK_12_50MHZ }, 88 { 6250000, SPI_CLK_6_250MHZ }, 89 { 3125000, SPI_CLK_3_125MHZ }, 90 { 1563000, SPI_CLK_1_563MHZ }, 91 { 781000, SPI_CLK_0_781MHZ }, 92 { 391000, SPI_CLK_0_391MHZ } 93 }; 94 95 static void bcm63xx_spi_setup_transfer(struct spi_device *spi, 96 struct spi_transfer *t) 97 { 98 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); 99 u8 clk_cfg, reg; 100 int i; 101 102 /* Find the closest clock configuration */ 103 for (i = 0; i < SPI_CLK_MASK; i++) { 104 if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) { 105 clk_cfg = bcm63xx_spi_freq_table[i][1]; 106 break; 107 } 108 } 109 110 /* No matching configuration found, default to lowest */ 111 if (i == SPI_CLK_MASK) 112 clk_cfg = SPI_CLK_0_391MHZ; 113 114 /* clear existing clock configuration bits of the register */ 115 reg = bcm_spi_readb(bs, SPI_CLK_CFG); 116 reg &= ~SPI_CLK_MASK; 117 reg |= clk_cfg; 118 119 bcm_spi_writeb(bs, reg, SPI_CLK_CFG); 120 dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n", 121 clk_cfg, t->speed_hz); 122 } 123 124 /* the spi->mode bits understood by this driver: */ 125 #define MODEBITS (SPI_CPOL | SPI_CPHA) 126 127 static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first, 128 unsigned int num_transfers) 129 { 130 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); 131 u16 msg_ctl; 132 u16 cmd; 133 u8 rx_tail; 134 unsigned int i, timeout = 0, prepend_len = 0, len = 0; 135 struct spi_transfer *t = first; 136 bool do_rx = false; 137 bool do_tx = false; 138 139 /* Disable the CMD_DONE interrupt */ 140 bcm_spi_writeb(bs, 0, SPI_INT_MASK); 141 142 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", 143 t->tx_buf, t->rx_buf, t->len); 144 145 if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND) 146 prepend_len = t->len; 147 148 /* prepare the buffer */ 149 for (i = 0; i < num_transfers; i++) { 150 if (t->tx_buf) { 151 do_tx = true; 152 memcpy_toio(bs->tx_io + len, t->tx_buf, t->len); 153 154 /* don't prepend more than one tx */ 155 if (t != first) 156 prepend_len = 0; 157 } 158 159 if (t->rx_buf) { 160 do_rx = true; 161 /* prepend is half-duplex write only */ 162 if (t == first) 163 prepend_len = 0; 164 } 165 166 len += t->len; 167 168 t = list_entry(t->transfer_list.next, struct spi_transfer, 169 transfer_list); 170 } 171 172 init_completion(&bs->done); 173 174 /* Fill in the Message control register */ 175 msg_ctl = (len << SPI_BYTE_CNT_SHIFT); 176 177 if (do_rx && do_tx && prepend_len == 0) 178 msg_ctl |= (SPI_FD_RW << bs->msg_type_shift); 179 else if (do_rx) 180 msg_ctl |= (SPI_HD_R << bs->msg_type_shift); 181 else if (do_tx) 182 msg_ctl |= (SPI_HD_W << bs->msg_type_shift); 183 184 switch (bs->msg_ctl_width) { 185 case 8: 186 bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL); 187 break; 188 case 16: 189 bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL); 190 break; 191 } 192 193 /* Issue the transfer */ 194 cmd = SPI_CMD_START_IMMEDIATE; 195 cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT); 196 cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT); 197 bcm_spi_writew(bs, cmd, SPI_CMD); 198 199 /* Enable the CMD_DONE interrupt */ 200 bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK); 201 202 timeout = wait_for_completion_timeout(&bs->done, HZ); 203 if (!timeout) 204 return -ETIMEDOUT; 205 206 if (!do_rx) 207 return 0; 208 209 len = 0; 210 t = first; 211 /* Read out all the data */ 212 for (i = 0; i < num_transfers; i++) { 213 if (t->rx_buf) 214 memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len); 215 216 if (t != first || prepend_len == 0) 217 len += t->len; 218 219 t = list_entry(t->transfer_list.next, struct spi_transfer, 220 transfer_list); 221 } 222 223 return 0; 224 } 225 226 static int bcm63xx_spi_transfer_one(struct spi_master *master, 227 struct spi_message *m) 228 { 229 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 230 struct spi_transfer *t, *first = NULL; 231 struct spi_device *spi = m->spi; 232 int status = 0; 233 unsigned int n_transfers = 0, total_len = 0; 234 bool can_use_prepend = false; 235 236 /* 237 * This SPI controller does not support keeping CS active after a 238 * transfer. 239 * Work around this by merging as many transfers we can into one big 240 * full-duplex transfers. 241 */ 242 list_for_each_entry(t, &m->transfers, transfer_list) { 243 if (!first) 244 first = t; 245 246 n_transfers++; 247 total_len += t->len; 248 249 if (n_transfers == 2 && !first->rx_buf && !t->tx_buf && 250 first->len <= BCM63XX_SPI_MAX_PREPEND) 251 can_use_prepend = true; 252 else if (can_use_prepend && t->tx_buf) 253 can_use_prepend = false; 254 255 /* we can only transfer one fifo worth of data */ 256 if ((can_use_prepend && 257 total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) || 258 (!can_use_prepend && total_len > bs->fifo_size)) { 259 dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n", 260 total_len, bs->fifo_size); 261 status = -EINVAL; 262 goto exit; 263 } 264 265 /* all combined transfers have to have the same speed */ 266 if (t->speed_hz != first->speed_hz) { 267 dev_err(&spi->dev, "unable to change speed between transfers\n"); 268 status = -EINVAL; 269 goto exit; 270 } 271 272 /* CS will be deasserted directly after transfer */ 273 if (t->delay_usecs) { 274 dev_err(&spi->dev, "unable to keep CS asserted after transfer\n"); 275 status = -EINVAL; 276 goto exit; 277 } 278 279 if (t->cs_change || 280 list_is_last(&t->transfer_list, &m->transfers)) { 281 /* configure adapter for a new transfer */ 282 bcm63xx_spi_setup_transfer(spi, first); 283 284 /* send the data */ 285 status = bcm63xx_txrx_bufs(spi, first, n_transfers); 286 if (status) 287 goto exit; 288 289 m->actual_length += total_len; 290 291 first = NULL; 292 n_transfers = 0; 293 total_len = 0; 294 can_use_prepend = false; 295 } 296 } 297 exit: 298 m->status = status; 299 spi_finalize_current_message(master); 300 301 return 0; 302 } 303 304 /* This driver supports single master mode only. Hence 305 * CMD_DONE is the only interrupt we care about 306 */ 307 static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id) 308 { 309 struct spi_master *master = (struct spi_master *)dev_id; 310 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 311 u8 intr; 312 313 /* Read interupts and clear them immediately */ 314 intr = bcm_spi_readb(bs, SPI_INT_STATUS); 315 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); 316 bcm_spi_writeb(bs, 0, SPI_INT_MASK); 317 318 /* A transfer completed */ 319 if (intr & SPI_INTR_CMD_DONE) 320 complete(&bs->done); 321 322 return IRQ_HANDLED; 323 } 324 325 326 static int bcm63xx_spi_probe(struct platform_device *pdev) 327 { 328 struct resource *r; 329 struct device *dev = &pdev->dev; 330 struct bcm63xx_spi_pdata *pdata = dev_get_platdata(&pdev->dev); 331 int irq; 332 struct spi_master *master; 333 struct clk *clk; 334 struct bcm63xx_spi *bs; 335 int ret; 336 337 irq = platform_get_irq(pdev, 0); 338 if (irq < 0) { 339 dev_err(dev, "no irq\n"); 340 return -ENXIO; 341 } 342 343 clk = devm_clk_get(dev, "spi"); 344 if (IS_ERR(clk)) { 345 dev_err(dev, "no clock for device\n"); 346 return PTR_ERR(clk); 347 } 348 349 master = spi_alloc_master(dev, sizeof(*bs)); 350 if (!master) { 351 dev_err(dev, "out of memory\n"); 352 return -ENOMEM; 353 } 354 355 bs = spi_master_get_devdata(master); 356 357 platform_set_drvdata(pdev, master); 358 bs->pdev = pdev; 359 360 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 361 bs->regs = devm_ioremap_resource(&pdev->dev, r); 362 if (IS_ERR(bs->regs)) { 363 ret = PTR_ERR(bs->regs); 364 goto out_err; 365 } 366 367 bs->irq = irq; 368 bs->clk = clk; 369 bs->fifo_size = pdata->fifo_size; 370 371 ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0, 372 pdev->name, master); 373 if (ret) { 374 dev_err(dev, "unable to request irq\n"); 375 goto out_err; 376 } 377 378 master->bus_num = pdata->bus_num; 379 master->num_chipselect = pdata->num_chipselect; 380 master->transfer_one_message = bcm63xx_spi_transfer_one; 381 master->mode_bits = MODEBITS; 382 master->bits_per_word_mask = SPI_BPW_MASK(8); 383 master->auto_runtime_pm = true; 384 bs->msg_type_shift = pdata->msg_type_shift; 385 bs->msg_ctl_width = pdata->msg_ctl_width; 386 bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA)); 387 bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA)); 388 389 switch (bs->msg_ctl_width) { 390 case 8: 391 case 16: 392 break; 393 default: 394 dev_err(dev, "unsupported MSG_CTL width: %d\n", 395 bs->msg_ctl_width); 396 goto out_err; 397 } 398 399 /* Initialize hardware */ 400 ret = clk_prepare_enable(bs->clk); 401 if (ret) 402 goto out_err; 403 404 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); 405 406 /* register and we are done */ 407 ret = devm_spi_register_master(dev, master); 408 if (ret) { 409 dev_err(dev, "spi register failed\n"); 410 goto out_clk_disable; 411 } 412 413 dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n", 414 r->start, irq, bs->fifo_size); 415 416 return 0; 417 418 out_clk_disable: 419 clk_disable_unprepare(clk); 420 out_err: 421 spi_master_put(master); 422 return ret; 423 } 424 425 static int bcm63xx_spi_remove(struct platform_device *pdev) 426 { 427 struct spi_master *master = platform_get_drvdata(pdev); 428 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 429 430 /* reset spi block */ 431 bcm_spi_writeb(bs, 0, SPI_INT_MASK); 432 433 /* HW shutdown */ 434 clk_disable_unprepare(bs->clk); 435 436 return 0; 437 } 438 439 #ifdef CONFIG_PM_SLEEP 440 static int bcm63xx_spi_suspend(struct device *dev) 441 { 442 struct spi_master *master = dev_get_drvdata(dev); 443 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 444 445 spi_master_suspend(master); 446 447 clk_disable_unprepare(bs->clk); 448 449 return 0; 450 } 451 452 static int bcm63xx_spi_resume(struct device *dev) 453 { 454 struct spi_master *master = dev_get_drvdata(dev); 455 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 456 int ret; 457 458 ret = clk_prepare_enable(bs->clk); 459 if (ret) 460 return ret; 461 462 spi_master_resume(master); 463 464 return 0; 465 } 466 #endif 467 468 static const struct dev_pm_ops bcm63xx_spi_pm_ops = { 469 SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_spi_suspend, bcm63xx_spi_resume) 470 }; 471 472 static struct platform_driver bcm63xx_spi_driver = { 473 .driver = { 474 .name = "bcm63xx-spi", 475 .owner = THIS_MODULE, 476 .pm = &bcm63xx_spi_pm_ops, 477 }, 478 .probe = bcm63xx_spi_probe, 479 .remove = bcm63xx_spi_remove, 480 }; 481 482 module_platform_driver(bcm63xx_spi_driver); 483 484 MODULE_ALIAS("platform:bcm63xx_spi"); 485 MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>"); 486 MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>"); 487 MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver"); 488 MODULE_LICENSE("GPL"); 489