1 /* 2 * Broadcom BCM63xx SPI controller support 3 * 4 * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org> 5 * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 2 10 * of the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the 19 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/init.h> 24 #include <linux/clk.h> 25 #include <linux/io.h> 26 #include <linux/module.h> 27 #include <linux/platform_device.h> 28 #include <linux/delay.h> 29 #include <linux/interrupt.h> 30 #include <linux/spi/spi.h> 31 #include <linux/completion.h> 32 #include <linux/err.h> 33 #include <linux/workqueue.h> 34 #include <linux/pm_runtime.h> 35 36 #include <bcm63xx_dev_spi.h> 37 38 #define PFX KBUILD_MODNAME 39 40 #define BCM63XX_SPI_MAX_PREPEND 15 41 42 struct bcm63xx_spi { 43 struct completion done; 44 45 void __iomem *regs; 46 int irq; 47 48 /* Platform data */ 49 u32 speed_hz; 50 unsigned fifo_size; 51 unsigned int msg_type_shift; 52 unsigned int msg_ctl_width; 53 54 /* data iomem */ 55 u8 __iomem *tx_io; 56 const u8 __iomem *rx_io; 57 58 struct clk *clk; 59 struct platform_device *pdev; 60 }; 61 62 static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs, 63 unsigned int offset) 64 { 65 return bcm_readb(bs->regs + bcm63xx_spireg(offset)); 66 } 67 68 static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs, 69 unsigned int offset) 70 { 71 return bcm_readw(bs->regs + bcm63xx_spireg(offset)); 72 } 73 74 static inline void bcm_spi_writeb(struct bcm63xx_spi *bs, 75 u8 value, unsigned int offset) 76 { 77 bcm_writeb(value, bs->regs + bcm63xx_spireg(offset)); 78 } 79 80 static inline void bcm_spi_writew(struct bcm63xx_spi *bs, 81 u16 value, unsigned int offset) 82 { 83 bcm_writew(value, bs->regs + bcm63xx_spireg(offset)); 84 } 85 86 static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = { 87 { 20000000, SPI_CLK_20MHZ }, 88 { 12500000, SPI_CLK_12_50MHZ }, 89 { 6250000, SPI_CLK_6_250MHZ }, 90 { 3125000, SPI_CLK_3_125MHZ }, 91 { 1563000, SPI_CLK_1_563MHZ }, 92 { 781000, SPI_CLK_0_781MHZ }, 93 { 391000, SPI_CLK_0_391MHZ } 94 }; 95 96 static int bcm63xx_spi_check_transfer(struct spi_device *spi, 97 struct spi_transfer *t) 98 { 99 u8 bits_per_word; 100 101 bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word; 102 if (bits_per_word != 8) { 103 dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n", 104 __func__, bits_per_word); 105 return -EINVAL; 106 } 107 108 if (spi->chip_select > spi->master->num_chipselect) { 109 dev_err(&spi->dev, "%s, unsupported slave %d\n", 110 __func__, spi->chip_select); 111 return -EINVAL; 112 } 113 114 return 0; 115 } 116 117 static void bcm63xx_spi_setup_transfer(struct spi_device *spi, 118 struct spi_transfer *t) 119 { 120 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); 121 u32 hz; 122 u8 clk_cfg, reg; 123 int i; 124 125 hz = (t) ? t->speed_hz : spi->max_speed_hz; 126 127 /* Find the closest clock configuration */ 128 for (i = 0; i < SPI_CLK_MASK; i++) { 129 if (hz >= bcm63xx_spi_freq_table[i][0]) { 130 clk_cfg = bcm63xx_spi_freq_table[i][1]; 131 break; 132 } 133 } 134 135 /* No matching configuration found, default to lowest */ 136 if (i == SPI_CLK_MASK) 137 clk_cfg = SPI_CLK_0_391MHZ; 138 139 /* clear existing clock configuration bits of the register */ 140 reg = bcm_spi_readb(bs, SPI_CLK_CFG); 141 reg &= ~SPI_CLK_MASK; 142 reg |= clk_cfg; 143 144 bcm_spi_writeb(bs, reg, SPI_CLK_CFG); 145 dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n", 146 clk_cfg, hz); 147 } 148 149 /* the spi->mode bits understood by this driver: */ 150 #define MODEBITS (SPI_CPOL | SPI_CPHA) 151 152 static int bcm63xx_spi_setup(struct spi_device *spi) 153 { 154 if (!spi->bits_per_word) 155 spi->bits_per_word = 8; 156 157 return 0; 158 } 159 160 static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first, 161 unsigned int num_transfers) 162 { 163 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); 164 u16 msg_ctl; 165 u16 cmd; 166 u8 rx_tail; 167 unsigned int i, timeout = 0, prepend_len = 0, len = 0; 168 struct spi_transfer *t = first; 169 bool do_rx = false; 170 bool do_tx = false; 171 172 /* Disable the CMD_DONE interrupt */ 173 bcm_spi_writeb(bs, 0, SPI_INT_MASK); 174 175 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", 176 t->tx_buf, t->rx_buf, t->len); 177 178 if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND) 179 prepend_len = t->len; 180 181 /* prepare the buffer */ 182 for (i = 0; i < num_transfers; i++) { 183 if (t->tx_buf) { 184 do_tx = true; 185 memcpy_toio(bs->tx_io + len, t->tx_buf, t->len); 186 187 /* don't prepend more than one tx */ 188 if (t != first) 189 prepend_len = 0; 190 } 191 192 if (t->rx_buf) { 193 do_rx = true; 194 /* prepend is half-duplex write only */ 195 if (t == first) 196 prepend_len = 0; 197 } 198 199 len += t->len; 200 201 t = list_entry(t->transfer_list.next, struct spi_transfer, 202 transfer_list); 203 } 204 205 len -= prepend_len; 206 207 init_completion(&bs->done); 208 209 /* Fill in the Message control register */ 210 msg_ctl = (len << SPI_BYTE_CNT_SHIFT); 211 212 if (do_rx && do_tx && prepend_len == 0) 213 msg_ctl |= (SPI_FD_RW << bs->msg_type_shift); 214 else if (do_rx) 215 msg_ctl |= (SPI_HD_R << bs->msg_type_shift); 216 else if (do_tx) 217 msg_ctl |= (SPI_HD_W << bs->msg_type_shift); 218 219 switch (bs->msg_ctl_width) { 220 case 8: 221 bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL); 222 break; 223 case 16: 224 bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL); 225 break; 226 } 227 228 /* Issue the transfer */ 229 cmd = SPI_CMD_START_IMMEDIATE; 230 cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT); 231 cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT); 232 bcm_spi_writew(bs, cmd, SPI_CMD); 233 234 /* Enable the CMD_DONE interrupt */ 235 bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK); 236 237 timeout = wait_for_completion_timeout(&bs->done, HZ); 238 if (!timeout) 239 return -ETIMEDOUT; 240 241 /* read out all data */ 242 rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL); 243 244 if (do_rx && rx_tail != len) 245 return -EIO; 246 247 if (!rx_tail) 248 return 0; 249 250 len = 0; 251 t = first; 252 /* Read out all the data */ 253 for (i = 0; i < num_transfers; i++) { 254 if (t->rx_buf) 255 memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len); 256 257 if (t != first || prepend_len == 0) 258 len += t->len; 259 260 t = list_entry(t->transfer_list.next, struct spi_transfer, 261 transfer_list); 262 } 263 264 return 0; 265 } 266 267 static int bcm63xx_spi_prepare_transfer(struct spi_master *master) 268 { 269 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 270 271 pm_runtime_get_sync(&bs->pdev->dev); 272 273 return 0; 274 } 275 276 static int bcm63xx_spi_unprepare_transfer(struct spi_master *master) 277 { 278 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 279 280 pm_runtime_put(&bs->pdev->dev); 281 282 return 0; 283 } 284 285 static int bcm63xx_spi_transfer_one(struct spi_master *master, 286 struct spi_message *m) 287 { 288 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 289 struct spi_transfer *t, *first = NULL; 290 struct spi_device *spi = m->spi; 291 int status = 0; 292 unsigned int n_transfers = 0, total_len = 0; 293 bool can_use_prepend = false; 294 295 /* 296 * This SPI controller does not support keeping CS active after a 297 * transfer. 298 * Work around this by merging as many transfers we can into one big 299 * full-duplex transfers. 300 */ 301 list_for_each_entry(t, &m->transfers, transfer_list) { 302 status = bcm63xx_spi_check_transfer(spi, t); 303 if (status < 0) 304 goto exit; 305 306 if (!first) 307 first = t; 308 309 n_transfers++; 310 total_len += t->len; 311 312 if (n_transfers == 2 && !first->rx_buf && !t->tx_buf && 313 first->len <= BCM63XX_SPI_MAX_PREPEND) 314 can_use_prepend = true; 315 else if (can_use_prepend && t->tx_buf) 316 can_use_prepend = false; 317 318 /* we can only transfer one fifo worth of data */ 319 if ((can_use_prepend && 320 total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) || 321 (!can_use_prepend && total_len > bs->fifo_size)) { 322 dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n", 323 total_len, bs->fifo_size); 324 status = -EINVAL; 325 goto exit; 326 } 327 328 /* all combined transfers have to have the same speed */ 329 if (t->speed_hz != first->speed_hz) { 330 dev_err(&spi->dev, "unable to change speed between transfers\n"); 331 status = -EINVAL; 332 goto exit; 333 } 334 335 /* CS will be deasserted directly after transfer */ 336 if (t->delay_usecs) { 337 dev_err(&spi->dev, "unable to keep CS asserted after transfer\n"); 338 status = -EINVAL; 339 goto exit; 340 } 341 342 if (t->cs_change || 343 list_is_last(&t->transfer_list, &m->transfers)) { 344 /* configure adapter for a new transfer */ 345 bcm63xx_spi_setup_transfer(spi, first); 346 347 /* send the data */ 348 status = bcm63xx_txrx_bufs(spi, first, n_transfers); 349 if (status) 350 goto exit; 351 352 m->actual_length += total_len; 353 354 first = NULL; 355 n_transfers = 0; 356 total_len = 0; 357 can_use_prepend = false; 358 } 359 } 360 exit: 361 m->status = status; 362 spi_finalize_current_message(master); 363 364 return 0; 365 } 366 367 /* This driver supports single master mode only. Hence 368 * CMD_DONE is the only interrupt we care about 369 */ 370 static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id) 371 { 372 struct spi_master *master = (struct spi_master *)dev_id; 373 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 374 u8 intr; 375 376 /* Read interupts and clear them immediately */ 377 intr = bcm_spi_readb(bs, SPI_INT_STATUS); 378 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); 379 bcm_spi_writeb(bs, 0, SPI_INT_MASK); 380 381 /* A transfer completed */ 382 if (intr & SPI_INTR_CMD_DONE) 383 complete(&bs->done); 384 385 return IRQ_HANDLED; 386 } 387 388 389 static int bcm63xx_spi_probe(struct platform_device *pdev) 390 { 391 struct resource *r; 392 struct device *dev = &pdev->dev; 393 struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data; 394 int irq; 395 struct spi_master *master; 396 struct clk *clk; 397 struct bcm63xx_spi *bs; 398 int ret; 399 400 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 401 if (!r) { 402 dev_err(dev, "no iomem\n"); 403 ret = -ENXIO; 404 goto out; 405 } 406 407 irq = platform_get_irq(pdev, 0); 408 if (irq < 0) { 409 dev_err(dev, "no irq\n"); 410 ret = -ENXIO; 411 goto out; 412 } 413 414 clk = clk_get(dev, "spi"); 415 if (IS_ERR(clk)) { 416 dev_err(dev, "no clock for device\n"); 417 ret = PTR_ERR(clk); 418 goto out; 419 } 420 421 master = spi_alloc_master(dev, sizeof(*bs)); 422 if (!master) { 423 dev_err(dev, "out of memory\n"); 424 ret = -ENOMEM; 425 goto out_clk; 426 } 427 428 bs = spi_master_get_devdata(master); 429 430 platform_set_drvdata(pdev, master); 431 bs->pdev = pdev; 432 433 if (!devm_request_mem_region(&pdev->dev, r->start, 434 resource_size(r), PFX)) { 435 dev_err(dev, "iomem request failed\n"); 436 ret = -ENXIO; 437 goto out_err; 438 } 439 440 bs->regs = devm_ioremap_nocache(&pdev->dev, r->start, 441 resource_size(r)); 442 if (!bs->regs) { 443 dev_err(dev, "unable to ioremap regs\n"); 444 ret = -ENOMEM; 445 goto out_err; 446 } 447 448 bs->irq = irq; 449 bs->clk = clk; 450 bs->fifo_size = pdata->fifo_size; 451 452 ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0, 453 pdev->name, master); 454 if (ret) { 455 dev_err(dev, "unable to request irq\n"); 456 goto out_err; 457 } 458 459 master->bus_num = pdata->bus_num; 460 master->num_chipselect = pdata->num_chipselect; 461 master->setup = bcm63xx_spi_setup; 462 master->prepare_transfer_hardware = bcm63xx_spi_prepare_transfer; 463 master->unprepare_transfer_hardware = bcm63xx_spi_unprepare_transfer; 464 master->transfer_one_message = bcm63xx_spi_transfer_one; 465 master->mode_bits = MODEBITS; 466 bs->speed_hz = pdata->speed_hz; 467 bs->msg_type_shift = pdata->msg_type_shift; 468 bs->msg_ctl_width = pdata->msg_ctl_width; 469 bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA)); 470 bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA)); 471 472 switch (bs->msg_ctl_width) { 473 case 8: 474 case 16: 475 break; 476 default: 477 dev_err(dev, "unsupported MSG_CTL width: %d\n", 478 bs->msg_ctl_width); 479 goto out_err; 480 } 481 482 /* Initialize hardware */ 483 clk_prepare_enable(bs->clk); 484 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); 485 486 /* register and we are done */ 487 ret = spi_register_master(master); 488 if (ret) { 489 dev_err(dev, "spi register failed\n"); 490 goto out_clk_disable; 491 } 492 493 dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n", 494 r->start, irq, bs->fifo_size); 495 496 return 0; 497 498 out_clk_disable: 499 clk_disable_unprepare(clk); 500 out_err: 501 platform_set_drvdata(pdev, NULL); 502 spi_master_put(master); 503 out_clk: 504 clk_put(clk); 505 out: 506 return ret; 507 } 508 509 static int bcm63xx_spi_remove(struct platform_device *pdev) 510 { 511 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); 512 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 513 514 spi_unregister_master(master); 515 516 /* reset spi block */ 517 bcm_spi_writeb(bs, 0, SPI_INT_MASK); 518 519 /* HW shutdown */ 520 clk_disable_unprepare(bs->clk); 521 clk_put(bs->clk); 522 523 platform_set_drvdata(pdev, 0); 524 525 spi_master_put(master); 526 527 return 0; 528 } 529 530 #ifdef CONFIG_PM 531 static int bcm63xx_spi_suspend(struct device *dev) 532 { 533 struct spi_master *master = 534 platform_get_drvdata(to_platform_device(dev)); 535 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 536 537 spi_master_suspend(master); 538 539 clk_disable_unprepare(bs->clk); 540 541 return 0; 542 } 543 544 static int bcm63xx_spi_resume(struct device *dev) 545 { 546 struct spi_master *master = 547 platform_get_drvdata(to_platform_device(dev)); 548 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 549 550 clk_prepare_enable(bs->clk); 551 552 spi_master_resume(master); 553 554 return 0; 555 } 556 557 static const struct dev_pm_ops bcm63xx_spi_pm_ops = { 558 .suspend = bcm63xx_spi_suspend, 559 .resume = bcm63xx_spi_resume, 560 }; 561 562 #define BCM63XX_SPI_PM_OPS (&bcm63xx_spi_pm_ops) 563 #else 564 #define BCM63XX_SPI_PM_OPS NULL 565 #endif 566 567 static struct platform_driver bcm63xx_spi_driver = { 568 .driver = { 569 .name = "bcm63xx-spi", 570 .owner = THIS_MODULE, 571 .pm = BCM63XX_SPI_PM_OPS, 572 }, 573 .probe = bcm63xx_spi_probe, 574 .remove = bcm63xx_spi_remove, 575 }; 576 577 module_platform_driver(bcm63xx_spi_driver); 578 579 MODULE_ALIAS("platform:bcm63xx_spi"); 580 MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>"); 581 MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>"); 582 MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver"); 583 MODULE_LICENSE("GPL"); 584