1 /* 2 * Broadcom BCM63xx SPI controller support 3 * 4 * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org> 5 * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 2 10 * of the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/clk.h> 20 #include <linux/io.h> 21 #include <linux/module.h> 22 #include <linux/platform_device.h> 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/spi/spi.h> 26 #include <linux/completion.h> 27 #include <linux/err.h> 28 #include <linux/pm_runtime.h> 29 30 #include <bcm63xx_dev_spi.h> 31 32 #define BCM63XX_SPI_MAX_PREPEND 15 33 34 struct bcm63xx_spi { 35 struct completion done; 36 37 void __iomem *regs; 38 int irq; 39 40 /* Platform data */ 41 unsigned fifo_size; 42 unsigned int msg_type_shift; 43 unsigned int msg_ctl_width; 44 45 /* data iomem */ 46 u8 __iomem *tx_io; 47 const u8 __iomem *rx_io; 48 49 struct clk *clk; 50 struct platform_device *pdev; 51 }; 52 53 static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs, 54 unsigned int offset) 55 { 56 return bcm_readb(bs->regs + bcm63xx_spireg(offset)); 57 } 58 59 static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs, 60 unsigned int offset) 61 { 62 return bcm_readw(bs->regs + bcm63xx_spireg(offset)); 63 } 64 65 static inline void bcm_spi_writeb(struct bcm63xx_spi *bs, 66 u8 value, unsigned int offset) 67 { 68 bcm_writeb(value, bs->regs + bcm63xx_spireg(offset)); 69 } 70 71 static inline void bcm_spi_writew(struct bcm63xx_spi *bs, 72 u16 value, unsigned int offset) 73 { 74 bcm_writew(value, bs->regs + bcm63xx_spireg(offset)); 75 } 76 77 static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = { 78 { 20000000, SPI_CLK_20MHZ }, 79 { 12500000, SPI_CLK_12_50MHZ }, 80 { 6250000, SPI_CLK_6_250MHZ }, 81 { 3125000, SPI_CLK_3_125MHZ }, 82 { 1563000, SPI_CLK_1_563MHZ }, 83 { 781000, SPI_CLK_0_781MHZ }, 84 { 391000, SPI_CLK_0_391MHZ } 85 }; 86 87 static void bcm63xx_spi_setup_transfer(struct spi_device *spi, 88 struct spi_transfer *t) 89 { 90 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); 91 u8 clk_cfg, reg; 92 int i; 93 94 /* Find the closest clock configuration */ 95 for (i = 0; i < SPI_CLK_MASK; i++) { 96 if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) { 97 clk_cfg = bcm63xx_spi_freq_table[i][1]; 98 break; 99 } 100 } 101 102 /* No matching configuration found, default to lowest */ 103 if (i == SPI_CLK_MASK) 104 clk_cfg = SPI_CLK_0_391MHZ; 105 106 /* clear existing clock configuration bits of the register */ 107 reg = bcm_spi_readb(bs, SPI_CLK_CFG); 108 reg &= ~SPI_CLK_MASK; 109 reg |= clk_cfg; 110 111 bcm_spi_writeb(bs, reg, SPI_CLK_CFG); 112 dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n", 113 clk_cfg, t->speed_hz); 114 } 115 116 /* the spi->mode bits understood by this driver: */ 117 #define MODEBITS (SPI_CPOL | SPI_CPHA) 118 119 static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first, 120 unsigned int num_transfers) 121 { 122 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); 123 u16 msg_ctl; 124 u16 cmd; 125 unsigned int i, timeout = 0, prepend_len = 0, len = 0; 126 struct spi_transfer *t = first; 127 bool do_rx = false; 128 bool do_tx = false; 129 130 /* Disable the CMD_DONE interrupt */ 131 bcm_spi_writeb(bs, 0, SPI_INT_MASK); 132 133 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", 134 t->tx_buf, t->rx_buf, t->len); 135 136 if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND) 137 prepend_len = t->len; 138 139 /* prepare the buffer */ 140 for (i = 0; i < num_transfers; i++) { 141 if (t->tx_buf) { 142 do_tx = true; 143 memcpy_toio(bs->tx_io + len, t->tx_buf, t->len); 144 145 /* don't prepend more than one tx */ 146 if (t != first) 147 prepend_len = 0; 148 } 149 150 if (t->rx_buf) { 151 do_rx = true; 152 /* prepend is half-duplex write only */ 153 if (t == first) 154 prepend_len = 0; 155 } 156 157 len += t->len; 158 159 t = list_entry(t->transfer_list.next, struct spi_transfer, 160 transfer_list); 161 } 162 163 reinit_completion(&bs->done); 164 165 /* Fill in the Message control register */ 166 msg_ctl = (len << SPI_BYTE_CNT_SHIFT); 167 168 if (do_rx && do_tx && prepend_len == 0) 169 msg_ctl |= (SPI_FD_RW << bs->msg_type_shift); 170 else if (do_rx) 171 msg_ctl |= (SPI_HD_R << bs->msg_type_shift); 172 else if (do_tx) 173 msg_ctl |= (SPI_HD_W << bs->msg_type_shift); 174 175 switch (bs->msg_ctl_width) { 176 case 8: 177 bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL); 178 break; 179 case 16: 180 bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL); 181 break; 182 } 183 184 /* Issue the transfer */ 185 cmd = SPI_CMD_START_IMMEDIATE; 186 cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT); 187 cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT); 188 bcm_spi_writew(bs, cmd, SPI_CMD); 189 190 /* Enable the CMD_DONE interrupt */ 191 bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK); 192 193 timeout = wait_for_completion_timeout(&bs->done, HZ); 194 if (!timeout) 195 return -ETIMEDOUT; 196 197 if (!do_rx) 198 return 0; 199 200 len = 0; 201 t = first; 202 /* Read out all the data */ 203 for (i = 0; i < num_transfers; i++) { 204 if (t->rx_buf) 205 memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len); 206 207 if (t != first || prepend_len == 0) 208 len += t->len; 209 210 t = list_entry(t->transfer_list.next, struct spi_transfer, 211 transfer_list); 212 } 213 214 return 0; 215 } 216 217 static int bcm63xx_spi_transfer_one(struct spi_master *master, 218 struct spi_message *m) 219 { 220 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 221 struct spi_transfer *t, *first = NULL; 222 struct spi_device *spi = m->spi; 223 int status = 0; 224 unsigned int n_transfers = 0, total_len = 0; 225 bool can_use_prepend = false; 226 227 /* 228 * This SPI controller does not support keeping CS active after a 229 * transfer. 230 * Work around this by merging as many transfers we can into one big 231 * full-duplex transfers. 232 */ 233 list_for_each_entry(t, &m->transfers, transfer_list) { 234 if (!first) 235 first = t; 236 237 n_transfers++; 238 total_len += t->len; 239 240 if (n_transfers == 2 && !first->rx_buf && !t->tx_buf && 241 first->len <= BCM63XX_SPI_MAX_PREPEND) 242 can_use_prepend = true; 243 else if (can_use_prepend && t->tx_buf) 244 can_use_prepend = false; 245 246 /* we can only transfer one fifo worth of data */ 247 if ((can_use_prepend && 248 total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) || 249 (!can_use_prepend && total_len > bs->fifo_size)) { 250 dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n", 251 total_len, bs->fifo_size); 252 status = -EINVAL; 253 goto exit; 254 } 255 256 /* all combined transfers have to have the same speed */ 257 if (t->speed_hz != first->speed_hz) { 258 dev_err(&spi->dev, "unable to change speed between transfers\n"); 259 status = -EINVAL; 260 goto exit; 261 } 262 263 /* CS will be deasserted directly after transfer */ 264 if (t->delay_usecs) { 265 dev_err(&spi->dev, "unable to keep CS asserted after transfer\n"); 266 status = -EINVAL; 267 goto exit; 268 } 269 270 if (t->cs_change || 271 list_is_last(&t->transfer_list, &m->transfers)) { 272 /* configure adapter for a new transfer */ 273 bcm63xx_spi_setup_transfer(spi, first); 274 275 /* send the data */ 276 status = bcm63xx_txrx_bufs(spi, first, n_transfers); 277 if (status) 278 goto exit; 279 280 m->actual_length += total_len; 281 282 first = NULL; 283 n_transfers = 0; 284 total_len = 0; 285 can_use_prepend = false; 286 } 287 } 288 exit: 289 m->status = status; 290 spi_finalize_current_message(master); 291 292 return 0; 293 } 294 295 /* This driver supports single master mode only. Hence 296 * CMD_DONE is the only interrupt we care about 297 */ 298 static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id) 299 { 300 struct spi_master *master = (struct spi_master *)dev_id; 301 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 302 u8 intr; 303 304 /* Read interupts and clear them immediately */ 305 intr = bcm_spi_readb(bs, SPI_INT_STATUS); 306 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); 307 bcm_spi_writeb(bs, 0, SPI_INT_MASK); 308 309 /* A transfer completed */ 310 if (intr & SPI_INTR_CMD_DONE) 311 complete(&bs->done); 312 313 return IRQ_HANDLED; 314 } 315 316 317 static int bcm63xx_spi_probe(struct platform_device *pdev) 318 { 319 struct resource *r; 320 struct device *dev = &pdev->dev; 321 struct bcm63xx_spi_pdata *pdata = dev_get_platdata(&pdev->dev); 322 int irq; 323 struct spi_master *master; 324 struct clk *clk; 325 struct bcm63xx_spi *bs; 326 int ret; 327 328 irq = platform_get_irq(pdev, 0); 329 if (irq < 0) { 330 dev_err(dev, "no irq\n"); 331 return -ENXIO; 332 } 333 334 clk = devm_clk_get(dev, "spi"); 335 if (IS_ERR(clk)) { 336 dev_err(dev, "no clock for device\n"); 337 return PTR_ERR(clk); 338 } 339 340 master = spi_alloc_master(dev, sizeof(*bs)); 341 if (!master) { 342 dev_err(dev, "out of memory\n"); 343 return -ENOMEM; 344 } 345 346 bs = spi_master_get_devdata(master); 347 init_completion(&bs->done); 348 349 platform_set_drvdata(pdev, master); 350 bs->pdev = pdev; 351 352 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 353 bs->regs = devm_ioremap_resource(&pdev->dev, r); 354 if (IS_ERR(bs->regs)) { 355 ret = PTR_ERR(bs->regs); 356 goto out_err; 357 } 358 359 bs->irq = irq; 360 bs->clk = clk; 361 bs->fifo_size = pdata->fifo_size; 362 363 ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0, 364 pdev->name, master); 365 if (ret) { 366 dev_err(dev, "unable to request irq\n"); 367 goto out_err; 368 } 369 370 master->bus_num = pdata->bus_num; 371 master->num_chipselect = pdata->num_chipselect; 372 master->transfer_one_message = bcm63xx_spi_transfer_one; 373 master->mode_bits = MODEBITS; 374 master->bits_per_word_mask = SPI_BPW_MASK(8); 375 master->auto_runtime_pm = true; 376 bs->msg_type_shift = pdata->msg_type_shift; 377 bs->msg_ctl_width = pdata->msg_ctl_width; 378 bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA)); 379 bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA)); 380 381 switch (bs->msg_ctl_width) { 382 case 8: 383 case 16: 384 break; 385 default: 386 dev_err(dev, "unsupported MSG_CTL width: %d\n", 387 bs->msg_ctl_width); 388 goto out_err; 389 } 390 391 /* Initialize hardware */ 392 ret = clk_prepare_enable(bs->clk); 393 if (ret) 394 goto out_err; 395 396 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); 397 398 /* register and we are done */ 399 ret = devm_spi_register_master(dev, master); 400 if (ret) { 401 dev_err(dev, "spi register failed\n"); 402 goto out_clk_disable; 403 } 404 405 dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n", 406 r->start, irq, bs->fifo_size); 407 408 return 0; 409 410 out_clk_disable: 411 clk_disable_unprepare(clk); 412 out_err: 413 spi_master_put(master); 414 return ret; 415 } 416 417 static int bcm63xx_spi_remove(struct platform_device *pdev) 418 { 419 struct spi_master *master = platform_get_drvdata(pdev); 420 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 421 422 /* reset spi block */ 423 bcm_spi_writeb(bs, 0, SPI_INT_MASK); 424 425 /* HW shutdown */ 426 clk_disable_unprepare(bs->clk); 427 428 return 0; 429 } 430 431 #ifdef CONFIG_PM_SLEEP 432 static int bcm63xx_spi_suspend(struct device *dev) 433 { 434 struct spi_master *master = dev_get_drvdata(dev); 435 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 436 437 spi_master_suspend(master); 438 439 clk_disable_unprepare(bs->clk); 440 441 return 0; 442 } 443 444 static int bcm63xx_spi_resume(struct device *dev) 445 { 446 struct spi_master *master = dev_get_drvdata(dev); 447 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 448 int ret; 449 450 ret = clk_prepare_enable(bs->clk); 451 if (ret) 452 return ret; 453 454 spi_master_resume(master); 455 456 return 0; 457 } 458 #endif 459 460 static const struct dev_pm_ops bcm63xx_spi_pm_ops = { 461 SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_spi_suspend, bcm63xx_spi_resume) 462 }; 463 464 static struct platform_driver bcm63xx_spi_driver = { 465 .driver = { 466 .name = "bcm63xx-spi", 467 .pm = &bcm63xx_spi_pm_ops, 468 }, 469 .probe = bcm63xx_spi_probe, 470 .remove = bcm63xx_spi_remove, 471 }; 472 473 module_platform_driver(bcm63xx_spi_driver); 474 475 MODULE_ALIAS("platform:bcm63xx_spi"); 476 MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>"); 477 MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>"); 478 MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver"); 479 MODULE_LICENSE("GPL"); 480