1 /* 2 * Broadcom BCM63XX High Speed SPI Controller driver 3 * 4 * Copyright 2000-2010 Broadcom Corporation 5 * Copyright 2012-2013 Jonas Gorski <jogo@openwrt.org> 6 * 7 * Licensed under the GNU/GPL. See COPYING for details. 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/io.h> 13 #include <linux/clk.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/delay.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/err.h> 19 #include <linux/interrupt.h> 20 #include <linux/spi/spi.h> 21 #include <linux/mutex.h> 22 23 #define HSSPI_GLOBAL_CTRL_REG 0x0 24 #define GLOBAL_CTRL_CS_POLARITY_SHIFT 0 25 #define GLOBAL_CTRL_CS_POLARITY_MASK 0x000000ff 26 #define GLOBAL_CTRL_PLL_CLK_CTRL_SHIFT 8 27 #define GLOBAL_CTRL_PLL_CLK_CTRL_MASK 0x0000ff00 28 #define GLOBAL_CTRL_CLK_GATE_SSOFF BIT(16) 29 #define GLOBAL_CTRL_CLK_POLARITY BIT(17) 30 #define GLOBAL_CTRL_MOSI_IDLE BIT(18) 31 32 #define HSSPI_GLOBAL_EXT_TRIGGER_REG 0x4 33 34 #define HSSPI_INT_STATUS_REG 0x8 35 #define HSSPI_INT_STATUS_MASKED_REG 0xc 36 #define HSSPI_INT_MASK_REG 0x10 37 38 #define HSSPI_PINGx_CMD_DONE(i) BIT((i * 8) + 0) 39 #define HSSPI_PINGx_RX_OVER(i) BIT((i * 8) + 1) 40 #define HSSPI_PINGx_TX_UNDER(i) BIT((i * 8) + 2) 41 #define HSSPI_PINGx_POLL_TIMEOUT(i) BIT((i * 8) + 3) 42 #define HSSPI_PINGx_CTRL_INVAL(i) BIT((i * 8) + 4) 43 44 #define HSSPI_INT_CLEAR_ALL 0xff001f1f 45 46 #define HSSPI_PINGPONG_COMMAND_REG(x) (0x80 + (x) * 0x40) 47 #define PINGPONG_CMD_COMMAND_MASK 0xf 48 #define PINGPONG_COMMAND_NOOP 0 49 #define PINGPONG_COMMAND_START_NOW 1 50 #define PINGPONG_COMMAND_START_TRIGGER 2 51 #define PINGPONG_COMMAND_HALT 3 52 #define PINGPONG_COMMAND_FLUSH 4 53 #define PINGPONG_CMD_PROFILE_SHIFT 8 54 #define PINGPONG_CMD_SS_SHIFT 12 55 56 #define HSSPI_PINGPONG_STATUS_REG(x) (0x84 + (x) * 0x40) 57 58 #define HSSPI_PROFILE_CLK_CTRL_REG(x) (0x100 + (x) * 0x20) 59 #define CLK_CTRL_FREQ_CTRL_MASK 0x0000ffff 60 #define CLK_CTRL_SPI_CLK_2X_SEL BIT(14) 61 #define CLK_CTRL_ACCUM_RST_ON_LOOP BIT(15) 62 63 #define HSSPI_PROFILE_SIGNAL_CTRL_REG(x) (0x104 + (x) * 0x20) 64 #define SIGNAL_CTRL_LATCH_RISING BIT(12) 65 #define SIGNAL_CTRL_LAUNCH_RISING BIT(13) 66 #define SIGNAL_CTRL_ASYNC_INPUT_PATH BIT(16) 67 68 #define HSSPI_PROFILE_MODE_CTRL_REG(x) (0x108 + (x) * 0x20) 69 #define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT 8 70 #define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT 12 71 #define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT 16 72 #define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT 18 73 #define MODE_CTRL_MODE_3WIRE BIT(20) 74 #define MODE_CTRL_PREPENDBYTE_CNT_SHIFT 24 75 76 #define HSSPI_FIFO_REG(x) (0x200 + (x) * 0x200) 77 78 79 #define HSSPI_OP_MULTIBIT BIT(11) 80 #define HSSPI_OP_CODE_SHIFT 13 81 #define HSSPI_OP_SLEEP (0 << HSSPI_OP_CODE_SHIFT) 82 #define HSSPI_OP_READ_WRITE (1 << HSSPI_OP_CODE_SHIFT) 83 #define HSSPI_OP_WRITE (2 << HSSPI_OP_CODE_SHIFT) 84 #define HSSPI_OP_READ (3 << HSSPI_OP_CODE_SHIFT) 85 #define HSSPI_OP_SETIRQ (4 << HSSPI_OP_CODE_SHIFT) 86 87 #define HSSPI_BUFFER_LEN 512 88 #define HSSPI_OPCODE_LEN 2 89 90 #define HSSPI_MAX_PREPEND_LEN 15 91 92 #define HSSPI_MAX_SYNC_CLOCK 30000000 93 94 #define HSSPI_BUS_NUM 1 /* 0 is legacy SPI */ 95 96 struct bcm63xx_hsspi { 97 struct completion done; 98 struct mutex bus_mutex; 99 100 struct platform_device *pdev; 101 struct clk *clk; 102 void __iomem *regs; 103 u8 __iomem *fifo; 104 105 u32 speed_hz; 106 u8 cs_polarity; 107 }; 108 109 static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned cs, 110 bool active) 111 { 112 u32 reg; 113 114 mutex_lock(&bs->bus_mutex); 115 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); 116 117 reg &= ~BIT(cs); 118 if (active == !(bs->cs_polarity & BIT(cs))) 119 reg |= BIT(cs); 120 121 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); 122 mutex_unlock(&bs->bus_mutex); 123 } 124 125 static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs, 126 struct spi_device *spi, int hz) 127 { 128 unsigned profile = spi->chip_select; 129 u32 reg; 130 131 reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz)); 132 __raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg, 133 bs->regs + HSSPI_PROFILE_CLK_CTRL_REG(profile)); 134 135 reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile)); 136 if (hz > HSSPI_MAX_SYNC_CLOCK) 137 reg |= SIGNAL_CTRL_ASYNC_INPUT_PATH; 138 else 139 reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH; 140 __raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile)); 141 142 mutex_lock(&bs->bus_mutex); 143 /* setup clock polarity */ 144 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); 145 reg &= ~GLOBAL_CTRL_CLK_POLARITY; 146 if (spi->mode & SPI_CPOL) 147 reg |= GLOBAL_CTRL_CLK_POLARITY; 148 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); 149 mutex_unlock(&bs->bus_mutex); 150 } 151 152 static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t) 153 { 154 struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master); 155 unsigned chip_select = spi->chip_select; 156 u16 opcode = 0; 157 int pending = t->len; 158 int step_size = HSSPI_BUFFER_LEN; 159 const u8 *tx = t->tx_buf; 160 u8 *rx = t->rx_buf; 161 162 bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz); 163 bcm63xx_hsspi_set_cs(bs, spi->chip_select, true); 164 165 if (tx && rx) 166 opcode = HSSPI_OP_READ_WRITE; 167 else if (tx) 168 opcode = HSSPI_OP_WRITE; 169 else if (rx) 170 opcode = HSSPI_OP_READ; 171 172 if (opcode != HSSPI_OP_READ) 173 step_size -= HSSPI_OPCODE_LEN; 174 175 if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) || 176 (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL)) 177 opcode |= HSSPI_OP_MULTIBIT; 178 179 __raw_writel(1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT | 180 1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT | 0xff, 181 bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select)); 182 183 while (pending > 0) { 184 int curr_step = min_t(int, step_size, pending); 185 186 reinit_completion(&bs->done); 187 if (tx) { 188 memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step); 189 tx += curr_step; 190 } 191 192 __raw_writew(opcode | curr_step, bs->fifo); 193 194 /* enable interrupt */ 195 __raw_writel(HSSPI_PINGx_CMD_DONE(0), 196 bs->regs + HSSPI_INT_MASK_REG); 197 198 /* start the transfer */ 199 __raw_writel(!chip_select << PINGPONG_CMD_SS_SHIFT | 200 chip_select << PINGPONG_CMD_PROFILE_SHIFT | 201 PINGPONG_COMMAND_START_NOW, 202 bs->regs + HSSPI_PINGPONG_COMMAND_REG(0)); 203 204 if (wait_for_completion_timeout(&bs->done, HZ) == 0) { 205 dev_err(&bs->pdev->dev, "transfer timed out!\n"); 206 return -ETIMEDOUT; 207 } 208 209 if (rx) { 210 memcpy_fromio(rx, bs->fifo, curr_step); 211 rx += curr_step; 212 } 213 214 pending -= curr_step; 215 } 216 217 return 0; 218 } 219 220 static int bcm63xx_hsspi_setup(struct spi_device *spi) 221 { 222 struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master); 223 u32 reg; 224 225 reg = __raw_readl(bs->regs + 226 HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select)); 227 reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING); 228 if (spi->mode & SPI_CPHA) 229 reg |= SIGNAL_CTRL_LAUNCH_RISING; 230 else 231 reg |= SIGNAL_CTRL_LATCH_RISING; 232 __raw_writel(reg, bs->regs + 233 HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select)); 234 235 mutex_lock(&bs->bus_mutex); 236 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); 237 238 /* only change actual polarities if there is no transfer */ 239 if ((reg & GLOBAL_CTRL_CS_POLARITY_MASK) == bs->cs_polarity) { 240 if (spi->mode & SPI_CS_HIGH) 241 reg |= BIT(spi->chip_select); 242 else 243 reg &= ~BIT(spi->chip_select); 244 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); 245 } 246 247 if (spi->mode & SPI_CS_HIGH) 248 bs->cs_polarity |= BIT(spi->chip_select); 249 else 250 bs->cs_polarity &= ~BIT(spi->chip_select); 251 252 mutex_unlock(&bs->bus_mutex); 253 254 return 0; 255 } 256 257 static int bcm63xx_hsspi_transfer_one(struct spi_master *master, 258 struct spi_message *msg) 259 { 260 struct bcm63xx_hsspi *bs = spi_master_get_devdata(master); 261 struct spi_transfer *t; 262 struct spi_device *spi = msg->spi; 263 int status = -EINVAL; 264 int dummy_cs; 265 u32 reg; 266 267 /* This controller does not support keeping CS active during idle. 268 * To work around this, we use the following ugly hack: 269 * 270 * a. Invert the target chip select's polarity so it will be active. 271 * b. Select a "dummy" chip select to use as the hardware target. 272 * c. Invert the dummy chip select's polarity so it will be inactive 273 * during the actual transfers. 274 * d. Tell the hardware to send to the dummy chip select. Thanks to 275 * the multiplexed nature of SPI the actual target will receive 276 * the transfer and we see its response. 277 * 278 * e. At the end restore the polarities again to their default values. 279 */ 280 281 dummy_cs = !spi->chip_select; 282 bcm63xx_hsspi_set_cs(bs, dummy_cs, true); 283 284 list_for_each_entry(t, &msg->transfers, transfer_list) { 285 status = bcm63xx_hsspi_do_txrx(spi, t); 286 if (status) 287 break; 288 289 msg->actual_length += t->len; 290 291 if (t->delay_usecs) 292 udelay(t->delay_usecs); 293 294 if (t->cs_change) 295 bcm63xx_hsspi_set_cs(bs, spi->chip_select, false); 296 } 297 298 mutex_lock(&bs->bus_mutex); 299 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); 300 reg &= ~GLOBAL_CTRL_CS_POLARITY_MASK; 301 reg |= bs->cs_polarity; 302 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); 303 mutex_unlock(&bs->bus_mutex); 304 305 msg->status = status; 306 spi_finalize_current_message(master); 307 308 return 0; 309 } 310 311 static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id) 312 { 313 struct bcm63xx_hsspi *bs = (struct bcm63xx_hsspi *)dev_id; 314 315 if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0) 316 return IRQ_NONE; 317 318 __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG); 319 __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG); 320 321 complete(&bs->done); 322 323 return IRQ_HANDLED; 324 } 325 326 static int bcm63xx_hsspi_probe(struct platform_device *pdev) 327 { 328 struct spi_master *master; 329 struct bcm63xx_hsspi *bs; 330 struct resource *res_mem; 331 void __iomem *regs; 332 struct device *dev = &pdev->dev; 333 struct clk *clk; 334 int irq, ret; 335 u32 reg, rate; 336 337 irq = platform_get_irq(pdev, 0); 338 if (irq < 0) { 339 dev_err(dev, "no irq\n"); 340 return -ENXIO; 341 } 342 343 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 344 regs = devm_ioremap_resource(dev, res_mem); 345 if (IS_ERR(regs)) 346 return PTR_ERR(regs); 347 348 clk = devm_clk_get(dev, "hsspi"); 349 350 if (IS_ERR(clk)) 351 return PTR_ERR(clk); 352 353 rate = clk_get_rate(clk); 354 if (!rate) 355 return -EINVAL; 356 357 ret = clk_prepare_enable(clk); 358 if (ret) 359 return ret; 360 361 master = spi_alloc_master(&pdev->dev, sizeof(*bs)); 362 if (!master) { 363 ret = -ENOMEM; 364 goto out_disable_clk; 365 } 366 367 bs = spi_master_get_devdata(master); 368 bs->pdev = pdev; 369 bs->clk = clk; 370 bs->regs = regs; 371 bs->speed_hz = rate; 372 bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0)); 373 374 mutex_init(&bs->bus_mutex); 375 init_completion(&bs->done); 376 377 master->bus_num = HSSPI_BUS_NUM; 378 master->num_chipselect = 8; 379 master->setup = bcm63xx_hsspi_setup; 380 master->transfer_one_message = bcm63xx_hsspi_transfer_one; 381 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | 382 SPI_RX_DUAL | SPI_TX_DUAL; 383 master->bits_per_word_mask = SPI_BPW_MASK(8); 384 master->auto_runtime_pm = true; 385 386 platform_set_drvdata(pdev, master); 387 388 /* Initialize the hardware */ 389 __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG); 390 391 /* clean up any pending interrupts */ 392 __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG); 393 394 /* read out default CS polarities */ 395 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); 396 bs->cs_polarity = reg & GLOBAL_CTRL_CS_POLARITY_MASK; 397 __raw_writel(reg | GLOBAL_CTRL_CLK_GATE_SSOFF, 398 bs->regs + HSSPI_GLOBAL_CTRL_REG); 399 400 ret = devm_request_irq(dev, irq, bcm63xx_hsspi_interrupt, IRQF_SHARED, 401 pdev->name, bs); 402 403 if (ret) 404 goto out_put_master; 405 406 /* register and we are done */ 407 ret = devm_spi_register_master(dev, master); 408 if (ret) 409 goto out_put_master; 410 411 return 0; 412 413 out_put_master: 414 spi_master_put(master); 415 out_disable_clk: 416 clk_disable_unprepare(clk); 417 return ret; 418 } 419 420 421 static int bcm63xx_hsspi_remove(struct platform_device *pdev) 422 { 423 struct spi_master *master = platform_get_drvdata(pdev); 424 struct bcm63xx_hsspi *bs = spi_master_get_devdata(master); 425 426 /* reset the hardware and block queue progress */ 427 __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG); 428 clk_disable_unprepare(bs->clk); 429 430 return 0; 431 } 432 433 #ifdef CONFIG_PM_SLEEP 434 static int bcm63xx_hsspi_suspend(struct device *dev) 435 { 436 struct spi_master *master = dev_get_drvdata(dev); 437 struct bcm63xx_hsspi *bs = spi_master_get_devdata(master); 438 439 spi_master_suspend(master); 440 clk_disable_unprepare(bs->clk); 441 442 return 0; 443 } 444 445 static int bcm63xx_hsspi_resume(struct device *dev) 446 { 447 struct spi_master *master = dev_get_drvdata(dev); 448 struct bcm63xx_hsspi *bs = spi_master_get_devdata(master); 449 int ret; 450 451 ret = clk_prepare_enable(bs->clk); 452 if (ret) 453 return ret; 454 455 spi_master_resume(master); 456 457 return 0; 458 } 459 #endif 460 461 static SIMPLE_DEV_PM_OPS(bcm63xx_hsspi_pm_ops, bcm63xx_hsspi_suspend, 462 bcm63xx_hsspi_resume); 463 464 static struct platform_driver bcm63xx_hsspi_driver = { 465 .driver = { 466 .name = "bcm63xx-hsspi", 467 .pm = &bcm63xx_hsspi_pm_ops, 468 }, 469 .probe = bcm63xx_hsspi_probe, 470 .remove = bcm63xx_hsspi_remove, 471 }; 472 473 module_platform_driver(bcm63xx_hsspi_driver); 474 475 MODULE_ALIAS("platform:bcm63xx_hsspi"); 476 MODULE_DESCRIPTION("Broadcom BCM63xx High Speed SPI Controller driver"); 477 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>"); 478 MODULE_LICENSE("GPL"); 479