1 /*
2  * Broadcom BCM63XX High Speed SPI Controller driver
3  *
4  * Copyright 2000-2010 Broadcom Corporation
5  * Copyright 2012-2013 Jonas Gorski <jogo@openwrt.org>
6  *
7  * Licensed under the GNU/GPL. See COPYING for details.
8  */
9 
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/io.h>
13 #include <linux/clk.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/err.h>
19 #include <linux/interrupt.h>
20 #include <linux/spi/spi.h>
21 #include <linux/mutex.h>
22 #include <linux/of.h>
23 #include <linux/reset.h>
24 
25 #define HSSPI_GLOBAL_CTRL_REG			0x0
26 #define GLOBAL_CTRL_CS_POLARITY_SHIFT		0
27 #define GLOBAL_CTRL_CS_POLARITY_MASK		0x000000ff
28 #define GLOBAL_CTRL_PLL_CLK_CTRL_SHIFT		8
29 #define GLOBAL_CTRL_PLL_CLK_CTRL_MASK		0x0000ff00
30 #define GLOBAL_CTRL_CLK_GATE_SSOFF		BIT(16)
31 #define GLOBAL_CTRL_CLK_POLARITY		BIT(17)
32 #define GLOBAL_CTRL_MOSI_IDLE			BIT(18)
33 
34 #define HSSPI_GLOBAL_EXT_TRIGGER_REG		0x4
35 
36 #define HSSPI_INT_STATUS_REG			0x8
37 #define HSSPI_INT_STATUS_MASKED_REG		0xc
38 #define HSSPI_INT_MASK_REG			0x10
39 
40 #define HSSPI_PINGx_CMD_DONE(i)			BIT((i * 8) + 0)
41 #define HSSPI_PINGx_RX_OVER(i)			BIT((i * 8) + 1)
42 #define HSSPI_PINGx_TX_UNDER(i)			BIT((i * 8) + 2)
43 #define HSSPI_PINGx_POLL_TIMEOUT(i)		BIT((i * 8) + 3)
44 #define HSSPI_PINGx_CTRL_INVAL(i)		BIT((i * 8) + 4)
45 
46 #define HSSPI_INT_CLEAR_ALL			0xff001f1f
47 
48 #define HSSPI_PINGPONG_COMMAND_REG(x)		(0x80 + (x) * 0x40)
49 #define PINGPONG_CMD_COMMAND_MASK		0xf
50 #define PINGPONG_COMMAND_NOOP			0
51 #define PINGPONG_COMMAND_START_NOW		1
52 #define PINGPONG_COMMAND_START_TRIGGER		2
53 #define PINGPONG_COMMAND_HALT			3
54 #define PINGPONG_COMMAND_FLUSH			4
55 #define PINGPONG_CMD_PROFILE_SHIFT		8
56 #define PINGPONG_CMD_SS_SHIFT			12
57 
58 #define HSSPI_PINGPONG_STATUS_REG(x)		(0x84 + (x) * 0x40)
59 
60 #define HSSPI_PROFILE_CLK_CTRL_REG(x)		(0x100 + (x) * 0x20)
61 #define CLK_CTRL_FREQ_CTRL_MASK			0x0000ffff
62 #define CLK_CTRL_SPI_CLK_2X_SEL			BIT(14)
63 #define CLK_CTRL_ACCUM_RST_ON_LOOP		BIT(15)
64 
65 #define HSSPI_PROFILE_SIGNAL_CTRL_REG(x)	(0x104 + (x) * 0x20)
66 #define SIGNAL_CTRL_LATCH_RISING		BIT(12)
67 #define SIGNAL_CTRL_LAUNCH_RISING		BIT(13)
68 #define SIGNAL_CTRL_ASYNC_INPUT_PATH		BIT(16)
69 
70 #define HSSPI_PROFILE_MODE_CTRL_REG(x)		(0x108 + (x) * 0x20)
71 #define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT	8
72 #define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT	12
73 #define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT	16
74 #define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT	18
75 #define MODE_CTRL_MODE_3WIRE			BIT(20)
76 #define MODE_CTRL_PREPENDBYTE_CNT_SHIFT		24
77 
78 #define HSSPI_FIFO_REG(x)			(0x200 + (x) * 0x200)
79 
80 
81 #define HSSPI_OP_MULTIBIT			BIT(11)
82 #define HSSPI_OP_CODE_SHIFT			13
83 #define HSSPI_OP_SLEEP				(0 << HSSPI_OP_CODE_SHIFT)
84 #define HSSPI_OP_READ_WRITE			(1 << HSSPI_OP_CODE_SHIFT)
85 #define HSSPI_OP_WRITE				(2 << HSSPI_OP_CODE_SHIFT)
86 #define HSSPI_OP_READ				(3 << HSSPI_OP_CODE_SHIFT)
87 #define HSSPI_OP_SETIRQ				(4 << HSSPI_OP_CODE_SHIFT)
88 
89 #define HSSPI_BUFFER_LEN			512
90 #define HSSPI_OPCODE_LEN			2
91 
92 #define HSSPI_MAX_PREPEND_LEN			15
93 
94 #define HSSPI_MAX_SYNC_CLOCK			30000000
95 
96 #define HSSPI_SPI_MAX_CS			8
97 #define HSSPI_BUS_NUM				1 /* 0 is legacy SPI */
98 
99 struct bcm63xx_hsspi {
100 	struct completion done;
101 	struct mutex bus_mutex;
102 
103 	struct platform_device *pdev;
104 	struct clk *clk;
105 	struct clk *pll_clk;
106 	void __iomem *regs;
107 	u8 __iomem *fifo;
108 
109 	u32 speed_hz;
110 	u8 cs_polarity;
111 };
112 
113 static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned int cs,
114 				 bool active)
115 {
116 	u32 reg;
117 
118 	mutex_lock(&bs->bus_mutex);
119 	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
120 
121 	reg &= ~BIT(cs);
122 	if (active == !(bs->cs_polarity & BIT(cs)))
123 		reg |= BIT(cs);
124 
125 	__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
126 	mutex_unlock(&bs->bus_mutex);
127 }
128 
129 static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs,
130 				  struct spi_device *spi, int hz)
131 {
132 	unsigned int profile = spi->chip_select;
133 	u32 reg;
134 
135 	reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
136 	__raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg,
137 		     bs->regs + HSSPI_PROFILE_CLK_CTRL_REG(profile));
138 
139 	reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
140 	if (hz > HSSPI_MAX_SYNC_CLOCK)
141 		reg |= SIGNAL_CTRL_ASYNC_INPUT_PATH;
142 	else
143 		reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH;
144 	__raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
145 
146 	mutex_lock(&bs->bus_mutex);
147 	/* setup clock polarity */
148 	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
149 	reg &= ~GLOBAL_CTRL_CLK_POLARITY;
150 	if (spi->mode & SPI_CPOL)
151 		reg |= GLOBAL_CTRL_CLK_POLARITY;
152 	__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
153 	mutex_unlock(&bs->bus_mutex);
154 }
155 
156 static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t)
157 {
158 	struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
159 	unsigned int chip_select = spi->chip_select;
160 	u16 opcode = 0;
161 	int pending = t->len;
162 	int step_size = HSSPI_BUFFER_LEN;
163 	const u8 *tx = t->tx_buf;
164 	u8 *rx = t->rx_buf;
165 
166 	bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz);
167 	bcm63xx_hsspi_set_cs(bs, spi->chip_select, true);
168 
169 	if (tx && rx)
170 		opcode = HSSPI_OP_READ_WRITE;
171 	else if (tx)
172 		opcode = HSSPI_OP_WRITE;
173 	else if (rx)
174 		opcode = HSSPI_OP_READ;
175 
176 	if (opcode != HSSPI_OP_READ)
177 		step_size -= HSSPI_OPCODE_LEN;
178 
179 	if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) ||
180 	    (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL))
181 		opcode |= HSSPI_OP_MULTIBIT;
182 
183 	__raw_writel(1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT |
184 		     1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT | 0xff,
185 		     bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
186 
187 	while (pending > 0) {
188 		int curr_step = min_t(int, step_size, pending);
189 
190 		reinit_completion(&bs->done);
191 		if (tx) {
192 			memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step);
193 			tx += curr_step;
194 		}
195 
196 		__raw_writew(opcode | curr_step, bs->fifo);
197 
198 		/* enable interrupt */
199 		__raw_writel(HSSPI_PINGx_CMD_DONE(0),
200 			     bs->regs + HSSPI_INT_MASK_REG);
201 
202 		/* start the transfer */
203 		__raw_writel(!chip_select << PINGPONG_CMD_SS_SHIFT |
204 			     chip_select << PINGPONG_CMD_PROFILE_SHIFT |
205 			     PINGPONG_COMMAND_START_NOW,
206 			     bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));
207 
208 		if (wait_for_completion_timeout(&bs->done, HZ) == 0) {
209 			dev_err(&bs->pdev->dev, "transfer timed out!\n");
210 			return -ETIMEDOUT;
211 		}
212 
213 		if (rx) {
214 			memcpy_fromio(rx, bs->fifo, curr_step);
215 			rx += curr_step;
216 		}
217 
218 		pending -= curr_step;
219 	}
220 
221 	return 0;
222 }
223 
224 static int bcm63xx_hsspi_setup(struct spi_device *spi)
225 {
226 	struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
227 	u32 reg;
228 
229 	reg = __raw_readl(bs->regs +
230 			  HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
231 	reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING);
232 	if (spi->mode & SPI_CPHA)
233 		reg |= SIGNAL_CTRL_LAUNCH_RISING;
234 	else
235 		reg |= SIGNAL_CTRL_LATCH_RISING;
236 	__raw_writel(reg, bs->regs +
237 		     HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
238 
239 	mutex_lock(&bs->bus_mutex);
240 	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
241 
242 	/* only change actual polarities if there is no transfer */
243 	if ((reg & GLOBAL_CTRL_CS_POLARITY_MASK) == bs->cs_polarity) {
244 		if (spi->mode & SPI_CS_HIGH)
245 			reg |= BIT(spi->chip_select);
246 		else
247 			reg &= ~BIT(spi->chip_select);
248 		__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
249 	}
250 
251 	if (spi->mode & SPI_CS_HIGH)
252 		bs->cs_polarity |= BIT(spi->chip_select);
253 	else
254 		bs->cs_polarity &= ~BIT(spi->chip_select);
255 
256 	mutex_unlock(&bs->bus_mutex);
257 
258 	return 0;
259 }
260 
261 static int bcm63xx_hsspi_transfer_one(struct spi_master *master,
262 				      struct spi_message *msg)
263 {
264 	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
265 	struct spi_transfer *t;
266 	struct spi_device *spi = msg->spi;
267 	int status = -EINVAL;
268 	int dummy_cs;
269 	u32 reg;
270 
271 	/* This controller does not support keeping CS active during idle.
272 	 * To work around this, we use the following ugly hack:
273 	 *
274 	 * a. Invert the target chip select's polarity so it will be active.
275 	 * b. Select a "dummy" chip select to use as the hardware target.
276 	 * c. Invert the dummy chip select's polarity so it will be inactive
277 	 *    during the actual transfers.
278 	 * d. Tell the hardware to send to the dummy chip select. Thanks to
279 	 *    the multiplexed nature of SPI the actual target will receive
280 	 *    the transfer and we see its response.
281 	 *
282 	 * e. At the end restore the polarities again to their default values.
283 	 */
284 
285 	dummy_cs = !spi->chip_select;
286 	bcm63xx_hsspi_set_cs(bs, dummy_cs, true);
287 
288 	list_for_each_entry(t, &msg->transfers, transfer_list) {
289 		status = bcm63xx_hsspi_do_txrx(spi, t);
290 		if (status)
291 			break;
292 
293 		msg->actual_length += t->len;
294 
295 		spi_transfer_delay_exec(t);
296 
297 		if (t->cs_change)
298 			bcm63xx_hsspi_set_cs(bs, spi->chip_select, false);
299 	}
300 
301 	mutex_lock(&bs->bus_mutex);
302 	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
303 	reg &= ~GLOBAL_CTRL_CS_POLARITY_MASK;
304 	reg |= bs->cs_polarity;
305 	__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
306 	mutex_unlock(&bs->bus_mutex);
307 
308 	msg->status = status;
309 	spi_finalize_current_message(master);
310 
311 	return 0;
312 }
313 
314 static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id)
315 {
316 	struct bcm63xx_hsspi *bs = (struct bcm63xx_hsspi *)dev_id;
317 
318 	if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0)
319 		return IRQ_NONE;
320 
321 	__raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
322 	__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
323 
324 	complete(&bs->done);
325 
326 	return IRQ_HANDLED;
327 }
328 
329 static int bcm63xx_hsspi_probe(struct platform_device *pdev)
330 {
331 	struct spi_master *master;
332 	struct bcm63xx_hsspi *bs;
333 	void __iomem *regs;
334 	struct device *dev = &pdev->dev;
335 	struct clk *clk, *pll_clk = NULL;
336 	int irq, ret;
337 	u32 reg, rate, num_cs = HSSPI_SPI_MAX_CS;
338 	struct reset_control *reset;
339 
340 	irq = platform_get_irq(pdev, 0);
341 	if (irq < 0)
342 		return irq;
343 
344 	regs = devm_platform_ioremap_resource(pdev, 0);
345 	if (IS_ERR(regs))
346 		return PTR_ERR(regs);
347 
348 	clk = devm_clk_get(dev, "hsspi");
349 
350 	if (IS_ERR(clk))
351 		return PTR_ERR(clk);
352 
353 	reset = devm_reset_control_get_optional_exclusive(dev, NULL);
354 	if (IS_ERR(reset))
355 		return PTR_ERR(reset);
356 
357 	ret = clk_prepare_enable(clk);
358 	if (ret)
359 		return ret;
360 
361 	ret = reset_control_reset(reset);
362 	if (ret) {
363 		dev_err(dev, "unable to reset device: %d\n", ret);
364 		goto out_disable_clk;
365 	}
366 
367 	rate = clk_get_rate(clk);
368 	if (!rate) {
369 		pll_clk = devm_clk_get(dev, "pll");
370 
371 		if (IS_ERR(pll_clk)) {
372 			ret = PTR_ERR(pll_clk);
373 			goto out_disable_clk;
374 		}
375 
376 		ret = clk_prepare_enable(pll_clk);
377 		if (ret)
378 			goto out_disable_clk;
379 
380 		rate = clk_get_rate(pll_clk);
381 		if (!rate) {
382 			ret = -EINVAL;
383 			goto out_disable_pll_clk;
384 		}
385 	}
386 
387 	master = spi_alloc_master(&pdev->dev, sizeof(*bs));
388 	if (!master) {
389 		ret = -ENOMEM;
390 		goto out_disable_pll_clk;
391 	}
392 
393 	bs = spi_master_get_devdata(master);
394 	bs->pdev = pdev;
395 	bs->clk = clk;
396 	bs->pll_clk = pll_clk;
397 	bs->regs = regs;
398 	bs->speed_hz = rate;
399 	bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0));
400 
401 	mutex_init(&bs->bus_mutex);
402 	init_completion(&bs->done);
403 
404 	master->dev.of_node = dev->of_node;
405 	if (!dev->of_node)
406 		master->bus_num = HSSPI_BUS_NUM;
407 
408 	of_property_read_u32(dev->of_node, "num-cs", &num_cs);
409 	if (num_cs > 8) {
410 		dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n",
411 			 num_cs);
412 		num_cs = HSSPI_SPI_MAX_CS;
413 	}
414 	master->num_chipselect = num_cs;
415 	master->setup = bcm63xx_hsspi_setup;
416 	master->transfer_one_message = bcm63xx_hsspi_transfer_one;
417 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH |
418 			    SPI_RX_DUAL | SPI_TX_DUAL;
419 	master->bits_per_word_mask = SPI_BPW_MASK(8);
420 	master->auto_runtime_pm = true;
421 
422 	platform_set_drvdata(pdev, master);
423 
424 	/* Initialize the hardware */
425 	__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
426 
427 	/* clean up any pending interrupts */
428 	__raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
429 
430 	/* read out default CS polarities */
431 	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
432 	bs->cs_polarity = reg & GLOBAL_CTRL_CS_POLARITY_MASK;
433 	__raw_writel(reg | GLOBAL_CTRL_CLK_GATE_SSOFF,
434 		     bs->regs + HSSPI_GLOBAL_CTRL_REG);
435 
436 	ret = devm_request_irq(dev, irq, bcm63xx_hsspi_interrupt, IRQF_SHARED,
437 			       pdev->name, bs);
438 
439 	if (ret)
440 		goto out_put_master;
441 
442 	/* register and we are done */
443 	ret = devm_spi_register_master(dev, master);
444 	if (ret)
445 		goto out_put_master;
446 
447 	return 0;
448 
449 out_put_master:
450 	spi_master_put(master);
451 out_disable_pll_clk:
452 	clk_disable_unprepare(pll_clk);
453 out_disable_clk:
454 	clk_disable_unprepare(clk);
455 	return ret;
456 }
457 
458 
459 static int bcm63xx_hsspi_remove(struct platform_device *pdev)
460 {
461 	struct spi_master *master = platform_get_drvdata(pdev);
462 	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
463 
464 	/* reset the hardware and block queue progress */
465 	__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
466 	clk_disable_unprepare(bs->pll_clk);
467 	clk_disable_unprepare(bs->clk);
468 
469 	return 0;
470 }
471 
472 #ifdef CONFIG_PM_SLEEP
473 static int bcm63xx_hsspi_suspend(struct device *dev)
474 {
475 	struct spi_master *master = dev_get_drvdata(dev);
476 	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
477 
478 	spi_master_suspend(master);
479 	clk_disable_unprepare(bs->pll_clk);
480 	clk_disable_unprepare(bs->clk);
481 
482 	return 0;
483 }
484 
485 static int bcm63xx_hsspi_resume(struct device *dev)
486 {
487 	struct spi_master *master = dev_get_drvdata(dev);
488 	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
489 	int ret;
490 
491 	ret = clk_prepare_enable(bs->clk);
492 	if (ret)
493 		return ret;
494 
495 	if (bs->pll_clk) {
496 		ret = clk_prepare_enable(bs->pll_clk);
497 		if (ret)
498 			return ret;
499 	}
500 
501 	spi_master_resume(master);
502 
503 	return 0;
504 }
505 #endif
506 
507 static SIMPLE_DEV_PM_OPS(bcm63xx_hsspi_pm_ops, bcm63xx_hsspi_suspend,
508 			 bcm63xx_hsspi_resume);
509 
510 static const struct of_device_id bcm63xx_hsspi_of_match[] = {
511 	{ .compatible = "brcm,bcm6328-hsspi", },
512 	{ },
513 };
514 MODULE_DEVICE_TABLE(of, bcm63xx_hsspi_of_match);
515 
516 static struct platform_driver bcm63xx_hsspi_driver = {
517 	.driver = {
518 		.name	= "bcm63xx-hsspi",
519 		.pm	= &bcm63xx_hsspi_pm_ops,
520 		.of_match_table = bcm63xx_hsspi_of_match,
521 	},
522 	.probe		= bcm63xx_hsspi_probe,
523 	.remove		= bcm63xx_hsspi_remove,
524 };
525 
526 module_platform_driver(bcm63xx_hsspi_driver);
527 
528 MODULE_ALIAS("platform:bcm63xx_hsspi");
529 MODULE_DESCRIPTION("Broadcom BCM63xx High Speed SPI Controller driver");
530 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
531 MODULE_LICENSE("GPL");
532