1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for Broadcom BCM2835 auxiliary SPI Controllers 4 * 5 * the driver does not rely on the native chipselects at all 6 * but only uses the gpio type chipselects 7 * 8 * Based on: spi-bcm2835.c 9 * 10 * Copyright (C) 2015 Martin Sperl 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/completion.h> 15 #include <linux/debugfs.h> 16 #include <linux/delay.h> 17 #include <linux/err.h> 18 #include <linux/interrupt.h> 19 #include <linux/io.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_address.h> 24 #include <linux/of_device.h> 25 #include <linux/of_irq.h> 26 #include <linux/regmap.h> 27 #include <linux/spi/spi.h> 28 #include <linux/spinlock.h> 29 30 /* define polling limits */ 31 static unsigned int polling_limit_us = 30; 32 module_param(polling_limit_us, uint, 0664); 33 MODULE_PARM_DESC(polling_limit_us, 34 "time in us to run a transfer in polling mode - if zero no polling is used\n"); 35 36 /* 37 * spi register defines 38 * 39 * note there is garbage in the "official" documentation, 40 * so some data is taken from the file: 41 * brcm_usrlib/dag/vmcsx/vcinclude/bcm2708_chip/aux_io.h 42 * inside of: 43 * http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz 44 */ 45 46 /* SPI register offsets */ 47 #define BCM2835_AUX_SPI_CNTL0 0x00 48 #define BCM2835_AUX_SPI_CNTL1 0x04 49 #define BCM2835_AUX_SPI_STAT 0x08 50 #define BCM2835_AUX_SPI_PEEK 0x0C 51 #define BCM2835_AUX_SPI_IO 0x20 52 #define BCM2835_AUX_SPI_TXHOLD 0x30 53 54 /* Bitfields in CNTL0 */ 55 #define BCM2835_AUX_SPI_CNTL0_SPEED 0xFFF00000 56 #define BCM2835_AUX_SPI_CNTL0_SPEED_MAX 0xFFF 57 #define BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT 20 58 #define BCM2835_AUX_SPI_CNTL0_CS 0x000E0000 59 #define BCM2835_AUX_SPI_CNTL0_POSTINPUT 0x00010000 60 #define BCM2835_AUX_SPI_CNTL0_VAR_CS 0x00008000 61 #define BCM2835_AUX_SPI_CNTL0_VAR_WIDTH 0x00004000 62 #define BCM2835_AUX_SPI_CNTL0_DOUTHOLD 0x00003000 63 #define BCM2835_AUX_SPI_CNTL0_ENABLE 0x00000800 64 #define BCM2835_AUX_SPI_CNTL0_IN_RISING 0x00000400 65 #define BCM2835_AUX_SPI_CNTL0_CLEARFIFO 0x00000200 66 #define BCM2835_AUX_SPI_CNTL0_OUT_RISING 0x00000100 67 #define BCM2835_AUX_SPI_CNTL0_CPOL 0x00000080 68 #define BCM2835_AUX_SPI_CNTL0_MSBF_OUT 0x00000040 69 #define BCM2835_AUX_SPI_CNTL0_SHIFTLEN 0x0000003F 70 71 /* Bitfields in CNTL1 */ 72 #define BCM2835_AUX_SPI_CNTL1_CSHIGH 0x00000700 73 #define BCM2835_AUX_SPI_CNTL1_TXEMPTY 0x00000080 74 #define BCM2835_AUX_SPI_CNTL1_IDLE 0x00000040 75 #define BCM2835_AUX_SPI_CNTL1_MSBF_IN 0x00000002 76 #define BCM2835_AUX_SPI_CNTL1_KEEP_IN 0x00000001 77 78 /* Bitfields in STAT */ 79 #define BCM2835_AUX_SPI_STAT_TX_LVL 0xFF000000 80 #define BCM2835_AUX_SPI_STAT_RX_LVL 0x00FF0000 81 #define BCM2835_AUX_SPI_STAT_TX_FULL 0x00000400 82 #define BCM2835_AUX_SPI_STAT_TX_EMPTY 0x00000200 83 #define BCM2835_AUX_SPI_STAT_RX_FULL 0x00000100 84 #define BCM2835_AUX_SPI_STAT_RX_EMPTY 0x00000080 85 #define BCM2835_AUX_SPI_STAT_BUSY 0x00000040 86 #define BCM2835_AUX_SPI_STAT_BITCOUNT 0x0000003F 87 88 struct bcm2835aux_spi { 89 void __iomem *regs; 90 struct clk *clk; 91 int irq; 92 u32 cntl[2]; 93 const u8 *tx_buf; 94 u8 *rx_buf; 95 int tx_len; 96 int rx_len; 97 int pending; 98 99 u64 count_transfer_polling; 100 u64 count_transfer_irq; 101 u64 count_transfer_irq_after_poll; 102 103 struct dentry *debugfs_dir; 104 }; 105 106 #if defined(CONFIG_DEBUG_FS) 107 static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs, 108 const char *dname) 109 { 110 char name[64]; 111 struct dentry *dir; 112 113 /* get full name */ 114 snprintf(name, sizeof(name), "spi-bcm2835aux-%s", dname); 115 116 /* the base directory */ 117 dir = debugfs_create_dir(name, NULL); 118 bs->debugfs_dir = dir; 119 120 /* the counters */ 121 debugfs_create_u64("count_transfer_polling", 0444, dir, 122 &bs->count_transfer_polling); 123 debugfs_create_u64("count_transfer_irq", 0444, dir, 124 &bs->count_transfer_irq); 125 debugfs_create_u64("count_transfer_irq_after_poll", 0444, dir, 126 &bs->count_transfer_irq_after_poll); 127 } 128 129 static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs) 130 { 131 debugfs_remove_recursive(bs->debugfs_dir); 132 bs->debugfs_dir = NULL; 133 } 134 #else 135 static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs, 136 const char *dname) 137 { 138 } 139 140 static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs) 141 { 142 } 143 #endif /* CONFIG_DEBUG_FS */ 144 145 static inline u32 bcm2835aux_rd(struct bcm2835aux_spi *bs, unsigned int reg) 146 { 147 return readl(bs->regs + reg); 148 } 149 150 static inline void bcm2835aux_wr(struct bcm2835aux_spi *bs, unsigned int reg, 151 u32 val) 152 { 153 writel(val, bs->regs + reg); 154 } 155 156 static inline void bcm2835aux_rd_fifo(struct bcm2835aux_spi *bs) 157 { 158 u32 data; 159 int count = min(bs->rx_len, 3); 160 161 data = bcm2835aux_rd(bs, BCM2835_AUX_SPI_IO); 162 if (bs->rx_buf) { 163 switch (count) { 164 case 3: 165 *bs->rx_buf++ = (data >> 16) & 0xff; 166 fallthrough; 167 case 2: 168 *bs->rx_buf++ = (data >> 8) & 0xff; 169 fallthrough; 170 case 1: 171 *bs->rx_buf++ = (data >> 0) & 0xff; 172 /* fallthrough - no default */ 173 } 174 } 175 bs->rx_len -= count; 176 bs->pending -= count; 177 } 178 179 static inline void bcm2835aux_wr_fifo(struct bcm2835aux_spi *bs) 180 { 181 u32 data; 182 u8 byte; 183 int count; 184 int i; 185 186 /* gather up to 3 bytes to write to the FIFO */ 187 count = min(bs->tx_len, 3); 188 data = 0; 189 for (i = 0; i < count; i++) { 190 byte = bs->tx_buf ? *bs->tx_buf++ : 0; 191 data |= byte << (8 * (2 - i)); 192 } 193 194 /* and set the variable bit-length */ 195 data |= (count * 8) << 24; 196 197 /* and decrement length */ 198 bs->tx_len -= count; 199 bs->pending += count; 200 201 /* write to the correct TX-register */ 202 if (bs->tx_len) 203 bcm2835aux_wr(bs, BCM2835_AUX_SPI_TXHOLD, data); 204 else 205 bcm2835aux_wr(bs, BCM2835_AUX_SPI_IO, data); 206 } 207 208 static void bcm2835aux_spi_reset_hw(struct bcm2835aux_spi *bs) 209 { 210 /* disable spi clearing fifo and interrupts */ 211 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, 0); 212 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, 213 BCM2835_AUX_SPI_CNTL0_CLEARFIFO); 214 } 215 216 static void bcm2835aux_spi_transfer_helper(struct bcm2835aux_spi *bs) 217 { 218 u32 stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT); 219 220 /* check if we have data to read */ 221 for (; bs->rx_len && (stat & BCM2835_AUX_SPI_STAT_RX_LVL); 222 stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT)) 223 bcm2835aux_rd_fifo(bs); 224 225 /* check if we have data to write */ 226 while (bs->tx_len && 227 (bs->pending < 12) && 228 (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) & 229 BCM2835_AUX_SPI_STAT_TX_FULL))) { 230 bcm2835aux_wr_fifo(bs); 231 } 232 } 233 234 static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id) 235 { 236 struct spi_master *master = dev_id; 237 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 238 239 /* IRQ may be shared, so return if our interrupts are disabled */ 240 if (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_CNTL1) & 241 (BCM2835_AUX_SPI_CNTL1_TXEMPTY | BCM2835_AUX_SPI_CNTL1_IDLE))) 242 return IRQ_NONE; 243 244 /* do common fifo handling */ 245 bcm2835aux_spi_transfer_helper(bs); 246 247 if (!bs->tx_len) { 248 /* disable tx fifo empty interrupt */ 249 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] | 250 BCM2835_AUX_SPI_CNTL1_IDLE); 251 } 252 253 /* and if rx_len is 0 then disable interrupts and wake up completion */ 254 if (!bs->rx_len) { 255 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); 256 spi_finalize_current_transfer(master); 257 } 258 259 return IRQ_HANDLED; 260 } 261 262 static int __bcm2835aux_spi_transfer_one_irq(struct spi_master *master, 263 struct spi_device *spi, 264 struct spi_transfer *tfr) 265 { 266 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 267 268 /* enable interrupts */ 269 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] | 270 BCM2835_AUX_SPI_CNTL1_TXEMPTY | 271 BCM2835_AUX_SPI_CNTL1_IDLE); 272 273 /* and wait for finish... */ 274 return 1; 275 } 276 277 static int bcm2835aux_spi_transfer_one_irq(struct spi_master *master, 278 struct spi_device *spi, 279 struct spi_transfer *tfr) 280 { 281 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 282 283 /* update statistics */ 284 bs->count_transfer_irq++; 285 286 /* fill in registers and fifos before enabling interrupts */ 287 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); 288 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]); 289 290 /* fill in tx fifo with data before enabling interrupts */ 291 while ((bs->tx_len) && 292 (bs->pending < 12) && 293 (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) & 294 BCM2835_AUX_SPI_STAT_TX_FULL))) { 295 bcm2835aux_wr_fifo(bs); 296 } 297 298 /* now run the interrupt mode */ 299 return __bcm2835aux_spi_transfer_one_irq(master, spi, tfr); 300 } 301 302 static int bcm2835aux_spi_transfer_one_poll(struct spi_master *master, 303 struct spi_device *spi, 304 struct spi_transfer *tfr) 305 { 306 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 307 unsigned long timeout; 308 309 /* update statistics */ 310 bs->count_transfer_polling++; 311 312 /* configure spi */ 313 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); 314 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]); 315 316 /* set the timeout to at least 2 jiffies */ 317 timeout = jiffies + 2 + HZ * polling_limit_us / 1000000; 318 319 /* loop until finished the transfer */ 320 while (bs->rx_len) { 321 322 /* do common fifo handling */ 323 bcm2835aux_spi_transfer_helper(bs); 324 325 /* there is still data pending to read check the timeout */ 326 if (bs->rx_len && time_after(jiffies, timeout)) { 327 dev_dbg_ratelimited(&spi->dev, 328 "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n", 329 jiffies - timeout, 330 bs->tx_len, bs->rx_len); 331 /* forward to interrupt handler */ 332 bs->count_transfer_irq_after_poll++; 333 return __bcm2835aux_spi_transfer_one_irq(master, 334 spi, tfr); 335 } 336 } 337 338 /* and return without waiting for completion */ 339 return 0; 340 } 341 342 static int bcm2835aux_spi_transfer_one(struct spi_master *master, 343 struct spi_device *spi, 344 struct spi_transfer *tfr) 345 { 346 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 347 unsigned long spi_hz, clk_hz, speed; 348 unsigned long hz_per_byte, byte_limit; 349 350 /* calculate the registers to handle 351 * 352 * note that we use the variable data mode, which 353 * is not optimal for longer transfers as we waste registers 354 * resulting (potentially) in more interrupts when transferring 355 * more than 12 bytes 356 */ 357 358 /* set clock */ 359 spi_hz = tfr->speed_hz; 360 clk_hz = clk_get_rate(bs->clk); 361 362 if (spi_hz >= clk_hz / 2) { 363 speed = 0; 364 } else if (spi_hz) { 365 speed = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1; 366 if (speed > BCM2835_AUX_SPI_CNTL0_SPEED_MAX) 367 speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX; 368 } else { /* the slowest we can go */ 369 speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX; 370 } 371 /* mask out old speed from previous spi_transfer */ 372 bs->cntl[0] &= ~(BCM2835_AUX_SPI_CNTL0_SPEED); 373 /* set the new speed */ 374 bs->cntl[0] |= speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT; 375 376 tfr->effective_speed_hz = clk_hz / (2 * (speed + 1)); 377 378 /* set transmit buffers and length */ 379 bs->tx_buf = tfr->tx_buf; 380 bs->rx_buf = tfr->rx_buf; 381 bs->tx_len = tfr->len; 382 bs->rx_len = tfr->len; 383 bs->pending = 0; 384 385 /* Calculate the estimated time in us the transfer runs. Note that 386 * there are 2 idle clocks cycles after each chunk getting 387 * transferred - in our case the chunk size is 3 bytes, so we 388 * approximate this by 9 cycles/byte. This is used to find the number 389 * of Hz per byte per polling limit. E.g., we can transfer 1 byte in 390 * 30 µs per 300,000 Hz of bus clock. 391 */ 392 hz_per_byte = polling_limit_us ? (9 * 1000000) / polling_limit_us : 0; 393 byte_limit = hz_per_byte ? tfr->effective_speed_hz / hz_per_byte : 1; 394 395 /* run in polling mode for short transfers */ 396 if (tfr->len < byte_limit) 397 return bcm2835aux_spi_transfer_one_poll(master, spi, tfr); 398 399 /* run in interrupt mode for all others */ 400 return bcm2835aux_spi_transfer_one_irq(master, spi, tfr); 401 } 402 403 static int bcm2835aux_spi_prepare_message(struct spi_master *master, 404 struct spi_message *msg) 405 { 406 struct spi_device *spi = msg->spi; 407 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 408 409 bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE | 410 BCM2835_AUX_SPI_CNTL0_VAR_WIDTH | 411 BCM2835_AUX_SPI_CNTL0_MSBF_OUT; 412 bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN; 413 414 /* handle all the modes */ 415 if (spi->mode & SPI_CPOL) { 416 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL; 417 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_OUT_RISING; 418 } else { 419 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_IN_RISING; 420 } 421 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); 422 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]); 423 424 return 0; 425 } 426 427 static int bcm2835aux_spi_unprepare_message(struct spi_master *master, 428 struct spi_message *msg) 429 { 430 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 431 432 bcm2835aux_spi_reset_hw(bs); 433 434 return 0; 435 } 436 437 static void bcm2835aux_spi_handle_err(struct spi_master *master, 438 struct spi_message *msg) 439 { 440 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 441 442 bcm2835aux_spi_reset_hw(bs); 443 } 444 445 static int bcm2835aux_spi_setup(struct spi_device *spi) 446 { 447 /* sanity check for native cs */ 448 if (spi->mode & SPI_NO_CS) 449 return 0; 450 451 if (spi->cs_gpiod) 452 return 0; 453 454 /* for dt-backwards compatibility: only support native on CS0 455 * known things not supported with broken native CS: 456 * * multiple chip-selects: cs0-cs2 are all 457 * simultaniously asserted whenever there is a transfer 458 * this even includes SPI_NO_CS 459 * * SPI_CS_HIGH: cs are always asserted low 460 * * cs_change: cs is deasserted after each spi_transfer 461 * * cs_delay_usec: cs is always deasserted one SCK cycle 462 * after the last transfer 463 * probably more... 464 */ 465 dev_warn(&spi->dev, 466 "Native CS is not supported - please configure cs-gpio in device-tree\n"); 467 468 if (spi->chip_select == 0) 469 return 0; 470 471 dev_warn(&spi->dev, "Native CS is not working for cs > 0\n"); 472 473 return -EINVAL; 474 } 475 476 static int bcm2835aux_spi_probe(struct platform_device *pdev) 477 { 478 struct spi_master *master; 479 struct bcm2835aux_spi *bs; 480 unsigned long clk_hz; 481 int err; 482 483 master = devm_spi_alloc_master(&pdev->dev, sizeof(*bs)); 484 if (!master) 485 return -ENOMEM; 486 487 platform_set_drvdata(pdev, master); 488 master->mode_bits = (SPI_CPOL | SPI_CS_HIGH | SPI_NO_CS); 489 master->bits_per_word_mask = SPI_BPW_MASK(8); 490 /* even though the driver never officially supported native CS 491 * allow a single native CS for legacy DT support purposes when 492 * no cs-gpio is configured. 493 * Known limitations for native cs are: 494 * * multiple chip-selects: cs0-cs2 are all simultaniously asserted 495 * whenever there is a transfer - this even includes SPI_NO_CS 496 * * SPI_CS_HIGH: is ignores - cs are always asserted low 497 * * cs_change: cs is deasserted after each spi_transfer 498 * * cs_delay_usec: cs is always deasserted one SCK cycle after 499 * a spi_transfer 500 */ 501 master->num_chipselect = 1; 502 master->setup = bcm2835aux_spi_setup; 503 master->transfer_one = bcm2835aux_spi_transfer_one; 504 master->handle_err = bcm2835aux_spi_handle_err; 505 master->prepare_message = bcm2835aux_spi_prepare_message; 506 master->unprepare_message = bcm2835aux_spi_unprepare_message; 507 master->dev.of_node = pdev->dev.of_node; 508 master->use_gpio_descriptors = true; 509 510 bs = spi_master_get_devdata(master); 511 512 /* the main area */ 513 bs->regs = devm_platform_ioremap_resource(pdev, 0); 514 if (IS_ERR(bs->regs)) 515 return PTR_ERR(bs->regs); 516 517 bs->clk = devm_clk_get(&pdev->dev, NULL); 518 if (IS_ERR(bs->clk)) { 519 err = PTR_ERR(bs->clk); 520 dev_err(&pdev->dev, "could not get clk: %d\n", err); 521 return err; 522 } 523 524 bs->irq = platform_get_irq(pdev, 0); 525 if (bs->irq <= 0) 526 return bs->irq ? bs->irq : -ENODEV; 527 528 /* this also enables the HW block */ 529 err = clk_prepare_enable(bs->clk); 530 if (err) { 531 dev_err(&pdev->dev, "could not prepare clock: %d\n", err); 532 return err; 533 } 534 535 /* just checking if the clock returns a sane value */ 536 clk_hz = clk_get_rate(bs->clk); 537 if (!clk_hz) { 538 dev_err(&pdev->dev, "clock returns 0 Hz\n"); 539 err = -ENODEV; 540 goto out_clk_disable; 541 } 542 543 /* reset SPI-HW block */ 544 bcm2835aux_spi_reset_hw(bs); 545 546 err = devm_request_irq(&pdev->dev, bs->irq, 547 bcm2835aux_spi_interrupt, 548 IRQF_SHARED, 549 dev_name(&pdev->dev), master); 550 if (err) { 551 dev_err(&pdev->dev, "could not request IRQ: %d\n", err); 552 goto out_clk_disable; 553 } 554 555 err = spi_register_master(master); 556 if (err) { 557 dev_err(&pdev->dev, "could not register SPI master: %d\n", err); 558 goto out_clk_disable; 559 } 560 561 bcm2835aux_debugfs_create(bs, dev_name(&pdev->dev)); 562 563 return 0; 564 565 out_clk_disable: 566 clk_disable_unprepare(bs->clk); 567 return err; 568 } 569 570 static int bcm2835aux_spi_remove(struct platform_device *pdev) 571 { 572 struct spi_master *master = platform_get_drvdata(pdev); 573 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 574 575 bcm2835aux_debugfs_remove(bs); 576 577 spi_unregister_master(master); 578 579 bcm2835aux_spi_reset_hw(bs); 580 581 /* disable the HW block by releasing the clock */ 582 clk_disable_unprepare(bs->clk); 583 584 return 0; 585 } 586 587 static const struct of_device_id bcm2835aux_spi_match[] = { 588 { .compatible = "brcm,bcm2835-aux-spi", }, 589 {} 590 }; 591 MODULE_DEVICE_TABLE(of, bcm2835aux_spi_match); 592 593 static struct platform_driver bcm2835aux_spi_driver = { 594 .driver = { 595 .name = "spi-bcm2835aux", 596 .of_match_table = bcm2835aux_spi_match, 597 }, 598 .probe = bcm2835aux_spi_probe, 599 .remove = bcm2835aux_spi_remove, 600 }; 601 module_platform_driver(bcm2835aux_spi_driver); 602 603 MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835 aux"); 604 MODULE_AUTHOR("Martin Sperl <kernel@martin.sperl.org>"); 605 MODULE_LICENSE("GPL"); 606