1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for Broadcom BCM2835 SPI Controllers 4 * 5 * Copyright (C) 2012 Chris Boot 6 * Copyright (C) 2013 Stephen Warren 7 * Copyright (C) 2015 Martin Sperl 8 * 9 * This driver is inspired by: 10 * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> 11 * spi-atmel.c, Copyright (C) 2006 Atmel Corporation 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/completion.h> 16 #include <linux/delay.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/dmaengine.h> 19 #include <linux/err.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/of.h> 25 #include <linux/of_address.h> 26 #include <linux/of_device.h> 27 #include <linux/of_gpio.h> 28 #include <linux/of_irq.h> 29 #include <linux/spi/spi.h> 30 31 /* SPI register offsets */ 32 #define BCM2835_SPI_CS 0x00 33 #define BCM2835_SPI_FIFO 0x04 34 #define BCM2835_SPI_CLK 0x08 35 #define BCM2835_SPI_DLEN 0x0c 36 #define BCM2835_SPI_LTOH 0x10 37 #define BCM2835_SPI_DC 0x14 38 39 /* Bitfields in CS */ 40 #define BCM2835_SPI_CS_LEN_LONG 0x02000000 41 #define BCM2835_SPI_CS_DMA_LEN 0x01000000 42 #define BCM2835_SPI_CS_CSPOL2 0x00800000 43 #define BCM2835_SPI_CS_CSPOL1 0x00400000 44 #define BCM2835_SPI_CS_CSPOL0 0x00200000 45 #define BCM2835_SPI_CS_RXF 0x00100000 46 #define BCM2835_SPI_CS_RXR 0x00080000 47 #define BCM2835_SPI_CS_TXD 0x00040000 48 #define BCM2835_SPI_CS_RXD 0x00020000 49 #define BCM2835_SPI_CS_DONE 0x00010000 50 #define BCM2835_SPI_CS_LEN 0x00002000 51 #define BCM2835_SPI_CS_REN 0x00001000 52 #define BCM2835_SPI_CS_ADCS 0x00000800 53 #define BCM2835_SPI_CS_INTR 0x00000400 54 #define BCM2835_SPI_CS_INTD 0x00000200 55 #define BCM2835_SPI_CS_DMAEN 0x00000100 56 #define BCM2835_SPI_CS_TA 0x00000080 57 #define BCM2835_SPI_CS_CSPOL 0x00000040 58 #define BCM2835_SPI_CS_CLEAR_RX 0x00000020 59 #define BCM2835_SPI_CS_CLEAR_TX 0x00000010 60 #define BCM2835_SPI_CS_CPOL 0x00000008 61 #define BCM2835_SPI_CS_CPHA 0x00000004 62 #define BCM2835_SPI_CS_CS_10 0x00000002 63 #define BCM2835_SPI_CS_CS_01 0x00000001 64 65 #define BCM2835_SPI_FIFO_SIZE 64 66 #define BCM2835_SPI_FIFO_SIZE_3_4 48 67 #define BCM2835_SPI_POLLING_LIMIT_US 30 68 #define BCM2835_SPI_POLLING_JIFFIES 2 69 #define BCM2835_SPI_DMA_MIN_LENGTH 96 70 #define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \ 71 | SPI_NO_CS | SPI_3WIRE) 72 73 #define DRV_NAME "spi-bcm2835" 74 75 /** 76 * struct bcm2835_spi - BCM2835 SPI controller 77 * @regs: base address of register map 78 * @clk: core clock, divided to calculate serial clock 79 * @irq: interrupt, signals TX FIFO empty or RX FIFO ¾ full 80 * @tfr: SPI transfer currently processed 81 * @tx_buf: pointer whence next transmitted byte is read 82 * @rx_buf: pointer where next received byte is written 83 * @tx_len: remaining bytes to transmit 84 * @rx_len: remaining bytes to receive 85 * @tx_prologue: bytes transmitted without DMA if first TX sglist entry's 86 * length is not a multiple of 4 (to overcome hardware limitation) 87 * @rx_prologue: bytes received without DMA if first RX sglist entry's 88 * length is not a multiple of 4 (to overcome hardware limitation) 89 * @tx_spillover: whether @tx_prologue spills over to second TX sglist entry 90 * @dma_pending: whether a DMA transfer is in progress 91 */ 92 struct bcm2835_spi { 93 void __iomem *regs; 94 struct clk *clk; 95 int irq; 96 struct spi_transfer *tfr; 97 const u8 *tx_buf; 98 u8 *rx_buf; 99 int tx_len; 100 int rx_len; 101 int tx_prologue; 102 int rx_prologue; 103 unsigned int tx_spillover; 104 unsigned int dma_pending; 105 }; 106 107 static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg) 108 { 109 return readl(bs->regs + reg); 110 } 111 112 static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val) 113 { 114 writel(val, bs->regs + reg); 115 } 116 117 static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs) 118 { 119 u8 byte; 120 121 while ((bs->rx_len) && 122 (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD)) { 123 byte = bcm2835_rd(bs, BCM2835_SPI_FIFO); 124 if (bs->rx_buf) 125 *bs->rx_buf++ = byte; 126 bs->rx_len--; 127 } 128 } 129 130 static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs) 131 { 132 u8 byte; 133 134 while ((bs->tx_len) && 135 (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) { 136 byte = bs->tx_buf ? *bs->tx_buf++ : 0; 137 bcm2835_wr(bs, BCM2835_SPI_FIFO, byte); 138 bs->tx_len--; 139 } 140 } 141 142 /** 143 * bcm2835_rd_fifo_count() - blindly read exactly @count bytes from RX FIFO 144 * @bs: BCM2835 SPI controller 145 * @count: bytes to read from RX FIFO 146 * 147 * The caller must ensure that @bs->rx_len is greater than or equal to @count, 148 * that the RX FIFO contains at least @count bytes and that the DMA Enable flag 149 * in the CS register is set (such that a read from the FIFO register receives 150 * 32-bit instead of just 8-bit). Moreover @bs->rx_buf must not be %NULL. 151 */ 152 static inline void bcm2835_rd_fifo_count(struct bcm2835_spi *bs, int count) 153 { 154 u32 val; 155 int len; 156 157 bs->rx_len -= count; 158 159 while (count > 0) { 160 val = bcm2835_rd(bs, BCM2835_SPI_FIFO); 161 len = min(count, 4); 162 memcpy(bs->rx_buf, &val, len); 163 bs->rx_buf += len; 164 count -= 4; 165 } 166 } 167 168 /** 169 * bcm2835_wr_fifo_count() - blindly write exactly @count bytes to TX FIFO 170 * @bs: BCM2835 SPI controller 171 * @count: bytes to write to TX FIFO 172 * 173 * The caller must ensure that @bs->tx_len is greater than or equal to @count, 174 * that the TX FIFO can accommodate @count bytes and that the DMA Enable flag 175 * in the CS register is set (such that a write to the FIFO register transmits 176 * 32-bit instead of just 8-bit). 177 */ 178 static inline void bcm2835_wr_fifo_count(struct bcm2835_spi *bs, int count) 179 { 180 u32 val; 181 int len; 182 183 bs->tx_len -= count; 184 185 while (count > 0) { 186 if (bs->tx_buf) { 187 len = min(count, 4); 188 memcpy(&val, bs->tx_buf, len); 189 bs->tx_buf += len; 190 } else { 191 val = 0; 192 } 193 bcm2835_wr(bs, BCM2835_SPI_FIFO, val); 194 count -= 4; 195 } 196 } 197 198 /** 199 * bcm2835_wait_tx_fifo_empty() - busy-wait for TX FIFO to empty 200 * @bs: BCM2835 SPI controller 201 * 202 * The caller must ensure that the RX FIFO can accommodate as many bytes 203 * as have been written to the TX FIFO: Transmission is halted once the 204 * RX FIFO is full, causing this function to spin forever. 205 */ 206 static inline void bcm2835_wait_tx_fifo_empty(struct bcm2835_spi *bs) 207 { 208 while (!(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE)) 209 cpu_relax(); 210 } 211 212 /** 213 * bcm2835_rd_fifo_blind() - blindly read up to @count bytes from RX FIFO 214 * @bs: BCM2835 SPI controller 215 * @count: bytes available for reading in RX FIFO 216 */ 217 static inline void bcm2835_rd_fifo_blind(struct bcm2835_spi *bs, int count) 218 { 219 u8 val; 220 221 count = min(count, bs->rx_len); 222 bs->rx_len -= count; 223 224 while (count) { 225 val = bcm2835_rd(bs, BCM2835_SPI_FIFO); 226 if (bs->rx_buf) 227 *bs->rx_buf++ = val; 228 count--; 229 } 230 } 231 232 /** 233 * bcm2835_wr_fifo_blind() - blindly write up to @count bytes to TX FIFO 234 * @bs: BCM2835 SPI controller 235 * @count: bytes available for writing in TX FIFO 236 */ 237 static inline void bcm2835_wr_fifo_blind(struct bcm2835_spi *bs, int count) 238 { 239 u8 val; 240 241 count = min(count, bs->tx_len); 242 bs->tx_len -= count; 243 244 while (count) { 245 val = bs->tx_buf ? *bs->tx_buf++ : 0; 246 bcm2835_wr(bs, BCM2835_SPI_FIFO, val); 247 count--; 248 } 249 } 250 251 static void bcm2835_spi_reset_hw(struct spi_master *master) 252 { 253 struct bcm2835_spi *bs = spi_master_get_devdata(master); 254 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); 255 256 /* Disable SPI interrupts and transfer */ 257 cs &= ~(BCM2835_SPI_CS_INTR | 258 BCM2835_SPI_CS_INTD | 259 BCM2835_SPI_CS_DMAEN | 260 BCM2835_SPI_CS_TA); 261 /* and reset RX/TX FIFOS */ 262 cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX; 263 264 /* and reset the SPI_HW */ 265 bcm2835_wr(bs, BCM2835_SPI_CS, cs); 266 /* as well as DLEN */ 267 bcm2835_wr(bs, BCM2835_SPI_DLEN, 0); 268 } 269 270 static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id) 271 { 272 struct spi_master *master = dev_id; 273 struct bcm2835_spi *bs = spi_master_get_devdata(master); 274 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); 275 276 /* 277 * An interrupt is signaled either if DONE is set (TX FIFO empty) 278 * or if RXR is set (RX FIFO >= ¾ full). 279 */ 280 if (cs & BCM2835_SPI_CS_RXF) 281 bcm2835_rd_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE); 282 else if (cs & BCM2835_SPI_CS_RXR) 283 bcm2835_rd_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE_3_4); 284 285 if (bs->tx_len && cs & BCM2835_SPI_CS_DONE) 286 bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE); 287 288 /* Read as many bytes as possible from FIFO */ 289 bcm2835_rd_fifo(bs); 290 /* Write as many bytes as possible to FIFO */ 291 bcm2835_wr_fifo(bs); 292 293 if (!bs->rx_len) { 294 /* Transfer complete - reset SPI HW */ 295 bcm2835_spi_reset_hw(master); 296 /* wake up the framework */ 297 complete(&master->xfer_completion); 298 } 299 300 return IRQ_HANDLED; 301 } 302 303 static int bcm2835_spi_transfer_one_irq(struct spi_master *master, 304 struct spi_device *spi, 305 struct spi_transfer *tfr, 306 u32 cs, bool fifo_empty) 307 { 308 struct bcm2835_spi *bs = spi_master_get_devdata(master); 309 310 /* 311 * Enable HW block, but with interrupts still disabled. 312 * Otherwise the empty TX FIFO would immediately trigger an interrupt. 313 */ 314 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA); 315 316 /* fill TX FIFO as much as possible */ 317 if (fifo_empty) 318 bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE); 319 bcm2835_wr_fifo(bs); 320 321 /* enable interrupts */ 322 cs |= BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA; 323 bcm2835_wr(bs, BCM2835_SPI_CS, cs); 324 325 /* signal that we need to wait for completion */ 326 return 1; 327 } 328 329 /** 330 * bcm2835_spi_transfer_prologue() - transfer first few bytes without DMA 331 * @master: SPI master 332 * @tfr: SPI transfer 333 * @bs: BCM2835 SPI controller 334 * @cs: CS register 335 * 336 * A limitation in DMA mode is that the FIFO must be accessed in 4 byte chunks. 337 * Only the final write access is permitted to transmit less than 4 bytes, the 338 * SPI controller deduces its intended size from the DLEN register. 339 * 340 * If a TX or RX sglist contains multiple entries, one per page, and the first 341 * entry starts in the middle of a page, that first entry's length may not be 342 * a multiple of 4. Subsequent entries are fine because they span an entire 343 * page, hence do have a length that's a multiple of 4. 344 * 345 * This cannot happen with kmalloc'ed buffers (which is what most clients use) 346 * because they are contiguous in physical memory and therefore not split on 347 * page boundaries by spi_map_buf(). But it *can* happen with vmalloc'ed 348 * buffers. 349 * 350 * The DMA engine is incapable of combining sglist entries into a continuous 351 * stream of 4 byte chunks, it treats every entry separately: A TX entry is 352 * rounded up a to a multiple of 4 bytes by transmitting surplus bytes, an RX 353 * entry is rounded up by throwing away received bytes. 354 * 355 * Overcome this limitation by transferring the first few bytes without DMA: 356 * E.g. if the first TX sglist entry's length is 23 and the first RX's is 42, 357 * write 3 bytes to the TX FIFO but read only 2 bytes from the RX FIFO. 358 * The residue of 1 byte in the RX FIFO is picked up by DMA. Together with 359 * the rest of the first RX sglist entry it makes up a multiple of 4 bytes. 360 * 361 * Should the RX prologue be larger, say, 3 vis-à-vis a TX prologue of 1, 362 * write 1 + 4 = 5 bytes to the TX FIFO and read 3 bytes from the RX FIFO. 363 * Caution, the additional 4 bytes spill over to the second TX sglist entry 364 * if the length of the first is *exactly* 1. 365 * 366 * At most 6 bytes are written and at most 3 bytes read. Do we know the 367 * transfer has this many bytes? Yes, see BCM2835_SPI_DMA_MIN_LENGTH. 368 * 369 * The FIFO is normally accessed with 8-bit width by the CPU and 32-bit width 370 * by the DMA engine. Toggling the DMA Enable flag in the CS register switches 371 * the width but also garbles the FIFO's contents. The prologue must therefore 372 * be transmitted in 32-bit width to ensure that the following DMA transfer can 373 * pick up the residue in the RX FIFO in ungarbled form. 374 */ 375 static void bcm2835_spi_transfer_prologue(struct spi_master *master, 376 struct spi_transfer *tfr, 377 struct bcm2835_spi *bs, 378 u32 cs) 379 { 380 int tx_remaining; 381 382 bs->tfr = tfr; 383 bs->tx_prologue = 0; 384 bs->rx_prologue = 0; 385 bs->tx_spillover = false; 386 387 if (!sg_is_last(&tfr->tx_sg.sgl[0])) 388 bs->tx_prologue = sg_dma_len(&tfr->tx_sg.sgl[0]) & 3; 389 390 if (!sg_is_last(&tfr->rx_sg.sgl[0])) { 391 bs->rx_prologue = sg_dma_len(&tfr->rx_sg.sgl[0]) & 3; 392 393 if (bs->rx_prologue > bs->tx_prologue) { 394 if (sg_is_last(&tfr->tx_sg.sgl[0])) { 395 bs->tx_prologue = bs->rx_prologue; 396 } else { 397 bs->tx_prologue += 4; 398 bs->tx_spillover = 399 !(sg_dma_len(&tfr->tx_sg.sgl[0]) & ~3); 400 } 401 } 402 } 403 404 /* rx_prologue > 0 implies tx_prologue > 0, so check only the latter */ 405 if (!bs->tx_prologue) 406 return; 407 408 /* Write and read RX prologue. Adjust first entry in RX sglist. */ 409 if (bs->rx_prologue) { 410 bcm2835_wr(bs, BCM2835_SPI_DLEN, bs->rx_prologue); 411 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA 412 | BCM2835_SPI_CS_DMAEN); 413 bcm2835_wr_fifo_count(bs, bs->rx_prologue); 414 bcm2835_wait_tx_fifo_empty(bs); 415 bcm2835_rd_fifo_count(bs, bs->rx_prologue); 416 bcm2835_spi_reset_hw(master); 417 418 dma_sync_single_for_device(master->dma_rx->device->dev, 419 sg_dma_address(&tfr->rx_sg.sgl[0]), 420 bs->rx_prologue, DMA_FROM_DEVICE); 421 422 sg_dma_address(&tfr->rx_sg.sgl[0]) += bs->rx_prologue; 423 sg_dma_len(&tfr->rx_sg.sgl[0]) -= bs->rx_prologue; 424 } 425 426 /* 427 * Write remaining TX prologue. Adjust first entry in TX sglist. 428 * Also adjust second entry if prologue spills over to it. 429 */ 430 tx_remaining = bs->tx_prologue - bs->rx_prologue; 431 if (tx_remaining) { 432 bcm2835_wr(bs, BCM2835_SPI_DLEN, tx_remaining); 433 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA 434 | BCM2835_SPI_CS_DMAEN); 435 bcm2835_wr_fifo_count(bs, tx_remaining); 436 bcm2835_wait_tx_fifo_empty(bs); 437 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_CLEAR_TX); 438 } 439 440 if (likely(!bs->tx_spillover)) { 441 sg_dma_address(&tfr->tx_sg.sgl[0]) += bs->tx_prologue; 442 sg_dma_len(&tfr->tx_sg.sgl[0]) -= bs->tx_prologue; 443 } else { 444 sg_dma_len(&tfr->tx_sg.sgl[0]) = 0; 445 sg_dma_address(&tfr->tx_sg.sgl[1]) += 4; 446 sg_dma_len(&tfr->tx_sg.sgl[1]) -= 4; 447 } 448 } 449 450 /** 451 * bcm2835_spi_undo_prologue() - reconstruct original sglist state 452 * @bs: BCM2835 SPI controller 453 * 454 * Undo changes which were made to an SPI transfer's sglist when transmitting 455 * the prologue. This is necessary to ensure the same memory ranges are 456 * unmapped that were originally mapped. 457 */ 458 static void bcm2835_spi_undo_prologue(struct bcm2835_spi *bs) 459 { 460 struct spi_transfer *tfr = bs->tfr; 461 462 if (!bs->tx_prologue) 463 return; 464 465 if (bs->rx_prologue) { 466 sg_dma_address(&tfr->rx_sg.sgl[0]) -= bs->rx_prologue; 467 sg_dma_len(&tfr->rx_sg.sgl[0]) += bs->rx_prologue; 468 } 469 470 if (likely(!bs->tx_spillover)) { 471 sg_dma_address(&tfr->tx_sg.sgl[0]) -= bs->tx_prologue; 472 sg_dma_len(&tfr->tx_sg.sgl[0]) += bs->tx_prologue; 473 } else { 474 sg_dma_len(&tfr->tx_sg.sgl[0]) = bs->tx_prologue - 4; 475 sg_dma_address(&tfr->tx_sg.sgl[1]) -= 4; 476 sg_dma_len(&tfr->tx_sg.sgl[1]) += 4; 477 } 478 } 479 480 static void bcm2835_spi_dma_done(void *data) 481 { 482 struct spi_master *master = data; 483 struct bcm2835_spi *bs = spi_master_get_devdata(master); 484 485 /* reset fifo and HW */ 486 bcm2835_spi_reset_hw(master); 487 488 /* and terminate tx-dma as we do not have an irq for it 489 * because when the rx dma will terminate and this callback 490 * is called the tx-dma must have finished - can't get to this 491 * situation otherwise... 492 */ 493 if (cmpxchg(&bs->dma_pending, true, false)) { 494 dmaengine_terminate_async(master->dma_tx); 495 bcm2835_spi_undo_prologue(bs); 496 } 497 498 /* and mark as completed */; 499 complete(&master->xfer_completion); 500 } 501 502 static int bcm2835_spi_prepare_sg(struct spi_master *master, 503 struct spi_transfer *tfr, 504 bool is_tx) 505 { 506 struct dma_chan *chan; 507 struct scatterlist *sgl; 508 unsigned int nents; 509 enum dma_transfer_direction dir; 510 unsigned long flags; 511 512 struct dma_async_tx_descriptor *desc; 513 dma_cookie_t cookie; 514 515 if (is_tx) { 516 dir = DMA_MEM_TO_DEV; 517 chan = master->dma_tx; 518 nents = tfr->tx_sg.nents; 519 sgl = tfr->tx_sg.sgl; 520 flags = 0 /* no tx interrupt */; 521 522 } else { 523 dir = DMA_DEV_TO_MEM; 524 chan = master->dma_rx; 525 nents = tfr->rx_sg.nents; 526 sgl = tfr->rx_sg.sgl; 527 flags = DMA_PREP_INTERRUPT; 528 } 529 /* prepare the channel */ 530 desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags); 531 if (!desc) 532 return -EINVAL; 533 534 /* set callback for rx */ 535 if (!is_tx) { 536 desc->callback = bcm2835_spi_dma_done; 537 desc->callback_param = master; 538 } 539 540 /* submit it to DMA-engine */ 541 cookie = dmaengine_submit(desc); 542 543 return dma_submit_error(cookie); 544 } 545 546 static int bcm2835_spi_transfer_one_dma(struct spi_master *master, 547 struct spi_device *spi, 548 struct spi_transfer *tfr, 549 u32 cs) 550 { 551 struct bcm2835_spi *bs = spi_master_get_devdata(master); 552 int ret; 553 554 /* 555 * Transfer first few bytes without DMA if length of first TX or RX 556 * sglist entry is not a multiple of 4 bytes (hardware limitation). 557 */ 558 bcm2835_spi_transfer_prologue(master, tfr, bs, cs); 559 560 /* setup tx-DMA */ 561 ret = bcm2835_spi_prepare_sg(master, tfr, true); 562 if (ret) 563 goto err_reset_hw; 564 565 /* start TX early */ 566 dma_async_issue_pending(master->dma_tx); 567 568 /* mark as dma pending */ 569 bs->dma_pending = 1; 570 571 /* set the DMA length */ 572 bcm2835_wr(bs, BCM2835_SPI_DLEN, bs->tx_len); 573 574 /* start the HW */ 575 bcm2835_wr(bs, BCM2835_SPI_CS, 576 cs | BCM2835_SPI_CS_TA | BCM2835_SPI_CS_DMAEN); 577 578 /* setup rx-DMA late - to run transfers while 579 * mapping of the rx buffers still takes place 580 * this saves 10us or more. 581 */ 582 ret = bcm2835_spi_prepare_sg(master, tfr, false); 583 if (ret) { 584 /* need to reset on errors */ 585 dmaengine_terminate_sync(master->dma_tx); 586 bs->dma_pending = false; 587 goto err_reset_hw; 588 } 589 590 /* start rx dma late */ 591 dma_async_issue_pending(master->dma_rx); 592 593 /* wait for wakeup in framework */ 594 return 1; 595 596 err_reset_hw: 597 bcm2835_spi_reset_hw(master); 598 bcm2835_spi_undo_prologue(bs); 599 return ret; 600 } 601 602 static bool bcm2835_spi_can_dma(struct spi_master *master, 603 struct spi_device *spi, 604 struct spi_transfer *tfr) 605 { 606 /* we start DMA efforts only on bigger transfers */ 607 if (tfr->len < BCM2835_SPI_DMA_MIN_LENGTH) 608 return false; 609 610 /* return OK */ 611 return true; 612 } 613 614 static void bcm2835_dma_release(struct spi_master *master) 615 { 616 if (master->dma_tx) { 617 dmaengine_terminate_sync(master->dma_tx); 618 dma_release_channel(master->dma_tx); 619 master->dma_tx = NULL; 620 } 621 if (master->dma_rx) { 622 dmaengine_terminate_sync(master->dma_rx); 623 dma_release_channel(master->dma_rx); 624 master->dma_rx = NULL; 625 } 626 } 627 628 static void bcm2835_dma_init(struct spi_master *master, struct device *dev) 629 { 630 struct dma_slave_config slave_config; 631 const __be32 *addr; 632 dma_addr_t dma_reg_base; 633 int ret; 634 635 /* base address in dma-space */ 636 addr = of_get_address(master->dev.of_node, 0, NULL, NULL); 637 if (!addr) { 638 dev_err(dev, "could not get DMA-register address - not using dma mode\n"); 639 goto err; 640 } 641 dma_reg_base = be32_to_cpup(addr); 642 643 /* get tx/rx dma */ 644 master->dma_tx = dma_request_slave_channel(dev, "tx"); 645 if (!master->dma_tx) { 646 dev_err(dev, "no tx-dma configuration found - not using dma mode\n"); 647 goto err; 648 } 649 master->dma_rx = dma_request_slave_channel(dev, "rx"); 650 if (!master->dma_rx) { 651 dev_err(dev, "no rx-dma configuration found - not using dma mode\n"); 652 goto err_release; 653 } 654 655 /* configure DMAs */ 656 slave_config.direction = DMA_MEM_TO_DEV; 657 slave_config.dst_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO); 658 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 659 660 ret = dmaengine_slave_config(master->dma_tx, &slave_config); 661 if (ret) 662 goto err_config; 663 664 slave_config.direction = DMA_DEV_TO_MEM; 665 slave_config.src_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO); 666 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 667 668 ret = dmaengine_slave_config(master->dma_rx, &slave_config); 669 if (ret) 670 goto err_config; 671 672 /* all went well, so set can_dma */ 673 master->can_dma = bcm2835_spi_can_dma; 674 /* need to do TX AND RX DMA, so we need dummy buffers */ 675 master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX; 676 677 return; 678 679 err_config: 680 dev_err(dev, "issue configuring dma: %d - not using DMA mode\n", 681 ret); 682 err_release: 683 bcm2835_dma_release(master); 684 err: 685 return; 686 } 687 688 static int bcm2835_spi_transfer_one_poll(struct spi_master *master, 689 struct spi_device *spi, 690 struct spi_transfer *tfr, 691 u32 cs, 692 unsigned long long xfer_time_us) 693 { 694 struct bcm2835_spi *bs = spi_master_get_devdata(master); 695 unsigned long timeout; 696 697 /* enable HW block without interrupts */ 698 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA); 699 700 /* fill in the fifo before timeout calculations 701 * if we are interrupted here, then the data is 702 * getting transferred by the HW while we are interrupted 703 */ 704 bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE); 705 706 /* set the timeout */ 707 timeout = jiffies + BCM2835_SPI_POLLING_JIFFIES; 708 709 /* loop until finished the transfer */ 710 while (bs->rx_len) { 711 /* fill in tx fifo with remaining data */ 712 bcm2835_wr_fifo(bs); 713 714 /* read from fifo as much as possible */ 715 bcm2835_rd_fifo(bs); 716 717 /* if there is still data pending to read 718 * then check the timeout 719 */ 720 if (bs->rx_len && time_after(jiffies, timeout)) { 721 dev_dbg_ratelimited(&spi->dev, 722 "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n", 723 jiffies - timeout, 724 bs->tx_len, bs->rx_len); 725 /* fall back to interrupt mode */ 726 return bcm2835_spi_transfer_one_irq(master, spi, 727 tfr, cs, false); 728 } 729 } 730 731 /* Transfer complete - reset SPI HW */ 732 bcm2835_spi_reset_hw(master); 733 /* and return without waiting for completion */ 734 return 0; 735 } 736 737 static int bcm2835_spi_transfer_one(struct spi_master *master, 738 struct spi_device *spi, 739 struct spi_transfer *tfr) 740 { 741 struct bcm2835_spi *bs = spi_master_get_devdata(master); 742 unsigned long spi_hz, clk_hz, cdiv; 743 unsigned long spi_used_hz; 744 unsigned long long xfer_time_us; 745 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); 746 747 /* set clock */ 748 spi_hz = tfr->speed_hz; 749 clk_hz = clk_get_rate(bs->clk); 750 751 if (spi_hz >= clk_hz / 2) { 752 cdiv = 2; /* clk_hz/2 is the fastest we can go */ 753 } else if (spi_hz) { 754 /* CDIV must be a multiple of two */ 755 cdiv = DIV_ROUND_UP(clk_hz, spi_hz); 756 cdiv += (cdiv % 2); 757 758 if (cdiv >= 65536) 759 cdiv = 0; /* 0 is the slowest we can go */ 760 } else { 761 cdiv = 0; /* 0 is the slowest we can go */ 762 } 763 spi_used_hz = cdiv ? (clk_hz / cdiv) : (clk_hz / 65536); 764 bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv); 765 766 /* handle all the 3-wire mode */ 767 if ((spi->mode & SPI_3WIRE) && (tfr->rx_buf)) 768 cs |= BCM2835_SPI_CS_REN; 769 else 770 cs &= ~BCM2835_SPI_CS_REN; 771 772 /* 773 * The driver always uses software-controlled GPIO Chip Select. 774 * Set the hardware-controlled native Chip Select to an invalid 775 * value to prevent it from interfering. 776 */ 777 cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01; 778 779 /* set transmit buffers and length */ 780 bs->tx_buf = tfr->tx_buf; 781 bs->rx_buf = tfr->rx_buf; 782 bs->tx_len = tfr->len; 783 bs->rx_len = tfr->len; 784 785 /* calculate the estimated time in us the transfer runs */ 786 xfer_time_us = (unsigned long long)tfr->len 787 * 9 /* clocks/byte - SPI-HW waits 1 clock after each byte */ 788 * 1000000; 789 do_div(xfer_time_us, spi_used_hz); 790 791 /* for short requests run polling*/ 792 if (xfer_time_us <= BCM2835_SPI_POLLING_LIMIT_US) 793 return bcm2835_spi_transfer_one_poll(master, spi, tfr, 794 cs, xfer_time_us); 795 796 /* run in dma mode if conditions are right */ 797 if (master->can_dma && bcm2835_spi_can_dma(master, spi, tfr)) 798 return bcm2835_spi_transfer_one_dma(master, spi, tfr, cs); 799 800 /* run in interrupt-mode */ 801 return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs, true); 802 } 803 804 static int bcm2835_spi_prepare_message(struct spi_master *master, 805 struct spi_message *msg) 806 { 807 struct spi_device *spi = msg->spi; 808 struct bcm2835_spi *bs = spi_master_get_devdata(master); 809 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); 810 int ret; 811 812 /* 813 * DMA transfers are limited to 16 bit (0 to 65535 bytes) by the SPI HW 814 * due to DLEN. Split up transfers (32-bit FIFO aligned) if the limit is 815 * exceeded. 816 */ 817 ret = spi_split_transfers_maxsize(master, msg, 65532, 818 GFP_KERNEL | GFP_DMA); 819 if (ret) 820 return ret; 821 822 cs &= ~(BCM2835_SPI_CS_CPOL | BCM2835_SPI_CS_CPHA); 823 824 if (spi->mode & SPI_CPOL) 825 cs |= BCM2835_SPI_CS_CPOL; 826 if (spi->mode & SPI_CPHA) 827 cs |= BCM2835_SPI_CS_CPHA; 828 829 bcm2835_wr(bs, BCM2835_SPI_CS, cs); 830 831 return 0; 832 } 833 834 static void bcm2835_spi_handle_err(struct spi_master *master, 835 struct spi_message *msg) 836 { 837 struct bcm2835_spi *bs = spi_master_get_devdata(master); 838 839 /* if an error occurred and we have an active dma, then terminate */ 840 if (cmpxchg(&bs->dma_pending, true, false)) { 841 dmaengine_terminate_sync(master->dma_tx); 842 dmaengine_terminate_sync(master->dma_rx); 843 bcm2835_spi_undo_prologue(bs); 844 } 845 /* and reset */ 846 bcm2835_spi_reset_hw(master); 847 } 848 849 static int chip_match_name(struct gpio_chip *chip, void *data) 850 { 851 return !strcmp(chip->label, data); 852 } 853 854 static int bcm2835_spi_setup(struct spi_device *spi) 855 { 856 int err; 857 struct gpio_chip *chip; 858 /* 859 * sanity checking the native-chipselects 860 */ 861 if (spi->mode & SPI_NO_CS) 862 return 0; 863 if (gpio_is_valid(spi->cs_gpio)) 864 return 0; 865 if (spi->chip_select > 1) { 866 /* error in the case of native CS requested with CS > 1 867 * officially there is a CS2, but it is not documented 868 * which GPIO is connected with that... 869 */ 870 dev_err(&spi->dev, 871 "setup: only two native chip-selects are supported\n"); 872 return -EINVAL; 873 } 874 /* now translate native cs to GPIO */ 875 876 /* get the gpio chip for the base */ 877 chip = gpiochip_find("pinctrl-bcm2835", chip_match_name); 878 if (!chip) 879 return 0; 880 881 /* and calculate the real CS */ 882 spi->cs_gpio = chip->base + 8 - spi->chip_select; 883 884 /* and set up the "mode" and level */ 885 dev_info(&spi->dev, "setting up native-CS%i as GPIO %i\n", 886 spi->chip_select, spi->cs_gpio); 887 888 /* set up GPIO as output and pull to the correct level */ 889 err = gpio_direction_output(spi->cs_gpio, 890 (spi->mode & SPI_CS_HIGH) ? 0 : 1); 891 if (err) { 892 dev_err(&spi->dev, 893 "could not set CS%i gpio %i as output: %i", 894 spi->chip_select, spi->cs_gpio, err); 895 return err; 896 } 897 898 return 0; 899 } 900 901 static int bcm2835_spi_probe(struct platform_device *pdev) 902 { 903 struct spi_master *master; 904 struct bcm2835_spi *bs; 905 struct resource *res; 906 int err; 907 908 master = spi_alloc_master(&pdev->dev, sizeof(*bs)); 909 if (!master) { 910 dev_err(&pdev->dev, "spi_alloc_master() failed\n"); 911 return -ENOMEM; 912 } 913 914 platform_set_drvdata(pdev, master); 915 916 master->mode_bits = BCM2835_SPI_MODE_BITS; 917 master->bits_per_word_mask = SPI_BPW_MASK(8); 918 master->num_chipselect = 3; 919 master->setup = bcm2835_spi_setup; 920 master->transfer_one = bcm2835_spi_transfer_one; 921 master->handle_err = bcm2835_spi_handle_err; 922 master->prepare_message = bcm2835_spi_prepare_message; 923 master->dev.of_node = pdev->dev.of_node; 924 925 bs = spi_master_get_devdata(master); 926 927 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 928 bs->regs = devm_ioremap_resource(&pdev->dev, res); 929 if (IS_ERR(bs->regs)) { 930 err = PTR_ERR(bs->regs); 931 goto out_master_put; 932 } 933 934 bs->clk = devm_clk_get(&pdev->dev, NULL); 935 if (IS_ERR(bs->clk)) { 936 err = PTR_ERR(bs->clk); 937 dev_err(&pdev->dev, "could not get clk: %d\n", err); 938 goto out_master_put; 939 } 940 941 bs->irq = platform_get_irq(pdev, 0); 942 if (bs->irq <= 0) { 943 dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq); 944 err = bs->irq ? bs->irq : -ENODEV; 945 goto out_master_put; 946 } 947 948 clk_prepare_enable(bs->clk); 949 950 bcm2835_dma_init(master, &pdev->dev); 951 952 /* initialise the hardware with the default polarities */ 953 bcm2835_wr(bs, BCM2835_SPI_CS, 954 BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX); 955 956 err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0, 957 dev_name(&pdev->dev), master); 958 if (err) { 959 dev_err(&pdev->dev, "could not request IRQ: %d\n", err); 960 goto out_clk_disable; 961 } 962 963 err = devm_spi_register_master(&pdev->dev, master); 964 if (err) { 965 dev_err(&pdev->dev, "could not register SPI master: %d\n", err); 966 goto out_clk_disable; 967 } 968 969 return 0; 970 971 out_clk_disable: 972 clk_disable_unprepare(bs->clk); 973 out_master_put: 974 spi_master_put(master); 975 return err; 976 } 977 978 static int bcm2835_spi_remove(struct platform_device *pdev) 979 { 980 struct spi_master *master = platform_get_drvdata(pdev); 981 struct bcm2835_spi *bs = spi_master_get_devdata(master); 982 983 /* Clear FIFOs, and disable the HW block */ 984 bcm2835_wr(bs, BCM2835_SPI_CS, 985 BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX); 986 987 clk_disable_unprepare(bs->clk); 988 989 bcm2835_dma_release(master); 990 991 return 0; 992 } 993 994 static const struct of_device_id bcm2835_spi_match[] = { 995 { .compatible = "brcm,bcm2835-spi", }, 996 {} 997 }; 998 MODULE_DEVICE_TABLE(of, bcm2835_spi_match); 999 1000 static struct platform_driver bcm2835_spi_driver = { 1001 .driver = { 1002 .name = DRV_NAME, 1003 .of_match_table = bcm2835_spi_match, 1004 }, 1005 .probe = bcm2835_spi_probe, 1006 .remove = bcm2835_spi_remove, 1007 }; 1008 module_platform_driver(bcm2835_spi_driver); 1009 1010 MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835"); 1011 MODULE_AUTHOR("Chris Boot <bootc@bootc.net>"); 1012 MODULE_LICENSE("GPL"); 1013